setup_64.c 32 KB

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  1. /*
  2. * Copyright (C) 1995 Linus Torvalds
  3. */
  4. /*
  5. * This file handles the architecture-dependent parts of initialization
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/sched.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mm.h>
  11. #include <linux/stddef.h>
  12. #include <linux/unistd.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/slab.h>
  15. #include <linux/user.h>
  16. #include <linux/a.out.h>
  17. #include <linux/screen_info.h>
  18. #include <linux/ioport.h>
  19. #include <linux/delay.h>
  20. #include <linux/init.h>
  21. #include <linux/initrd.h>
  22. #include <linux/highmem.h>
  23. #include <linux/bootmem.h>
  24. #include <linux/module.h>
  25. #include <asm/processor.h>
  26. #include <linux/console.h>
  27. #include <linux/seq_file.h>
  28. #include <linux/crash_dump.h>
  29. #include <linux/root_dev.h>
  30. #include <linux/pci.h>
  31. #include <linux/efi.h>
  32. #include <linux/acpi.h>
  33. #include <linux/kallsyms.h>
  34. #include <linux/edd.h>
  35. #include <linux/mmzone.h>
  36. #include <linux/kexec.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/dmi.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/ctype.h>
  41. #include <linux/uaccess.h>
  42. #include <asm/mtrr.h>
  43. #include <asm/uaccess.h>
  44. #include <asm/system.h>
  45. #include <asm/vsyscall.h>
  46. #include <asm/io.h>
  47. #include <asm/smp.h>
  48. #include <asm/msr.h>
  49. #include <asm/desc.h>
  50. #include <video/edid.h>
  51. #include <asm/e820.h>
  52. #include <asm/dma.h>
  53. #include <asm/gart.h>
  54. #include <asm/mpspec.h>
  55. #include <asm/mmu_context.h>
  56. #include <asm/proto.h>
  57. #include <asm/setup.h>
  58. #include <asm/mach_apic.h>
  59. #include <asm/numa.h>
  60. #include <asm/sections.h>
  61. #include <asm/dmi.h>
  62. #include <asm/cacheflush.h>
  63. #include <asm/mce.h>
  64. #include <asm/ds.h>
  65. #ifdef CONFIG_PARAVIRT
  66. #include <asm/paravirt.h>
  67. #else
  68. #define ARCH_SETUP
  69. #endif
  70. /*
  71. * Machine setup..
  72. */
  73. struct cpuinfo_x86 boot_cpu_data __read_mostly;
  74. EXPORT_SYMBOL(boot_cpu_data);
  75. unsigned long mmu_cr4_features;
  76. /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  77. int bootloader_type;
  78. unsigned long saved_video_mode;
  79. int force_mwait __cpuinitdata;
  80. /*
  81. * Early DMI memory
  82. */
  83. int dmi_alloc_index;
  84. char dmi_alloc_data[DMI_MAX_DATA];
  85. /*
  86. * Setup options
  87. */
  88. struct screen_info screen_info;
  89. EXPORT_SYMBOL(screen_info);
  90. struct sys_desc_table_struct {
  91. unsigned short length;
  92. unsigned char table[0];
  93. };
  94. struct edid_info edid_info;
  95. EXPORT_SYMBOL_GPL(edid_info);
  96. extern int root_mountflags;
  97. char __initdata command_line[COMMAND_LINE_SIZE];
  98. struct resource standard_io_resources[] = {
  99. { .name = "dma1", .start = 0x00, .end = 0x1f,
  100. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  101. { .name = "pic1", .start = 0x20, .end = 0x21,
  102. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  103. { .name = "timer0", .start = 0x40, .end = 0x43,
  104. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  105. { .name = "timer1", .start = 0x50, .end = 0x53,
  106. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  107. { .name = "keyboard", .start = 0x60, .end = 0x6f,
  108. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  109. { .name = "dma page reg", .start = 0x80, .end = 0x8f,
  110. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  111. { .name = "pic2", .start = 0xa0, .end = 0xa1,
  112. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  113. { .name = "dma2", .start = 0xc0, .end = 0xdf,
  114. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  115. { .name = "fpu", .start = 0xf0, .end = 0xff,
  116. .flags = IORESOURCE_BUSY | IORESOURCE_IO }
  117. };
  118. #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
  119. static struct resource data_resource = {
  120. .name = "Kernel data",
  121. .start = 0,
  122. .end = 0,
  123. .flags = IORESOURCE_RAM,
  124. };
  125. static struct resource code_resource = {
  126. .name = "Kernel code",
  127. .start = 0,
  128. .end = 0,
  129. .flags = IORESOURCE_RAM,
  130. };
  131. static struct resource bss_resource = {
  132. .name = "Kernel bss",
  133. .start = 0,
  134. .end = 0,
  135. .flags = IORESOURCE_RAM,
  136. };
  137. static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
  138. #ifdef CONFIG_PROC_VMCORE
  139. /* elfcorehdr= specifies the location of elf core header
  140. * stored by the crashed kernel. This option will be passed
  141. * by kexec loader to the capture kernel.
  142. */
  143. static int __init setup_elfcorehdr(char *arg)
  144. {
  145. char *end;
  146. if (!arg)
  147. return -EINVAL;
  148. elfcorehdr_addr = memparse(arg, &end);
  149. return end > arg ? 0 : -EINVAL;
  150. }
  151. early_param("elfcorehdr", setup_elfcorehdr);
  152. #endif
  153. #ifndef CONFIG_NUMA
  154. static void __init
  155. contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
  156. {
  157. unsigned long bootmap_size, bootmap;
  158. bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
  159. bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
  160. if (bootmap == -1L)
  161. panic("Cannot find bootmem map of size %ld\n", bootmap_size);
  162. bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
  163. e820_register_active_regions(0, start_pfn, end_pfn);
  164. free_bootmem_with_active_regions(0, end_pfn);
  165. reserve_bootmem(bootmap, bootmap_size);
  166. }
  167. #endif
  168. #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
  169. struct edd edd;
  170. #ifdef CONFIG_EDD_MODULE
  171. EXPORT_SYMBOL(edd);
  172. #endif
  173. /**
  174. * copy_edd() - Copy the BIOS EDD information
  175. * from boot_params into a safe place.
  176. *
  177. */
  178. static inline void copy_edd(void)
  179. {
  180. memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
  181. sizeof(edd.mbr_signature));
  182. memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
  183. edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
  184. edd.edd_info_nr = boot_params.eddbuf_entries;
  185. }
  186. #else
  187. static inline void copy_edd(void)
  188. {
  189. }
  190. #endif
  191. #ifdef CONFIG_KEXEC
  192. static void __init reserve_crashkernel(void)
  193. {
  194. unsigned long long free_mem;
  195. unsigned long long crash_size, crash_base;
  196. int ret;
  197. free_mem =
  198. ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
  199. ret = parse_crashkernel(boot_command_line, free_mem,
  200. &crash_size, &crash_base);
  201. if (ret == 0 && crash_size) {
  202. if (crash_base > 0) {
  203. printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
  204. "for crashkernel (System RAM: %ldMB)\n",
  205. (unsigned long)(crash_size >> 20),
  206. (unsigned long)(crash_base >> 20),
  207. (unsigned long)(free_mem >> 20));
  208. crashk_res.start = crash_base;
  209. crashk_res.end = crash_base + crash_size - 1;
  210. reserve_bootmem(crash_base, crash_size);
  211. } else
  212. printk(KERN_INFO "crashkernel reservation failed - "
  213. "you have to specify a base address\n");
  214. }
  215. }
  216. #else
  217. static inline void __init reserve_crashkernel(void)
  218. {}
  219. #endif
  220. #define EBDA_ADDR_POINTER 0x40E
  221. unsigned __initdata ebda_addr;
  222. unsigned __initdata ebda_size;
  223. static void __init discover_ebda(void)
  224. {
  225. /*
  226. * there is a real-mode segmented pointer pointing to the
  227. * 4K EBDA area at 0x40E
  228. */
  229. ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
  230. /*
  231. * There can be some situations, like paravirtualized guests,
  232. * in which there is no available ebda information. In such
  233. * case, just skip it
  234. */
  235. if (!ebda_addr) {
  236. ebda_size = 0;
  237. return;
  238. }
  239. ebda_addr <<= 4;
  240. ebda_size = *(unsigned short *)__va(ebda_addr);
  241. /* Round EBDA up to pages */
  242. if (ebda_size == 0)
  243. ebda_size = 1;
  244. ebda_size <<= 10;
  245. ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
  246. if (ebda_size > 64*1024)
  247. ebda_size = 64*1024;
  248. }
  249. /* Overridden in paravirt.c if CONFIG_PARAVIRT */
  250. void __attribute__((weak)) __init memory_setup(void)
  251. {
  252. machine_specific_memory_setup();
  253. }
  254. void __init setup_arch(char **cmdline_p)
  255. {
  256. unsigned i;
  257. printk(KERN_INFO "Command line: %s\n", boot_command_line);
  258. ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
  259. screen_info = boot_params.screen_info;
  260. edid_info = boot_params.edid_info;
  261. saved_video_mode = boot_params.hdr.vid_mode;
  262. bootloader_type = boot_params.hdr.type_of_loader;
  263. #ifdef CONFIG_BLK_DEV_RAM
  264. rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
  265. rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
  266. rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
  267. #endif
  268. #ifdef CONFIG_EFI
  269. if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
  270. "EL64", 4))
  271. efi_enabled = 1;
  272. #endif
  273. ARCH_SETUP
  274. memory_setup();
  275. copy_edd();
  276. if (!boot_params.hdr.root_flags)
  277. root_mountflags &= ~MS_RDONLY;
  278. init_mm.start_code = (unsigned long) &_text;
  279. init_mm.end_code = (unsigned long) &_etext;
  280. init_mm.end_data = (unsigned long) &_edata;
  281. init_mm.brk = (unsigned long) &_end;
  282. code_resource.start = virt_to_phys(&_text);
  283. code_resource.end = virt_to_phys(&_etext)-1;
  284. data_resource.start = virt_to_phys(&_etext);
  285. data_resource.end = virt_to_phys(&_edata)-1;
  286. bss_resource.start = virt_to_phys(&__bss_start);
  287. bss_resource.end = virt_to_phys(&__bss_stop)-1;
  288. early_identify_cpu(&boot_cpu_data);
  289. strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
  290. *cmdline_p = command_line;
  291. parse_early_param();
  292. finish_e820_parsing();
  293. early_gart_iommu_check();
  294. e820_register_active_regions(0, 0, -1UL);
  295. /*
  296. * partially used pages are not usable - thus
  297. * we are rounding upwards:
  298. */
  299. end_pfn = e820_end_of_ram();
  300. num_physpages = end_pfn;
  301. check_efer();
  302. discover_ebda();
  303. init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
  304. if (efi_enabled)
  305. efi_init();
  306. dmi_scan_machine();
  307. io_delay_init();
  308. #ifdef CONFIG_SMP
  309. /* setup to use the static apicid table during kernel startup */
  310. x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
  311. #endif
  312. #ifdef CONFIG_ACPI
  313. /*
  314. * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
  315. * Call this early for SRAT node setup.
  316. */
  317. acpi_boot_table_init();
  318. #endif
  319. /* How many end-of-memory variables you have, grandma! */
  320. max_low_pfn = end_pfn;
  321. max_pfn = end_pfn;
  322. high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
  323. /* Remove active ranges so rediscovery with NUMA-awareness happens */
  324. remove_all_active_ranges();
  325. #ifdef CONFIG_ACPI_NUMA
  326. /*
  327. * Parse SRAT to discover nodes.
  328. */
  329. acpi_numa_init();
  330. #endif
  331. #ifdef CONFIG_NUMA
  332. numa_initmem_init(0, end_pfn);
  333. #else
  334. contig_initmem_init(0, end_pfn);
  335. #endif
  336. /* Reserve direct mapping */
  337. reserve_bootmem_generic(table_start << PAGE_SHIFT,
  338. (table_end - table_start) << PAGE_SHIFT);
  339. /* reserve kernel */
  340. reserve_bootmem_generic(__pa_symbol(&_text),
  341. __pa_symbol(&_end) - __pa_symbol(&_text));
  342. /*
  343. * reserve physical page 0 - it's a special BIOS page on many boxes,
  344. * enabling clean reboots, SMP operation, laptop functions.
  345. */
  346. reserve_bootmem_generic(0, PAGE_SIZE);
  347. /* reserve ebda region */
  348. if (ebda_addr)
  349. reserve_bootmem_generic(ebda_addr, ebda_size);
  350. #ifdef CONFIG_NUMA
  351. /* reserve nodemap region */
  352. if (nodemap_addr)
  353. reserve_bootmem_generic(nodemap_addr, nodemap_size);
  354. #endif
  355. #ifdef CONFIG_SMP
  356. /* Reserve SMP trampoline */
  357. reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
  358. #endif
  359. #ifdef CONFIG_ACPI_SLEEP
  360. /*
  361. * Reserve low memory region for sleep support.
  362. */
  363. acpi_reserve_bootmem();
  364. #endif
  365. if (efi_enabled) {
  366. efi_map_memmap();
  367. efi_reserve_bootmem();
  368. }
  369. /*
  370. * Find and reserve possible boot-time SMP configuration:
  371. */
  372. find_smp_config();
  373. #ifdef CONFIG_BLK_DEV_INITRD
  374. if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
  375. unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
  376. unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
  377. unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
  378. unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
  379. if (ramdisk_end <= end_of_mem) {
  380. reserve_bootmem_generic(ramdisk_image, ramdisk_size);
  381. initrd_start = ramdisk_image + PAGE_OFFSET;
  382. initrd_end = initrd_start+ramdisk_size;
  383. } else {
  384. printk(KERN_ERR "initrd extends beyond end of memory "
  385. "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
  386. ramdisk_end, end_of_mem);
  387. initrd_start = 0;
  388. }
  389. }
  390. #endif
  391. reserve_crashkernel();
  392. paging_init();
  393. map_vsyscall();
  394. early_quirks();
  395. /*
  396. * set this early, so we dont allocate cpu0
  397. * if MADT list doesnt list BSP first
  398. * mpparse.c/MP_processor_info() allocates logical cpu numbers.
  399. */
  400. cpu_set(0, cpu_present_map);
  401. #ifdef CONFIG_ACPI
  402. /*
  403. * Read APIC and some other early information from ACPI tables.
  404. */
  405. acpi_boot_init();
  406. #endif
  407. init_cpu_to_node();
  408. /*
  409. * get boot-time SMP configuration:
  410. */
  411. if (smp_found_config)
  412. get_smp_config();
  413. init_apic_mappings();
  414. ioapic_init_mappings();
  415. /*
  416. * We trust e820 completely. No explicit ROM probing in memory.
  417. */
  418. e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
  419. e820_mark_nosave_regions();
  420. /* request I/O space for devices used on all i[345]86 PCs */
  421. for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
  422. request_resource(&ioport_resource, &standard_io_resources[i]);
  423. e820_setup_gap();
  424. #ifdef CONFIG_VT
  425. #if defined(CONFIG_VGA_CONSOLE)
  426. if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
  427. conswitchp = &vga_con;
  428. #elif defined(CONFIG_DUMMY_CONSOLE)
  429. conswitchp = &dummy_con;
  430. #endif
  431. #endif
  432. }
  433. static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
  434. {
  435. unsigned int *v;
  436. if (c->extended_cpuid_level < 0x80000004)
  437. return 0;
  438. v = (unsigned int *) c->x86_model_id;
  439. cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  440. cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  441. cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  442. c->x86_model_id[48] = 0;
  443. return 1;
  444. }
  445. static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
  446. {
  447. unsigned int n, dummy, eax, ebx, ecx, edx;
  448. n = c->extended_cpuid_level;
  449. if (n >= 0x80000005) {
  450. cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
  451. printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
  452. "D cache %dK (%d bytes/line)\n",
  453. edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
  454. c->x86_cache_size = (ecx>>24) + (edx>>24);
  455. /* On K8 L1 TLB is inclusive, so don't count it */
  456. c->x86_tlbsize = 0;
  457. }
  458. if (n >= 0x80000006) {
  459. cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
  460. ecx = cpuid_ecx(0x80000006);
  461. c->x86_cache_size = ecx >> 16;
  462. c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
  463. printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
  464. c->x86_cache_size, ecx & 0xFF);
  465. }
  466. if (n >= 0x80000008) {
  467. cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
  468. c->x86_virt_bits = (eax >> 8) & 0xff;
  469. c->x86_phys_bits = eax & 0xff;
  470. }
  471. }
  472. #ifdef CONFIG_NUMA
  473. static int nearby_node(int apicid)
  474. {
  475. int i, node;
  476. for (i = apicid - 1; i >= 0; i--) {
  477. node = apicid_to_node[i];
  478. if (node != NUMA_NO_NODE && node_online(node))
  479. return node;
  480. }
  481. for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
  482. node = apicid_to_node[i];
  483. if (node != NUMA_NO_NODE && node_online(node))
  484. return node;
  485. }
  486. return first_node(node_online_map); /* Shouldn't happen */
  487. }
  488. #endif
  489. /*
  490. * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  491. * Assumes number of cores is a power of two.
  492. */
  493. static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
  494. {
  495. #ifdef CONFIG_SMP
  496. unsigned bits;
  497. #ifdef CONFIG_NUMA
  498. int cpu = smp_processor_id();
  499. int node = 0;
  500. unsigned apicid = hard_smp_processor_id();
  501. #endif
  502. bits = c->x86_coreid_bits;
  503. /* Low order bits define the core id (index of core in socket) */
  504. c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
  505. /* Convert the APIC ID into the socket ID */
  506. c->phys_proc_id = phys_pkg_id(bits);
  507. #ifdef CONFIG_NUMA
  508. node = c->phys_proc_id;
  509. if (apicid_to_node[apicid] != NUMA_NO_NODE)
  510. node = apicid_to_node[apicid];
  511. if (!node_online(node)) {
  512. /* Two possibilities here:
  513. - The CPU is missing memory and no node was created.
  514. In that case try picking one from a nearby CPU
  515. - The APIC IDs differ from the HyperTransport node IDs
  516. which the K8 northbridge parsing fills in.
  517. Assume they are all increased by a constant offset,
  518. but in the same order as the HT nodeids.
  519. If that doesn't result in a usable node fall back to the
  520. path for the previous case. */
  521. int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
  522. if (ht_nodeid >= 0 &&
  523. apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
  524. node = apicid_to_node[ht_nodeid];
  525. /* Pick a nearby node */
  526. if (!node_online(node))
  527. node = nearby_node(apicid);
  528. }
  529. numa_set_node(cpu, node);
  530. printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
  531. #endif
  532. #endif
  533. }
  534. static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
  535. {
  536. #ifdef CONFIG_SMP
  537. unsigned bits, ecx;
  538. /* Multi core CPU? */
  539. if (c->extended_cpuid_level < 0x80000008)
  540. return;
  541. ecx = cpuid_ecx(0x80000008);
  542. c->x86_max_cores = (ecx & 0xff) + 1;
  543. /* CPU telling us the core id bits shift? */
  544. bits = (ecx >> 12) & 0xF;
  545. /* Otherwise recompute */
  546. if (bits == 0) {
  547. while ((1 << bits) < c->x86_max_cores)
  548. bits++;
  549. }
  550. c->x86_coreid_bits = bits;
  551. #endif
  552. }
  553. #define ENABLE_C1E_MASK 0x18000000
  554. #define CPUID_PROCESSOR_SIGNATURE 1
  555. #define CPUID_XFAM 0x0ff00000
  556. #define CPUID_XFAM_K8 0x00000000
  557. #define CPUID_XFAM_10H 0x00100000
  558. #define CPUID_XFAM_11H 0x00200000
  559. #define CPUID_XMOD 0x000f0000
  560. #define CPUID_XMOD_REV_F 0x00040000
  561. /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  562. static __cpuinit int amd_apic_timer_broken(void)
  563. {
  564. u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
  565. switch (eax & CPUID_XFAM) {
  566. case CPUID_XFAM_K8:
  567. if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
  568. break;
  569. case CPUID_XFAM_10H:
  570. case CPUID_XFAM_11H:
  571. rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
  572. if (lo & ENABLE_C1E_MASK)
  573. return 1;
  574. break;
  575. default:
  576. /* err on the side of caution */
  577. return 1;
  578. }
  579. return 0;
  580. }
  581. static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  582. {
  583. early_init_amd_mc(c);
  584. /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
  585. if (c->x86_power & (1<<8))
  586. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  587. }
  588. static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  589. {
  590. unsigned level;
  591. #ifdef CONFIG_SMP
  592. unsigned long value;
  593. /*
  594. * Disable TLB flush filter by setting HWCR.FFDIS on K8
  595. * bit 6 of msr C001_0015
  596. *
  597. * Errata 63 for SH-B3 steppings
  598. * Errata 122 for all steppings (F+ have it disabled by default)
  599. */
  600. if (c->x86 == 15) {
  601. rdmsrl(MSR_K8_HWCR, value);
  602. value |= 1 << 6;
  603. wrmsrl(MSR_K8_HWCR, value);
  604. }
  605. #endif
  606. /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  607. 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  608. clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
  609. /* On C+ stepping K8 rep microcode works well for copy/memset */
  610. level = cpuid_eax(1);
  611. if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
  612. level >= 0x0f58))
  613. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  614. if (c->x86 == 0x10 || c->x86 == 0x11)
  615. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  616. /* Enable workaround for FXSAVE leak */
  617. if (c->x86 >= 6)
  618. set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
  619. level = get_model_name(c);
  620. if (!level) {
  621. switch (c->x86) {
  622. case 15:
  623. /* Should distinguish Models here, but this is only
  624. a fallback anyways. */
  625. strcpy(c->x86_model_id, "Hammer");
  626. break;
  627. }
  628. }
  629. display_cacheinfo(c);
  630. /* Multi core CPU? */
  631. if (c->extended_cpuid_level >= 0x80000008)
  632. amd_detect_cmp(c);
  633. if (c->extended_cpuid_level >= 0x80000006 &&
  634. (cpuid_edx(0x80000006) & 0xf000))
  635. num_cache_leaves = 4;
  636. else
  637. num_cache_leaves = 3;
  638. if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
  639. set_cpu_cap(c, X86_FEATURE_K8);
  640. /* MFENCE stops RDTSC speculation */
  641. set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
  642. /* Family 10 doesn't support C states in MWAIT so don't use it */
  643. if (c->x86 == 0x10 && !force_mwait)
  644. clear_cpu_cap(c, X86_FEATURE_MWAIT);
  645. if (amd_apic_timer_broken())
  646. disable_apic_timer = 1;
  647. }
  648. void __cpuinit detect_ht(struct cpuinfo_x86 *c)
  649. {
  650. #ifdef CONFIG_SMP
  651. u32 eax, ebx, ecx, edx;
  652. int index_msb, core_bits;
  653. cpuid(1, &eax, &ebx, &ecx, &edx);
  654. if (!cpu_has(c, X86_FEATURE_HT))
  655. return;
  656. if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
  657. goto out;
  658. smp_num_siblings = (ebx & 0xff0000) >> 16;
  659. if (smp_num_siblings == 1) {
  660. printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
  661. } else if (smp_num_siblings > 1) {
  662. if (smp_num_siblings > NR_CPUS) {
  663. printk(KERN_WARNING "CPU: Unsupported number of "
  664. "siblings %d", smp_num_siblings);
  665. smp_num_siblings = 1;
  666. return;
  667. }
  668. index_msb = get_count_order(smp_num_siblings);
  669. c->phys_proc_id = phys_pkg_id(index_msb);
  670. smp_num_siblings = smp_num_siblings / c->x86_max_cores;
  671. index_msb = get_count_order(smp_num_siblings);
  672. core_bits = get_count_order(c->x86_max_cores);
  673. c->cpu_core_id = phys_pkg_id(index_msb) &
  674. ((1 << core_bits) - 1);
  675. }
  676. out:
  677. if ((c->x86_max_cores * smp_num_siblings) > 1) {
  678. printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
  679. c->phys_proc_id);
  680. printk(KERN_INFO "CPU: Processor Core ID: %d\n",
  681. c->cpu_core_id);
  682. }
  683. #endif
  684. }
  685. /*
  686. * find out the number of processor cores on the die
  687. */
  688. static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
  689. {
  690. unsigned int eax, t;
  691. if (c->cpuid_level < 4)
  692. return 1;
  693. cpuid_count(4, 0, &eax, &t, &t, &t);
  694. if (eax & 0x1f)
  695. return ((eax >> 26) + 1);
  696. else
  697. return 1;
  698. }
  699. static void srat_detect_node(void)
  700. {
  701. #ifdef CONFIG_NUMA
  702. unsigned node;
  703. int cpu = smp_processor_id();
  704. int apicid = hard_smp_processor_id();
  705. /* Don't do the funky fallback heuristics the AMD version employs
  706. for now. */
  707. node = apicid_to_node[apicid];
  708. if (node == NUMA_NO_NODE)
  709. node = first_node(node_online_map);
  710. numa_set_node(cpu, node);
  711. printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
  712. #endif
  713. }
  714. static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  715. {
  716. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  717. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  718. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  719. }
  720. static void __cpuinit init_intel(struct cpuinfo_x86 *c)
  721. {
  722. /* Cache sizes */
  723. unsigned n;
  724. init_intel_cacheinfo(c);
  725. if (c->cpuid_level > 9) {
  726. unsigned eax = cpuid_eax(10);
  727. /* Check for version and the number of counters */
  728. if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
  729. set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
  730. }
  731. if (cpu_has_ds) {
  732. unsigned int l1, l2;
  733. rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
  734. if (!(l1 & (1<<11)))
  735. set_cpu_cap(c, X86_FEATURE_BTS);
  736. if (!(l1 & (1<<12)))
  737. set_cpu_cap(c, X86_FEATURE_PEBS);
  738. }
  739. if (cpu_has_bts)
  740. ds_init_intel(c);
  741. n = c->extended_cpuid_level;
  742. if (n >= 0x80000008) {
  743. unsigned eax = cpuid_eax(0x80000008);
  744. c->x86_virt_bits = (eax >> 8) & 0xff;
  745. c->x86_phys_bits = eax & 0xff;
  746. /* CPUID workaround for Intel 0F34 CPU */
  747. if (c->x86_vendor == X86_VENDOR_INTEL &&
  748. c->x86 == 0xF && c->x86_model == 0x3 &&
  749. c->x86_mask == 0x4)
  750. c->x86_phys_bits = 36;
  751. }
  752. if (c->x86 == 15)
  753. c->x86_cache_alignment = c->x86_clflush_size * 2;
  754. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  755. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  756. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  757. if (c->x86 == 6)
  758. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  759. set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
  760. c->x86_max_cores = intel_num_cpu_cores(c);
  761. srat_detect_node();
  762. }
  763. static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
  764. {
  765. char *v = c->x86_vendor_id;
  766. if (!strcmp(v, "AuthenticAMD"))
  767. c->x86_vendor = X86_VENDOR_AMD;
  768. else if (!strcmp(v, "GenuineIntel"))
  769. c->x86_vendor = X86_VENDOR_INTEL;
  770. else
  771. c->x86_vendor = X86_VENDOR_UNKNOWN;
  772. }
  773. struct cpu_model_info {
  774. int vendor;
  775. int family;
  776. char *model_names[16];
  777. };
  778. /* Do some early cpuid on the boot CPU to get some parameter that are
  779. needed before check_bugs. Everything advanced is in identify_cpu
  780. below. */
  781. static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
  782. {
  783. u32 tfms, xlvl;
  784. c->loops_per_jiffy = loops_per_jiffy;
  785. c->x86_cache_size = -1;
  786. c->x86_vendor = X86_VENDOR_UNKNOWN;
  787. c->x86_model = c->x86_mask = 0; /* So far unknown... */
  788. c->x86_vendor_id[0] = '\0'; /* Unset */
  789. c->x86_model_id[0] = '\0'; /* Unset */
  790. c->x86_clflush_size = 64;
  791. c->x86_cache_alignment = c->x86_clflush_size;
  792. c->x86_max_cores = 1;
  793. c->x86_coreid_bits = 0;
  794. c->extended_cpuid_level = 0;
  795. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  796. /* Get vendor name */
  797. cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
  798. (unsigned int *)&c->x86_vendor_id[0],
  799. (unsigned int *)&c->x86_vendor_id[8],
  800. (unsigned int *)&c->x86_vendor_id[4]);
  801. get_cpu_vendor(c);
  802. /* Initialize the standard set of capabilities */
  803. /* Note that the vendor-specific code below might override */
  804. /* Intel-defined flags: level 0x00000001 */
  805. if (c->cpuid_level >= 0x00000001) {
  806. __u32 misc;
  807. cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
  808. &c->x86_capability[0]);
  809. c->x86 = (tfms >> 8) & 0xf;
  810. c->x86_model = (tfms >> 4) & 0xf;
  811. c->x86_mask = tfms & 0xf;
  812. if (c->x86 == 0xf)
  813. c->x86 += (tfms >> 20) & 0xff;
  814. if (c->x86 >= 0x6)
  815. c->x86_model += ((tfms >> 16) & 0xF) << 4;
  816. if (c->x86_capability[0] & (1<<19))
  817. c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
  818. } else {
  819. /* Have CPUID level 0 only - unheard of */
  820. c->x86 = 4;
  821. }
  822. #ifdef CONFIG_SMP
  823. c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
  824. #endif
  825. /* AMD-defined flags: level 0x80000001 */
  826. xlvl = cpuid_eax(0x80000000);
  827. c->extended_cpuid_level = xlvl;
  828. if ((xlvl & 0xffff0000) == 0x80000000) {
  829. if (xlvl >= 0x80000001) {
  830. c->x86_capability[1] = cpuid_edx(0x80000001);
  831. c->x86_capability[6] = cpuid_ecx(0x80000001);
  832. }
  833. if (xlvl >= 0x80000004)
  834. get_model_name(c); /* Default name */
  835. }
  836. /* Transmeta-defined flags: level 0x80860001 */
  837. xlvl = cpuid_eax(0x80860000);
  838. if ((xlvl & 0xffff0000) == 0x80860000) {
  839. /* Don't set x86_cpuid_level here for now to not confuse. */
  840. if (xlvl >= 0x80860001)
  841. c->x86_capability[2] = cpuid_edx(0x80860001);
  842. }
  843. c->extended_cpuid_level = cpuid_eax(0x80000000);
  844. if (c->extended_cpuid_level >= 0x80000007)
  845. c->x86_power = cpuid_edx(0x80000007);
  846. switch (c->x86_vendor) {
  847. case X86_VENDOR_AMD:
  848. early_init_amd(c);
  849. break;
  850. }
  851. }
  852. /*
  853. * This does the hard work of actually picking apart the CPU stuff...
  854. */
  855. void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
  856. {
  857. int i;
  858. early_identify_cpu(c);
  859. init_scattered_cpuid_features(c);
  860. c->apicid = phys_pkg_id(0);
  861. /*
  862. * Vendor-specific initialization. In this section we
  863. * canonicalize the feature flags, meaning if there are
  864. * features a certain CPU supports which CPUID doesn't
  865. * tell us, CPUID claiming incorrect flags, or other bugs,
  866. * we handle them here.
  867. *
  868. * At the end of this section, c->x86_capability better
  869. * indicate the features this CPU genuinely supports!
  870. */
  871. switch (c->x86_vendor) {
  872. case X86_VENDOR_AMD:
  873. init_amd(c);
  874. break;
  875. case X86_VENDOR_INTEL:
  876. init_intel(c);
  877. break;
  878. case X86_VENDOR_UNKNOWN:
  879. default:
  880. display_cacheinfo(c);
  881. break;
  882. }
  883. select_idle_routine(c);
  884. detect_ht(c);
  885. /*
  886. * On SMP, boot_cpu_data holds the common feature set between
  887. * all CPUs; so make sure that we indicate which features are
  888. * common between the CPUs. The first time this routine gets
  889. * executed, c == &boot_cpu_data.
  890. */
  891. if (c != &boot_cpu_data) {
  892. /* AND the already accumulated flags with these */
  893. for (i = 0; i < NCAPINTS; i++)
  894. boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
  895. }
  896. #ifdef CONFIG_X86_MCE
  897. mcheck_init(c);
  898. #endif
  899. if (c != &boot_cpu_data)
  900. mtrr_ap_init();
  901. #ifdef CONFIG_NUMA
  902. numa_add_cpu(smp_processor_id());
  903. #endif
  904. switch (c->x86_vendor) {
  905. case X86_VENDOR_AMD:
  906. early_init_amd(c);
  907. break;
  908. case X86_VENDOR_INTEL:
  909. early_init_intel(c);
  910. break;
  911. }
  912. }
  913. void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
  914. {
  915. if (c->x86_model_id[0])
  916. printk(KERN_INFO "%s", c->x86_model_id);
  917. if (c->x86_mask || c->cpuid_level >= 0)
  918. printk(KERN_CONT " stepping %02x\n", c->x86_mask);
  919. else
  920. printk(KERN_CONT "\n");
  921. }
  922. /*
  923. * Get CPU information for use by the procfs.
  924. */
  925. static int show_cpuinfo(struct seq_file *m, void *v)
  926. {
  927. struct cpuinfo_x86 *c = v;
  928. int cpu = 0, i;
  929. /*
  930. * These flag bits must match the definitions in <asm/cpufeature.h>.
  931. * NULL means this bit is undefined or reserved; either way it doesn't
  932. * have meaning as far as Linux is concerned. Note that it's important
  933. * to realize there is a difference between this table and CPUID -- if
  934. * applications want to get the raw CPUID data, they should access
  935. * /dev/cpu/<cpu_nr>/cpuid instead.
  936. */
  937. static const char *const x86_cap_flags[] = {
  938. /* Intel-defined */
  939. "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
  940. "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
  941. "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
  942. "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
  943. /* AMD-defined */
  944. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  945. NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
  946. NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
  947. NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
  948. "3dnowext", "3dnow",
  949. /* Transmeta-defined */
  950. "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
  951. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  952. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  953. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  954. /* Other (Linux-defined) */
  955. "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
  956. NULL, NULL, NULL, NULL,
  957. "constant_tsc", "up", NULL, "arch_perfmon",
  958. "pebs", "bts", NULL, "sync_rdtsc",
  959. "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  960. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  961. /* Intel-defined (#2) */
  962. "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
  963. "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
  964. NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
  965. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  966. /* VIA/Cyrix/Centaur-defined */
  967. NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
  968. "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
  969. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  970. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  971. /* AMD-defined (#2) */
  972. "lahf_lm", "cmp_legacy", "svm", "extapic",
  973. "cr8_legacy", "abm", "sse4a", "misalignsse",
  974. "3dnowprefetch", "osvw", "ibs", "sse5",
  975. "skinit", "wdt", NULL, NULL,
  976. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  977. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  978. /* Auxiliary (Linux-defined) */
  979. "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  980. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  981. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  982. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  983. };
  984. static const char *const x86_power_flags[] = {
  985. "ts", /* temperature sensor */
  986. "fid", /* frequency id control */
  987. "vid", /* voltage id control */
  988. "ttp", /* thermal trip */
  989. "tm",
  990. "stc",
  991. "100mhzsteps",
  992. "hwpstate",
  993. "", /* tsc invariant mapped to constant_tsc */
  994. /* nothing */
  995. };
  996. #ifdef CONFIG_SMP
  997. cpu = c->cpu_index;
  998. #endif
  999. seq_printf(m, "processor\t: %u\n"
  1000. "vendor_id\t: %s\n"
  1001. "cpu family\t: %d\n"
  1002. "model\t\t: %d\n"
  1003. "model name\t: %s\n",
  1004. (unsigned)cpu,
  1005. c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
  1006. c->x86,
  1007. (int)c->x86_model,
  1008. c->x86_model_id[0] ? c->x86_model_id : "unknown");
  1009. if (c->x86_mask || c->cpuid_level >= 0)
  1010. seq_printf(m, "stepping\t: %d\n", c->x86_mask);
  1011. else
  1012. seq_printf(m, "stepping\t: unknown\n");
  1013. if (cpu_has(c, X86_FEATURE_TSC)) {
  1014. unsigned int freq = cpufreq_quick_get((unsigned)cpu);
  1015. if (!freq)
  1016. freq = cpu_khz;
  1017. seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
  1018. freq / 1000, (freq % 1000));
  1019. }
  1020. /* Cache size */
  1021. if (c->x86_cache_size >= 0)
  1022. seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
  1023. #ifdef CONFIG_SMP
  1024. if (smp_num_siblings * c->x86_max_cores > 1) {
  1025. seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
  1026. seq_printf(m, "siblings\t: %d\n",
  1027. cpus_weight(per_cpu(cpu_core_map, cpu)));
  1028. seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
  1029. seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
  1030. }
  1031. #endif
  1032. seq_printf(m,
  1033. "fpu\t\t: yes\n"
  1034. "fpu_exception\t: yes\n"
  1035. "cpuid level\t: %d\n"
  1036. "wp\t\t: yes\n"
  1037. "flags\t\t:",
  1038. c->cpuid_level);
  1039. for (i = 0; i < 32*NCAPINTS; i++)
  1040. if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
  1041. seq_printf(m, " %s", x86_cap_flags[i]);
  1042. seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
  1043. c->loops_per_jiffy/(500000/HZ),
  1044. (c->loops_per_jiffy/(5000/HZ)) % 100);
  1045. if (c->x86_tlbsize > 0)
  1046. seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
  1047. seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
  1048. seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
  1049. seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
  1050. c->x86_phys_bits, c->x86_virt_bits);
  1051. seq_printf(m, "power management:");
  1052. for (i = 0; i < 32; i++) {
  1053. if (c->x86_power & (1 << i)) {
  1054. if (i < ARRAY_SIZE(x86_power_flags) &&
  1055. x86_power_flags[i])
  1056. seq_printf(m, "%s%s",
  1057. x86_power_flags[i][0]?" ":"",
  1058. x86_power_flags[i]);
  1059. else
  1060. seq_printf(m, " [%d]", i);
  1061. }
  1062. }
  1063. seq_printf(m, "\n\n");
  1064. return 0;
  1065. }
  1066. static void *c_start(struct seq_file *m, loff_t *pos)
  1067. {
  1068. if (*pos == 0) /* just in case, cpu 0 is not the first */
  1069. *pos = first_cpu(cpu_online_map);
  1070. if ((*pos) < NR_CPUS && cpu_online(*pos))
  1071. return &cpu_data(*pos);
  1072. return NULL;
  1073. }
  1074. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  1075. {
  1076. *pos = next_cpu(*pos, cpu_online_map);
  1077. return c_start(m, pos);
  1078. }
  1079. static void c_stop(struct seq_file *m, void *v)
  1080. {
  1081. }
  1082. struct seq_operations cpuinfo_op = {
  1083. .start = c_start,
  1084. .next = c_next,
  1085. .stop = c_stop,
  1086. .show = show_cpuinfo,
  1087. };