at91sam9g45.dtsi 21 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/dma/at91.h>
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. / {
  17. model = "Atmel AT91SAM9G45 family SoC";
  18. compatible = "atmel,at91sam9g45";
  19. interrupt-parent = <&aic>;
  20. aliases {
  21. serial0 = &dbgu;
  22. serial1 = &usart0;
  23. serial2 = &usart1;
  24. serial3 = &usart2;
  25. serial4 = &usart3;
  26. gpio0 = &pioA;
  27. gpio1 = &pioB;
  28. gpio2 = &pioC;
  29. gpio3 = &pioD;
  30. gpio4 = &pioE;
  31. tcb0 = &tcb0;
  32. tcb1 = &tcb1;
  33. i2c0 = &i2c0;
  34. i2c1 = &i2c1;
  35. ssc0 = &ssc0;
  36. ssc1 = &ssc1;
  37. };
  38. cpus {
  39. cpu@0 {
  40. compatible = "arm,arm926ejs";
  41. };
  42. };
  43. memory {
  44. reg = <0x70000000 0x10000000>;
  45. };
  46. ahb {
  47. compatible = "simple-bus";
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. ranges;
  51. apb {
  52. compatible = "simple-bus";
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55. ranges;
  56. aic: interrupt-controller@fffff000 {
  57. #interrupt-cells = <3>;
  58. compatible = "atmel,at91rm9200-aic";
  59. interrupt-controller;
  60. reg = <0xfffff000 0x200>;
  61. atmel,external-irqs = <31>;
  62. };
  63. ramc0: ramc@ffffe400 {
  64. compatible = "atmel,at91sam9g45-ddramc";
  65. reg = <0xffffe400 0x200
  66. 0xffffe600 0x200>;
  67. };
  68. pmc: pmc@fffffc00 {
  69. compatible = "atmel,at91rm9200-pmc";
  70. reg = <0xfffffc00 0x100>;
  71. };
  72. rstc@fffffd00 {
  73. compatible = "atmel,at91sam9g45-rstc";
  74. reg = <0xfffffd00 0x10>;
  75. };
  76. pit: timer@fffffd30 {
  77. compatible = "atmel,at91sam9260-pit";
  78. reg = <0xfffffd30 0xf>;
  79. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  80. };
  81. shdwc@fffffd10 {
  82. compatible = "atmel,at91sam9rl-shdwc";
  83. reg = <0xfffffd10 0x10>;
  84. };
  85. tcb0: timer@fff7c000 {
  86. compatible = "atmel,at91rm9200-tcb";
  87. reg = <0xfff7c000 0x100>;
  88. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  89. };
  90. tcb1: timer@fffd4000 {
  91. compatible = "atmel,at91rm9200-tcb";
  92. reg = <0xfffd4000 0x100>;
  93. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  94. };
  95. dma: dma-controller@ffffec00 {
  96. compatible = "atmel,at91sam9g45-dma";
  97. reg = <0xffffec00 0x200>;
  98. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  99. #dma-cells = <2>;
  100. };
  101. pinctrl@fffff200 {
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  105. ranges = <0xfffff200 0xfffff200 0xa00>;
  106. atmel,mux-mask = <
  107. /* A B */
  108. 0xffffffff 0xffc003ff /* pioA */
  109. 0xffffffff 0x800f8f00 /* pioB */
  110. 0xffffffff 0x00000e00 /* pioC */
  111. 0xffffffff 0xff0c1381 /* pioD */
  112. 0xffffffff 0x81ffff81 /* pioE */
  113. >;
  114. /* shared pinctrl settings */
  115. dbgu {
  116. pinctrl_dbgu: dbgu-0 {
  117. atmel,pins =
  118. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  119. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  120. };
  121. };
  122. usart0 {
  123. pinctrl_usart0: usart0-0 {
  124. atmel,pins =
  125. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
  126. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  127. };
  128. pinctrl_usart0_rts: usart0_rts-0 {
  129. atmel,pins =
  130. <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
  131. };
  132. pinctrl_usart0_cts: usart0_cts-0 {
  133. atmel,pins =
  134. <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
  135. };
  136. };
  137. uart1 {
  138. pinctrl_usart1: usart1-0 {
  139. atmel,pins =
  140. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
  141. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  142. };
  143. pinctrl_usart1_rts: usart1_rts-0 {
  144. atmel,pins =
  145. <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
  146. };
  147. pinctrl_usart1_cts: usart1_cts-0 {
  148. atmel,pins =
  149. <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
  150. };
  151. };
  152. usart2 {
  153. pinctrl_usart2: usart2-0 {
  154. atmel,pins =
  155. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  156. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  157. };
  158. pinctrl_usart2_rts: usart2_rts-0 {
  159. atmel,pins =
  160. <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
  161. };
  162. pinctrl_usart2_cts: usart2_cts-0 {
  163. atmel,pins =
  164. <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
  165. };
  166. };
  167. usart3 {
  168. pinctrl_usart3: usart3-0 {
  169. atmel,pins =
  170. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
  171. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  172. };
  173. pinctrl_usart3_rts: usart3_rts-0 {
  174. atmel,pins =
  175. <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
  176. };
  177. pinctrl_usart3_cts: usart3_cts-0 {
  178. atmel,pins =
  179. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
  180. };
  181. };
  182. nand {
  183. pinctrl_nand: nand-0 {
  184. atmel,pins =
  185. <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
  186. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  187. };
  188. };
  189. macb {
  190. pinctrl_macb_rmii: macb_rmii-0 {
  191. atmel,pins =
  192. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  193. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  194. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  195. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  196. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  197. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  198. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  199. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  200. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  201. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
  202. };
  203. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  204. atmel,pins =
  205. <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
  206. AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
  207. AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
  208. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
  209. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  210. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  211. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
  212. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  213. };
  214. };
  215. mmc0 {
  216. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  217. atmel,pins =
  218. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
  219. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  220. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
  221. };
  222. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  223. atmel,pins =
  224. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  225. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  226. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  227. };
  228. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  229. atmel,pins =
  230. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  231. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  232. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  233. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
  234. };
  235. };
  236. mmc1 {
  237. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  238. atmel,pins =
  239. <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
  240. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
  241. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  242. };
  243. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  244. atmel,pins =
  245. <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  246. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
  247. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
  248. };
  249. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  250. atmel,pins =
  251. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
  252. AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  253. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
  254. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
  255. };
  256. };
  257. ssc0 {
  258. pinctrl_ssc0_tx: ssc0_tx-0 {
  259. atmel,pins =
  260. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
  261. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
  262. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
  263. };
  264. pinctrl_ssc0_rx: ssc0_rx-0 {
  265. atmel,pins =
  266. <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
  267. AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
  268. AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
  269. };
  270. };
  271. ssc1 {
  272. pinctrl_ssc1_tx: ssc1_tx-0 {
  273. atmel,pins =
  274. <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
  275. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
  276. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
  277. };
  278. pinctrl_ssc1_rx: ssc1_rx-0 {
  279. atmel,pins =
  280. <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
  281. AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
  282. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
  283. };
  284. };
  285. spi0 {
  286. pinctrl_spi0: spi0-0 {
  287. atmel,pins =
  288. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
  289. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
  290. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
  291. };
  292. };
  293. spi1 {
  294. pinctrl_spi1: spi1-0 {
  295. atmel,pins =
  296. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
  297. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
  298. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
  299. };
  300. };
  301. tcb0 {
  302. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  303. atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  304. };
  305. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  306. atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  307. };
  308. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  309. atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  310. };
  311. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  312. atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  313. };
  314. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  315. atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  316. };
  317. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  318. atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  319. };
  320. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  321. atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  322. };
  323. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  324. atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  325. };
  326. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  327. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  328. };
  329. };
  330. tcb1 {
  331. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  332. atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  333. };
  334. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  335. atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  336. };
  337. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  338. atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  339. };
  340. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  341. atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  342. };
  343. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  344. atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  345. };
  346. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  347. atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  348. };
  349. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  350. atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  351. };
  352. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  353. atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  354. };
  355. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  356. atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  357. };
  358. };
  359. pioA: gpio@fffff200 {
  360. compatible = "atmel,at91rm9200-gpio";
  361. reg = <0xfffff200 0x200>;
  362. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  363. #gpio-cells = <2>;
  364. gpio-controller;
  365. interrupt-controller;
  366. #interrupt-cells = <2>;
  367. };
  368. pioB: gpio@fffff400 {
  369. compatible = "atmel,at91rm9200-gpio";
  370. reg = <0xfffff400 0x200>;
  371. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  372. #gpio-cells = <2>;
  373. gpio-controller;
  374. interrupt-controller;
  375. #interrupt-cells = <2>;
  376. };
  377. pioC: gpio@fffff600 {
  378. compatible = "atmel,at91rm9200-gpio";
  379. reg = <0xfffff600 0x200>;
  380. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  381. #gpio-cells = <2>;
  382. gpio-controller;
  383. interrupt-controller;
  384. #interrupt-cells = <2>;
  385. };
  386. pioD: gpio@fffff800 {
  387. compatible = "atmel,at91rm9200-gpio";
  388. reg = <0xfffff800 0x200>;
  389. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  390. #gpio-cells = <2>;
  391. gpio-controller;
  392. interrupt-controller;
  393. #interrupt-cells = <2>;
  394. };
  395. pioE: gpio@fffffa00 {
  396. compatible = "atmel,at91rm9200-gpio";
  397. reg = <0xfffffa00 0x200>;
  398. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  399. #gpio-cells = <2>;
  400. gpio-controller;
  401. interrupt-controller;
  402. #interrupt-cells = <2>;
  403. };
  404. };
  405. dbgu: serial@ffffee00 {
  406. compatible = "atmel,at91sam9260-usart";
  407. reg = <0xffffee00 0x200>;
  408. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  409. pinctrl-names = "default";
  410. pinctrl-0 = <&pinctrl_dbgu>;
  411. status = "disabled";
  412. };
  413. usart0: serial@fff8c000 {
  414. compatible = "atmel,at91sam9260-usart";
  415. reg = <0xfff8c000 0x200>;
  416. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  417. atmel,use-dma-rx;
  418. atmel,use-dma-tx;
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&pinctrl_usart0>;
  421. status = "disabled";
  422. };
  423. usart1: serial@fff90000 {
  424. compatible = "atmel,at91sam9260-usart";
  425. reg = <0xfff90000 0x200>;
  426. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  427. atmel,use-dma-rx;
  428. atmel,use-dma-tx;
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&pinctrl_usart1>;
  431. status = "disabled";
  432. };
  433. usart2: serial@fff94000 {
  434. compatible = "atmel,at91sam9260-usart";
  435. reg = <0xfff94000 0x200>;
  436. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  437. atmel,use-dma-rx;
  438. atmel,use-dma-tx;
  439. pinctrl-names = "default";
  440. pinctrl-0 = <&pinctrl_usart2>;
  441. status = "disabled";
  442. };
  443. usart3: serial@fff98000 {
  444. compatible = "atmel,at91sam9260-usart";
  445. reg = <0xfff98000 0x200>;
  446. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
  447. atmel,use-dma-rx;
  448. atmel,use-dma-tx;
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&pinctrl_usart3>;
  451. status = "disabled";
  452. };
  453. macb0: ethernet@fffbc000 {
  454. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  455. reg = <0xfffbc000 0x100>;
  456. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
  457. pinctrl-names = "default";
  458. pinctrl-0 = <&pinctrl_macb_rmii>;
  459. status = "disabled";
  460. };
  461. i2c0: i2c@fff84000 {
  462. compatible = "atmel,at91sam9g10-i2c";
  463. reg = <0xfff84000 0x100>;
  464. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
  465. #address-cells = <1>;
  466. #size-cells = <0>;
  467. status = "disabled";
  468. };
  469. i2c1: i2c@fff88000 {
  470. compatible = "atmel,at91sam9g10-i2c";
  471. reg = <0xfff88000 0x100>;
  472. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
  473. #address-cells = <1>;
  474. #size-cells = <0>;
  475. status = "disabled";
  476. };
  477. ssc0: ssc@fff9c000 {
  478. compatible = "atmel,at91sam9g45-ssc";
  479. reg = <0xfff9c000 0x4000>;
  480. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  481. pinctrl-names = "default";
  482. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  483. status = "disabled";
  484. };
  485. ssc1: ssc@fffa0000 {
  486. compatible = "atmel,at91sam9g45-ssc";
  487. reg = <0xfffa0000 0x4000>;
  488. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  491. status = "disabled";
  492. };
  493. adc0: adc@fffb0000 {
  494. compatible = "atmel,at91sam9260-adc";
  495. reg = <0xfffb0000 0x100>;
  496. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  497. atmel,adc-use-external-triggers;
  498. atmel,adc-channels-used = <0xff>;
  499. atmel,adc-vref = <3300>;
  500. atmel,adc-num-channels = <8>;
  501. atmel,adc-startup-time = <40>;
  502. atmel,adc-channel-base = <0x30>;
  503. atmel,adc-drdy-mask = <0x10000>;
  504. atmel,adc-status-register = <0x1c>;
  505. atmel,adc-trigger-register = <0x08>;
  506. atmel,adc-res = <8 10>;
  507. atmel,adc-res-names = "lowres", "highres";
  508. atmel,adc-use-res = "highres";
  509. trigger@0 {
  510. trigger-name = "external-rising";
  511. trigger-value = <0x1>;
  512. trigger-external;
  513. };
  514. trigger@1 {
  515. trigger-name = "external-falling";
  516. trigger-value = <0x2>;
  517. trigger-external;
  518. };
  519. trigger@2 {
  520. trigger-name = "external-any";
  521. trigger-value = <0x3>;
  522. trigger-external;
  523. };
  524. trigger@3 {
  525. trigger-name = "continuous";
  526. trigger-value = <0x6>;
  527. };
  528. };
  529. mmc0: mmc@fff80000 {
  530. compatible = "atmel,hsmci";
  531. reg = <0xfff80000 0x600>;
  532. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  533. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
  534. dma-names = "rxtx";
  535. #address-cells = <1>;
  536. #size-cells = <0>;
  537. status = "disabled";
  538. };
  539. mmc1: mmc@fffd0000 {
  540. compatible = "atmel,hsmci";
  541. reg = <0xfffd0000 0x600>;
  542. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
  543. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
  544. dma-names = "rxtx";
  545. #address-cells = <1>;
  546. #size-cells = <0>;
  547. status = "disabled";
  548. };
  549. watchdog@fffffd40 {
  550. compatible = "atmel,at91sam9260-wdt";
  551. reg = <0xfffffd40 0x10>;
  552. status = "disabled";
  553. };
  554. spi0: spi@fffa4000 {
  555. #address-cells = <1>;
  556. #size-cells = <0>;
  557. compatible = "atmel,at91rm9200-spi";
  558. reg = <0xfffa4000 0x200>;
  559. interrupts = <14 4 3>;
  560. pinctrl-names = "default";
  561. pinctrl-0 = <&pinctrl_spi0>;
  562. status = "disabled";
  563. };
  564. spi1: spi@fffa8000 {
  565. #address-cells = <1>;
  566. #size-cells = <0>;
  567. compatible = "atmel,at91rm9200-spi";
  568. reg = <0xfffa8000 0x200>;
  569. interrupts = <15 4 3>;
  570. pinctrl-names = "default";
  571. pinctrl-0 = <&pinctrl_spi1>;
  572. status = "disabled";
  573. };
  574. usb2: gadget@fff78000 {
  575. #address-cells = <1>;
  576. #size-cells = <0>;
  577. compatible = "atmel,at91sam9rl-udc";
  578. reg = <0x00600000 0x80000
  579. 0xfff78000 0x400>;
  580. interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
  581. status = "disabled";
  582. ep0 {
  583. reg = <0>;
  584. atmel,fifo-size = <64>;
  585. atmel,nb-banks = <1>;
  586. };
  587. ep1 {
  588. reg = <1>;
  589. atmel,fifo-size = <1024>;
  590. atmel,nb-banks = <2>;
  591. atmel,can-dma;
  592. atmel,can-isoc;
  593. };
  594. ep2 {
  595. reg = <2>;
  596. atmel,fifo-size = <1024>;
  597. atmel,nb-banks = <2>;
  598. atmel,can-dma;
  599. atmel,can-isoc;
  600. };
  601. ep3 {
  602. reg = <3>;
  603. atmel,fifo-size = <1024>;
  604. atmel,nb-banks = <3>;
  605. atmel,can-dma;
  606. };
  607. ep4 {
  608. reg = <4>;
  609. atmel,fifo-size = <1024>;
  610. atmel,nb-banks = <3>;
  611. atmel,can-dma;
  612. };
  613. ep5 {
  614. reg = <5>;
  615. atmel,fifo-size = <1024>;
  616. atmel,nb-banks = <3>;
  617. atmel,can-dma;
  618. atmel,can-isoc;
  619. };
  620. ep6 {
  621. reg = <6>;
  622. atmel,fifo-size = <1024>;
  623. atmel,nb-banks = <3>;
  624. atmel,can-dma;
  625. atmel,can-isoc;
  626. };
  627. };
  628. };
  629. nand0: nand@40000000 {
  630. compatible = "atmel,at91rm9200-nand";
  631. #address-cells = <1>;
  632. #size-cells = <1>;
  633. reg = <0x40000000 0x10000000
  634. 0xffffe200 0x200
  635. >;
  636. atmel,nand-addr-offset = <21>;
  637. atmel,nand-cmd-offset = <22>;
  638. pinctrl-names = "default";
  639. pinctrl-0 = <&pinctrl_nand>;
  640. gpios = <&pioC 8 GPIO_ACTIVE_HIGH
  641. &pioC 14 GPIO_ACTIVE_HIGH
  642. 0
  643. >;
  644. status = "disabled";
  645. };
  646. usb0: ohci@00700000 {
  647. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  648. reg = <0x00700000 0x100000>;
  649. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  650. status = "disabled";
  651. };
  652. usb1: ehci@00800000 {
  653. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  654. reg = <0x00800000 0x100000>;
  655. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  656. status = "disabled";
  657. };
  658. };
  659. i2c@0 {
  660. compatible = "i2c-gpio";
  661. gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
  662. &pioA 21 GPIO_ACTIVE_HIGH /* scl */
  663. >;
  664. i2c-gpio,sda-open-drain;
  665. i2c-gpio,scl-open-drain;
  666. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  667. #address-cells = <1>;
  668. #size-cells = <0>;
  669. status = "disabled";
  670. };
  671. };