ptrace.c 17 KB

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  1. /*
  2. * PowerPC version
  3. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  4. *
  5. * Derived from "arch/m68k/kernel/ptrace.c"
  6. * Copyright (C) 1994 by Hamish Macdonald
  7. * Taken from linux/kernel/ptrace.c and modified for M680x0.
  8. * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
  9. *
  10. * Modified by Cort Dougan (cort@hq.fsmlabs.com)
  11. * and Paul Mackerras (paulus@samba.org).
  12. *
  13. * This file is subject to the terms and conditions of the GNU General
  14. * Public License. See the file README.legal in the main directory of
  15. * this archive for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/sched.h>
  19. #include <linux/mm.h>
  20. #include <linux/smp.h>
  21. #include <linux/errno.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/regset.h>
  24. #include <linux/elf.h>
  25. #include <linux/user.h>
  26. #include <linux/security.h>
  27. #include <linux/signal.h>
  28. #include <linux/seccomp.h>
  29. #include <linux/audit.h>
  30. #ifdef CONFIG_PPC32
  31. #include <linux/module.h>
  32. #endif
  33. #include <asm/uaccess.h>
  34. #include <asm/page.h>
  35. #include <asm/pgtable.h>
  36. #include <asm/system.h>
  37. /*
  38. * does not yet catch signals sent when the child dies.
  39. * in exit.c or in signal.c.
  40. */
  41. /*
  42. * Set of msr bits that gdb can change on behalf of a process.
  43. */
  44. #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
  45. #define MSR_DEBUGCHANGE 0
  46. #else
  47. #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
  48. #endif
  49. /*
  50. * Max register writeable via put_reg
  51. */
  52. #ifdef CONFIG_PPC32
  53. #define PT_MAX_PUT_REG PT_MQ
  54. #else
  55. #define PT_MAX_PUT_REG PT_CCR
  56. #endif
  57. /*
  58. * Get contents of register REGNO in task TASK.
  59. */
  60. unsigned long ptrace_get_reg(struct task_struct *task, int regno)
  61. {
  62. unsigned long tmp = 0;
  63. if (task->thread.regs == NULL)
  64. return -EIO;
  65. if (regno == PT_MSR) {
  66. tmp = ((unsigned long *)task->thread.regs)[PT_MSR];
  67. return tmp | task->thread.fpexc_mode;
  68. }
  69. if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
  70. return ((unsigned long *)task->thread.regs)[regno];
  71. return -EIO;
  72. }
  73. /*
  74. * Write contents of register REGNO in task TASK.
  75. */
  76. int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
  77. {
  78. if (task->thread.regs == NULL)
  79. return -EIO;
  80. if (regno <= PT_MAX_PUT_REG || regno == PT_TRAP) {
  81. if (regno == PT_MSR)
  82. data = (data & MSR_DEBUGCHANGE)
  83. | (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
  84. /* We prevent mucking around with the reserved area of trap
  85. * which are used internally by the kernel
  86. */
  87. if (regno == PT_TRAP)
  88. data &= 0xfff0;
  89. ((unsigned long *)task->thread.regs)[regno] = data;
  90. return 0;
  91. }
  92. return -EIO;
  93. }
  94. static int fpr_get(struct task_struct *target, const struct user_regset *regset,
  95. unsigned int pos, unsigned int count,
  96. void *kbuf, void __user *ubuf)
  97. {
  98. flush_fp_to_thread(target);
  99. BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
  100. offsetof(struct thread_struct, fpr[32]));
  101. return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  102. &target->thread.fpr, 0, -1);
  103. }
  104. static int fpr_set(struct task_struct *target, const struct user_regset *regset,
  105. unsigned int pos, unsigned int count,
  106. const void *kbuf, const void __user *ubuf)
  107. {
  108. flush_fp_to_thread(target);
  109. BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
  110. offsetof(struct thread_struct, fpr[32]));
  111. return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  112. &target->thread.fpr, 0, -1);
  113. }
  114. static int get_fpregs(void __user *data, struct task_struct *task,
  115. int has_fpscr)
  116. {
  117. unsigned int count = has_fpscr ? 33 : 32;
  118. if (!access_ok(VERIFY_WRITE, data, count * sizeof(double)))
  119. return -EFAULT;
  120. return fpr_get(task, NULL, 0, count * sizeof(double), NULL, data);
  121. }
  122. static int set_fpregs(void __user *data, struct task_struct *task,
  123. int has_fpscr)
  124. {
  125. unsigned int count = has_fpscr ? 33 : 32;
  126. if (!access_ok(VERIFY_READ, data, count * sizeof(double)))
  127. return -EFAULT;
  128. return fpr_set(task, NULL, 0, count * sizeof(double), NULL, data);
  129. }
  130. #ifdef CONFIG_ALTIVEC
  131. /*
  132. * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
  133. * The transfer totals 34 quadword. Quadwords 0-31 contain the
  134. * corresponding vector registers. Quadword 32 contains the vscr as the
  135. * last word (offset 12) within that quadword. Quadword 33 contains the
  136. * vrsave as the first word (offset 0) within the quadword.
  137. *
  138. * This definition of the VMX state is compatible with the current PPC32
  139. * ptrace interface. This allows signal handling and ptrace to use the
  140. * same structures. This also simplifies the implementation of a bi-arch
  141. * (combined (32- and 64-bit) gdb.
  142. */
  143. static int vr_active(struct task_struct *target,
  144. const struct user_regset *regset)
  145. {
  146. flush_altivec_to_thread(target);
  147. return target->thread.used_vr ? regset->n : 0;
  148. }
  149. static int vr_get(struct task_struct *target, const struct user_regset *regset,
  150. unsigned int pos, unsigned int count,
  151. void *kbuf, void __user *ubuf)
  152. {
  153. int ret;
  154. flush_altivec_to_thread(target);
  155. BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
  156. offsetof(struct thread_struct, vr[32]));
  157. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
  158. &target->thread.vr, 0,
  159. 33 * sizeof(vector128));
  160. if (!ret) {
  161. /*
  162. * Copy out only the low-order word of vrsave.
  163. */
  164. union {
  165. elf_vrreg_t reg;
  166. u32 word;
  167. } vrsave;
  168. memset(&vrsave, 0, sizeof(vrsave));
  169. vrsave.word = target->thread.vrsave;
  170. ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
  171. 33 * sizeof(vector128), -1);
  172. }
  173. return ret;
  174. }
  175. static int vr_set(struct task_struct *target, const struct user_regset *regset,
  176. unsigned int pos, unsigned int count,
  177. const void *kbuf, const void __user *ubuf)
  178. {
  179. int ret;
  180. flush_altivec_to_thread(target);
  181. BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
  182. offsetof(struct thread_struct, vr[32]));
  183. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
  184. &target->thread.vr, 0, 33 * sizeof(vector128));
  185. if (!ret && count > 0) {
  186. /*
  187. * We use only the first word of vrsave.
  188. */
  189. union {
  190. elf_vrreg_t reg;
  191. u32 word;
  192. } vrsave;
  193. memset(&vrsave, 0, sizeof(vrsave));
  194. vrsave.word = target->thread.vrsave;
  195. ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
  196. 33 * sizeof(vector128), -1);
  197. if (!ret)
  198. target->thread.vrsave = vrsave.word;
  199. }
  200. return ret;
  201. }
  202. /*
  203. * Get contents of AltiVec register state in task TASK
  204. */
  205. static int get_vrregs(unsigned long __user *data, struct task_struct *task)
  206. {
  207. if (!access_ok(VERIFY_WRITE, data,
  208. 33 * sizeof(vector128) + sizeof(u32)))
  209. return -EFAULT;
  210. return vr_get(task, NULL, 0, 33 * sizeof(vector128) + sizeof(u32),
  211. NULL, data);
  212. }
  213. /*
  214. * Write contents of AltiVec register state into task TASK.
  215. */
  216. static int set_vrregs(struct task_struct *task, unsigned long __user *data)
  217. {
  218. if (!access_ok(VERIFY_READ, data, 33 * sizeof(vector128) + sizeof(u32)))
  219. return -EFAULT;
  220. return vr_set(task, NULL, 0, 33 * sizeof(vector128) + sizeof(u32),
  221. NULL, data);
  222. }
  223. #endif /* CONFIG_ALTIVEC */
  224. #ifdef CONFIG_SPE
  225. /*
  226. * For get_evrregs/set_evrregs functions 'data' has the following layout:
  227. *
  228. * struct {
  229. * u32 evr[32];
  230. * u64 acc;
  231. * u32 spefscr;
  232. * }
  233. */
  234. /*
  235. * Get contents of SPE register state in task TASK.
  236. */
  237. static int get_evrregs(unsigned long *data, struct task_struct *task)
  238. {
  239. int i;
  240. if (!access_ok(VERIFY_WRITE, data, 35 * sizeof(unsigned long)))
  241. return -EFAULT;
  242. /* copy SPEFSCR */
  243. if (__put_user(task->thread.spefscr, &data[34]))
  244. return -EFAULT;
  245. /* copy SPE registers EVR[0] .. EVR[31] */
  246. for (i = 0; i < 32; i++, data++)
  247. if (__put_user(task->thread.evr[i], data))
  248. return -EFAULT;
  249. /* copy ACC */
  250. if (__put_user64(task->thread.acc, (unsigned long long *)data))
  251. return -EFAULT;
  252. return 0;
  253. }
  254. /*
  255. * Write contents of SPE register state into task TASK.
  256. */
  257. static int set_evrregs(struct task_struct *task, unsigned long *data)
  258. {
  259. int i;
  260. if (!access_ok(VERIFY_READ, data, 35 * sizeof(unsigned long)))
  261. return -EFAULT;
  262. /* copy SPEFSCR */
  263. if (__get_user(task->thread.spefscr, &data[34]))
  264. return -EFAULT;
  265. /* copy SPE registers EVR[0] .. EVR[31] */
  266. for (i = 0; i < 32; i++, data++)
  267. if (__get_user(task->thread.evr[i], data))
  268. return -EFAULT;
  269. /* copy ACC */
  270. if (__get_user64(task->thread.acc, (unsigned long long*)data))
  271. return -EFAULT;
  272. return 0;
  273. }
  274. #endif /* CONFIG_SPE */
  275. void user_enable_single_step(struct task_struct *task)
  276. {
  277. struct pt_regs *regs = task->thread.regs;
  278. if (regs != NULL) {
  279. #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
  280. task->thread.dbcr0 = DBCR0_IDM | DBCR0_IC;
  281. regs->msr |= MSR_DE;
  282. #else
  283. regs->msr |= MSR_SE;
  284. #endif
  285. }
  286. set_tsk_thread_flag(task, TIF_SINGLESTEP);
  287. }
  288. void user_disable_single_step(struct task_struct *task)
  289. {
  290. struct pt_regs *regs = task->thread.regs;
  291. if (regs != NULL) {
  292. #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
  293. task->thread.dbcr0 = 0;
  294. regs->msr &= ~MSR_DE;
  295. #else
  296. regs->msr &= ~MSR_SE;
  297. #endif
  298. }
  299. clear_tsk_thread_flag(task, TIF_SINGLESTEP);
  300. }
  301. static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
  302. unsigned long data)
  303. {
  304. /* We only support one DABR and no IABRS at the moment */
  305. if (addr > 0)
  306. return -EINVAL;
  307. /* The bottom 3 bits are flags */
  308. if ((data & ~0x7UL) >= TASK_SIZE)
  309. return -EIO;
  310. /* Ensure translation is on */
  311. if (data && !(data & DABR_TRANSLATION))
  312. return -EIO;
  313. task->thread.dabr = data;
  314. return 0;
  315. }
  316. /*
  317. * Called by kernel/ptrace.c when detaching..
  318. *
  319. * Make sure single step bits etc are not set.
  320. */
  321. void ptrace_disable(struct task_struct *child)
  322. {
  323. /* make sure the single step bit is not set. */
  324. user_disable_single_step(child);
  325. }
  326. /*
  327. * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
  328. * we mark them as obsolete now, they will be removed in a future version
  329. */
  330. static long arch_ptrace_old(struct task_struct *child, long request, long addr,
  331. long data)
  332. {
  333. int ret = -EPERM;
  334. switch(request) {
  335. case PPC_PTRACE_GETREGS: { /* Get GPRs 0 - 31. */
  336. int i;
  337. unsigned long *reg = &((unsigned long *)child->thread.regs)[0];
  338. unsigned long __user *tmp = (unsigned long __user *)addr;
  339. CHECK_FULL_REGS(child->thread.regs);
  340. for (i = 0; i < 32; i++) {
  341. ret = put_user(*reg, tmp);
  342. if (ret)
  343. break;
  344. reg++;
  345. tmp++;
  346. }
  347. break;
  348. }
  349. case PPC_PTRACE_SETREGS: { /* Set GPRs 0 - 31. */
  350. int i;
  351. unsigned long *reg = &((unsigned long *)child->thread.regs)[0];
  352. unsigned long __user *tmp = (unsigned long __user *)addr;
  353. CHECK_FULL_REGS(child->thread.regs);
  354. for (i = 0; i < 32; i++) {
  355. ret = get_user(*reg, tmp);
  356. if (ret)
  357. break;
  358. reg++;
  359. tmp++;
  360. }
  361. break;
  362. }
  363. case PPC_PTRACE_GETFPREGS: { /* Get FPRs 0 - 31. */
  364. flush_fp_to_thread(child);
  365. ret = get_fpregs((void __user *)addr, child, 0);
  366. break;
  367. }
  368. case PPC_PTRACE_SETFPREGS: { /* Get FPRs 0 - 31. */
  369. flush_fp_to_thread(child);
  370. ret = set_fpregs((void __user *)addr, child, 0);
  371. break;
  372. }
  373. }
  374. return ret;
  375. }
  376. long arch_ptrace(struct task_struct *child, long request, long addr, long data)
  377. {
  378. int ret = -EPERM;
  379. switch (request) {
  380. /* when I and D space are separate, these will need to be fixed. */
  381. case PTRACE_PEEKTEXT: /* read word at location addr. */
  382. case PTRACE_PEEKDATA:
  383. ret = generic_ptrace_peekdata(child, addr, data);
  384. break;
  385. /* read the word at location addr in the USER area. */
  386. case PTRACE_PEEKUSR: {
  387. unsigned long index, tmp;
  388. ret = -EIO;
  389. /* convert to index and check */
  390. #ifdef CONFIG_PPC32
  391. index = (unsigned long) addr >> 2;
  392. if ((addr & 3) || (index > PT_FPSCR)
  393. || (child->thread.regs == NULL))
  394. #else
  395. index = (unsigned long) addr >> 3;
  396. if ((addr & 7) || (index > PT_FPSCR))
  397. #endif
  398. break;
  399. CHECK_FULL_REGS(child->thread.regs);
  400. if (index < PT_FPR0) {
  401. tmp = ptrace_get_reg(child, (int) index);
  402. } else {
  403. flush_fp_to_thread(child);
  404. tmp = ((unsigned long *)child->thread.fpr)[index - PT_FPR0];
  405. }
  406. ret = put_user(tmp,(unsigned long __user *) data);
  407. break;
  408. }
  409. /* If I and D space are separate, this will have to be fixed. */
  410. case PTRACE_POKETEXT: /* write the word at location addr. */
  411. case PTRACE_POKEDATA:
  412. ret = generic_ptrace_pokedata(child, addr, data);
  413. break;
  414. /* write the word at location addr in the USER area */
  415. case PTRACE_POKEUSR: {
  416. unsigned long index;
  417. ret = -EIO;
  418. /* convert to index and check */
  419. #ifdef CONFIG_PPC32
  420. index = (unsigned long) addr >> 2;
  421. if ((addr & 3) || (index > PT_FPSCR)
  422. || (child->thread.regs == NULL))
  423. #else
  424. index = (unsigned long) addr >> 3;
  425. if ((addr & 7) || (index > PT_FPSCR))
  426. #endif
  427. break;
  428. CHECK_FULL_REGS(child->thread.regs);
  429. if (index < PT_FPR0) {
  430. ret = ptrace_put_reg(child, index, data);
  431. } else {
  432. flush_fp_to_thread(child);
  433. ((unsigned long *)child->thread.fpr)[index - PT_FPR0] = data;
  434. ret = 0;
  435. }
  436. break;
  437. }
  438. case PTRACE_GET_DEBUGREG: {
  439. ret = -EINVAL;
  440. /* We only support one DABR and no IABRS at the moment */
  441. if (addr > 0)
  442. break;
  443. ret = put_user(child->thread.dabr,
  444. (unsigned long __user *)data);
  445. break;
  446. }
  447. case PTRACE_SET_DEBUGREG:
  448. ret = ptrace_set_debugreg(child, addr, data);
  449. break;
  450. #ifdef CONFIG_PPC64
  451. case PTRACE_GETREGS64:
  452. #endif
  453. case PTRACE_GETREGS: { /* Get all pt_regs from the child. */
  454. int ui;
  455. if (!access_ok(VERIFY_WRITE, (void __user *)data,
  456. sizeof(struct pt_regs))) {
  457. ret = -EIO;
  458. break;
  459. }
  460. CHECK_FULL_REGS(child->thread.regs);
  461. ret = 0;
  462. for (ui = 0; ui < PT_REGS_COUNT; ui ++) {
  463. ret |= __put_user(ptrace_get_reg(child, ui),
  464. (unsigned long __user *) data);
  465. data += sizeof(long);
  466. }
  467. break;
  468. }
  469. #ifdef CONFIG_PPC64
  470. case PTRACE_SETREGS64:
  471. #endif
  472. case PTRACE_SETREGS: { /* Set all gp regs in the child. */
  473. unsigned long tmp;
  474. int ui;
  475. if (!access_ok(VERIFY_READ, (void __user *)data,
  476. sizeof(struct pt_regs))) {
  477. ret = -EIO;
  478. break;
  479. }
  480. CHECK_FULL_REGS(child->thread.regs);
  481. ret = 0;
  482. for (ui = 0; ui < PT_REGS_COUNT; ui ++) {
  483. ret = __get_user(tmp, (unsigned long __user *) data);
  484. if (ret)
  485. break;
  486. ptrace_put_reg(child, ui, tmp);
  487. data += sizeof(long);
  488. }
  489. break;
  490. }
  491. case PTRACE_GETFPREGS: { /* Get the child FPU state (FPR0...31 + FPSCR) */
  492. flush_fp_to_thread(child);
  493. ret = get_fpregs((void __user *)data, child, 1);
  494. break;
  495. }
  496. case PTRACE_SETFPREGS: { /* Set the child FPU state (FPR0...31 + FPSCR) */
  497. flush_fp_to_thread(child);
  498. ret = set_fpregs((void __user *)data, child, 1);
  499. break;
  500. }
  501. #ifdef CONFIG_ALTIVEC
  502. case PTRACE_GETVRREGS:
  503. /* Get the child altivec register state. */
  504. flush_altivec_to_thread(child);
  505. ret = get_vrregs((unsigned long __user *)data, child);
  506. break;
  507. case PTRACE_SETVRREGS:
  508. /* Set the child altivec register state. */
  509. flush_altivec_to_thread(child);
  510. ret = set_vrregs(child, (unsigned long __user *)data);
  511. break;
  512. #endif
  513. #ifdef CONFIG_SPE
  514. case PTRACE_GETEVRREGS:
  515. /* Get the child spe register state. */
  516. flush_spe_to_thread(child);
  517. ret = get_evrregs((unsigned long __user *)data, child);
  518. break;
  519. case PTRACE_SETEVRREGS:
  520. /* Set the child spe register state. */
  521. /* this is to clear the MSR_SPE bit to force a reload
  522. * of register state from memory */
  523. flush_spe_to_thread(child);
  524. ret = set_evrregs(child, (unsigned long __user *)data);
  525. break;
  526. #endif
  527. /* Old reverse args ptrace callss */
  528. case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
  529. case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
  530. case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
  531. case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */
  532. ret = arch_ptrace_old(child, request, addr, data);
  533. break;
  534. default:
  535. ret = ptrace_request(child, request, addr, data);
  536. break;
  537. }
  538. return ret;
  539. }
  540. static void do_syscall_trace(void)
  541. {
  542. /* the 0x80 provides a way for the tracing parent to distinguish
  543. between a syscall stop and SIGTRAP delivery */
  544. ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
  545. ? 0x80 : 0));
  546. /*
  547. * this isn't the same as continuing with a signal, but it will do
  548. * for normal use. strace only continues with a signal if the
  549. * stopping signal is not SIGTRAP. -brl
  550. */
  551. if (current->exit_code) {
  552. send_sig(current->exit_code, current, 1);
  553. current->exit_code = 0;
  554. }
  555. }
  556. void do_syscall_trace_enter(struct pt_regs *regs)
  557. {
  558. secure_computing(regs->gpr[0]);
  559. if (test_thread_flag(TIF_SYSCALL_TRACE)
  560. && (current->ptrace & PT_PTRACED))
  561. do_syscall_trace();
  562. if (unlikely(current->audit_context)) {
  563. #ifdef CONFIG_PPC64
  564. if (!test_thread_flag(TIF_32BIT))
  565. audit_syscall_entry(AUDIT_ARCH_PPC64,
  566. regs->gpr[0],
  567. regs->gpr[3], regs->gpr[4],
  568. regs->gpr[5], regs->gpr[6]);
  569. else
  570. #endif
  571. audit_syscall_entry(AUDIT_ARCH_PPC,
  572. regs->gpr[0],
  573. regs->gpr[3] & 0xffffffff,
  574. regs->gpr[4] & 0xffffffff,
  575. regs->gpr[5] & 0xffffffff,
  576. regs->gpr[6] & 0xffffffff);
  577. }
  578. }
  579. void do_syscall_trace_leave(struct pt_regs *regs)
  580. {
  581. if (unlikely(current->audit_context))
  582. audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
  583. regs->result);
  584. if ((test_thread_flag(TIF_SYSCALL_TRACE)
  585. || test_thread_flag(TIF_SINGLESTEP))
  586. && (current->ptrace & PT_PTRACED))
  587. do_syscall_trace();
  588. }