omap5.dtsi 4.2 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. * Based on "omap4.dtsi"
  8. */
  9. /*
  10. * Carveout for multimedia usecases
  11. * It should be the last 48MB of the first 512MB memory part
  12. * In theory, it should not even exist. That zone should be reserved
  13. * dynamically during the .reserve callback.
  14. */
  15. /memreserve/ 0x9d000000 0x03000000;
  16. /include/ "skeleton.dtsi"
  17. / {
  18. compatible = "ti,omap5";
  19. interrupt-parent = <&gic>;
  20. aliases {
  21. serial0 = &uart1;
  22. serial1 = &uart2;
  23. serial2 = &uart3;
  24. serial3 = &uart4;
  25. serial4 = &uart5;
  26. serial5 = &uart6;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,cortex-a15";
  31. timer {
  32. compatible = "arm,armv7-timer";
  33. /* 14th PPI IRQ, active low level-sensitive */
  34. interrupts = <1 14 0x308>;
  35. clock-frequency = <6144000>;
  36. };
  37. };
  38. cpu@1 {
  39. compatible = "arm,cortex-a15";
  40. timer {
  41. compatible = "arm,armv7-timer";
  42. /* 14th PPI IRQ, active low level-sensitive */
  43. interrupts = <1 14 0x308>;
  44. clock-frequency = <6144000>;
  45. };
  46. };
  47. };
  48. /*
  49. * The soc node represents the soc top level view. It is uses for IPs
  50. * that are not memory mapped in the MPU view or for the MPU itself.
  51. */
  52. soc {
  53. compatible = "ti,omap-infra";
  54. mpu {
  55. compatible = "ti,omap5-mpu";
  56. ti,hwmods = "mpu";
  57. };
  58. };
  59. /*
  60. * XXX: Use a flat representation of the OMAP3 interconnect.
  61. * The real OMAP interconnect network is quite complex.
  62. * Since that will not bring real advantage to represent that in DT for
  63. * the moment, just use a fake OCP bus entry to represent the whole bus
  64. * hierarchy.
  65. */
  66. ocp {
  67. compatible = "ti,omap4-l3-noc", "simple-bus";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. ranges;
  71. ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  72. gic: interrupt-controller@48211000 {
  73. compatible = "arm,cortex-a15-gic";
  74. interrupt-controller;
  75. #interrupt-cells = <3>;
  76. reg = <0x48211000 0x1000>,
  77. <0x48212000 0x1000>;
  78. };
  79. gpio1: gpio@4ae10000 {
  80. compatible = "ti,omap4-gpio";
  81. ti,hwmods = "gpio1";
  82. gpio-controller;
  83. #gpio-cells = <2>;
  84. interrupt-controller;
  85. #interrupt-cells = <1>;
  86. };
  87. gpio2: gpio@48055000 {
  88. compatible = "ti,omap4-gpio";
  89. ti,hwmods = "gpio2";
  90. gpio-controller;
  91. #gpio-cells = <2>;
  92. interrupt-controller;
  93. #interrupt-cells = <1>;
  94. };
  95. gpio3: gpio@48057000 {
  96. compatible = "ti,omap4-gpio";
  97. ti,hwmods = "gpio3";
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. interrupt-controller;
  101. #interrupt-cells = <1>;
  102. };
  103. gpio4: gpio@48059000 {
  104. compatible = "ti,omap4-gpio";
  105. ti,hwmods = "gpio4";
  106. gpio-controller;
  107. #gpio-cells = <2>;
  108. interrupt-controller;
  109. #interrupt-cells = <1>;
  110. };
  111. gpio5: gpio@4805b000 {
  112. compatible = "ti,omap4-gpio";
  113. ti,hwmods = "gpio5";
  114. gpio-controller;
  115. #gpio-cells = <2>;
  116. interrupt-controller;
  117. #interrupt-cells = <1>;
  118. };
  119. gpio6: gpio@4805d000 {
  120. compatible = "ti,omap4-gpio";
  121. ti,hwmods = "gpio6";
  122. gpio-controller;
  123. #gpio-cells = <2>;
  124. interrupt-controller;
  125. #interrupt-cells = <1>;
  126. };
  127. gpio7: gpio@48051000 {
  128. compatible = "ti,omap4-gpio";
  129. ti,hwmods = "gpio7";
  130. gpio-controller;
  131. #gpio-cells = <2>;
  132. interrupt-controller;
  133. #interrupt-cells = <1>;
  134. };
  135. gpio8: gpio@48053000 {
  136. compatible = "ti,omap4-gpio";
  137. ti,hwmods = "gpio8";
  138. gpio-controller;
  139. #gpio-cells = <2>;
  140. interrupt-controller;
  141. #interrupt-cells = <1>;
  142. };
  143. uart1: serial@4806a000 {
  144. compatible = "ti,omap4-uart";
  145. ti,hwmods = "uart1";
  146. clock-frequency = <48000000>;
  147. };
  148. uart2: serial@4806c000 {
  149. compatible = "ti,omap4-uart";
  150. ti,hwmods = "uart2";
  151. clock-frequency = <48000000>;
  152. };
  153. uart3: serial@48020000 {
  154. compatible = "ti,omap4-uart";
  155. ti,hwmods = "uart3";
  156. clock-frequency = <48000000>;
  157. };
  158. uart4: serial@4806e000 {
  159. compatible = "ti,omap4-uart";
  160. ti,hwmods = "uart4";
  161. clock-frequency = <48000000>;
  162. };
  163. uart5: serial@48066000 {
  164. compatible = "ti,omap5-uart";
  165. ti,hwmods = "uart5";
  166. clock-frequency = <48000000>;
  167. };
  168. uart6: serial@48068000 {
  169. compatible = "ti,omap6-uart";
  170. ti,hwmods = "uart6";
  171. clock-frequency = <48000000>;
  172. };
  173. };
  174. };