ak4642.c 12 KB

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  1. /*
  2. * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on wm8731.c by Richard Purdie
  8. * Based on ak4535.c by Richard Purdie
  9. * Based on wm8753.c by Liam Girdwood
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. /* ** CAUTION **
  16. *
  17. * This is very simple driver.
  18. * It can use headphone output / stereo input only
  19. *
  20. * AK4642 is tested.
  21. * AK4643 is tested.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/i2c.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include <linux/module.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #define AK4642_VERSION "0.0.1"
  32. #define PW_MGMT1 0x00
  33. #define PW_MGMT2 0x01
  34. #define SG_SL1 0x02
  35. #define SG_SL2 0x03
  36. #define MD_CTL1 0x04
  37. #define MD_CTL2 0x05
  38. #define TIMER 0x06
  39. #define ALC_CTL1 0x07
  40. #define ALC_CTL2 0x08
  41. #define L_IVC 0x09
  42. #define L_DVC 0x0a
  43. #define ALC_CTL3 0x0b
  44. #define R_IVC 0x0c
  45. #define R_DVC 0x0d
  46. #define MD_CTL3 0x0e
  47. #define MD_CTL4 0x0f
  48. #define PW_MGMT3 0x10
  49. #define DF_S 0x11
  50. #define FIL3_0 0x12
  51. #define FIL3_1 0x13
  52. #define FIL3_2 0x14
  53. #define FIL3_3 0x15
  54. #define EQ_0 0x16
  55. #define EQ_1 0x17
  56. #define EQ_2 0x18
  57. #define EQ_3 0x19
  58. #define EQ_4 0x1a
  59. #define EQ_5 0x1b
  60. #define FIL1_0 0x1c
  61. #define FIL1_1 0x1d
  62. #define FIL1_2 0x1e
  63. #define FIL1_3 0x1f
  64. #define PW_MGMT4 0x20
  65. #define MD_CTL5 0x21
  66. #define LO_MS 0x22
  67. #define HP_MS 0x23
  68. #define SPK_MS 0x24
  69. #define AK4642_CACHEREGNUM 0x25
  70. /* PW_MGMT1*/
  71. #define PMVCM (1 << 6) /* VCOM Power Management */
  72. #define PMMIN (1 << 5) /* MIN Input Power Management */
  73. #define PMDAC (1 << 2) /* DAC Power Management */
  74. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  75. /* PW_MGMT2 */
  76. #define HPMTN (1 << 6)
  77. #define PMHPL (1 << 5)
  78. #define PMHPR (1 << 4)
  79. #define MS (1 << 3) /* master/slave select */
  80. #define MCKO (1 << 1)
  81. #define PMPLL (1 << 0)
  82. #define PMHP_MASK (PMHPL | PMHPR)
  83. #define PMHP PMHP_MASK
  84. /* PW_MGMT3 */
  85. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  86. /* SG_SL1 */
  87. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  88. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  89. #define PMMP (1 << 2) /* MPWR pin Power Management */
  90. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  91. /* TIMER */
  92. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
  93. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  94. /* ALC_CTL1 */
  95. #define ALC (1 << 5) /* ALC Enable */
  96. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  97. /* MD_CTL1 */
  98. #define PLL3 (1 << 7)
  99. #define PLL2 (1 << 6)
  100. #define PLL1 (1 << 5)
  101. #define PLL0 (1 << 4)
  102. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  103. #define BCKO_MASK (1 << 3)
  104. #define BCKO_64 BCKO_MASK
  105. #define DIF_MASK (3 << 0)
  106. #define DSP (0 << 0)
  107. #define RIGHT_J (1 << 0)
  108. #define LEFT_J (2 << 0)
  109. #define I2S (3 << 0)
  110. /* MD_CTL2 */
  111. #define FS0 (1 << 0)
  112. #define FS1 (1 << 1)
  113. #define FS2 (1 << 2)
  114. #define FS3 (1 << 5)
  115. #define FS_MASK (FS0 | FS1 | FS2 | FS3)
  116. /* MD_CTL3 */
  117. #define BST1 (1 << 3)
  118. /* MD_CTL4 */
  119. #define DACH (1 << 0)
  120. /*
  121. * Playback Volume (table 39)
  122. *
  123. * max : 0x00 : +12.0 dB
  124. * ( 0.5 dB step )
  125. * min : 0xFE : -115.0 dB
  126. * mute: 0xFF
  127. */
  128. static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
  129. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  130. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  131. 0, 0xFF, 1, out_tlv),
  132. SOC_SINGLE("Headphone Switch", PW_MGMT2, 6, 1, 0),
  133. };
  134. static const struct snd_kcontrol_new ak4642_hpout_mixer_controls[] = {
  135. SOC_DAPM_SINGLE("DACH", MD_CTL4, 0, 1, 0),
  136. };
  137. static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
  138. /* Outputs */
  139. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  140. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  141. SND_SOC_DAPM_MIXER("HPOUTL Mixer", PW_MGMT2, 5, 0,
  142. &ak4642_hpout_mixer_controls[0],
  143. ARRAY_SIZE(ak4642_hpout_mixer_controls)),
  144. SND_SOC_DAPM_MIXER("HPOUTR Mixer", PW_MGMT2, 4, 0,
  145. &ak4642_hpout_mixer_controls[0],
  146. ARRAY_SIZE(ak4642_hpout_mixer_controls)),
  147. /* DAC */
  148. SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
  149. };
  150. static const struct snd_soc_dapm_route ak4642_intercon[] = {
  151. /* Outputs */
  152. {"HPOUTL", NULL, "HPOUTL Mixer"},
  153. {"HPOUTR", NULL, "HPOUTR Mixer"},
  154. {"HPOUTL Mixer", "DACH", "DAC"},
  155. {"HPOUTR Mixer", "DACH", "DAC"},
  156. };
  157. /* codec private data */
  158. struct ak4642_priv {
  159. unsigned int sysclk;
  160. enum snd_soc_control_type control_type;
  161. };
  162. /*
  163. * ak4642 register cache
  164. */
  165. static const u8 ak4642_reg[AK4642_CACHEREGNUM] = {
  166. 0x00, 0x00, 0x01, 0x00,
  167. 0x02, 0x00, 0x00, 0x00,
  168. 0xe1, 0xe1, 0x18, 0x00,
  169. 0xe1, 0x18, 0x11, 0x08,
  170. 0x00, 0x00, 0x00, 0x00,
  171. 0x00, 0x00, 0x00, 0x00,
  172. 0x00, 0x00, 0x00, 0x00,
  173. 0x00, 0x00, 0x00, 0x00,
  174. 0x00, 0x00, 0x00, 0x00,
  175. 0x00,
  176. };
  177. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  178. struct snd_soc_dai *dai)
  179. {
  180. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  181. struct snd_soc_codec *codec = dai->codec;
  182. if (is_play) {
  183. /*
  184. * start headphone output
  185. *
  186. * PLL, Master Mode
  187. * Audio I/F Format :MSB justified (ADC & DAC)
  188. * Bass Boost Level : Middle
  189. *
  190. * This operation came from example code of
  191. * "ASAHI KASEI AK4642" (japanese) manual p97.
  192. */
  193. snd_soc_write(codec, L_IVC, 0x91); /* volume */
  194. snd_soc_write(codec, R_IVC, 0x91); /* volume */
  195. } else {
  196. /*
  197. * start stereo input
  198. *
  199. * PLL Master Mode
  200. * Audio I/F Format:MSB justified (ADC & DAC)
  201. * Pre MIC AMP:+20dB
  202. * MIC Power On
  203. * ALC setting:Refer to Table 35
  204. * ALC bit=“1”
  205. *
  206. * This operation came from example code of
  207. * "ASAHI KASEI AK4642" (japanese) manual p94.
  208. */
  209. snd_soc_write(codec, SG_SL1, PMMP | MGAIN0);
  210. snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
  211. snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
  212. snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
  213. snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
  214. }
  215. return 0;
  216. }
  217. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  218. struct snd_soc_dai *dai)
  219. {
  220. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  221. struct snd_soc_codec *codec = dai->codec;
  222. if (is_play) {
  223. } else {
  224. /* stop stereo input */
  225. snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
  226. snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
  227. snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
  228. }
  229. }
  230. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  231. int clk_id, unsigned int freq, int dir)
  232. {
  233. struct snd_soc_codec *codec = codec_dai->codec;
  234. u8 pll;
  235. switch (freq) {
  236. case 11289600:
  237. pll = PLL2;
  238. break;
  239. case 12288000:
  240. pll = PLL2 | PLL0;
  241. break;
  242. case 12000000:
  243. pll = PLL2 | PLL1;
  244. break;
  245. case 24000000:
  246. pll = PLL2 | PLL1 | PLL0;
  247. break;
  248. case 13500000:
  249. pll = PLL3 | PLL2;
  250. break;
  251. case 27000000:
  252. pll = PLL3 | PLL2 | PLL0;
  253. break;
  254. default:
  255. return -EINVAL;
  256. }
  257. snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
  258. return 0;
  259. }
  260. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  261. {
  262. struct snd_soc_codec *codec = dai->codec;
  263. u8 data;
  264. u8 bcko;
  265. data = MCKO | PMPLL; /* use MCKO */
  266. bcko = 0;
  267. /* set master/slave audio interface */
  268. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  269. case SND_SOC_DAIFMT_CBM_CFM:
  270. data |= MS;
  271. bcko = BCKO_64;
  272. break;
  273. case SND_SOC_DAIFMT_CBS_CFS:
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
  279. snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
  280. /* format type */
  281. data = 0;
  282. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  283. case SND_SOC_DAIFMT_LEFT_J:
  284. data = LEFT_J;
  285. break;
  286. case SND_SOC_DAIFMT_I2S:
  287. data = I2S;
  288. break;
  289. /* FIXME
  290. * Please add RIGHT_J / DSP support here
  291. */
  292. default:
  293. return -EINVAL;
  294. break;
  295. }
  296. snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
  297. return 0;
  298. }
  299. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  300. struct snd_pcm_hw_params *params,
  301. struct snd_soc_dai *dai)
  302. {
  303. struct snd_soc_codec *codec = dai->codec;
  304. u8 rate;
  305. switch (params_rate(params)) {
  306. case 7350:
  307. rate = FS2;
  308. break;
  309. case 8000:
  310. rate = 0;
  311. break;
  312. case 11025:
  313. rate = FS2 | FS0;
  314. break;
  315. case 12000:
  316. rate = FS0;
  317. break;
  318. case 14700:
  319. rate = FS2 | FS1;
  320. break;
  321. case 16000:
  322. rate = FS1;
  323. break;
  324. case 22050:
  325. rate = FS2 | FS1 | FS0;
  326. break;
  327. case 24000:
  328. rate = FS1 | FS0;
  329. break;
  330. case 29400:
  331. rate = FS3 | FS2 | FS1;
  332. break;
  333. case 32000:
  334. rate = FS3 | FS1;
  335. break;
  336. case 44100:
  337. rate = FS3 | FS2 | FS1 | FS0;
  338. break;
  339. case 48000:
  340. rate = FS3 | FS1 | FS0;
  341. break;
  342. default:
  343. return -EINVAL;
  344. break;
  345. }
  346. snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
  347. return 0;
  348. }
  349. static int ak4642_set_bias_level(struct snd_soc_codec *codec,
  350. enum snd_soc_bias_level level)
  351. {
  352. switch (level) {
  353. case SND_SOC_BIAS_OFF:
  354. snd_soc_write(codec, PW_MGMT1, 0x00);
  355. break;
  356. default:
  357. snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
  358. break;
  359. }
  360. codec->dapm.bias_level = level;
  361. return 0;
  362. }
  363. static struct snd_soc_dai_ops ak4642_dai_ops = {
  364. .startup = ak4642_dai_startup,
  365. .shutdown = ak4642_dai_shutdown,
  366. .set_sysclk = ak4642_dai_set_sysclk,
  367. .set_fmt = ak4642_dai_set_fmt,
  368. .hw_params = ak4642_dai_hw_params,
  369. };
  370. static struct snd_soc_dai_driver ak4642_dai = {
  371. .name = "ak4642-hifi",
  372. .playback = {
  373. .stream_name = "Playback",
  374. .channels_min = 1,
  375. .channels_max = 2,
  376. .rates = SNDRV_PCM_RATE_8000_48000,
  377. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  378. .capture = {
  379. .stream_name = "Capture",
  380. .channels_min = 1,
  381. .channels_max = 2,
  382. .rates = SNDRV_PCM_RATE_8000_48000,
  383. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  384. .ops = &ak4642_dai_ops,
  385. .symmetric_rates = 1,
  386. };
  387. static int ak4642_resume(struct snd_soc_codec *codec)
  388. {
  389. snd_soc_cache_sync(codec);
  390. return 0;
  391. }
  392. static int ak4642_probe(struct snd_soc_codec *codec)
  393. {
  394. struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
  395. int ret;
  396. dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
  397. ret = snd_soc_codec_set_cache_io(codec, 8, 8, ak4642->control_type);
  398. if (ret < 0) {
  399. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  400. return ret;
  401. }
  402. snd_soc_add_controls(codec, ak4642_snd_controls,
  403. ARRAY_SIZE(ak4642_snd_controls));
  404. ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  405. return 0;
  406. }
  407. static int ak4642_remove(struct snd_soc_codec *codec)
  408. {
  409. ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
  410. return 0;
  411. }
  412. static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
  413. .probe = ak4642_probe,
  414. .remove = ak4642_remove,
  415. .resume = ak4642_resume,
  416. .set_bias_level = ak4642_set_bias_level,
  417. .reg_cache_size = ARRAY_SIZE(ak4642_reg),
  418. .reg_word_size = sizeof(u8),
  419. .reg_cache_default = ak4642_reg,
  420. .dapm_widgets = ak4642_dapm_widgets,
  421. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  422. .dapm_routes = ak4642_intercon,
  423. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  424. };
  425. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  426. static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
  427. const struct i2c_device_id *id)
  428. {
  429. struct ak4642_priv *ak4642;
  430. int ret;
  431. ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
  432. if (!ak4642)
  433. return -ENOMEM;
  434. i2c_set_clientdata(i2c, ak4642);
  435. ak4642->control_type = SND_SOC_I2C;
  436. ret = snd_soc_register_codec(&i2c->dev,
  437. &soc_codec_dev_ak4642, &ak4642_dai, 1);
  438. if (ret < 0)
  439. kfree(ak4642);
  440. return ret;
  441. }
  442. static __devexit int ak4642_i2c_remove(struct i2c_client *client)
  443. {
  444. snd_soc_unregister_codec(&client->dev);
  445. kfree(i2c_get_clientdata(client));
  446. return 0;
  447. }
  448. static const struct i2c_device_id ak4642_i2c_id[] = {
  449. { "ak4642", 0 },
  450. { "ak4643", 0 },
  451. { }
  452. };
  453. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  454. static struct i2c_driver ak4642_i2c_driver = {
  455. .driver = {
  456. .name = "ak4642-codec",
  457. .owner = THIS_MODULE,
  458. },
  459. .probe = ak4642_i2c_probe,
  460. .remove = __devexit_p(ak4642_i2c_remove),
  461. .id_table = ak4642_i2c_id,
  462. };
  463. #endif
  464. static int __init ak4642_modinit(void)
  465. {
  466. int ret = 0;
  467. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  468. ret = i2c_add_driver(&ak4642_i2c_driver);
  469. #endif
  470. return ret;
  471. }
  472. module_init(ak4642_modinit);
  473. static void __exit ak4642_exit(void)
  474. {
  475. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  476. i2c_del_driver(&ak4642_i2c_driver);
  477. #endif
  478. }
  479. module_exit(ak4642_exit);
  480. MODULE_DESCRIPTION("Soc AK4642 driver");
  481. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  482. MODULE_LICENSE("GPL");