ci13xxx_udc.c 72 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  71. /* ctrl register bank access */
  72. static DEFINE_SPINLOCK(udc_lock);
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* UDC descriptor */
  91. static struct ci13xxx *_udc;
  92. /* Interrupt statistics */
  93. #define ISR_MASK 0x1F
  94. static struct {
  95. u32 test;
  96. u32 ui;
  97. u32 uei;
  98. u32 pci;
  99. u32 uri;
  100. u32 sli;
  101. u32 none;
  102. struct {
  103. u32 cnt;
  104. u32 buf[ISR_MASK+1];
  105. u32 idx;
  106. } hndl;
  107. } isr_statistics;
  108. /**
  109. * ffs_nr: find first (least significant) bit set
  110. * @x: the word to search
  111. *
  112. * This function returns bit number (instead of position)
  113. */
  114. static int ffs_nr(u32 x)
  115. {
  116. int n = ffs(x);
  117. return n ? n-1 : 32;
  118. }
  119. /******************************************************************************
  120. * HW block
  121. *****************************************************************************/
  122. /* register bank descriptor */
  123. static struct {
  124. unsigned lpm; /* is LPM? */
  125. void __iomem *abs; /* bus map offset */
  126. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  127. size_t size; /* bank size */
  128. } hw_bank;
  129. /* MSM specific */
  130. #define ABS_AHBBURST (0x0090UL)
  131. #define ABS_AHBMODE (0x0098UL)
  132. /* UDC register map */
  133. #define ABS_CAPLENGTH (0x100UL)
  134. #define ABS_HCCPARAMS (0x108UL)
  135. #define ABS_DCCPARAMS (0x124UL)
  136. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  137. /* offset to CAPLENTGH (addr + data) */
  138. #define CAP_USBCMD (0x000UL)
  139. #define CAP_USBSTS (0x004UL)
  140. #define CAP_USBINTR (0x008UL)
  141. #define CAP_DEVICEADDR (0x014UL)
  142. #define CAP_ENDPTLISTADDR (0x018UL)
  143. #define CAP_PORTSC (0x044UL)
  144. #define CAP_DEVLC (0x084UL)
  145. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  146. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  147. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  148. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  149. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  150. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  151. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  152. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  153. /* maximum number of enpoints: valid only after hw_device_reset() */
  154. static unsigned hw_ep_max;
  155. /**
  156. * hw_ep_bit: calculates the bit number
  157. * @num: endpoint number
  158. * @dir: endpoint direction
  159. *
  160. * This function returns bit number
  161. */
  162. static inline int hw_ep_bit(int num, int dir)
  163. {
  164. return num + (dir ? 16 : 0);
  165. }
  166. /**
  167. * hw_aread: reads from register bitfield
  168. * @addr: address relative to bus map
  169. * @mask: bitfield mask
  170. *
  171. * This function returns register bitfield data
  172. */
  173. static u32 hw_aread(u32 addr, u32 mask)
  174. {
  175. return ioread32(addr + hw_bank.abs) & mask;
  176. }
  177. /**
  178. * hw_awrite: writes to register bitfield
  179. * @addr: address relative to bus map
  180. * @mask: bitfield mask
  181. * @data: new data
  182. */
  183. static void hw_awrite(u32 addr, u32 mask, u32 data)
  184. {
  185. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  186. addr + hw_bank.abs);
  187. }
  188. /**
  189. * hw_cread: reads from register bitfield
  190. * @addr: address relative to CAP offset plus content
  191. * @mask: bitfield mask
  192. *
  193. * This function returns register bitfield data
  194. */
  195. static u32 hw_cread(u32 addr, u32 mask)
  196. {
  197. return ioread32(addr + hw_bank.cap) & mask;
  198. }
  199. /**
  200. * hw_cwrite: writes to register bitfield
  201. * @addr: address relative to CAP offset plus content
  202. * @mask: bitfield mask
  203. * @data: new data
  204. */
  205. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  206. {
  207. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  208. addr + hw_bank.cap);
  209. }
  210. /**
  211. * hw_ctest_and_clear: tests & clears register bitfield
  212. * @addr: address relative to CAP offset plus content
  213. * @mask: bitfield mask
  214. *
  215. * This function returns register bitfield data
  216. */
  217. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  218. {
  219. u32 reg = hw_cread(addr, mask);
  220. iowrite32(reg, addr + hw_bank.cap);
  221. return reg;
  222. }
  223. /**
  224. * hw_ctest_and_write: tests & writes register bitfield
  225. * @addr: address relative to CAP offset plus content
  226. * @mask: bitfield mask
  227. * @data: new data
  228. *
  229. * This function returns register bitfield data
  230. */
  231. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  232. {
  233. u32 reg = hw_cread(addr, ~0);
  234. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  235. return (reg & mask) >> ffs_nr(mask);
  236. }
  237. static int hw_device_init(void __iomem *base)
  238. {
  239. u32 reg;
  240. /* bank is a module variable */
  241. hw_bank.abs = base;
  242. hw_bank.cap = hw_bank.abs;
  243. hw_bank.cap += ABS_CAPLENGTH;
  244. hw_bank.cap += ioread8(hw_bank.cap);
  245. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  246. hw_bank.lpm = reg;
  247. hw_bank.size = hw_bank.cap - hw_bank.abs;
  248. hw_bank.size += CAP_LAST;
  249. hw_bank.size /= sizeof(u32);
  250. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  251. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  252. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  253. return -ENODEV;
  254. /* setup lock mode ? */
  255. /* ENDPTSETUPSTAT is '0' by default */
  256. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  257. return 0;
  258. }
  259. /**
  260. * hw_device_reset: resets chip (execute without interruption)
  261. * @base: register base address
  262. *
  263. * This function returns an error code
  264. */
  265. static int hw_device_reset(struct ci13xxx *udc)
  266. {
  267. /* should flush & stop before reset */
  268. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  269. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  270. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  271. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  272. udelay(10); /* not RTOS friendly */
  273. if (udc->udc_driver->notify_event)
  274. udc->udc_driver->notify_event(udc,
  275. CI13XXX_CONTROLLER_RESET_EVENT);
  276. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  277. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  278. /* USBMODE should be configured step by step */
  279. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  280. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  281. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  282. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  283. pr_err("cannot enter in device mode");
  284. pr_err("lpm = %i", hw_bank.lpm);
  285. return -ENODEV;
  286. }
  287. return 0;
  288. }
  289. /**
  290. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  291. * without interruption)
  292. * @dma: 0 => disable, !0 => enable and set dma engine
  293. *
  294. * This function returns an error code
  295. */
  296. static int hw_device_state(u32 dma)
  297. {
  298. if (dma) {
  299. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  300. /* interrupt, error, port change, reset, sleep/suspend */
  301. hw_cwrite(CAP_USBINTR, ~0,
  302. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  303. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  304. } else {
  305. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  306. hw_cwrite(CAP_USBINTR, ~0, 0);
  307. }
  308. return 0;
  309. }
  310. /**
  311. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  312. * @num: endpoint number
  313. * @dir: endpoint direction
  314. *
  315. * This function returns an error code
  316. */
  317. static int hw_ep_flush(int num, int dir)
  318. {
  319. int n = hw_ep_bit(num, dir);
  320. do {
  321. /* flush any pending transfer */
  322. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  323. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  324. cpu_relax();
  325. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  326. return 0;
  327. }
  328. /**
  329. * hw_ep_disable: disables endpoint (execute without interruption)
  330. * @num: endpoint number
  331. * @dir: endpoint direction
  332. *
  333. * This function returns an error code
  334. */
  335. static int hw_ep_disable(int num, int dir)
  336. {
  337. hw_ep_flush(num, dir);
  338. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  339. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  340. return 0;
  341. }
  342. /**
  343. * hw_ep_enable: enables endpoint (execute without interruption)
  344. * @num: endpoint number
  345. * @dir: endpoint direction
  346. * @type: endpoint type
  347. *
  348. * This function returns an error code
  349. */
  350. static int hw_ep_enable(int num, int dir, int type)
  351. {
  352. u32 mask, data;
  353. if (dir) {
  354. mask = ENDPTCTRL_TXT; /* type */
  355. data = type << ffs_nr(mask);
  356. mask |= ENDPTCTRL_TXS; /* unstall */
  357. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  358. data |= ENDPTCTRL_TXR;
  359. mask |= ENDPTCTRL_TXE; /* enable */
  360. data |= ENDPTCTRL_TXE;
  361. } else {
  362. mask = ENDPTCTRL_RXT; /* type */
  363. data = type << ffs_nr(mask);
  364. mask |= ENDPTCTRL_RXS; /* unstall */
  365. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  366. data |= ENDPTCTRL_RXR;
  367. mask |= ENDPTCTRL_RXE; /* enable */
  368. data |= ENDPTCTRL_RXE;
  369. }
  370. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  371. return 0;
  372. }
  373. /**
  374. * hw_ep_get_halt: return endpoint halt status
  375. * @num: endpoint number
  376. * @dir: endpoint direction
  377. *
  378. * This function returns 1 if endpoint halted
  379. */
  380. static int hw_ep_get_halt(int num, int dir)
  381. {
  382. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  383. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  384. }
  385. /**
  386. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  387. * interruption)
  388. * @n: bit number (endpoint)
  389. *
  390. * This function returns setup status
  391. */
  392. static int hw_test_and_clear_setup_status(int n)
  393. {
  394. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  395. }
  396. /**
  397. * hw_ep_prime: primes endpoint (execute without interruption)
  398. * @num: endpoint number
  399. * @dir: endpoint direction
  400. * @is_ctrl: true if control endpoint
  401. *
  402. * This function returns an error code
  403. */
  404. static int hw_ep_prime(int num, int dir, int is_ctrl)
  405. {
  406. int n = hw_ep_bit(num, dir);
  407. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  408. return -EAGAIN;
  409. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  410. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  411. cpu_relax();
  412. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  413. return -EAGAIN;
  414. /* status shoult be tested according with manual but it doesn't work */
  415. return 0;
  416. }
  417. /**
  418. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  419. * without interruption)
  420. * @num: endpoint number
  421. * @dir: endpoint direction
  422. * @value: true => stall, false => unstall
  423. *
  424. * This function returns an error code
  425. */
  426. static int hw_ep_set_halt(int num, int dir, int value)
  427. {
  428. if (value != 0 && value != 1)
  429. return -EINVAL;
  430. do {
  431. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  432. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  433. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  434. /* data toggle - reserved for EP0 but it's in ESS */
  435. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  436. } while (value != hw_ep_get_halt(num, dir));
  437. return 0;
  438. }
  439. /**
  440. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  441. * interruption)
  442. * @n: interrupt bit
  443. *
  444. * This function returns an error code
  445. */
  446. static int hw_intr_clear(int n)
  447. {
  448. if (n >= REG_BITS)
  449. return -EINVAL;
  450. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  451. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  452. return 0;
  453. }
  454. /**
  455. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  456. * interruption)
  457. * @n: interrupt bit
  458. *
  459. * This function returns an error code
  460. */
  461. static int hw_intr_force(int n)
  462. {
  463. if (n >= REG_BITS)
  464. return -EINVAL;
  465. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  466. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  467. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  468. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  469. return 0;
  470. }
  471. /**
  472. * hw_is_port_high_speed: test if port is high speed
  473. *
  474. * This function returns true if high speed port
  475. */
  476. static int hw_port_is_high_speed(void)
  477. {
  478. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  479. hw_cread(CAP_PORTSC, PORTSC_HSP);
  480. }
  481. /**
  482. * hw_port_test_get: reads port test mode value
  483. *
  484. * This function returns port test mode value
  485. */
  486. static u8 hw_port_test_get(void)
  487. {
  488. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  489. }
  490. /**
  491. * hw_port_test_set: writes port test mode (execute without interruption)
  492. * @mode: new value
  493. *
  494. * This function returns an error code
  495. */
  496. static int hw_port_test_set(u8 mode)
  497. {
  498. const u8 TEST_MODE_MAX = 7;
  499. if (mode > TEST_MODE_MAX)
  500. return -EINVAL;
  501. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  502. return 0;
  503. }
  504. /**
  505. * hw_read_intr_enable: returns interrupt enable register
  506. *
  507. * This function returns register data
  508. */
  509. static u32 hw_read_intr_enable(void)
  510. {
  511. return hw_cread(CAP_USBINTR, ~0);
  512. }
  513. /**
  514. * hw_read_intr_status: returns interrupt status register
  515. *
  516. * This function returns register data
  517. */
  518. static u32 hw_read_intr_status(void)
  519. {
  520. return hw_cread(CAP_USBSTS, ~0);
  521. }
  522. /**
  523. * hw_register_read: reads all device registers (execute without interruption)
  524. * @buf: destination buffer
  525. * @size: buffer size
  526. *
  527. * This function returns number of registers read
  528. */
  529. static size_t hw_register_read(u32 *buf, size_t size)
  530. {
  531. unsigned i;
  532. if (size > hw_bank.size)
  533. size = hw_bank.size;
  534. for (i = 0; i < size; i++)
  535. buf[i] = hw_aread(i * sizeof(u32), ~0);
  536. return size;
  537. }
  538. /**
  539. * hw_register_write: writes to register
  540. * @addr: register address
  541. * @data: register value
  542. *
  543. * This function returns an error code
  544. */
  545. static int hw_register_write(u16 addr, u32 data)
  546. {
  547. /* align */
  548. addr /= sizeof(u32);
  549. if (addr >= hw_bank.size)
  550. return -EINVAL;
  551. /* align */
  552. addr *= sizeof(u32);
  553. hw_awrite(addr, ~0, data);
  554. return 0;
  555. }
  556. /**
  557. * hw_test_and_clear_complete: test & clear complete status (execute without
  558. * interruption)
  559. * @n: bit number (endpoint)
  560. *
  561. * This function returns complete status
  562. */
  563. static int hw_test_and_clear_complete(int n)
  564. {
  565. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  566. }
  567. /**
  568. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  569. * without interruption)
  570. *
  571. * This function returns active interrutps
  572. */
  573. static u32 hw_test_and_clear_intr_active(void)
  574. {
  575. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  576. hw_cwrite(CAP_USBSTS, ~0, reg);
  577. return reg;
  578. }
  579. /**
  580. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  581. * interruption)
  582. *
  583. * This function returns guard value
  584. */
  585. static int hw_test_and_clear_setup_guard(void)
  586. {
  587. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  588. }
  589. /**
  590. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  591. * interruption)
  592. *
  593. * This function returns guard value
  594. */
  595. static int hw_test_and_set_setup_guard(void)
  596. {
  597. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  598. }
  599. /**
  600. * hw_usb_set_address: configures USB address (execute without interruption)
  601. * @value: new USB address
  602. *
  603. * This function returns an error code
  604. */
  605. static int hw_usb_set_address(u8 value)
  606. {
  607. /* advance */
  608. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  609. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  610. return 0;
  611. }
  612. /**
  613. * hw_usb_reset: restart device after a bus reset (execute without
  614. * interruption)
  615. *
  616. * This function returns an error code
  617. */
  618. static int hw_usb_reset(void)
  619. {
  620. hw_usb_set_address(0);
  621. /* ESS flushes only at end?!? */
  622. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  623. /* clear setup token semaphores */
  624. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  625. /* clear complete status */
  626. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  627. /* wait until all bits cleared */
  628. while (hw_cread(CAP_ENDPTPRIME, ~0))
  629. udelay(10); /* not RTOS friendly */
  630. /* reset all endpoints ? */
  631. /* reset internal status and wait for further instructions
  632. no need to verify the port reset status (ESS does it) */
  633. return 0;
  634. }
  635. /******************************************************************************
  636. * DBG block
  637. *****************************************************************************/
  638. /**
  639. * show_device: prints information about device capabilities and status
  640. *
  641. * Check "device.h" for details
  642. */
  643. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  644. char *buf)
  645. {
  646. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  647. struct usb_gadget *gadget = &udc->gadget;
  648. int n = 0;
  649. dbg_trace("[%s] %p\n", __func__, buf);
  650. if (attr == NULL || buf == NULL) {
  651. dev_err(dev, "[%s] EINVAL\n", __func__);
  652. return 0;
  653. }
  654. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  655. gadget->speed);
  656. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  657. gadget->is_dualspeed);
  658. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  659. gadget->is_otg);
  660. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  661. gadget->is_a_peripheral);
  662. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  663. gadget->b_hnp_enable);
  664. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  665. gadget->a_hnp_support);
  666. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  667. gadget->a_alt_hnp_support);
  668. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  669. (gadget->name ? gadget->name : ""));
  670. return n;
  671. }
  672. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  673. /**
  674. * show_driver: prints information about attached gadget (if any)
  675. *
  676. * Check "device.h" for details
  677. */
  678. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  679. char *buf)
  680. {
  681. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  682. struct usb_gadget_driver *driver = udc->driver;
  683. int n = 0;
  684. dbg_trace("[%s] %p\n", __func__, buf);
  685. if (attr == NULL || buf == NULL) {
  686. dev_err(dev, "[%s] EINVAL\n", __func__);
  687. return 0;
  688. }
  689. if (driver == NULL)
  690. return scnprintf(buf, PAGE_SIZE,
  691. "There is no gadget attached!\n");
  692. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  693. (driver->function ? driver->function : ""));
  694. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  695. driver->speed);
  696. return n;
  697. }
  698. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  699. /* Maximum event message length */
  700. #define DBG_DATA_MSG 64UL
  701. /* Maximum event messages */
  702. #define DBG_DATA_MAX 128UL
  703. /* Event buffer descriptor */
  704. static struct {
  705. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  706. unsigned idx; /* index */
  707. unsigned tty; /* print to console? */
  708. rwlock_t lck; /* lock */
  709. } dbg_data = {
  710. .idx = 0,
  711. .tty = 0,
  712. .lck = __RW_LOCK_UNLOCKED(lck)
  713. };
  714. /**
  715. * dbg_dec: decrements debug event index
  716. * @idx: buffer index
  717. */
  718. static void dbg_dec(unsigned *idx)
  719. {
  720. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  721. }
  722. /**
  723. * dbg_inc: increments debug event index
  724. * @idx: buffer index
  725. */
  726. static void dbg_inc(unsigned *idx)
  727. {
  728. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  729. }
  730. /**
  731. * dbg_print: prints the common part of the event
  732. * @addr: endpoint address
  733. * @name: event name
  734. * @status: status
  735. * @extra: extra information
  736. */
  737. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  738. {
  739. struct timeval tval;
  740. unsigned int stamp;
  741. unsigned long flags;
  742. write_lock_irqsave(&dbg_data.lck, flags);
  743. do_gettimeofday(&tval);
  744. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  745. stamp = stamp * 1000000 + tval.tv_usec;
  746. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  747. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  748. stamp, addr, name, status, extra);
  749. dbg_inc(&dbg_data.idx);
  750. write_unlock_irqrestore(&dbg_data.lck, flags);
  751. if (dbg_data.tty != 0)
  752. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  753. stamp, addr, name, status, extra);
  754. }
  755. /**
  756. * dbg_done: prints a DONE event
  757. * @addr: endpoint address
  758. * @td: transfer descriptor
  759. * @status: status
  760. */
  761. static void dbg_done(u8 addr, const u32 token, int status)
  762. {
  763. char msg[DBG_DATA_MSG];
  764. scnprintf(msg, sizeof(msg), "%d %02X",
  765. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  766. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  767. dbg_print(addr, "DONE", status, msg);
  768. }
  769. /**
  770. * dbg_event: prints a generic event
  771. * @addr: endpoint address
  772. * @name: event name
  773. * @status: status
  774. */
  775. static void dbg_event(u8 addr, const char *name, int status)
  776. {
  777. if (name != NULL)
  778. dbg_print(addr, name, status, "");
  779. }
  780. /*
  781. * dbg_queue: prints a QUEUE event
  782. * @addr: endpoint address
  783. * @req: USB request
  784. * @status: status
  785. */
  786. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  787. {
  788. char msg[DBG_DATA_MSG];
  789. if (req != NULL) {
  790. scnprintf(msg, sizeof(msg),
  791. "%d %d", !req->no_interrupt, req->length);
  792. dbg_print(addr, "QUEUE", status, msg);
  793. }
  794. }
  795. /**
  796. * dbg_setup: prints a SETUP event
  797. * @addr: endpoint address
  798. * @req: setup request
  799. */
  800. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  801. {
  802. char msg[DBG_DATA_MSG];
  803. if (req != NULL) {
  804. scnprintf(msg, sizeof(msg),
  805. "%02X %02X %04X %04X %d", req->bRequestType,
  806. req->bRequest, le16_to_cpu(req->wValue),
  807. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  808. dbg_print(addr, "SETUP", 0, msg);
  809. }
  810. }
  811. /**
  812. * show_events: displays the event buffer
  813. *
  814. * Check "device.h" for details
  815. */
  816. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  817. char *buf)
  818. {
  819. unsigned long flags;
  820. unsigned i, j, n = 0;
  821. dbg_trace("[%s] %p\n", __func__, buf);
  822. if (attr == NULL || buf == NULL) {
  823. dev_err(dev, "[%s] EINVAL\n", __func__);
  824. return 0;
  825. }
  826. read_lock_irqsave(&dbg_data.lck, flags);
  827. i = dbg_data.idx;
  828. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  829. n += strlen(dbg_data.buf[i]);
  830. if (n >= PAGE_SIZE) {
  831. n -= strlen(dbg_data.buf[i]);
  832. break;
  833. }
  834. }
  835. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  836. j += scnprintf(buf + j, PAGE_SIZE - j,
  837. "%s", dbg_data.buf[i]);
  838. read_unlock_irqrestore(&dbg_data.lck, flags);
  839. return n;
  840. }
  841. /**
  842. * store_events: configure if events are going to be also printed to console
  843. *
  844. * Check "device.h" for details
  845. */
  846. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  847. const char *buf, size_t count)
  848. {
  849. unsigned tty;
  850. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  851. if (attr == NULL || buf == NULL) {
  852. dev_err(dev, "[%s] EINVAL\n", __func__);
  853. goto done;
  854. }
  855. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  856. dev_err(dev, "<1|0>: enable|disable console log\n");
  857. goto done;
  858. }
  859. dbg_data.tty = tty;
  860. dev_info(dev, "tty = %u", dbg_data.tty);
  861. done:
  862. return count;
  863. }
  864. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  865. /**
  866. * show_inters: interrupt status, enable status and historic
  867. *
  868. * Check "device.h" for details
  869. */
  870. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  871. char *buf)
  872. {
  873. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  874. unsigned long flags;
  875. u32 intr;
  876. unsigned i, j, n = 0;
  877. dbg_trace("[%s] %p\n", __func__, buf);
  878. if (attr == NULL || buf == NULL) {
  879. dev_err(dev, "[%s] EINVAL\n", __func__);
  880. return 0;
  881. }
  882. spin_lock_irqsave(udc->lock, flags);
  883. n += scnprintf(buf + n, PAGE_SIZE - n,
  884. "status = %08x\n", hw_read_intr_status());
  885. n += scnprintf(buf + n, PAGE_SIZE - n,
  886. "enable = %08x\n", hw_read_intr_enable());
  887. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  888. isr_statistics.test);
  889. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  890. isr_statistics.ui);
  891. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  892. isr_statistics.uei);
  893. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  894. isr_statistics.pci);
  895. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  896. isr_statistics.uri);
  897. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  898. isr_statistics.sli);
  899. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  900. isr_statistics.none);
  901. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  902. isr_statistics.hndl.cnt);
  903. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  904. i &= ISR_MASK;
  905. intr = isr_statistics.hndl.buf[i];
  906. if (USBi_UI & intr)
  907. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  908. intr &= ~USBi_UI;
  909. if (USBi_UEI & intr)
  910. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  911. intr &= ~USBi_UEI;
  912. if (USBi_PCI & intr)
  913. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  914. intr &= ~USBi_PCI;
  915. if (USBi_URI & intr)
  916. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  917. intr &= ~USBi_URI;
  918. if (USBi_SLI & intr)
  919. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  920. intr &= ~USBi_SLI;
  921. if (intr)
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  923. if (isr_statistics.hndl.buf[i])
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  925. }
  926. spin_unlock_irqrestore(udc->lock, flags);
  927. return n;
  928. }
  929. /**
  930. * store_inters: enable & force or disable an individual interrutps
  931. * (to be used for test purposes only)
  932. *
  933. * Check "device.h" for details
  934. */
  935. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  936. const char *buf, size_t count)
  937. {
  938. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  939. unsigned long flags;
  940. unsigned en, bit;
  941. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  942. if (attr == NULL || buf == NULL) {
  943. dev_err(dev, "[%s] EINVAL\n", __func__);
  944. goto done;
  945. }
  946. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  947. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  948. goto done;
  949. }
  950. spin_lock_irqsave(udc->lock, flags);
  951. if (en) {
  952. if (hw_intr_force(bit))
  953. dev_err(dev, "invalid bit number\n");
  954. else
  955. isr_statistics.test++;
  956. } else {
  957. if (hw_intr_clear(bit))
  958. dev_err(dev, "invalid bit number\n");
  959. }
  960. spin_unlock_irqrestore(udc->lock, flags);
  961. done:
  962. return count;
  963. }
  964. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  965. /**
  966. * show_port_test: reads port test mode
  967. *
  968. * Check "device.h" for details
  969. */
  970. static ssize_t show_port_test(struct device *dev,
  971. struct device_attribute *attr, char *buf)
  972. {
  973. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  974. unsigned long flags;
  975. unsigned mode;
  976. dbg_trace("[%s] %p\n", __func__, buf);
  977. if (attr == NULL || buf == NULL) {
  978. dev_err(dev, "[%s] EINVAL\n", __func__);
  979. return 0;
  980. }
  981. spin_lock_irqsave(udc->lock, flags);
  982. mode = hw_port_test_get();
  983. spin_unlock_irqrestore(udc->lock, flags);
  984. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  985. }
  986. /**
  987. * store_port_test: writes port test mode
  988. *
  989. * Check "device.h" for details
  990. */
  991. static ssize_t store_port_test(struct device *dev,
  992. struct device_attribute *attr,
  993. const char *buf, size_t count)
  994. {
  995. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  996. unsigned long flags;
  997. unsigned mode;
  998. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  999. if (attr == NULL || buf == NULL) {
  1000. dev_err(dev, "[%s] EINVAL\n", __func__);
  1001. goto done;
  1002. }
  1003. if (sscanf(buf, "%u", &mode) != 1) {
  1004. dev_err(dev, "<mode>: set port test mode");
  1005. goto done;
  1006. }
  1007. spin_lock_irqsave(udc->lock, flags);
  1008. if (hw_port_test_set(mode))
  1009. dev_err(dev, "invalid mode\n");
  1010. spin_unlock_irqrestore(udc->lock, flags);
  1011. done:
  1012. return count;
  1013. }
  1014. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1015. show_port_test, store_port_test);
  1016. /**
  1017. * show_qheads: DMA contents of all queue heads
  1018. *
  1019. * Check "device.h" for details
  1020. */
  1021. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1022. char *buf)
  1023. {
  1024. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1025. unsigned long flags;
  1026. unsigned i, j, n = 0;
  1027. dbg_trace("[%s] %p\n", __func__, buf);
  1028. if (attr == NULL || buf == NULL) {
  1029. dev_err(dev, "[%s] EINVAL\n", __func__);
  1030. return 0;
  1031. }
  1032. spin_lock_irqsave(udc->lock, flags);
  1033. for (i = 0; i < hw_ep_max/2; i++) {
  1034. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1035. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1036. n += scnprintf(buf + n, PAGE_SIZE - n,
  1037. "EP=%02i: RX=%08X TX=%08X\n",
  1038. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1039. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1040. n += scnprintf(buf + n, PAGE_SIZE - n,
  1041. " %04X: %08X %08X\n", j,
  1042. *((u32 *)mEpRx->qh.ptr + j),
  1043. *((u32 *)mEpTx->qh.ptr + j));
  1044. }
  1045. }
  1046. spin_unlock_irqrestore(udc->lock, flags);
  1047. return n;
  1048. }
  1049. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1050. /**
  1051. * show_registers: dumps all registers
  1052. *
  1053. * Check "device.h" for details
  1054. */
  1055. #define DUMP_ENTRIES 512
  1056. static ssize_t show_registers(struct device *dev,
  1057. struct device_attribute *attr, char *buf)
  1058. {
  1059. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1060. unsigned long flags;
  1061. u32 *dump;
  1062. unsigned i, k, n = 0;
  1063. dbg_trace("[%s] %p\n", __func__, buf);
  1064. if (attr == NULL || buf == NULL) {
  1065. dev_err(dev, "[%s] EINVAL\n", __func__);
  1066. return 0;
  1067. }
  1068. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1069. if (!dump) {
  1070. dev_err(dev, "%s: out of memory\n", __func__);
  1071. return 0;
  1072. }
  1073. spin_lock_irqsave(udc->lock, flags);
  1074. k = hw_register_read(dump, DUMP_ENTRIES);
  1075. spin_unlock_irqrestore(udc->lock, flags);
  1076. for (i = 0; i < k; i++) {
  1077. n += scnprintf(buf + n, PAGE_SIZE - n,
  1078. "reg[0x%04X] = 0x%08X\n",
  1079. i * (unsigned)sizeof(u32), dump[i]);
  1080. }
  1081. kfree(dump);
  1082. return n;
  1083. }
  1084. /**
  1085. * store_registers: writes value to register address
  1086. *
  1087. * Check "device.h" for details
  1088. */
  1089. static ssize_t store_registers(struct device *dev,
  1090. struct device_attribute *attr,
  1091. const char *buf, size_t count)
  1092. {
  1093. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1094. unsigned long addr, data, flags;
  1095. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1096. if (attr == NULL || buf == NULL) {
  1097. dev_err(dev, "[%s] EINVAL\n", __func__);
  1098. goto done;
  1099. }
  1100. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1101. dev_err(dev, "<addr> <data>: write data to register address");
  1102. goto done;
  1103. }
  1104. spin_lock_irqsave(udc->lock, flags);
  1105. if (hw_register_write(addr, data))
  1106. dev_err(dev, "invalid address range\n");
  1107. spin_unlock_irqrestore(udc->lock, flags);
  1108. done:
  1109. return count;
  1110. }
  1111. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1112. show_registers, store_registers);
  1113. /**
  1114. * show_requests: DMA contents of all requests currently queued (all endpts)
  1115. *
  1116. * Check "device.h" for details
  1117. */
  1118. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1119. char *buf)
  1120. {
  1121. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1122. unsigned long flags;
  1123. struct list_head *ptr = NULL;
  1124. struct ci13xxx_req *req = NULL;
  1125. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1126. dbg_trace("[%s] %p\n", __func__, buf);
  1127. if (attr == NULL || buf == NULL) {
  1128. dev_err(dev, "[%s] EINVAL\n", __func__);
  1129. return 0;
  1130. }
  1131. spin_lock_irqsave(udc->lock, flags);
  1132. for (i = 0; i < hw_ep_max; i++)
  1133. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1134. {
  1135. req = list_entry(ptr, struct ci13xxx_req, queue);
  1136. n += scnprintf(buf + n, PAGE_SIZE - n,
  1137. "EP=%02i: TD=%08X %s\n",
  1138. i % hw_ep_max/2, (u32)req->dma,
  1139. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1140. for (j = 0; j < qSize; j++)
  1141. n += scnprintf(buf + n, PAGE_SIZE - n,
  1142. " %04X: %08X\n", j,
  1143. *((u32 *)req->ptr + j));
  1144. }
  1145. spin_unlock_irqrestore(udc->lock, flags);
  1146. return n;
  1147. }
  1148. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1149. /**
  1150. * dbg_create_files: initializes the attribute interface
  1151. * @dev: device
  1152. *
  1153. * This function returns an error code
  1154. */
  1155. __maybe_unused static int dbg_create_files(struct device *dev)
  1156. {
  1157. int retval = 0;
  1158. if (dev == NULL)
  1159. return -EINVAL;
  1160. retval = device_create_file(dev, &dev_attr_device);
  1161. if (retval)
  1162. goto done;
  1163. retval = device_create_file(dev, &dev_attr_driver);
  1164. if (retval)
  1165. goto rm_device;
  1166. retval = device_create_file(dev, &dev_attr_events);
  1167. if (retval)
  1168. goto rm_driver;
  1169. retval = device_create_file(dev, &dev_attr_inters);
  1170. if (retval)
  1171. goto rm_events;
  1172. retval = device_create_file(dev, &dev_attr_port_test);
  1173. if (retval)
  1174. goto rm_inters;
  1175. retval = device_create_file(dev, &dev_attr_qheads);
  1176. if (retval)
  1177. goto rm_port_test;
  1178. retval = device_create_file(dev, &dev_attr_registers);
  1179. if (retval)
  1180. goto rm_qheads;
  1181. retval = device_create_file(dev, &dev_attr_requests);
  1182. if (retval)
  1183. goto rm_registers;
  1184. return 0;
  1185. rm_registers:
  1186. device_remove_file(dev, &dev_attr_registers);
  1187. rm_qheads:
  1188. device_remove_file(dev, &dev_attr_qheads);
  1189. rm_port_test:
  1190. device_remove_file(dev, &dev_attr_port_test);
  1191. rm_inters:
  1192. device_remove_file(dev, &dev_attr_inters);
  1193. rm_events:
  1194. device_remove_file(dev, &dev_attr_events);
  1195. rm_driver:
  1196. device_remove_file(dev, &dev_attr_driver);
  1197. rm_device:
  1198. device_remove_file(dev, &dev_attr_device);
  1199. done:
  1200. return retval;
  1201. }
  1202. /**
  1203. * dbg_remove_files: destroys the attribute interface
  1204. * @dev: device
  1205. *
  1206. * This function returns an error code
  1207. */
  1208. __maybe_unused static int dbg_remove_files(struct device *dev)
  1209. {
  1210. if (dev == NULL)
  1211. return -EINVAL;
  1212. device_remove_file(dev, &dev_attr_requests);
  1213. device_remove_file(dev, &dev_attr_registers);
  1214. device_remove_file(dev, &dev_attr_qheads);
  1215. device_remove_file(dev, &dev_attr_port_test);
  1216. device_remove_file(dev, &dev_attr_inters);
  1217. device_remove_file(dev, &dev_attr_events);
  1218. device_remove_file(dev, &dev_attr_driver);
  1219. device_remove_file(dev, &dev_attr_device);
  1220. return 0;
  1221. }
  1222. /******************************************************************************
  1223. * UTIL block
  1224. *****************************************************************************/
  1225. /**
  1226. * _usb_addr: calculates endpoint address from direction & number
  1227. * @ep: endpoint
  1228. */
  1229. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1230. {
  1231. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1232. }
  1233. /**
  1234. * _hardware_queue: configures a request at hardware level
  1235. * @gadget: gadget
  1236. * @mEp: endpoint
  1237. *
  1238. * This function returns an error code
  1239. */
  1240. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1241. {
  1242. unsigned i;
  1243. int ret = 0;
  1244. unsigned length = mReq->req.length;
  1245. trace("%p, %p", mEp, mReq);
  1246. /* don't queue twice */
  1247. if (mReq->req.status == -EALREADY)
  1248. return -EALREADY;
  1249. mReq->req.status = -EALREADY;
  1250. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1251. mReq->req.dma = \
  1252. dma_map_single(mEp->device, mReq->req.buf,
  1253. length, mEp->dir ? DMA_TO_DEVICE :
  1254. DMA_FROM_DEVICE);
  1255. if (mReq->req.dma == 0)
  1256. return -ENOMEM;
  1257. mReq->map = 1;
  1258. }
  1259. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1260. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1261. &mReq->zdma);
  1262. if (mReq->zptr == NULL) {
  1263. if (mReq->map) {
  1264. dma_unmap_single(mEp->device, mReq->req.dma,
  1265. length, mEp->dir ? DMA_TO_DEVICE :
  1266. DMA_FROM_DEVICE);
  1267. mReq->req.dma = DMA_ADDR_INVALID;
  1268. mReq->map = 0;
  1269. }
  1270. return -ENOMEM;
  1271. }
  1272. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1273. mReq->zptr->next = TD_TERMINATE;
  1274. mReq->zptr->token = TD_STATUS_ACTIVE;
  1275. if (!mReq->req.no_interrupt)
  1276. mReq->zptr->token |= TD_IOC;
  1277. }
  1278. /*
  1279. * TD configuration
  1280. * TODO - handle requests which spawns into several TDs
  1281. */
  1282. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1283. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1284. mReq->ptr->token &= TD_TOTAL_BYTES;
  1285. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1286. if (mReq->zptr) {
  1287. mReq->ptr->next = mReq->zdma;
  1288. } else {
  1289. mReq->ptr->next = TD_TERMINATE;
  1290. if (!mReq->req.no_interrupt)
  1291. mReq->ptr->token |= TD_IOC;
  1292. }
  1293. mReq->ptr->page[0] = mReq->req.dma;
  1294. for (i = 1; i < 5; i++)
  1295. mReq->ptr->page[i] =
  1296. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1297. if (!list_empty(&mEp->qh.queue)) {
  1298. struct ci13xxx_req *mReqPrev;
  1299. int n = hw_ep_bit(mEp->num, mEp->dir);
  1300. int tmp_stat;
  1301. mReqPrev = list_entry(mEp->qh.queue.prev,
  1302. struct ci13xxx_req, queue);
  1303. if (mReqPrev->zptr)
  1304. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1305. else
  1306. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1307. wmb();
  1308. if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  1309. goto done;
  1310. do {
  1311. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1312. tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
  1313. } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
  1314. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
  1315. if (tmp_stat)
  1316. goto done;
  1317. }
  1318. /* QH configuration */
  1319. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1320. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1321. mEp->qh.ptr->cap |= QH_ZLT;
  1322. wmb(); /* synchronize before ep prime */
  1323. ret = hw_ep_prime(mEp->num, mEp->dir,
  1324. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1325. done:
  1326. return ret;
  1327. }
  1328. /**
  1329. * _hardware_dequeue: handles a request at hardware level
  1330. * @gadget: gadget
  1331. * @mEp: endpoint
  1332. *
  1333. * This function returns an error code
  1334. */
  1335. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1336. {
  1337. trace("%p, %p", mEp, mReq);
  1338. if (mReq->req.status != -EALREADY)
  1339. return -EINVAL;
  1340. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1341. return -EBUSY;
  1342. if (mReq->zptr) {
  1343. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1344. return -EBUSY;
  1345. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1346. mReq->zptr = NULL;
  1347. }
  1348. mReq->req.status = 0;
  1349. if (mReq->map) {
  1350. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1351. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1352. mReq->req.dma = DMA_ADDR_INVALID;
  1353. mReq->map = 0;
  1354. }
  1355. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1356. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1357. mReq->req.status = -1;
  1358. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1359. mReq->req.status = -1;
  1360. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1361. mReq->req.status = -1;
  1362. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1363. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1364. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1365. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1366. return mReq->req.actual;
  1367. }
  1368. /**
  1369. * _ep_nuke: dequeues all endpoint requests
  1370. * @mEp: endpoint
  1371. *
  1372. * This function returns an error code
  1373. * Caller must hold lock
  1374. */
  1375. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1376. __releases(mEp->lock)
  1377. __acquires(mEp->lock)
  1378. {
  1379. trace("%p", mEp);
  1380. if (mEp == NULL)
  1381. return -EINVAL;
  1382. hw_ep_flush(mEp->num, mEp->dir);
  1383. while (!list_empty(&mEp->qh.queue)) {
  1384. /* pop oldest request */
  1385. struct ci13xxx_req *mReq = \
  1386. list_entry(mEp->qh.queue.next,
  1387. struct ci13xxx_req, queue);
  1388. list_del_init(&mReq->queue);
  1389. mReq->req.status = -ESHUTDOWN;
  1390. if (mReq->req.complete != NULL) {
  1391. spin_unlock(mEp->lock);
  1392. mReq->req.complete(&mEp->ep, &mReq->req);
  1393. spin_lock(mEp->lock);
  1394. }
  1395. }
  1396. return 0;
  1397. }
  1398. /**
  1399. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1400. * @gadget: gadget
  1401. *
  1402. * This function returns an error code
  1403. */
  1404. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1405. {
  1406. struct usb_ep *ep;
  1407. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1408. unsigned long flags;
  1409. trace("%p", gadget);
  1410. if (gadget == NULL)
  1411. return -EINVAL;
  1412. spin_lock_irqsave(udc->lock, flags);
  1413. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1414. udc->remote_wakeup = 0;
  1415. udc->suspended = 0;
  1416. spin_unlock_irqrestore(udc->lock, flags);
  1417. /* flush all endpoints */
  1418. gadget_for_each_ep(ep, gadget) {
  1419. usb_ep_fifo_flush(ep);
  1420. }
  1421. usb_ep_fifo_flush(&udc->ep0out.ep);
  1422. usb_ep_fifo_flush(&udc->ep0in.ep);
  1423. udc->driver->disconnect(gadget);
  1424. /* make sure to disable all endpoints */
  1425. gadget_for_each_ep(ep, gadget) {
  1426. usb_ep_disable(ep);
  1427. }
  1428. if (udc->status != NULL) {
  1429. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1430. udc->status = NULL;
  1431. }
  1432. return 0;
  1433. }
  1434. /******************************************************************************
  1435. * ISR block
  1436. *****************************************************************************/
  1437. /**
  1438. * isr_reset_handler: USB reset interrupt handler
  1439. * @udc: UDC device
  1440. *
  1441. * This function resets USB engine after a bus reset occurred
  1442. */
  1443. static void isr_reset_handler(struct ci13xxx *udc)
  1444. __releases(udc->lock)
  1445. __acquires(udc->lock)
  1446. {
  1447. int retval;
  1448. trace("%p", udc);
  1449. if (udc == NULL) {
  1450. err("EINVAL");
  1451. return;
  1452. }
  1453. dbg_event(0xFF, "BUS RST", 0);
  1454. spin_unlock(udc->lock);
  1455. retval = _gadget_stop_activity(&udc->gadget);
  1456. if (retval)
  1457. goto done;
  1458. retval = hw_usb_reset();
  1459. if (retval)
  1460. goto done;
  1461. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1462. if (udc->status == NULL)
  1463. retval = -ENOMEM;
  1464. spin_lock(udc->lock);
  1465. done:
  1466. if (retval)
  1467. err("error: %i", retval);
  1468. }
  1469. /**
  1470. * isr_get_status_complete: get_status request complete function
  1471. * @ep: endpoint
  1472. * @req: request handled
  1473. *
  1474. * Caller must release lock
  1475. */
  1476. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1477. {
  1478. trace("%p, %p", ep, req);
  1479. if (ep == NULL || req == NULL) {
  1480. err("EINVAL");
  1481. return;
  1482. }
  1483. kfree(req->buf);
  1484. usb_ep_free_request(ep, req);
  1485. }
  1486. /**
  1487. * isr_get_status_response: get_status request response
  1488. * @udc: udc struct
  1489. * @setup: setup request packet
  1490. *
  1491. * This function returns an error code
  1492. */
  1493. static int isr_get_status_response(struct ci13xxx *udc,
  1494. struct usb_ctrlrequest *setup)
  1495. __releases(mEp->lock)
  1496. __acquires(mEp->lock)
  1497. {
  1498. struct ci13xxx_ep *mEp = &udc->ep0in;
  1499. struct usb_request *req = NULL;
  1500. gfp_t gfp_flags = GFP_ATOMIC;
  1501. int dir, num, retval;
  1502. trace("%p, %p", mEp, setup);
  1503. if (mEp == NULL || setup == NULL)
  1504. return -EINVAL;
  1505. spin_unlock(mEp->lock);
  1506. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1507. spin_lock(mEp->lock);
  1508. if (req == NULL)
  1509. return -ENOMEM;
  1510. req->complete = isr_get_status_complete;
  1511. req->length = 2;
  1512. req->buf = kzalloc(req->length, gfp_flags);
  1513. if (req->buf == NULL) {
  1514. retval = -ENOMEM;
  1515. goto err_free_req;
  1516. }
  1517. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1518. /* Assume that device is bus powered for now. */
  1519. *((u16 *)req->buf) = _udc->remote_wakeup << 1;
  1520. retval = 0;
  1521. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1522. == USB_RECIP_ENDPOINT) {
  1523. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1524. TX : RX;
  1525. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1526. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1527. }
  1528. /* else do nothing; reserved for future use */
  1529. spin_unlock(mEp->lock);
  1530. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1531. spin_lock(mEp->lock);
  1532. if (retval)
  1533. goto err_free_buf;
  1534. return 0;
  1535. err_free_buf:
  1536. kfree(req->buf);
  1537. err_free_req:
  1538. spin_unlock(mEp->lock);
  1539. usb_ep_free_request(&mEp->ep, req);
  1540. spin_lock(mEp->lock);
  1541. return retval;
  1542. }
  1543. /**
  1544. * isr_setup_status_complete: setup_status request complete function
  1545. * @ep: endpoint
  1546. * @req: request handled
  1547. *
  1548. * Caller must release lock. Put the port in test mode if test mode
  1549. * feature is selected.
  1550. */
  1551. static void
  1552. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1553. {
  1554. struct ci13xxx *udc = req->context;
  1555. unsigned long flags;
  1556. trace("%p, %p", ep, req);
  1557. spin_lock_irqsave(udc->lock, flags);
  1558. if (udc->test_mode)
  1559. hw_port_test_set(udc->test_mode);
  1560. spin_unlock_irqrestore(udc->lock, flags);
  1561. }
  1562. /**
  1563. * isr_setup_status_phase: queues the status phase of a setup transation
  1564. * @udc: udc struct
  1565. *
  1566. * This function returns an error code
  1567. */
  1568. static int isr_setup_status_phase(struct ci13xxx *udc)
  1569. __releases(mEp->lock)
  1570. __acquires(mEp->lock)
  1571. {
  1572. int retval;
  1573. struct ci13xxx_ep *mEp;
  1574. trace("%p", udc);
  1575. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1576. udc->status->context = udc;
  1577. udc->status->complete = isr_setup_status_complete;
  1578. spin_unlock(mEp->lock);
  1579. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1580. spin_lock(mEp->lock);
  1581. return retval;
  1582. }
  1583. /**
  1584. * isr_tr_complete_low: transaction complete low level handler
  1585. * @mEp: endpoint
  1586. *
  1587. * This function returns an error code
  1588. * Caller must hold lock
  1589. */
  1590. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1591. __releases(mEp->lock)
  1592. __acquires(mEp->lock)
  1593. {
  1594. struct ci13xxx_req *mReq, *mReqTemp;
  1595. struct ci13xxx_ep *mEpTemp = mEp;
  1596. int uninitialized_var(retval);
  1597. trace("%p", mEp);
  1598. if (list_empty(&mEp->qh.queue))
  1599. return -EINVAL;
  1600. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1601. queue) {
  1602. retval = _hardware_dequeue(mEp, mReq);
  1603. if (retval < 0)
  1604. break;
  1605. list_del_init(&mReq->queue);
  1606. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1607. if (mReq->req.complete != NULL) {
  1608. spin_unlock(mEp->lock);
  1609. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1610. mReq->req.length)
  1611. mEpTemp = &_udc->ep0in;
  1612. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1613. spin_lock(mEp->lock);
  1614. }
  1615. }
  1616. if (retval == -EBUSY)
  1617. retval = 0;
  1618. if (retval < 0)
  1619. dbg_event(_usb_addr(mEp), "DONE", retval);
  1620. return retval;
  1621. }
  1622. /**
  1623. * isr_tr_complete_handler: transaction complete interrupt handler
  1624. * @udc: UDC descriptor
  1625. *
  1626. * This function handles traffic events
  1627. */
  1628. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1629. __releases(udc->lock)
  1630. __acquires(udc->lock)
  1631. {
  1632. unsigned i;
  1633. u8 tmode = 0;
  1634. trace("%p", udc);
  1635. if (udc == NULL) {
  1636. err("EINVAL");
  1637. return;
  1638. }
  1639. for (i = 0; i < hw_ep_max; i++) {
  1640. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1641. int type, num, dir, err = -EINVAL;
  1642. struct usb_ctrlrequest req;
  1643. if (mEp->desc == NULL)
  1644. continue; /* not configured */
  1645. if (hw_test_and_clear_complete(i)) {
  1646. err = isr_tr_complete_low(mEp);
  1647. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1648. if (err > 0) /* needs status phase */
  1649. err = isr_setup_status_phase(udc);
  1650. if (err < 0) {
  1651. dbg_event(_usb_addr(mEp),
  1652. "ERROR", err);
  1653. spin_unlock(udc->lock);
  1654. if (usb_ep_set_halt(&mEp->ep))
  1655. err("error: ep_set_halt");
  1656. spin_lock(udc->lock);
  1657. }
  1658. }
  1659. }
  1660. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1661. !hw_test_and_clear_setup_status(i))
  1662. continue;
  1663. if (i != 0) {
  1664. warn("ctrl traffic received at endpoint");
  1665. continue;
  1666. }
  1667. /*
  1668. * Flush data and handshake transactions of previous
  1669. * setup packet.
  1670. */
  1671. _ep_nuke(&udc->ep0out);
  1672. _ep_nuke(&udc->ep0in);
  1673. /* read_setup_packet */
  1674. do {
  1675. hw_test_and_set_setup_guard();
  1676. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1677. } while (!hw_test_and_clear_setup_guard());
  1678. type = req.bRequestType;
  1679. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1680. dbg_setup(_usb_addr(mEp), &req);
  1681. switch (req.bRequest) {
  1682. case USB_REQ_CLEAR_FEATURE:
  1683. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1684. le16_to_cpu(req.wValue) ==
  1685. USB_ENDPOINT_HALT) {
  1686. if (req.wLength != 0)
  1687. break;
  1688. num = le16_to_cpu(req.wIndex);
  1689. dir = num & USB_ENDPOINT_DIR_MASK;
  1690. num &= USB_ENDPOINT_NUMBER_MASK;
  1691. if (dir) /* TX */
  1692. num += hw_ep_max/2;
  1693. if (!udc->ci13xxx_ep[num].wedge) {
  1694. spin_unlock(udc->lock);
  1695. err = usb_ep_clear_halt(
  1696. &udc->ci13xxx_ep[num].ep);
  1697. spin_lock(udc->lock);
  1698. if (err)
  1699. break;
  1700. }
  1701. err = isr_setup_status_phase(udc);
  1702. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1703. le16_to_cpu(req.wValue) ==
  1704. USB_DEVICE_REMOTE_WAKEUP) {
  1705. if (req.wLength != 0)
  1706. break;
  1707. udc->remote_wakeup = 0;
  1708. err = isr_setup_status_phase(udc);
  1709. } else {
  1710. goto delegate;
  1711. }
  1712. break;
  1713. case USB_REQ_GET_STATUS:
  1714. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1715. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1716. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1717. goto delegate;
  1718. if (le16_to_cpu(req.wLength) != 2 ||
  1719. le16_to_cpu(req.wValue) != 0)
  1720. break;
  1721. err = isr_get_status_response(udc, &req);
  1722. break;
  1723. case USB_REQ_SET_ADDRESS:
  1724. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1725. goto delegate;
  1726. if (le16_to_cpu(req.wLength) != 0 ||
  1727. le16_to_cpu(req.wIndex) != 0)
  1728. break;
  1729. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1730. if (err)
  1731. break;
  1732. err = isr_setup_status_phase(udc);
  1733. break;
  1734. case USB_REQ_SET_FEATURE:
  1735. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1736. le16_to_cpu(req.wValue) ==
  1737. USB_ENDPOINT_HALT) {
  1738. if (req.wLength != 0)
  1739. break;
  1740. num = le16_to_cpu(req.wIndex);
  1741. dir = num & USB_ENDPOINT_DIR_MASK;
  1742. num &= USB_ENDPOINT_NUMBER_MASK;
  1743. if (dir) /* TX */
  1744. num += hw_ep_max/2;
  1745. spin_unlock(udc->lock);
  1746. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1747. spin_lock(udc->lock);
  1748. if (!err)
  1749. isr_setup_status_phase(udc);
  1750. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1751. if (req.wLength != 0)
  1752. break;
  1753. switch (le16_to_cpu(req.wValue)) {
  1754. case USB_DEVICE_REMOTE_WAKEUP:
  1755. udc->remote_wakeup = 1;
  1756. err = isr_setup_status_phase(udc);
  1757. break;
  1758. case USB_DEVICE_TEST_MODE:
  1759. tmode = le16_to_cpu(req.wIndex) >> 8;
  1760. switch (tmode) {
  1761. case TEST_J:
  1762. case TEST_K:
  1763. case TEST_SE0_NAK:
  1764. case TEST_PACKET:
  1765. case TEST_FORCE_EN:
  1766. udc->test_mode = tmode;
  1767. err = isr_setup_status_phase(
  1768. udc);
  1769. break;
  1770. default:
  1771. break;
  1772. }
  1773. default:
  1774. goto delegate;
  1775. }
  1776. } else {
  1777. goto delegate;
  1778. }
  1779. break;
  1780. default:
  1781. delegate:
  1782. if (req.wLength == 0) /* no data phase */
  1783. udc->ep0_dir = TX;
  1784. spin_unlock(udc->lock);
  1785. err = udc->driver->setup(&udc->gadget, &req);
  1786. spin_lock(udc->lock);
  1787. break;
  1788. }
  1789. if (err < 0) {
  1790. dbg_event(_usb_addr(mEp), "ERROR", err);
  1791. spin_unlock(udc->lock);
  1792. if (usb_ep_set_halt(&mEp->ep))
  1793. err("error: ep_set_halt");
  1794. spin_lock(udc->lock);
  1795. }
  1796. }
  1797. }
  1798. /******************************************************************************
  1799. * ENDPT block
  1800. *****************************************************************************/
  1801. /**
  1802. * ep_enable: configure endpoint, making it usable
  1803. *
  1804. * Check usb_ep_enable() at "usb_gadget.h" for details
  1805. */
  1806. static int ep_enable(struct usb_ep *ep,
  1807. const struct usb_endpoint_descriptor *desc)
  1808. {
  1809. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1810. int retval = 0;
  1811. unsigned long flags;
  1812. trace("%p, %p", ep, desc);
  1813. if (ep == NULL || desc == NULL)
  1814. return -EINVAL;
  1815. spin_lock_irqsave(mEp->lock, flags);
  1816. /* only internal SW should enable ctrl endpts */
  1817. mEp->desc = desc;
  1818. if (!list_empty(&mEp->qh.queue))
  1819. warn("enabling a non-empty endpoint!");
  1820. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1821. mEp->num = usb_endpoint_num(desc);
  1822. mEp->type = usb_endpoint_type(desc);
  1823. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1824. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1825. mEp->qh.ptr->cap = 0;
  1826. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1827. mEp->qh.ptr->cap |= QH_IOS;
  1828. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1829. mEp->qh.ptr->cap &= ~QH_MULT;
  1830. else
  1831. mEp->qh.ptr->cap &= ~QH_ZLT;
  1832. mEp->qh.ptr->cap |=
  1833. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1834. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1835. /*
  1836. * Enable endpoints in the HW other than ep0 as ep0
  1837. * is always enabled
  1838. */
  1839. if (mEp->num)
  1840. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1841. spin_unlock_irqrestore(mEp->lock, flags);
  1842. return retval;
  1843. }
  1844. /**
  1845. * ep_disable: endpoint is no longer usable
  1846. *
  1847. * Check usb_ep_disable() at "usb_gadget.h" for details
  1848. */
  1849. static int ep_disable(struct usb_ep *ep)
  1850. {
  1851. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1852. int direction, retval = 0;
  1853. unsigned long flags;
  1854. trace("%p", ep);
  1855. if (ep == NULL)
  1856. return -EINVAL;
  1857. else if (mEp->desc == NULL)
  1858. return -EBUSY;
  1859. spin_lock_irqsave(mEp->lock, flags);
  1860. /* only internal SW should disable ctrl endpts */
  1861. direction = mEp->dir;
  1862. do {
  1863. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1864. retval |= _ep_nuke(mEp);
  1865. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1866. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1867. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1868. } while (mEp->dir != direction);
  1869. mEp->desc = NULL;
  1870. spin_unlock_irqrestore(mEp->lock, flags);
  1871. return retval;
  1872. }
  1873. /**
  1874. * ep_alloc_request: allocate a request object to use with this endpoint
  1875. *
  1876. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1877. */
  1878. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1879. {
  1880. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1881. struct ci13xxx_req *mReq = NULL;
  1882. trace("%p, %i", ep, gfp_flags);
  1883. if (ep == NULL) {
  1884. err("EINVAL");
  1885. return NULL;
  1886. }
  1887. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1888. if (mReq != NULL) {
  1889. INIT_LIST_HEAD(&mReq->queue);
  1890. mReq->req.dma = DMA_ADDR_INVALID;
  1891. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1892. &mReq->dma);
  1893. if (mReq->ptr == NULL) {
  1894. kfree(mReq);
  1895. mReq = NULL;
  1896. }
  1897. }
  1898. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1899. return (mReq == NULL) ? NULL : &mReq->req;
  1900. }
  1901. /**
  1902. * ep_free_request: frees a request object
  1903. *
  1904. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1905. */
  1906. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1907. {
  1908. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1909. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1910. unsigned long flags;
  1911. trace("%p, %p", ep, req);
  1912. if (ep == NULL || req == NULL) {
  1913. err("EINVAL");
  1914. return;
  1915. } else if (!list_empty(&mReq->queue)) {
  1916. err("EBUSY");
  1917. return;
  1918. }
  1919. spin_lock_irqsave(mEp->lock, flags);
  1920. if (mReq->ptr)
  1921. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1922. kfree(mReq);
  1923. dbg_event(_usb_addr(mEp), "FREE", 0);
  1924. spin_unlock_irqrestore(mEp->lock, flags);
  1925. }
  1926. /**
  1927. * ep_queue: queues (submits) an I/O request to an endpoint
  1928. *
  1929. * Check usb_ep_queue()* at usb_gadget.h" for details
  1930. */
  1931. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1932. gfp_t __maybe_unused gfp_flags)
  1933. {
  1934. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1935. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1936. int retval = 0;
  1937. unsigned long flags;
  1938. trace("%p, %p, %X", ep, req, gfp_flags);
  1939. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1940. return -EINVAL;
  1941. spin_lock_irqsave(mEp->lock, flags);
  1942. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1943. if (req->length)
  1944. mEp = (_udc->ep0_dir == RX) ?
  1945. &_udc->ep0out : &_udc->ep0in;
  1946. if (!list_empty(&mEp->qh.queue)) {
  1947. _ep_nuke(mEp);
  1948. retval = -EOVERFLOW;
  1949. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1950. }
  1951. }
  1952. /* first nuke then test link, e.g. previous status has not sent */
  1953. if (!list_empty(&mReq->queue)) {
  1954. retval = -EBUSY;
  1955. err("request already in queue");
  1956. goto done;
  1957. }
  1958. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1959. req->length = (4 * CI13XXX_PAGE_SIZE);
  1960. retval = -EMSGSIZE;
  1961. warn("request length truncated");
  1962. }
  1963. dbg_queue(_usb_addr(mEp), req, retval);
  1964. /* push request */
  1965. mReq->req.status = -EINPROGRESS;
  1966. mReq->req.actual = 0;
  1967. retval = _hardware_enqueue(mEp, mReq);
  1968. if (retval == -EALREADY) {
  1969. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1970. retval = 0;
  1971. }
  1972. if (!retval)
  1973. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1974. done:
  1975. spin_unlock_irqrestore(mEp->lock, flags);
  1976. return retval;
  1977. }
  1978. /**
  1979. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1980. *
  1981. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1982. */
  1983. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1984. {
  1985. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1986. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1987. unsigned long flags;
  1988. trace("%p, %p", ep, req);
  1989. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1990. mEp->desc == NULL || list_empty(&mReq->queue) ||
  1991. list_empty(&mEp->qh.queue))
  1992. return -EINVAL;
  1993. spin_lock_irqsave(mEp->lock, flags);
  1994. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1995. hw_ep_flush(mEp->num, mEp->dir);
  1996. /* pop request */
  1997. list_del_init(&mReq->queue);
  1998. if (mReq->map) {
  1999. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2000. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2001. mReq->req.dma = DMA_ADDR_INVALID;
  2002. mReq->map = 0;
  2003. }
  2004. req->status = -ECONNRESET;
  2005. if (mReq->req.complete != NULL) {
  2006. spin_unlock(mEp->lock);
  2007. mReq->req.complete(&mEp->ep, &mReq->req);
  2008. spin_lock(mEp->lock);
  2009. }
  2010. spin_unlock_irqrestore(mEp->lock, flags);
  2011. return 0;
  2012. }
  2013. /**
  2014. * ep_set_halt: sets the endpoint halt feature
  2015. *
  2016. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2017. */
  2018. static int ep_set_halt(struct usb_ep *ep, int value)
  2019. {
  2020. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2021. int direction, retval = 0;
  2022. unsigned long flags;
  2023. trace("%p, %i", ep, value);
  2024. if (ep == NULL || mEp->desc == NULL)
  2025. return -EINVAL;
  2026. spin_lock_irqsave(mEp->lock, flags);
  2027. #ifndef STALL_IN
  2028. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2029. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2030. !list_empty(&mEp->qh.queue)) {
  2031. spin_unlock_irqrestore(mEp->lock, flags);
  2032. return -EAGAIN;
  2033. }
  2034. #endif
  2035. direction = mEp->dir;
  2036. do {
  2037. dbg_event(_usb_addr(mEp), "HALT", value);
  2038. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  2039. if (!value)
  2040. mEp->wedge = 0;
  2041. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2042. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2043. } while (mEp->dir != direction);
  2044. spin_unlock_irqrestore(mEp->lock, flags);
  2045. return retval;
  2046. }
  2047. /**
  2048. * ep_set_wedge: sets the halt feature and ignores clear requests
  2049. *
  2050. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2051. */
  2052. static int ep_set_wedge(struct usb_ep *ep)
  2053. {
  2054. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2055. unsigned long flags;
  2056. trace("%p", ep);
  2057. if (ep == NULL || mEp->desc == NULL)
  2058. return -EINVAL;
  2059. spin_lock_irqsave(mEp->lock, flags);
  2060. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2061. mEp->wedge = 1;
  2062. spin_unlock_irqrestore(mEp->lock, flags);
  2063. return usb_ep_set_halt(ep);
  2064. }
  2065. /**
  2066. * ep_fifo_flush: flushes contents of a fifo
  2067. *
  2068. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2069. */
  2070. static void ep_fifo_flush(struct usb_ep *ep)
  2071. {
  2072. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2073. unsigned long flags;
  2074. trace("%p", ep);
  2075. if (ep == NULL) {
  2076. err("%02X: -EINVAL", _usb_addr(mEp));
  2077. return;
  2078. }
  2079. spin_lock_irqsave(mEp->lock, flags);
  2080. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2081. hw_ep_flush(mEp->num, mEp->dir);
  2082. spin_unlock_irqrestore(mEp->lock, flags);
  2083. }
  2084. /**
  2085. * Endpoint-specific part of the API to the USB controller hardware
  2086. * Check "usb_gadget.h" for details
  2087. */
  2088. static const struct usb_ep_ops usb_ep_ops = {
  2089. .enable = ep_enable,
  2090. .disable = ep_disable,
  2091. .alloc_request = ep_alloc_request,
  2092. .free_request = ep_free_request,
  2093. .queue = ep_queue,
  2094. .dequeue = ep_dequeue,
  2095. .set_halt = ep_set_halt,
  2096. .set_wedge = ep_set_wedge,
  2097. .fifo_flush = ep_fifo_flush,
  2098. };
  2099. /******************************************************************************
  2100. * GADGET block
  2101. *****************************************************************************/
  2102. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2103. {
  2104. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2105. unsigned long flags;
  2106. int gadget_ready = 0;
  2107. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2108. return -EOPNOTSUPP;
  2109. spin_lock_irqsave(udc->lock, flags);
  2110. udc->vbus_active = is_active;
  2111. if (udc->driver)
  2112. gadget_ready = 1;
  2113. spin_unlock_irqrestore(udc->lock, flags);
  2114. if (gadget_ready) {
  2115. if (is_active) {
  2116. pm_runtime_get_sync(&_gadget->dev);
  2117. hw_device_reset(udc);
  2118. hw_device_state(udc->ep0out.qh.dma);
  2119. } else {
  2120. hw_device_state(0);
  2121. if (udc->udc_driver->notify_event)
  2122. udc->udc_driver->notify_event(udc,
  2123. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2124. _gadget_stop_activity(&udc->gadget);
  2125. pm_runtime_put_sync(&_gadget->dev);
  2126. }
  2127. }
  2128. return 0;
  2129. }
  2130. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2131. {
  2132. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2133. unsigned long flags;
  2134. int ret = 0;
  2135. trace();
  2136. spin_lock_irqsave(udc->lock, flags);
  2137. if (!udc->remote_wakeup) {
  2138. ret = -EOPNOTSUPP;
  2139. trace("remote wakeup feature is not enabled\n");
  2140. goto out;
  2141. }
  2142. if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
  2143. ret = -EINVAL;
  2144. trace("port is not suspended\n");
  2145. goto out;
  2146. }
  2147. hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2148. out:
  2149. spin_unlock_irqrestore(udc->lock, flags);
  2150. return ret;
  2151. }
  2152. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2153. {
  2154. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2155. if (udc->transceiver)
  2156. return otg_set_power(udc->transceiver, mA);
  2157. return -ENOTSUPP;
  2158. }
  2159. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2160. int (*bind)(struct usb_gadget *));
  2161. static int ci13xxx_stop(struct usb_gadget_driver *driver);
  2162. /**
  2163. * Device operations part of the API to the USB controller hardware,
  2164. * which don't involve endpoints (or i/o)
  2165. * Check "usb_gadget.h" for details
  2166. */
  2167. static const struct usb_gadget_ops usb_gadget_ops = {
  2168. .vbus_session = ci13xxx_vbus_session,
  2169. .wakeup = ci13xxx_wakeup,
  2170. .vbus_draw = ci13xxx_vbus_draw,
  2171. .start = ci13xxx_start,
  2172. .stop = ci13xxx_stop,
  2173. };
  2174. /**
  2175. * ci13xxx_start: register a gadget driver
  2176. * @driver: the driver being registered
  2177. * @bind: the driver's bind callback
  2178. *
  2179. * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
  2180. * Interrupts are enabled here.
  2181. */
  2182. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2183. int (*bind)(struct usb_gadget *))
  2184. {
  2185. struct ci13xxx *udc = _udc;
  2186. unsigned long flags;
  2187. int i, j;
  2188. int retval = -ENOMEM;
  2189. trace("%p", driver);
  2190. if (driver == NULL ||
  2191. bind == NULL ||
  2192. driver->setup == NULL ||
  2193. driver->disconnect == NULL ||
  2194. driver->suspend == NULL ||
  2195. driver->resume == NULL)
  2196. return -EINVAL;
  2197. else if (udc == NULL)
  2198. return -ENODEV;
  2199. else if (udc->driver != NULL)
  2200. return -EBUSY;
  2201. /* alloc resources */
  2202. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2203. sizeof(struct ci13xxx_qh),
  2204. 64, CI13XXX_PAGE_SIZE);
  2205. if (udc->qh_pool == NULL)
  2206. return -ENOMEM;
  2207. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2208. sizeof(struct ci13xxx_td),
  2209. 64, CI13XXX_PAGE_SIZE);
  2210. if (udc->td_pool == NULL) {
  2211. dma_pool_destroy(udc->qh_pool);
  2212. udc->qh_pool = NULL;
  2213. return -ENOMEM;
  2214. }
  2215. spin_lock_irqsave(udc->lock, flags);
  2216. info("hw_ep_max = %d", hw_ep_max);
  2217. udc->gadget.dev.driver = NULL;
  2218. retval = 0;
  2219. for (i = 0; i < hw_ep_max/2; i++) {
  2220. for (j = RX; j <= TX; j++) {
  2221. int k = i + j * hw_ep_max/2;
  2222. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2223. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2224. (j == TX) ? "in" : "out");
  2225. mEp->lock = udc->lock;
  2226. mEp->device = &udc->gadget.dev;
  2227. mEp->td_pool = udc->td_pool;
  2228. mEp->ep.name = mEp->name;
  2229. mEp->ep.ops = &usb_ep_ops;
  2230. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2231. INIT_LIST_HEAD(&mEp->qh.queue);
  2232. spin_unlock_irqrestore(udc->lock, flags);
  2233. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2234. &mEp->qh.dma);
  2235. spin_lock_irqsave(udc->lock, flags);
  2236. if (mEp->qh.ptr == NULL)
  2237. retval = -ENOMEM;
  2238. else
  2239. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2240. /* skip ep0 out and in endpoints */
  2241. if (i == 0)
  2242. continue;
  2243. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2244. }
  2245. }
  2246. if (retval)
  2247. goto done;
  2248. spin_unlock_irqrestore(udc->lock, flags);
  2249. udc->ep0out.ep.desc = &ctrl_endpt_out_desc;
  2250. retval = usb_ep_enable(&udc->ep0out.ep);
  2251. if (retval)
  2252. return retval;
  2253. udc->ep0in.ep.desc = &ctrl_endpt_in_desc;
  2254. retval = usb_ep_enable(&udc->ep0in.ep);
  2255. if (retval)
  2256. return retval;
  2257. spin_lock_irqsave(udc->lock, flags);
  2258. udc->gadget.ep0 = &udc->ep0in.ep;
  2259. /* bind gadget */
  2260. driver->driver.bus = NULL;
  2261. udc->gadget.dev.driver = &driver->driver;
  2262. spin_unlock_irqrestore(udc->lock, flags);
  2263. retval = bind(&udc->gadget); /* MAY SLEEP */
  2264. spin_lock_irqsave(udc->lock, flags);
  2265. if (retval) {
  2266. udc->gadget.dev.driver = NULL;
  2267. goto done;
  2268. }
  2269. udc->driver = driver;
  2270. pm_runtime_get_sync(&udc->gadget.dev);
  2271. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2272. if (udc->vbus_active) {
  2273. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2274. hw_device_reset(udc);
  2275. } else {
  2276. pm_runtime_put_sync(&udc->gadget.dev);
  2277. goto done;
  2278. }
  2279. }
  2280. retval = hw_device_state(udc->ep0out.qh.dma);
  2281. if (retval)
  2282. pm_runtime_put_sync(&udc->gadget.dev);
  2283. done:
  2284. spin_unlock_irqrestore(udc->lock, flags);
  2285. return retval;
  2286. }
  2287. /**
  2288. * ci13xxx_stop: unregister a gadget driver
  2289. *
  2290. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2291. */
  2292. static int ci13xxx_stop(struct usb_gadget_driver *driver)
  2293. {
  2294. struct ci13xxx *udc = _udc;
  2295. unsigned long i, flags;
  2296. trace("%p", driver);
  2297. if (driver == NULL ||
  2298. driver->unbind == NULL ||
  2299. driver->setup == NULL ||
  2300. driver->disconnect == NULL ||
  2301. driver->suspend == NULL ||
  2302. driver->resume == NULL ||
  2303. driver != udc->driver)
  2304. return -EINVAL;
  2305. spin_lock_irqsave(udc->lock, flags);
  2306. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2307. udc->vbus_active) {
  2308. hw_device_state(0);
  2309. if (udc->udc_driver->notify_event)
  2310. udc->udc_driver->notify_event(udc,
  2311. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2312. spin_unlock_irqrestore(udc->lock, flags);
  2313. _gadget_stop_activity(&udc->gadget);
  2314. spin_lock_irqsave(udc->lock, flags);
  2315. pm_runtime_put(&udc->gadget.dev);
  2316. }
  2317. /* unbind gadget */
  2318. spin_unlock_irqrestore(udc->lock, flags);
  2319. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2320. spin_lock_irqsave(udc->lock, flags);
  2321. udc->gadget.dev.driver = NULL;
  2322. /* free resources */
  2323. for (i = 0; i < hw_ep_max; i++) {
  2324. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2325. if (!list_empty(&mEp->ep.ep_list))
  2326. list_del_init(&mEp->ep.ep_list);
  2327. if (mEp->qh.ptr != NULL)
  2328. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2329. }
  2330. udc->gadget.ep0 = NULL;
  2331. udc->driver = NULL;
  2332. spin_unlock_irqrestore(udc->lock, flags);
  2333. if (udc->td_pool != NULL) {
  2334. dma_pool_destroy(udc->td_pool);
  2335. udc->td_pool = NULL;
  2336. }
  2337. if (udc->qh_pool != NULL) {
  2338. dma_pool_destroy(udc->qh_pool);
  2339. udc->qh_pool = NULL;
  2340. }
  2341. return 0;
  2342. }
  2343. /******************************************************************************
  2344. * BUS block
  2345. *****************************************************************************/
  2346. /**
  2347. * udc_irq: global interrupt handler
  2348. *
  2349. * This function returns IRQ_HANDLED if the IRQ has been handled
  2350. * It locks access to registers
  2351. */
  2352. static irqreturn_t udc_irq(void)
  2353. {
  2354. struct ci13xxx *udc = _udc;
  2355. irqreturn_t retval;
  2356. u32 intr;
  2357. trace();
  2358. if (udc == NULL) {
  2359. err("ENODEV");
  2360. return IRQ_HANDLED;
  2361. }
  2362. spin_lock(udc->lock);
  2363. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2364. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2365. USBMODE_CM_DEVICE) {
  2366. spin_unlock(udc->lock);
  2367. return IRQ_NONE;
  2368. }
  2369. }
  2370. intr = hw_test_and_clear_intr_active();
  2371. if (intr) {
  2372. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2373. isr_statistics.hndl.idx &= ISR_MASK;
  2374. isr_statistics.hndl.cnt++;
  2375. /* order defines priority - do NOT change it */
  2376. if (USBi_URI & intr) {
  2377. isr_statistics.uri++;
  2378. isr_reset_handler(udc);
  2379. }
  2380. if (USBi_PCI & intr) {
  2381. isr_statistics.pci++;
  2382. udc->gadget.speed = hw_port_is_high_speed() ?
  2383. USB_SPEED_HIGH : USB_SPEED_FULL;
  2384. if (udc->suspended) {
  2385. spin_unlock(udc->lock);
  2386. udc->driver->resume(&udc->gadget);
  2387. spin_lock(udc->lock);
  2388. udc->suspended = 0;
  2389. }
  2390. }
  2391. if (USBi_UEI & intr)
  2392. isr_statistics.uei++;
  2393. if (USBi_UI & intr) {
  2394. isr_statistics.ui++;
  2395. isr_tr_complete_handler(udc);
  2396. }
  2397. if (USBi_SLI & intr) {
  2398. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  2399. udc->suspended = 1;
  2400. spin_unlock(udc->lock);
  2401. udc->driver->suspend(&udc->gadget);
  2402. spin_lock(udc->lock);
  2403. }
  2404. isr_statistics.sli++;
  2405. }
  2406. retval = IRQ_HANDLED;
  2407. } else {
  2408. isr_statistics.none++;
  2409. retval = IRQ_NONE;
  2410. }
  2411. spin_unlock(udc->lock);
  2412. return retval;
  2413. }
  2414. /**
  2415. * udc_release: driver release function
  2416. * @dev: device
  2417. *
  2418. * Currently does nothing
  2419. */
  2420. static void udc_release(struct device *dev)
  2421. {
  2422. trace("%p", dev);
  2423. if (dev == NULL)
  2424. err("EINVAL");
  2425. }
  2426. /**
  2427. * udc_probe: parent probe must call this to initialize UDC
  2428. * @dev: parent device
  2429. * @regs: registers base address
  2430. * @name: driver name
  2431. *
  2432. * This function returns an error code
  2433. * No interrupts active, the IRQ has not been requested yet
  2434. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2435. */
  2436. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2437. void __iomem *regs)
  2438. {
  2439. struct ci13xxx *udc;
  2440. int retval = 0;
  2441. trace("%p, %p, %p", dev, regs, driver->name);
  2442. if (dev == NULL || regs == NULL || driver == NULL ||
  2443. driver->name == NULL)
  2444. return -EINVAL;
  2445. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2446. if (udc == NULL)
  2447. return -ENOMEM;
  2448. udc->lock = &udc_lock;
  2449. udc->regs = regs;
  2450. udc->udc_driver = driver;
  2451. udc->gadget.ops = &usb_gadget_ops;
  2452. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2453. udc->gadget.is_dualspeed = 1;
  2454. udc->gadget.is_otg = 0;
  2455. udc->gadget.name = driver->name;
  2456. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2457. udc->gadget.ep0 = NULL;
  2458. dev_set_name(&udc->gadget.dev, "gadget");
  2459. udc->gadget.dev.dma_mask = dev->dma_mask;
  2460. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2461. udc->gadget.dev.parent = dev;
  2462. udc->gadget.dev.release = udc_release;
  2463. retval = hw_device_init(regs);
  2464. if (retval < 0)
  2465. goto free_udc;
  2466. udc->transceiver = otg_get_transceiver();
  2467. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2468. if (udc->transceiver == NULL) {
  2469. retval = -ENODEV;
  2470. goto free_udc;
  2471. }
  2472. }
  2473. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2474. retval = hw_device_reset(udc);
  2475. if (retval)
  2476. goto put_transceiver;
  2477. }
  2478. retval = device_register(&udc->gadget.dev);
  2479. if (retval) {
  2480. put_device(&udc->gadget.dev);
  2481. goto put_transceiver;
  2482. }
  2483. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2484. retval = dbg_create_files(&udc->gadget.dev);
  2485. #endif
  2486. if (retval)
  2487. goto unreg_device;
  2488. if (udc->transceiver) {
  2489. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2490. if (retval)
  2491. goto remove_dbg;
  2492. }
  2493. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2494. if (retval)
  2495. goto remove_trans;
  2496. pm_runtime_no_callbacks(&udc->gadget.dev);
  2497. pm_runtime_enable(&udc->gadget.dev);
  2498. _udc = udc;
  2499. return retval;
  2500. remove_trans:
  2501. if (udc->transceiver) {
  2502. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2503. otg_put_transceiver(udc->transceiver);
  2504. }
  2505. err("error = %i", retval);
  2506. remove_dbg:
  2507. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2508. dbg_remove_files(&udc->gadget.dev);
  2509. #endif
  2510. unreg_device:
  2511. device_unregister(&udc->gadget.dev);
  2512. put_transceiver:
  2513. if (udc->transceiver)
  2514. otg_put_transceiver(udc->transceiver);
  2515. free_udc:
  2516. kfree(udc);
  2517. _udc = NULL;
  2518. return retval;
  2519. }
  2520. /**
  2521. * udc_remove: parent remove must call this to remove UDC
  2522. *
  2523. * No interrupts active, the IRQ has been released
  2524. */
  2525. static void udc_remove(void)
  2526. {
  2527. struct ci13xxx *udc = _udc;
  2528. if (udc == NULL) {
  2529. err("EINVAL");
  2530. return;
  2531. }
  2532. usb_del_gadget_udc(&udc->gadget);
  2533. if (udc->transceiver) {
  2534. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2535. otg_put_transceiver(udc->transceiver);
  2536. }
  2537. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2538. dbg_remove_files(&udc->gadget.dev);
  2539. #endif
  2540. device_unregister(&udc->gadget.dev);
  2541. kfree(udc);
  2542. _udc = NULL;
  2543. }