setup.c 9.4 KB

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  1. /* $Id: setup.c,v 1.72 2002/02/09 19:49:30 davem Exp $
  2. * linux/arch/sparc64/kernel/setup.c
  3. *
  4. * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
  5. * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/sched.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mm.h>
  11. #include <linux/stddef.h>
  12. #include <linux/unistd.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/slab.h>
  15. #include <asm/smp.h>
  16. #include <linux/user.h>
  17. #include <linux/screen_info.h>
  18. #include <linux/delay.h>
  19. #include <linux/fs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/syscalls.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/major.h>
  24. #include <linux/string.h>
  25. #include <linux/init.h>
  26. #include <linux/inet.h>
  27. #include <linux/console.h>
  28. #include <linux/root_dev.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/cpu.h>
  31. #include <linux/initrd.h>
  32. #include <asm/system.h>
  33. #include <asm/io.h>
  34. #include <asm/processor.h>
  35. #include <asm/oplib.h>
  36. #include <asm/page.h>
  37. #include <asm/pgtable.h>
  38. #include <asm/idprom.h>
  39. #include <asm/head.h>
  40. #include <asm/starfire.h>
  41. #include <asm/mmu_context.h>
  42. #include <asm/timer.h>
  43. #include <asm/sections.h>
  44. #include <asm/setup.h>
  45. #include <asm/mmu.h>
  46. #include <asm/ns87303.h>
  47. #ifdef CONFIG_IP_PNP
  48. #include <net/ipconfig.h>
  49. #endif
  50. /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  51. * operations in asm/ns87303.h
  52. */
  53. DEFINE_SPINLOCK(ns87303_lock);
  54. struct screen_info screen_info = {
  55. 0, 0, /* orig-x, orig-y */
  56. 0, /* unused */
  57. 0, /* orig-video-page */
  58. 0, /* orig-video-mode */
  59. 128, /* orig-video-cols */
  60. 0, 0, 0, /* unused, ega_bx, unused */
  61. 54, /* orig-video-lines */
  62. 0, /* orig-video-isVGA */
  63. 16 /* orig-video-points */
  64. };
  65. void (*prom_palette)(int);
  66. void (*prom_keyboard)(void);
  67. static void
  68. prom_console_write(struct console *con, const char *s, unsigned n)
  69. {
  70. prom_write(s, n);
  71. }
  72. unsigned int boot_flags = 0;
  73. #define BOOTME_DEBUG 0x1
  74. /* Exported for mm/init.c:paging_init. */
  75. unsigned long cmdline_memory_size = 0;
  76. static struct console prom_early_console = {
  77. .name = "earlyprom",
  78. .write = prom_console_write,
  79. .flags = CON_PRINTBUFFER | CON_BOOT,
  80. .index = -1,
  81. };
  82. /* XXX Implement this at some point... */
  83. void kernel_enter_debugger(void)
  84. {
  85. }
  86. /*
  87. * Process kernel command line switches that are specific to the
  88. * SPARC or that require special low-level processing.
  89. */
  90. static void __init process_switch(char c)
  91. {
  92. switch (c) {
  93. case 'd':
  94. boot_flags |= BOOTME_DEBUG;
  95. break;
  96. case 's':
  97. break;
  98. case 'h':
  99. prom_printf("boot_flags_init: Halt!\n");
  100. prom_halt();
  101. break;
  102. case 'p':
  103. /* Just ignore, this behavior is now the default. */
  104. break;
  105. case 'P':
  106. /* Force UltraSPARC-III P-Cache on. */
  107. if (tlb_type != cheetah) {
  108. printk("BOOT: Ignoring P-Cache force option.\n");
  109. break;
  110. }
  111. cheetah_pcache_forced_on = 1;
  112. add_taint(TAINT_MACHINE_CHECK);
  113. cheetah_enable_pcache();
  114. break;
  115. default:
  116. printk("Unknown boot switch (-%c)\n", c);
  117. break;
  118. }
  119. }
  120. static void __init boot_flags_init(char *commands)
  121. {
  122. while (*commands) {
  123. /* Move to the start of the next "argument". */
  124. while (*commands && *commands == ' ')
  125. commands++;
  126. /* Process any command switches, otherwise skip it. */
  127. if (*commands == '\0')
  128. break;
  129. if (*commands == '-') {
  130. commands++;
  131. while (*commands && *commands != ' ')
  132. process_switch(*commands++);
  133. continue;
  134. }
  135. if (!strncmp(commands, "mem=", 4)) {
  136. /*
  137. * "mem=XXX[kKmM]" overrides the PROM-reported
  138. * memory size.
  139. */
  140. cmdline_memory_size = simple_strtoul(commands + 4,
  141. &commands, 0);
  142. if (*commands == 'K' || *commands == 'k') {
  143. cmdline_memory_size <<= 10;
  144. commands++;
  145. } else if (*commands=='M' || *commands=='m') {
  146. cmdline_memory_size <<= 20;
  147. commands++;
  148. }
  149. }
  150. while (*commands && *commands != ' ')
  151. commands++;
  152. }
  153. }
  154. extern void panic_setup(char *, int *);
  155. extern unsigned short root_flags;
  156. extern unsigned short root_dev;
  157. extern unsigned short ram_flags;
  158. #define RAMDISK_IMAGE_START_MASK 0x07FF
  159. #define RAMDISK_PROMPT_FLAG 0x8000
  160. #define RAMDISK_LOAD_FLAG 0x4000
  161. extern int root_mountflags;
  162. char reboot_command[COMMAND_LINE_SIZE];
  163. static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
  164. void __init per_cpu_patch(void)
  165. {
  166. struct cpuid_patch_entry *p;
  167. unsigned long ver;
  168. int is_jbus;
  169. if (tlb_type == spitfire && !this_is_starfire)
  170. return;
  171. is_jbus = 0;
  172. if (tlb_type != hypervisor) {
  173. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  174. is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
  175. (ver >> 32UL) == __SERRANO_ID);
  176. }
  177. p = &__cpuid_patch;
  178. while (p < &__cpuid_patch_end) {
  179. unsigned long addr = p->addr;
  180. unsigned int *insns;
  181. switch (tlb_type) {
  182. case spitfire:
  183. insns = &p->starfire[0];
  184. break;
  185. case cheetah:
  186. case cheetah_plus:
  187. if (is_jbus)
  188. insns = &p->cheetah_jbus[0];
  189. else
  190. insns = &p->cheetah_safari[0];
  191. break;
  192. case hypervisor:
  193. insns = &p->sun4v[0];
  194. break;
  195. default:
  196. prom_printf("Unknown cpu type, halting.\n");
  197. prom_halt();
  198. };
  199. *(unsigned int *) (addr + 0) = insns[0];
  200. wmb();
  201. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  202. *(unsigned int *) (addr + 4) = insns[1];
  203. wmb();
  204. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  205. *(unsigned int *) (addr + 8) = insns[2];
  206. wmb();
  207. __asm__ __volatile__("flush %0" : : "r" (addr + 8));
  208. *(unsigned int *) (addr + 12) = insns[3];
  209. wmb();
  210. __asm__ __volatile__("flush %0" : : "r" (addr + 12));
  211. p++;
  212. }
  213. }
  214. void __init sun4v_patch(void)
  215. {
  216. extern void sun4v_hvapi_init(void);
  217. struct sun4v_1insn_patch_entry *p1;
  218. struct sun4v_2insn_patch_entry *p2;
  219. if (tlb_type != hypervisor)
  220. return;
  221. p1 = &__sun4v_1insn_patch;
  222. while (p1 < &__sun4v_1insn_patch_end) {
  223. unsigned long addr = p1->addr;
  224. *(unsigned int *) (addr + 0) = p1->insn;
  225. wmb();
  226. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  227. p1++;
  228. }
  229. p2 = &__sun4v_2insn_patch;
  230. while (p2 < &__sun4v_2insn_patch_end) {
  231. unsigned long addr = p2->addr;
  232. *(unsigned int *) (addr + 0) = p2->insns[0];
  233. wmb();
  234. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  235. *(unsigned int *) (addr + 4) = p2->insns[1];
  236. wmb();
  237. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  238. p2++;
  239. }
  240. sun4v_hvapi_init();
  241. }
  242. #ifdef CONFIG_SMP
  243. void __init boot_cpu_id_too_large(int cpu)
  244. {
  245. prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
  246. cpu, NR_CPUS);
  247. prom_halt();
  248. }
  249. #endif
  250. void __init setup_arch(char **cmdline_p)
  251. {
  252. /* Initialize PROM console and command line. */
  253. *cmdline_p = prom_getbootargs();
  254. strcpy(boot_command_line, *cmdline_p);
  255. boot_flags_init(*cmdline_p);
  256. register_console(&prom_early_console);
  257. if (tlb_type == hypervisor)
  258. printk("ARCH: SUN4V\n");
  259. else
  260. printk("ARCH: SUN4U\n");
  261. #ifdef CONFIG_DUMMY_CONSOLE
  262. conswitchp = &dummy_con;
  263. #elif defined(CONFIG_PROM_CONSOLE)
  264. conswitchp = &prom_con;
  265. #endif
  266. idprom_init();
  267. if (!root_flags)
  268. root_mountflags &= ~MS_RDONLY;
  269. ROOT_DEV = old_decode_dev(root_dev);
  270. #ifdef CONFIG_BLK_DEV_RAM
  271. rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
  272. rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
  273. rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
  274. #endif
  275. task_thread_info(&init_task)->kregs = &fake_swapper_regs;
  276. #ifdef CONFIG_IP_PNP
  277. if (!ic_set_manually) {
  278. int chosen = prom_finddevice ("/chosen");
  279. u32 cl, sv, gw;
  280. cl = prom_getintdefault (chosen, "client-ip", 0);
  281. sv = prom_getintdefault (chosen, "server-ip", 0);
  282. gw = prom_getintdefault (chosen, "gateway-ip", 0);
  283. if (cl && sv) {
  284. ic_myaddr = cl;
  285. ic_servaddr = sv;
  286. if (gw)
  287. ic_gateway = gw;
  288. #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
  289. ic_proto_enabled = 0;
  290. #endif
  291. }
  292. }
  293. #endif
  294. /* Get boot processor trap_block[] setup. */
  295. init_cur_cpu_trap(current_thread_info());
  296. paging_init();
  297. }
  298. /* BUFFER is PAGE_SIZE bytes long. */
  299. extern char *sparc_cpu_type;
  300. extern char *sparc_fpu_type;
  301. extern void smp_info(struct seq_file *);
  302. extern void smp_bogo(struct seq_file *);
  303. extern void mmu_info(struct seq_file *);
  304. unsigned int dcache_parity_tl1_occurred;
  305. unsigned int icache_parity_tl1_occurred;
  306. int ncpus_probed;
  307. static int show_cpuinfo(struct seq_file *m, void *__unused)
  308. {
  309. seq_printf(m,
  310. "cpu\t\t: %s\n"
  311. "fpu\t\t: %s\n"
  312. "prom\t\t: %s\n"
  313. "type\t\t: %s\n"
  314. "ncpus probed\t: %d\n"
  315. "ncpus active\t: %d\n"
  316. "D$ parity tl1\t: %u\n"
  317. "I$ parity tl1\t: %u\n"
  318. #ifndef CONFIG_SMP
  319. "Cpu0ClkTck\t: %016lx\n"
  320. #endif
  321. ,
  322. sparc_cpu_type,
  323. sparc_fpu_type,
  324. prom_version,
  325. ((tlb_type == hypervisor) ?
  326. "sun4v" :
  327. "sun4u"),
  328. ncpus_probed,
  329. num_online_cpus(),
  330. dcache_parity_tl1_occurred,
  331. icache_parity_tl1_occurred
  332. #ifndef CONFIG_SMP
  333. , cpu_data(0).clock_tick
  334. #endif
  335. );
  336. #ifdef CONFIG_SMP
  337. smp_bogo(m);
  338. #endif
  339. mmu_info(m);
  340. #ifdef CONFIG_SMP
  341. smp_info(m);
  342. #endif
  343. return 0;
  344. }
  345. static void *c_start(struct seq_file *m, loff_t *pos)
  346. {
  347. /* The pointer we are returning is arbitrary,
  348. * it just has to be non-NULL and not IS_ERR
  349. * in the success case.
  350. */
  351. return *pos == 0 ? &c_start : NULL;
  352. }
  353. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  354. {
  355. ++*pos;
  356. return c_start(m, pos);
  357. }
  358. static void c_stop(struct seq_file *m, void *v)
  359. {
  360. }
  361. const struct seq_operations cpuinfo_op = {
  362. .start =c_start,
  363. .next = c_next,
  364. .stop = c_stop,
  365. .show = show_cpuinfo,
  366. };
  367. extern int stop_a_enabled;
  368. void sun_do_break(void)
  369. {
  370. if (!stop_a_enabled)
  371. return;
  372. prom_printf("\n");
  373. flush_user_windows();
  374. prom_cmdline();
  375. }
  376. int stop_a_enabled = 1;