devices.c 15 KB

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  1. /*
  2. * Author: MontaVista Software, Inc.
  3. * <source@mvista.com>
  4. *
  5. * Based on the OMAP devices.c
  6. *
  7. * 2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  15. * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  16. * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License
  20. * as published by the Free Software Foundation; either version 2
  21. * of the License, or (at your option) any later version.
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  30. * MA 02110-1301, USA.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/init.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/gpio.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/serial.h>
  39. #include <mach/irqs.h>
  40. #include <mach/hardware.h>
  41. #include <mach/common.h>
  42. #include <mach/mmc.h>
  43. #include "devices.h"
  44. #if defined(CONFIG_ARCH_MX1)
  45. static struct resource imx1_camera_resources[] = {
  46. {
  47. .start = 0x00224000,
  48. .end = 0x00224010,
  49. .flags = IORESOURCE_MEM,
  50. }, {
  51. .start = MX1_CSI_INT,
  52. .end = MX1_CSI_INT,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. };
  56. static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
  57. struct platform_device imx1_camera_device = {
  58. .name = "mx1-camera",
  59. .id = 0, /* This is used to put cameras on this interface */
  60. .dev = {
  61. .dma_mask = &imx1_camera_dmamask,
  62. .coherent_dma_mask = DMA_BIT_MASK(32),
  63. },
  64. .resource = imx1_camera_resources,
  65. .num_resources = ARRAY_SIZE(imx1_camera_resources),
  66. };
  67. static struct resource imx_rtc_resources[] = {
  68. {
  69. .start = 0x00204000,
  70. .end = 0x00204024,
  71. .flags = IORESOURCE_MEM,
  72. }, {
  73. .start = MX1_RTC_INT,
  74. .end = MX1_RTC_INT,
  75. .flags = IORESOURCE_IRQ,
  76. }, {
  77. .start = MX1_RTC_SAMINT,
  78. .end = MX1_RTC_SAMINT,
  79. .flags = IORESOURCE_IRQ,
  80. },
  81. };
  82. struct platform_device imx_rtc_device = {
  83. .name = "rtc-imx",
  84. .id = 0,
  85. .resource = imx_rtc_resources,
  86. .num_resources = ARRAY_SIZE(imx_rtc_resources),
  87. };
  88. static struct resource imx_wdt_resources[] = {
  89. {
  90. .start = 0x00201000,
  91. .end = 0x00201008,
  92. .flags = IORESOURCE_MEM,
  93. }, {
  94. .start = MX1_WDT_INT,
  95. .end = MX1_WDT_INT,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. struct platform_device imx_wdt_device = {
  100. .name = "imx-wdt",
  101. .id = 0,
  102. .resource = imx_wdt_resources,
  103. .num_resources = ARRAY_SIZE(imx_wdt_resources),
  104. };
  105. static struct resource imx_usb_resources[] = {
  106. {
  107. .start = 0x00212000,
  108. .end = 0x00212148,
  109. .flags = IORESOURCE_MEM,
  110. }, {
  111. .start = MX1_USBD_INT0,
  112. .end = MX1_USBD_INT0,
  113. .flags = IORESOURCE_IRQ,
  114. }, {
  115. .start = MX1_USBD_INT1,
  116. .end = MX1_USBD_INT1,
  117. .flags = IORESOURCE_IRQ,
  118. }, {
  119. .start = MX1_USBD_INT2,
  120. .end = MX1_USBD_INT2,
  121. .flags = IORESOURCE_IRQ,
  122. }, {
  123. .start = MX1_USBD_INT3,
  124. .end = MX1_USBD_INT3,
  125. .flags = IORESOURCE_IRQ,
  126. }, {
  127. .start = MX1_USBD_INT4,
  128. .end = MX1_USBD_INT4,
  129. .flags = IORESOURCE_IRQ,
  130. }, {
  131. .start = MX1_USBD_INT5,
  132. .end = MX1_USBD_INT5,
  133. .flags = IORESOURCE_IRQ,
  134. }, {
  135. .start = MX1_USBD_INT6,
  136. .end = MX1_USBD_INT6,
  137. .flags = IORESOURCE_IRQ,
  138. },
  139. };
  140. struct platform_device imx_usb_device = {
  141. .name = "imx_udc",
  142. .id = 0,
  143. .num_resources = ARRAY_SIZE(imx_usb_resources),
  144. .resource = imx_usb_resources,
  145. };
  146. /* GPIO port description */
  147. static struct mxc_gpio_port imx_gpio_ports[] = {
  148. {
  149. .chip.label = "gpio-0",
  150. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
  151. .irq = MX1_GPIO_INT_PORTA,
  152. .virtual_irq_start = MXC_GPIO_IRQ_START,
  153. }, {
  154. .chip.label = "gpio-1",
  155. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
  156. .irq = MX1_GPIO_INT_PORTB,
  157. .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
  158. }, {
  159. .chip.label = "gpio-2",
  160. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
  161. .irq = MX1_GPIO_INT_PORTC,
  162. .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
  163. }, {
  164. .chip.label = "gpio-3",
  165. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
  166. .irq = MX1_GPIO_INT_PORTD,
  167. .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
  168. }
  169. };
  170. int __init imx1_register_gpios(void)
  171. {
  172. return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
  173. }
  174. #endif
  175. #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
  176. /*
  177. * General Purpose Timer
  178. * - i.MX21: 3 timers
  179. * - i.MX27: 6 timers
  180. */
  181. #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
  182. static struct resource timer ## n ##_resources[] = { \
  183. { \
  184. .start = baseaddr, \
  185. .end = baseaddr + SZ_4K - 1, \
  186. .flags = IORESOURCE_MEM, \
  187. }, { \
  188. .start = irq, \
  189. .end = irq, \
  190. .flags = IORESOURCE_IRQ, \
  191. } \
  192. }; \
  193. \
  194. struct platform_device mxc_gpt ## n = { \
  195. .name = "imx_gpt", \
  196. .id = n, \
  197. .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
  198. .resource = timer ## n ## _resources, \
  199. }
  200. /* We use gpt1 as system timer, so do not add a device for this one */
  201. DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
  202. DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
  203. #ifdef CONFIG_MACH_MX27
  204. DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
  205. DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
  206. DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
  207. #endif
  208. /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
  209. static struct resource mxc_wdt_resources[] = {
  210. {
  211. .start = MX2x_WDOG_BASE_ADDR,
  212. .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
  213. .flags = IORESOURCE_MEM,
  214. },
  215. };
  216. struct platform_device mxc_wdt = {
  217. .name = "imx2-wdt",
  218. .id = 0,
  219. .num_resources = ARRAY_SIZE(mxc_wdt_resources),
  220. .resource = mxc_wdt_resources,
  221. };
  222. static struct resource mxc_w1_master_resources[] = {
  223. {
  224. .start = MX2x_OWIRE_BASE_ADDR,
  225. .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
  226. .flags = IORESOURCE_MEM,
  227. },
  228. };
  229. struct platform_device mxc_w1_master_device = {
  230. .name = "mxc_w1",
  231. .id = 0,
  232. .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
  233. .resource = mxc_w1_master_resources,
  234. };
  235. /*
  236. * lcdc:
  237. * - i.MX1: the basic controller
  238. * - i.MX21: to be checked
  239. * - i.MX27: like i.MX1, with slightly variations
  240. */
  241. static struct resource mxc_fb[] = {
  242. {
  243. .start = MX2x_LCDC_BASE_ADDR,
  244. .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
  245. .flags = IORESOURCE_MEM,
  246. }, {
  247. .start = MX2x_INT_LCDC,
  248. .end = MX2x_INT_LCDC,
  249. .flags = IORESOURCE_IRQ,
  250. }
  251. };
  252. /* mxc lcd driver */
  253. struct platform_device mxc_fb_device = {
  254. .name = "imx-fb",
  255. .id = 0,
  256. .num_resources = ARRAY_SIZE(mxc_fb),
  257. .resource = mxc_fb,
  258. .dev = {
  259. .coherent_dma_mask = DMA_BIT_MASK(32),
  260. },
  261. };
  262. #ifdef CONFIG_MACH_MX27
  263. static struct resource mxc_fec_resources[] = {
  264. {
  265. .start = MX27_FEC_BASE_ADDR,
  266. .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
  267. .flags = IORESOURCE_MEM,
  268. }, {
  269. .start = MX27_INT_FEC,
  270. .end = MX27_INT_FEC,
  271. .flags = IORESOURCE_IRQ,
  272. },
  273. };
  274. struct platform_device mxc_fec_device = {
  275. .name = "fec",
  276. .id = 0,
  277. .num_resources = ARRAY_SIZE(mxc_fec_resources),
  278. .resource = mxc_fec_resources,
  279. };
  280. #endif
  281. static struct resource mxc_pwm_resources[] = {
  282. {
  283. .start = MX2x_PWM_BASE_ADDR,
  284. .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
  285. .flags = IORESOURCE_MEM,
  286. }, {
  287. .start = MX2x_INT_PWM,
  288. .end = MX2x_INT_PWM,
  289. .flags = IORESOURCE_IRQ,
  290. }
  291. };
  292. struct platform_device mxc_pwm_device = {
  293. .name = "mxc_pwm",
  294. .id = 0,
  295. .num_resources = ARRAY_SIZE(mxc_pwm_resources),
  296. .resource = mxc_pwm_resources,
  297. };
  298. #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
  299. static struct resource mxc_sdhc_resources ## n[] = { \
  300. { \
  301. .start = baseaddr, \
  302. .end = baseaddr + SZ_4K - 1, \
  303. .flags = IORESOURCE_MEM, \
  304. }, { \
  305. .start = irq, \
  306. .end = irq, \
  307. .flags = IORESOURCE_IRQ, \
  308. }, { \
  309. .start = dmareq, \
  310. .end = dmareq, \
  311. .flags = IORESOURCE_DMA, \
  312. }, \
  313. }; \
  314. \
  315. static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
  316. \
  317. struct platform_device mxc_sdhc_device ## n = { \
  318. .name = "mxc-mmc", \
  319. .id = n, \
  320. .dev = { \
  321. .dma_mask = &mxc_sdhc ## n ## _dmamask, \
  322. .coherent_dma_mask = DMA_BIT_MASK(32), \
  323. }, \
  324. .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
  325. .resource = mxc_sdhc_resources ## n, \
  326. }
  327. DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
  328. DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
  329. #ifdef CONFIG_MACH_MX27
  330. static struct resource otg_resources[] = {
  331. {
  332. .start = MX27_USBOTG_BASE_ADDR,
  333. .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
  334. .flags = IORESOURCE_MEM,
  335. }, {
  336. .start = MX27_INT_USB3,
  337. .end = MX27_INT_USB3,
  338. .flags = IORESOURCE_IRQ,
  339. },
  340. };
  341. static u64 otg_dmamask = DMA_BIT_MASK(32);
  342. /* OTG gadget device */
  343. struct platform_device mxc_otg_udc_device = {
  344. .name = "fsl-usb2-udc",
  345. .id = -1,
  346. .dev = {
  347. .dma_mask = &otg_dmamask,
  348. .coherent_dma_mask = DMA_BIT_MASK(32),
  349. },
  350. .resource = otg_resources,
  351. .num_resources = ARRAY_SIZE(otg_resources),
  352. };
  353. /* OTG host */
  354. struct platform_device mxc_otg_host = {
  355. .name = "mxc-ehci",
  356. .id = 0,
  357. .dev = {
  358. .coherent_dma_mask = DMA_BIT_MASK(32),
  359. .dma_mask = &otg_dmamask,
  360. },
  361. .resource = otg_resources,
  362. .num_resources = ARRAY_SIZE(otg_resources),
  363. };
  364. /* USB host 1 */
  365. static u64 usbh1_dmamask = DMA_BIT_MASK(32);
  366. static struct resource mxc_usbh1_resources[] = {
  367. {
  368. .start = MX27_USBOTG_BASE_ADDR + 0x200,
  369. .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
  370. .flags = IORESOURCE_MEM,
  371. }, {
  372. .start = MX27_INT_USB1,
  373. .end = MX27_INT_USB1,
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. };
  377. struct platform_device mxc_usbh1 = {
  378. .name = "mxc-ehci",
  379. .id = 1,
  380. .dev = {
  381. .coherent_dma_mask = DMA_BIT_MASK(32),
  382. .dma_mask = &usbh1_dmamask,
  383. },
  384. .resource = mxc_usbh1_resources,
  385. .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
  386. };
  387. /* USB host 2 */
  388. static u64 usbh2_dmamask = DMA_BIT_MASK(32);
  389. static struct resource mxc_usbh2_resources[] = {
  390. {
  391. .start = MX27_USBOTG_BASE_ADDR + 0x400,
  392. .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
  393. .flags = IORESOURCE_MEM,
  394. }, {
  395. .start = MX27_INT_USB2,
  396. .end = MX27_INT_USB2,
  397. .flags = IORESOURCE_IRQ,
  398. },
  399. };
  400. struct platform_device mxc_usbh2 = {
  401. .name = "mxc-ehci",
  402. .id = 2,
  403. .dev = {
  404. .coherent_dma_mask = DMA_BIT_MASK(32),
  405. .dma_mask = &usbh2_dmamask,
  406. },
  407. .resource = mxc_usbh2_resources,
  408. .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
  409. };
  410. #endif
  411. #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
  412. { \
  413. .name = _name, \
  414. .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  415. .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  416. .flags = IORESOURCE_DMA, \
  417. }
  418. #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
  419. static struct resource imx_ssi_resources ## n[] = { \
  420. { \
  421. .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
  422. .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
  423. .flags = IORESOURCE_MEM, \
  424. }, { \
  425. .start = MX2x_INT_SSI1, \
  426. .end = MX2x_INT_SSI1, \
  427. .flags = IORESOURCE_IRQ, \
  428. }, \
  429. DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
  430. DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
  431. DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
  432. DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
  433. }; \
  434. \
  435. struct platform_device imx_ssi_device ## n = { \
  436. .name = "imx-ssi", \
  437. .id = n, \
  438. .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
  439. .resource = imx_ssi_resources ## n, \
  440. }
  441. DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  442. DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  443. #ifdef CONFIG_MACH_MX27
  444. #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
  445. static struct resource imx2x_uart_resources ## n[] = { \
  446. { \
  447. .start = baseaddr, \
  448. .end = baseaddr + 0xb5, \
  449. .flags = IORESOURCE_MEM, \
  450. }, { \
  451. .start = irq, \
  452. .end = irq, \
  453. .flags = IORESOURCE_IRQ, \
  454. }, \
  455. }; \
  456. \
  457. struct platform_device imx2x_uart_device ## n = { \
  458. .name = "imx-uart", \
  459. .id = n, \
  460. .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
  461. .resource = imx2x_uart_resources ## n, \
  462. }
  463. DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
  464. DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
  465. DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
  466. DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
  467. DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
  468. DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
  469. #endif
  470. /* GPIO port description */
  471. #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
  472. { \
  473. .chip.label = "gpio-" #n, \
  474. .irq = _irq, \
  475. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  476. n * 0x100), \
  477. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  478. }
  479. #define DEFINE_MXC_GPIO_PORT(SOC, n) \
  480. { \
  481. .chip.label = "gpio-" #n, \
  482. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  483. n * 0x100), \
  484. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  485. }
  486. #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
  487. static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
  488. DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
  489. DEFINE_MXC_GPIO_PORT(SOC, 1), \
  490. DEFINE_MXC_GPIO_PORT(SOC, 2), \
  491. DEFINE_MXC_GPIO_PORT(SOC, 3), \
  492. DEFINE_MXC_GPIO_PORT(SOC, 4), \
  493. DEFINE_MXC_GPIO_PORT(SOC, 5), \
  494. }
  495. #ifdef CONFIG_MACH_MX21
  496. DEFINE_MXC_GPIO_PORTS(MX21, imx21);
  497. int __init imx21_register_gpios(void)
  498. {
  499. return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
  500. }
  501. #endif
  502. #ifdef CONFIG_MACH_MX27
  503. DEFINE_MXC_GPIO_PORTS(MX27, imx27);
  504. int __init imx27_register_gpios(void)
  505. {
  506. return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
  507. }
  508. #endif
  509. #ifdef CONFIG_MACH_MX21
  510. static struct resource mx21_usbhc_resources[] = {
  511. {
  512. .start = MX21_USBOTG_BASE_ADDR,
  513. .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
  514. .flags = IORESOURCE_MEM,
  515. },
  516. {
  517. .start = MX21_INT_USBHOST,
  518. .end = MX21_INT_USBHOST,
  519. .flags = IORESOURCE_IRQ,
  520. },
  521. };
  522. struct platform_device mx21_usbhc_device = {
  523. .name = "imx21-hcd",
  524. .id = 0,
  525. .dev = {
  526. .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
  527. .coherent_dma_mask = DMA_BIT_MASK(32),
  528. },
  529. .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
  530. .resource = mx21_usbhc_resources,
  531. };
  532. #endif
  533. #endif