twl4030.c 72 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x00, /* REG_CODEC_MODE (0x1) */
  43. 0x00, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x00, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0f, /* REG_ATXL1PGA (0xA) */
  52. 0x0f, /* REG_ATXR1PGA (0xB) */
  53. 0x0f, /* REG_AVTXL2PGA (0xC) */
  54. 0x0f, /* REG_AVTXR2PGA (0xD) */
  55. 0x00, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x3f, /* REG_ARXR1PGA (0x10) */
  58. 0x3f, /* REG_ARXL1PGA (0x11) */
  59. 0x3f, /* REG_ARXR2PGA (0x12) */
  60. 0x3f, /* REG_ARXL2PGA (0x13) */
  61. 0x25, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x00, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x55, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x00, /* REG_HS_SEL (0x22) */
  76. 0x00, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x05, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x79, /* REG_DTMF_TONOFF (0x35) */
  95. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x06, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. struct snd_soc_codec codec;
  120. unsigned int codec_powered;
  121. /* reference counts of AIF/APLL users */
  122. unsigned int apll_enabled;
  123. struct snd_pcm_substream *master_substream;
  124. struct snd_pcm_substream *slave_substream;
  125. unsigned int configured;
  126. unsigned int rate;
  127. unsigned int sample_bits;
  128. unsigned int channels;
  129. unsigned int sysclk;
  130. /* Output (with associated amp) states */
  131. u8 hsl_enabled, hsr_enabled;
  132. u8 earpiece_enabled;
  133. u8 predrivel_enabled, predriver_enabled;
  134. u8 carkitl_enabled, carkitr_enabled;
  135. };
  136. /*
  137. * read twl4030 register cache
  138. */
  139. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  140. unsigned int reg)
  141. {
  142. u8 *cache = codec->reg_cache;
  143. if (reg >= TWL4030_CACHEREGNUM)
  144. return -EIO;
  145. return cache[reg];
  146. }
  147. /*
  148. * write twl4030 register cache
  149. */
  150. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  151. u8 reg, u8 value)
  152. {
  153. u8 *cache = codec->reg_cache;
  154. if (reg >= TWL4030_CACHEREGNUM)
  155. return;
  156. cache[reg] = value;
  157. }
  158. /*
  159. * write to the twl4030 register space
  160. */
  161. static int twl4030_write(struct snd_soc_codec *codec,
  162. unsigned int reg, unsigned int value)
  163. {
  164. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  165. int write_to_reg = 0;
  166. twl4030_write_reg_cache(codec, reg, value);
  167. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  168. /* Decide if the given register can be written */
  169. switch (reg) {
  170. case TWL4030_REG_EAR_CTL:
  171. if (twl4030->earpiece_enabled)
  172. write_to_reg = 1;
  173. break;
  174. case TWL4030_REG_PREDL_CTL:
  175. if (twl4030->predrivel_enabled)
  176. write_to_reg = 1;
  177. break;
  178. case TWL4030_REG_PREDR_CTL:
  179. if (twl4030->predriver_enabled)
  180. write_to_reg = 1;
  181. break;
  182. case TWL4030_REG_PRECKL_CTL:
  183. if (twl4030->carkitl_enabled)
  184. write_to_reg = 1;
  185. break;
  186. case TWL4030_REG_PRECKR_CTL:
  187. if (twl4030->carkitr_enabled)
  188. write_to_reg = 1;
  189. break;
  190. case TWL4030_REG_HS_GAIN_SET:
  191. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  192. write_to_reg = 1;
  193. break;
  194. default:
  195. /* All other register can be written */
  196. write_to_reg = 1;
  197. break;
  198. }
  199. if (write_to_reg)
  200. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  201. value, reg);
  202. }
  203. return 0;
  204. }
  205. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  206. {
  207. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  208. int mode;
  209. if (enable == twl4030->codec_powered)
  210. return;
  211. if (enable)
  212. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  213. else
  214. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  215. if (mode >= 0) {
  216. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  217. twl4030->codec_powered = enable;
  218. }
  219. /* REVISIT: this delay is present in TI sample drivers */
  220. /* but there seems to be no TRM requirement for it */
  221. udelay(10);
  222. }
  223. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  224. {
  225. int i, difference = 0;
  226. u8 val;
  227. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  228. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  229. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  230. if (val != twl4030_reg[i]) {
  231. difference++;
  232. dev_dbg(codec->dev,
  233. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  234. i, val, twl4030_reg[i]);
  235. }
  236. }
  237. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  238. difference, difference ? "Not OK" : "OK");
  239. }
  240. static void twl4030_init_chip(struct platform_device *pdev)
  241. {
  242. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  243. struct twl4030_setup_data *setup = socdev->codec_data;
  244. struct snd_soc_codec *codec = socdev->card->codec;
  245. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  246. u8 reg, byte;
  247. int i = 0;
  248. /* Check defaults, if instructed before anything else */
  249. if (setup && setup->check_defaults)
  250. twl4030_check_defaults(codec);
  251. /* Refresh APLL_CTL register from HW */
  252. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  253. TWL4030_REG_APLL_CTL);
  254. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  255. /* anti-pop when changing analog gain */
  256. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  257. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  258. reg | TWL4030_SMOOTH_ANAVOL_EN);
  259. twl4030_write(codec, TWL4030_REG_OPTION,
  260. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  261. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  262. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  263. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  264. /* Machine dependent setup */
  265. if (!setup)
  266. return;
  267. /* Configuration for headset ramp delay from setup data */
  268. if (setup->sysclk != twl4030->sysclk)
  269. dev_warn(codec->dev,
  270. "Mismatch in APLL mclk: %u (configured: %u)\n",
  271. setup->sysclk, twl4030->sysclk);
  272. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  273. reg &= ~TWL4030_RAMP_DELAY;
  274. reg |= (setup->ramp_delay_value << 2);
  275. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  276. /* initiate offset cancellation */
  277. twl4030_codec_enable(codec, 1);
  278. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  279. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  280. reg |= setup->offset_cncl_path;
  281. twl4030_write(codec, TWL4030_REG_ANAMICL,
  282. reg | TWL4030_CNCL_OFFSET_START);
  283. /* wait for offset cancellation to complete */
  284. do {
  285. /* this takes a little while, so don't slam i2c */
  286. udelay(2000);
  287. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  288. TWL4030_REG_ANAMICL);
  289. } while ((i++ < 100) &&
  290. ((byte & TWL4030_CNCL_OFFSET_START) ==
  291. TWL4030_CNCL_OFFSET_START));
  292. /* Make sure that the reg_cache has the same value as the HW */
  293. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  294. twl4030_codec_enable(codec, 0);
  295. }
  296. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  297. {
  298. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  299. int status = -1;
  300. if (enable) {
  301. twl4030->apll_enabled++;
  302. if (twl4030->apll_enabled == 1)
  303. status = twl4030_codec_enable_resource(
  304. TWL4030_CODEC_RES_APLL);
  305. } else {
  306. twl4030->apll_enabled--;
  307. if (!twl4030->apll_enabled)
  308. status = twl4030_codec_disable_resource(
  309. TWL4030_CODEC_RES_APLL);
  310. }
  311. if (status >= 0)
  312. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  313. }
  314. /* Earpiece */
  315. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  316. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  317. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  318. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  319. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  320. };
  321. /* PreDrive Left */
  322. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  323. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  324. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  325. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  326. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  327. };
  328. /* PreDrive Right */
  329. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  330. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  331. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  332. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  333. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  334. };
  335. /* Headset Left */
  336. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  337. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  338. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  339. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  340. };
  341. /* Headset Right */
  342. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  343. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  344. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  345. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  346. };
  347. /* Carkit Left */
  348. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  349. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  350. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  351. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  352. };
  353. /* Carkit Right */
  354. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  355. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  356. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  357. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  358. };
  359. /* Handsfree Left */
  360. static const char *twl4030_handsfreel_texts[] =
  361. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  362. static const struct soc_enum twl4030_handsfreel_enum =
  363. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  364. ARRAY_SIZE(twl4030_handsfreel_texts),
  365. twl4030_handsfreel_texts);
  366. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  367. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  368. /* Handsfree Left virtual mute */
  369. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  370. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  371. /* Handsfree Right */
  372. static const char *twl4030_handsfreer_texts[] =
  373. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  374. static const struct soc_enum twl4030_handsfreer_enum =
  375. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  376. ARRAY_SIZE(twl4030_handsfreer_texts),
  377. twl4030_handsfreer_texts);
  378. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  379. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  380. /* Handsfree Right virtual mute */
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  382. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  383. /* Vibra */
  384. /* Vibra audio path selection */
  385. static const char *twl4030_vibra_texts[] =
  386. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  387. static const struct soc_enum twl4030_vibra_enum =
  388. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  389. ARRAY_SIZE(twl4030_vibra_texts),
  390. twl4030_vibra_texts);
  391. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  392. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  393. /* Vibra path selection: local vibrator (PWM) or audio driven */
  394. static const char *twl4030_vibrapath_texts[] =
  395. {"Local vibrator", "Audio"};
  396. static const struct soc_enum twl4030_vibrapath_enum =
  397. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  398. ARRAY_SIZE(twl4030_vibrapath_texts),
  399. twl4030_vibrapath_texts);
  400. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  401. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  402. /* Left analog microphone selection */
  403. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  404. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  405. TWL4030_REG_ANAMICL, 0, 1, 0),
  406. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  407. TWL4030_REG_ANAMICL, 1, 1, 0),
  408. SOC_DAPM_SINGLE("AUXL Capture Switch",
  409. TWL4030_REG_ANAMICL, 2, 1, 0),
  410. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  411. TWL4030_REG_ANAMICL, 3, 1, 0),
  412. };
  413. /* Right analog microphone selection */
  414. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  415. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  416. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  417. };
  418. /* TX1 L/R Analog/Digital microphone selection */
  419. static const char *twl4030_micpathtx1_texts[] =
  420. {"Analog", "Digimic0"};
  421. static const struct soc_enum twl4030_micpathtx1_enum =
  422. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  423. ARRAY_SIZE(twl4030_micpathtx1_texts),
  424. twl4030_micpathtx1_texts);
  425. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  426. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  427. /* TX2 L/R Analog/Digital microphone selection */
  428. static const char *twl4030_micpathtx2_texts[] =
  429. {"Analog", "Digimic1"};
  430. static const struct soc_enum twl4030_micpathtx2_enum =
  431. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  432. ARRAY_SIZE(twl4030_micpathtx2_texts),
  433. twl4030_micpathtx2_texts);
  434. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  435. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  436. /* Analog bypass for AudioR1 */
  437. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  438. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  439. /* Analog bypass for AudioL1 */
  440. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  441. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  442. /* Analog bypass for AudioR2 */
  443. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  444. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  445. /* Analog bypass for AudioL2 */
  446. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  447. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  448. /* Analog bypass for Voice */
  449. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  450. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  451. /* Digital bypass gain, 0 mutes the bypass */
  452. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  453. TLV_DB_RANGE_HEAD(2),
  454. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  455. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  456. };
  457. /* Digital bypass left (TX1L -> RX2L) */
  458. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  459. SOC_DAPM_SINGLE_TLV("Volume",
  460. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  461. twl4030_dapm_dbypass_tlv);
  462. /* Digital bypass right (TX1R -> RX2R) */
  463. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  464. SOC_DAPM_SINGLE_TLV("Volume",
  465. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  466. twl4030_dapm_dbypass_tlv);
  467. /*
  468. * Voice Sidetone GAIN volume control:
  469. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  470. */
  471. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  472. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  473. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  474. SOC_DAPM_SINGLE_TLV("Volume",
  475. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  476. twl4030_dapm_dbypassv_tlv);
  477. static int micpath_event(struct snd_soc_dapm_widget *w,
  478. struct snd_kcontrol *kcontrol, int event)
  479. {
  480. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  481. unsigned char adcmicsel, micbias_ctl;
  482. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  483. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  484. /* Prepare the bits for the given TX path:
  485. * shift_l == 0: TX1 microphone path
  486. * shift_l == 2: TX2 microphone path */
  487. if (e->shift_l) {
  488. /* TX2 microphone path */
  489. if (adcmicsel & TWL4030_TX2IN_SEL)
  490. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  491. else
  492. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  493. } else {
  494. /* TX1 microphone path */
  495. if (adcmicsel & TWL4030_TX1IN_SEL)
  496. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  497. else
  498. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  499. }
  500. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  501. return 0;
  502. }
  503. /*
  504. * Output PGA builder:
  505. * Handle the muting and unmuting of the given output (turning off the
  506. * amplifier associated with the output pin)
  507. * On mute bypass the reg_cache and write 0 to the register
  508. * On unmute: restore the register content from the reg_cache
  509. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  510. */
  511. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  512. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  513. struct snd_kcontrol *kcontrol, int event) \
  514. { \
  515. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  516. \
  517. switch (event) { \
  518. case SND_SOC_DAPM_POST_PMU: \
  519. twl4030->pin_name##_enabled = 1; \
  520. twl4030_write(w->codec, reg, \
  521. twl4030_read_reg_cache(w->codec, reg)); \
  522. break; \
  523. case SND_SOC_DAPM_POST_PMD: \
  524. twl4030->pin_name##_enabled = 0; \
  525. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  526. 0, reg); \
  527. break; \
  528. } \
  529. return 0; \
  530. }
  531. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  532. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  533. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  534. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  535. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  536. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  537. {
  538. unsigned char hs_ctl;
  539. hs_ctl = twl4030_read_reg_cache(codec, reg);
  540. if (ramp) {
  541. /* HF ramp-up */
  542. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  543. twl4030_write(codec, reg, hs_ctl);
  544. udelay(10);
  545. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  546. twl4030_write(codec, reg, hs_ctl);
  547. udelay(40);
  548. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  549. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  550. twl4030_write(codec, reg, hs_ctl);
  551. } else {
  552. /* HF ramp-down */
  553. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  554. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  555. twl4030_write(codec, reg, hs_ctl);
  556. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  557. twl4030_write(codec, reg, hs_ctl);
  558. udelay(40);
  559. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  560. twl4030_write(codec, reg, hs_ctl);
  561. }
  562. }
  563. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  564. struct snd_kcontrol *kcontrol, int event)
  565. {
  566. switch (event) {
  567. case SND_SOC_DAPM_POST_PMU:
  568. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  569. break;
  570. case SND_SOC_DAPM_POST_PMD:
  571. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  572. break;
  573. }
  574. return 0;
  575. }
  576. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  577. struct snd_kcontrol *kcontrol, int event)
  578. {
  579. switch (event) {
  580. case SND_SOC_DAPM_POST_PMU:
  581. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  582. break;
  583. case SND_SOC_DAPM_POST_PMD:
  584. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  585. break;
  586. }
  587. return 0;
  588. }
  589. static int vibramux_event(struct snd_soc_dapm_widget *w,
  590. struct snd_kcontrol *kcontrol, int event)
  591. {
  592. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  593. return 0;
  594. }
  595. static int apll_event(struct snd_soc_dapm_widget *w,
  596. struct snd_kcontrol *kcontrol, int event)
  597. {
  598. switch (event) {
  599. case SND_SOC_DAPM_PRE_PMU:
  600. twl4030_apll_enable(w->codec, 1);
  601. break;
  602. case SND_SOC_DAPM_POST_PMD:
  603. twl4030_apll_enable(w->codec, 0);
  604. break;
  605. }
  606. return 0;
  607. }
  608. static int aif_event(struct snd_soc_dapm_widget *w,
  609. struct snd_kcontrol *kcontrol, int event)
  610. {
  611. u8 audio_if;
  612. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  613. switch (event) {
  614. case SND_SOC_DAPM_PRE_PMU:
  615. /* Enable AIF */
  616. /* enable the PLL before we use it to clock the DAI */
  617. twl4030_apll_enable(w->codec, 1);
  618. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  619. audio_if | TWL4030_AIF_EN);
  620. break;
  621. case SND_SOC_DAPM_POST_PMD:
  622. /* disable the DAI before we stop it's source PLL */
  623. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  624. audio_if & ~TWL4030_AIF_EN);
  625. twl4030_apll_enable(w->codec, 0);
  626. break;
  627. }
  628. return 0;
  629. }
  630. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  631. {
  632. struct snd_soc_device *socdev = codec->socdev;
  633. struct twl4030_setup_data *setup = socdev->codec_data;
  634. unsigned char hs_gain, hs_pop;
  635. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  636. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  637. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  638. 8388608, 16777216, 33554432, 67108864};
  639. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  640. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  641. /* Enable external mute control, this dramatically reduces
  642. * the pop-noise */
  643. if (setup && setup->hs_extmute) {
  644. if (setup->set_hs_extmute) {
  645. setup->set_hs_extmute(1);
  646. } else {
  647. hs_pop |= TWL4030_EXTMUTE;
  648. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  649. }
  650. }
  651. if (ramp) {
  652. /* Headset ramp-up according to the TRM */
  653. hs_pop |= TWL4030_VMID_EN;
  654. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  655. /* Actually write to the register */
  656. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  657. hs_gain,
  658. TWL4030_REG_HS_GAIN_SET);
  659. hs_pop |= TWL4030_RAMP_EN;
  660. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  661. /* Wait ramp delay time + 1, so the VMID can settle */
  662. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  663. twl4030->sysclk) + 1);
  664. } else {
  665. /* Headset ramp-down _not_ according to
  666. * the TRM, but in a way that it is working */
  667. hs_pop &= ~TWL4030_RAMP_EN;
  668. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  669. /* Wait ramp delay time + 1, so the VMID can settle */
  670. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  671. twl4030->sysclk) + 1);
  672. /* Bypass the reg_cache to mute the headset */
  673. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  674. hs_gain & (~0x0f),
  675. TWL4030_REG_HS_GAIN_SET);
  676. hs_pop &= ~TWL4030_VMID_EN;
  677. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  678. }
  679. /* Disable external mute */
  680. if (setup && setup->hs_extmute) {
  681. if (setup->set_hs_extmute) {
  682. setup->set_hs_extmute(0);
  683. } else {
  684. hs_pop &= ~TWL4030_EXTMUTE;
  685. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  686. }
  687. }
  688. }
  689. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  690. struct snd_kcontrol *kcontrol, int event)
  691. {
  692. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  693. switch (event) {
  694. case SND_SOC_DAPM_POST_PMU:
  695. /* Do the ramp-up only once */
  696. if (!twl4030->hsr_enabled)
  697. headset_ramp(w->codec, 1);
  698. twl4030->hsl_enabled = 1;
  699. break;
  700. case SND_SOC_DAPM_POST_PMD:
  701. /* Do the ramp-down only if both headsetL/R is disabled */
  702. if (!twl4030->hsr_enabled)
  703. headset_ramp(w->codec, 0);
  704. twl4030->hsl_enabled = 0;
  705. break;
  706. }
  707. return 0;
  708. }
  709. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  710. struct snd_kcontrol *kcontrol, int event)
  711. {
  712. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  713. switch (event) {
  714. case SND_SOC_DAPM_POST_PMU:
  715. /* Do the ramp-up only once */
  716. if (!twl4030->hsl_enabled)
  717. headset_ramp(w->codec, 1);
  718. twl4030->hsr_enabled = 1;
  719. break;
  720. case SND_SOC_DAPM_POST_PMD:
  721. /* Do the ramp-down only if both headsetL/R is disabled */
  722. if (!twl4030->hsl_enabled)
  723. headset_ramp(w->codec, 0);
  724. twl4030->hsr_enabled = 0;
  725. break;
  726. }
  727. return 0;
  728. }
  729. /*
  730. * Some of the gain controls in TWL (mostly those which are associated with
  731. * the outputs) are implemented in an interesting way:
  732. * 0x0 : Power down (mute)
  733. * 0x1 : 6dB
  734. * 0x2 : 0 dB
  735. * 0x3 : -6 dB
  736. * Inverting not going to help with these.
  737. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  738. */
  739. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  740. xinvert, tlv_array) \
  741. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  742. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  743. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  744. .tlv.p = (tlv_array), \
  745. .info = snd_soc_info_volsw, \
  746. .get = snd_soc_get_volsw_twl4030, \
  747. .put = snd_soc_put_volsw_twl4030, \
  748. .private_value = (unsigned long)&(struct soc_mixer_control) \
  749. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  750. .max = xmax, .invert = xinvert} }
  751. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  752. xinvert, tlv_array) \
  753. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  754. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  755. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  756. .tlv.p = (tlv_array), \
  757. .info = snd_soc_info_volsw_2r, \
  758. .get = snd_soc_get_volsw_r2_twl4030,\
  759. .put = snd_soc_put_volsw_r2_twl4030, \
  760. .private_value = (unsigned long)&(struct soc_mixer_control) \
  761. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  762. .rshift = xshift, .max = xmax, .invert = xinvert} }
  763. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  764. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  765. xinvert, tlv_array)
  766. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  767. struct snd_ctl_elem_value *ucontrol)
  768. {
  769. struct soc_mixer_control *mc =
  770. (struct soc_mixer_control *)kcontrol->private_value;
  771. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  772. unsigned int reg = mc->reg;
  773. unsigned int shift = mc->shift;
  774. unsigned int rshift = mc->rshift;
  775. int max = mc->max;
  776. int mask = (1 << fls(max)) - 1;
  777. ucontrol->value.integer.value[0] =
  778. (snd_soc_read(codec, reg) >> shift) & mask;
  779. if (ucontrol->value.integer.value[0])
  780. ucontrol->value.integer.value[0] =
  781. max + 1 - ucontrol->value.integer.value[0];
  782. if (shift != rshift) {
  783. ucontrol->value.integer.value[1] =
  784. (snd_soc_read(codec, reg) >> rshift) & mask;
  785. if (ucontrol->value.integer.value[1])
  786. ucontrol->value.integer.value[1] =
  787. max + 1 - ucontrol->value.integer.value[1];
  788. }
  789. return 0;
  790. }
  791. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  792. struct snd_ctl_elem_value *ucontrol)
  793. {
  794. struct soc_mixer_control *mc =
  795. (struct soc_mixer_control *)kcontrol->private_value;
  796. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  797. unsigned int reg = mc->reg;
  798. unsigned int shift = mc->shift;
  799. unsigned int rshift = mc->rshift;
  800. int max = mc->max;
  801. int mask = (1 << fls(max)) - 1;
  802. unsigned short val, val2, val_mask;
  803. val = (ucontrol->value.integer.value[0] & mask);
  804. val_mask = mask << shift;
  805. if (val)
  806. val = max + 1 - val;
  807. val = val << shift;
  808. if (shift != rshift) {
  809. val2 = (ucontrol->value.integer.value[1] & mask);
  810. val_mask |= mask << rshift;
  811. if (val2)
  812. val2 = max + 1 - val2;
  813. val |= val2 << rshift;
  814. }
  815. return snd_soc_update_bits(codec, reg, val_mask, val);
  816. }
  817. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  818. struct snd_ctl_elem_value *ucontrol)
  819. {
  820. struct soc_mixer_control *mc =
  821. (struct soc_mixer_control *)kcontrol->private_value;
  822. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  823. unsigned int reg = mc->reg;
  824. unsigned int reg2 = mc->rreg;
  825. unsigned int shift = mc->shift;
  826. int max = mc->max;
  827. int mask = (1<<fls(max))-1;
  828. ucontrol->value.integer.value[0] =
  829. (snd_soc_read(codec, reg) >> shift) & mask;
  830. ucontrol->value.integer.value[1] =
  831. (snd_soc_read(codec, reg2) >> shift) & mask;
  832. if (ucontrol->value.integer.value[0])
  833. ucontrol->value.integer.value[0] =
  834. max + 1 - ucontrol->value.integer.value[0];
  835. if (ucontrol->value.integer.value[1])
  836. ucontrol->value.integer.value[1] =
  837. max + 1 - ucontrol->value.integer.value[1];
  838. return 0;
  839. }
  840. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  841. struct snd_ctl_elem_value *ucontrol)
  842. {
  843. struct soc_mixer_control *mc =
  844. (struct soc_mixer_control *)kcontrol->private_value;
  845. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  846. unsigned int reg = mc->reg;
  847. unsigned int reg2 = mc->rreg;
  848. unsigned int shift = mc->shift;
  849. int max = mc->max;
  850. int mask = (1 << fls(max)) - 1;
  851. int err;
  852. unsigned short val, val2, val_mask;
  853. val_mask = mask << shift;
  854. val = (ucontrol->value.integer.value[0] & mask);
  855. val2 = (ucontrol->value.integer.value[1] & mask);
  856. if (val)
  857. val = max + 1 - val;
  858. if (val2)
  859. val2 = max + 1 - val2;
  860. val = val << shift;
  861. val2 = val2 << shift;
  862. err = snd_soc_update_bits(codec, reg, val_mask, val);
  863. if (err < 0)
  864. return err;
  865. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  866. return err;
  867. }
  868. /* Codec operation modes */
  869. static const char *twl4030_op_modes_texts[] = {
  870. "Option 2 (voice/audio)", "Option 1 (audio)"
  871. };
  872. static const struct soc_enum twl4030_op_modes_enum =
  873. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  874. ARRAY_SIZE(twl4030_op_modes_texts),
  875. twl4030_op_modes_texts);
  876. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  877. struct snd_ctl_elem_value *ucontrol)
  878. {
  879. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  880. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  881. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  882. unsigned short val;
  883. unsigned short mask, bitmask;
  884. if (twl4030->configured) {
  885. printk(KERN_ERR "twl4030 operation mode cannot be "
  886. "changed on-the-fly\n");
  887. return -EBUSY;
  888. }
  889. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  890. ;
  891. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  892. return -EINVAL;
  893. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  894. mask = (bitmask - 1) << e->shift_l;
  895. if (e->shift_l != e->shift_r) {
  896. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  897. return -EINVAL;
  898. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  899. mask |= (bitmask - 1) << e->shift_r;
  900. }
  901. return snd_soc_update_bits(codec, e->reg, mask, val);
  902. }
  903. /*
  904. * FGAIN volume control:
  905. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  906. */
  907. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  908. /*
  909. * CGAIN volume control:
  910. * 0 dB to 12 dB in 6 dB steps
  911. * value 2 and 3 means 12 dB
  912. */
  913. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  914. /*
  915. * Voice Downlink GAIN volume control:
  916. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  917. */
  918. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  919. /*
  920. * Analog playback gain
  921. * -24 dB to 12 dB in 2 dB steps
  922. */
  923. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  924. /*
  925. * Gain controls tied to outputs
  926. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  927. */
  928. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  929. /*
  930. * Gain control for earpiece amplifier
  931. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  932. */
  933. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  934. /*
  935. * Capture gain after the ADCs
  936. * from 0 dB to 31 dB in 1 dB steps
  937. */
  938. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  939. /*
  940. * Gain control for input amplifiers
  941. * 0 dB to 30 dB in 6 dB steps
  942. */
  943. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  944. /* AVADC clock priority */
  945. static const char *twl4030_avadc_clk_priority_texts[] = {
  946. "Voice high priority", "HiFi high priority"
  947. };
  948. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  949. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  950. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  951. twl4030_avadc_clk_priority_texts);
  952. static const char *twl4030_rampdelay_texts[] = {
  953. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  954. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  955. "3495/2581/1748 ms"
  956. };
  957. static const struct soc_enum twl4030_rampdelay_enum =
  958. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  959. ARRAY_SIZE(twl4030_rampdelay_texts),
  960. twl4030_rampdelay_texts);
  961. /* Vibra H-bridge direction mode */
  962. static const char *twl4030_vibradirmode_texts[] = {
  963. "Vibra H-bridge direction", "Audio data MSB",
  964. };
  965. static const struct soc_enum twl4030_vibradirmode_enum =
  966. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  967. ARRAY_SIZE(twl4030_vibradirmode_texts),
  968. twl4030_vibradirmode_texts);
  969. /* Vibra H-bridge direction */
  970. static const char *twl4030_vibradir_texts[] = {
  971. "Positive polarity", "Negative polarity",
  972. };
  973. static const struct soc_enum twl4030_vibradir_enum =
  974. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  975. ARRAY_SIZE(twl4030_vibradir_texts),
  976. twl4030_vibradir_texts);
  977. /* Digimic Left and right swapping */
  978. static const char *twl4030_digimicswap_texts[] = {
  979. "Not swapped", "Swapped",
  980. };
  981. static const struct soc_enum twl4030_digimicswap_enum =
  982. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  983. ARRAY_SIZE(twl4030_digimicswap_texts),
  984. twl4030_digimicswap_texts);
  985. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  986. /* Codec operation mode control */
  987. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  988. snd_soc_get_enum_double,
  989. snd_soc_put_twl4030_opmode_enum_double),
  990. /* Common playback gain controls */
  991. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  992. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  993. 0, 0x3f, 0, digital_fine_tlv),
  994. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  995. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  996. 0, 0x3f, 0, digital_fine_tlv),
  997. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  998. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  999. 6, 0x2, 0, digital_coarse_tlv),
  1000. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  1001. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1002. 6, 0x2, 0, digital_coarse_tlv),
  1003. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1004. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1005. 3, 0x12, 1, analog_tlv),
  1006. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1007. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1008. 3, 0x12, 1, analog_tlv),
  1009. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1010. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1011. 1, 1, 0),
  1012. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1013. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1014. 1, 1, 0),
  1015. /* Common voice downlink gain controls */
  1016. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1017. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1018. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1019. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1020. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1021. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1022. /* Separate output gain controls */
  1023. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1024. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1025. 4, 3, 0, output_tvl),
  1026. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1027. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1028. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1029. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1030. 4, 3, 0, output_tvl),
  1031. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1032. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1033. /* Common capture gain controls */
  1034. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1035. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1036. 0, 0x1f, 0, digital_capture_tlv),
  1037. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1038. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1039. 0, 0x1f, 0, digital_capture_tlv),
  1040. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1041. 0, 3, 5, 0, input_gain_tlv),
  1042. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1043. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1044. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1045. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1046. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1047. };
  1048. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1049. /* Left channel inputs */
  1050. SND_SOC_DAPM_INPUT("MAINMIC"),
  1051. SND_SOC_DAPM_INPUT("HSMIC"),
  1052. SND_SOC_DAPM_INPUT("AUXL"),
  1053. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1054. /* Right channel inputs */
  1055. SND_SOC_DAPM_INPUT("SUBMIC"),
  1056. SND_SOC_DAPM_INPUT("AUXR"),
  1057. /* Digital microphones (Stereo) */
  1058. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1059. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1060. /* Outputs */
  1061. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1062. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1063. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1064. SND_SOC_DAPM_OUTPUT("HSOL"),
  1065. SND_SOC_DAPM_OUTPUT("HSOR"),
  1066. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1067. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1068. SND_SOC_DAPM_OUTPUT("HFL"),
  1069. SND_SOC_DAPM_OUTPUT("HFR"),
  1070. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1071. /* AIF and APLL clocks for running DAIs (including loopback) */
  1072. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1073. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1074. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1075. /* DACs */
  1076. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1077. SND_SOC_NOPM, 0, 0),
  1078. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1079. SND_SOC_NOPM, 0, 0),
  1080. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1081. SND_SOC_NOPM, 0, 0),
  1082. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1083. SND_SOC_NOPM, 0, 0),
  1084. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1085. SND_SOC_NOPM, 0, 0),
  1086. /* Analog bypasses */
  1087. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1088. &twl4030_dapm_abypassr1_control),
  1089. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1090. &twl4030_dapm_abypassl1_control),
  1091. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1092. &twl4030_dapm_abypassr2_control),
  1093. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1094. &twl4030_dapm_abypassl2_control),
  1095. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1096. &twl4030_dapm_abypassv_control),
  1097. /* Master analog loopback switch */
  1098. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1099. NULL, 0),
  1100. /* Digital bypasses */
  1101. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1102. &twl4030_dapm_dbypassl_control),
  1103. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1104. &twl4030_dapm_dbypassr_control),
  1105. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1106. &twl4030_dapm_dbypassv_control),
  1107. /* Digital mixers, power control for the physical DACs */
  1108. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1109. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1110. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1111. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1112. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1113. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1114. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1115. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1116. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1117. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1118. /* Analog mixers, power control for the physical PGAs */
  1119. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1120. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1121. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1122. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1123. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1124. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1125. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1126. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1127. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1128. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1129. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1130. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1131. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1132. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1133. /* Output MIXER controls */
  1134. /* Earpiece */
  1135. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1136. &twl4030_dapm_earpiece_controls[0],
  1137. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1138. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1139. 0, 0, NULL, 0, earpiecepga_event,
  1140. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1141. /* PreDrivL/R */
  1142. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1143. &twl4030_dapm_predrivel_controls[0],
  1144. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1145. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1146. 0, 0, NULL, 0, predrivelpga_event,
  1147. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1148. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1149. &twl4030_dapm_predriver_controls[0],
  1150. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1151. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1152. 0, 0, NULL, 0, predriverpga_event,
  1153. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1154. /* HeadsetL/R */
  1155. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1156. &twl4030_dapm_hsol_controls[0],
  1157. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1158. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1159. 0, 0, NULL, 0, headsetlpga_event,
  1160. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1161. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1162. &twl4030_dapm_hsor_controls[0],
  1163. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1164. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1165. 0, 0, NULL, 0, headsetrpga_event,
  1166. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1167. /* CarkitL/R */
  1168. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1169. &twl4030_dapm_carkitl_controls[0],
  1170. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1171. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1172. 0, 0, NULL, 0, carkitlpga_event,
  1173. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1174. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1175. &twl4030_dapm_carkitr_controls[0],
  1176. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1177. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1178. 0, 0, NULL, 0, carkitrpga_event,
  1179. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1180. /* Output MUX controls */
  1181. /* HandsfreeL/R */
  1182. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1183. &twl4030_dapm_handsfreel_control),
  1184. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1185. &twl4030_dapm_handsfreelmute_control),
  1186. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1187. 0, 0, NULL, 0, handsfreelpga_event,
  1188. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1189. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1190. &twl4030_dapm_handsfreer_control),
  1191. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1192. &twl4030_dapm_handsfreermute_control),
  1193. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1194. 0, 0, NULL, 0, handsfreerpga_event,
  1195. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1196. /* Vibra */
  1197. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1198. &twl4030_dapm_vibra_control, vibramux_event,
  1199. SND_SOC_DAPM_PRE_PMU),
  1200. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1201. &twl4030_dapm_vibrapath_control),
  1202. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1203. capture */
  1204. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1205. SND_SOC_NOPM, 0, 0),
  1206. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1207. SND_SOC_NOPM, 0, 0),
  1208. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1209. SND_SOC_NOPM, 0, 0),
  1210. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1211. SND_SOC_NOPM, 0, 0),
  1212. /* Analog/Digital mic path selection.
  1213. TX1 Left/Right: either analog Left/Right or Digimic0
  1214. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1215. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1216. &twl4030_dapm_micpathtx1_control, micpath_event,
  1217. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1218. SND_SOC_DAPM_POST_REG),
  1219. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1220. &twl4030_dapm_micpathtx2_control, micpath_event,
  1221. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1222. SND_SOC_DAPM_POST_REG),
  1223. /* Analog input mixers for the capture amplifiers */
  1224. SND_SOC_DAPM_MIXER("Analog Left",
  1225. TWL4030_REG_ANAMICL, 4, 0,
  1226. &twl4030_dapm_analoglmic_controls[0],
  1227. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1228. SND_SOC_DAPM_MIXER("Analog Right",
  1229. TWL4030_REG_ANAMICR, 4, 0,
  1230. &twl4030_dapm_analogrmic_controls[0],
  1231. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1232. SND_SOC_DAPM_PGA("ADC Physical Left",
  1233. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1234. SND_SOC_DAPM_PGA("ADC Physical Right",
  1235. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1236. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1237. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1238. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1239. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1240. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1241. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1242. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1243. };
  1244. static const struct snd_soc_dapm_route intercon[] = {
  1245. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1246. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1247. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1248. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1249. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1250. /* Supply for the digital part (APLL) */
  1251. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1252. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1253. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1254. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1255. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1256. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1257. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1258. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1259. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1260. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1261. /* Internal playback routings */
  1262. /* Earpiece */
  1263. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1264. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1265. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1266. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1267. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1268. /* PreDrivL */
  1269. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1270. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1271. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1272. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1273. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1274. /* PreDrivR */
  1275. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1276. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1277. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1278. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1279. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1280. /* HeadsetL */
  1281. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1282. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1283. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1284. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1285. /* HeadsetR */
  1286. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1287. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1288. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1289. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1290. /* CarkitL */
  1291. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1292. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1293. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1294. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1295. /* CarkitR */
  1296. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1297. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1298. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1299. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1300. /* HandsfreeL */
  1301. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1302. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1303. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1304. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1305. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1306. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1307. /* HandsfreeR */
  1308. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1309. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1310. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1311. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1312. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1313. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1314. /* Vibra */
  1315. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1316. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1317. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1318. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1319. /* outputs */
  1320. /* Must be always connected (for AIF and APLL) */
  1321. {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
  1322. {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
  1323. {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
  1324. {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
  1325. /* Must be always connected (for APLL) */
  1326. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1327. /* Physical outputs */
  1328. {"EARPIECE", NULL, "Earpiece PGA"},
  1329. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1330. {"PREDRIVER", NULL, "PredriveR PGA"},
  1331. {"HSOL", NULL, "HeadsetL PGA"},
  1332. {"HSOR", NULL, "HeadsetR PGA"},
  1333. {"CARKITL", NULL, "CarkitL PGA"},
  1334. {"CARKITR", NULL, "CarkitR PGA"},
  1335. {"HFL", NULL, "HandsfreeL PGA"},
  1336. {"HFR", NULL, "HandsfreeR PGA"},
  1337. {"Vibra Route", "Audio", "Vibra Mux"},
  1338. {"VIBRA", NULL, "Vibra Route"},
  1339. /* Capture path */
  1340. /* Must be always connected (for AIF and APLL) */
  1341. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1342. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1343. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1344. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1345. /* Physical inputs */
  1346. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1347. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1348. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1349. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1350. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1351. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1352. {"ADC Physical Left", NULL, "Analog Left"},
  1353. {"ADC Physical Right", NULL, "Analog Right"},
  1354. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1355. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1356. /* TX1 Left capture path */
  1357. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1358. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1359. /* TX1 Right capture path */
  1360. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1361. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1362. /* TX2 Left capture path */
  1363. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1364. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1365. /* TX2 Right capture path */
  1366. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1367. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1368. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1369. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1370. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1371. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1372. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1373. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1374. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1375. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1376. /* Analog bypass routes */
  1377. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1378. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1379. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1380. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1381. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1382. /* Supply for the Analog loopbacks */
  1383. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1384. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1385. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1386. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1387. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1388. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1389. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1390. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1391. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1392. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1393. /* Digital bypass routes */
  1394. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1395. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1396. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1397. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1398. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1399. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1400. };
  1401. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1402. {
  1403. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1404. ARRAY_SIZE(twl4030_dapm_widgets));
  1405. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1406. return 0;
  1407. }
  1408. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1409. enum snd_soc_bias_level level)
  1410. {
  1411. switch (level) {
  1412. case SND_SOC_BIAS_ON:
  1413. break;
  1414. case SND_SOC_BIAS_PREPARE:
  1415. break;
  1416. case SND_SOC_BIAS_STANDBY:
  1417. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1418. twl4030_codec_enable(codec, 1);
  1419. break;
  1420. case SND_SOC_BIAS_OFF:
  1421. twl4030_codec_enable(codec, 0);
  1422. break;
  1423. }
  1424. codec->bias_level = level;
  1425. return 0;
  1426. }
  1427. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1428. struct snd_pcm_substream *mst_substream)
  1429. {
  1430. struct snd_pcm_substream *slv_substream;
  1431. /* Pick the stream, which need to be constrained */
  1432. if (mst_substream == twl4030->master_substream)
  1433. slv_substream = twl4030->slave_substream;
  1434. else if (mst_substream == twl4030->slave_substream)
  1435. slv_substream = twl4030->master_substream;
  1436. else /* This should not happen.. */
  1437. return;
  1438. /* Set the constraints according to the already configured stream */
  1439. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1440. SNDRV_PCM_HW_PARAM_RATE,
  1441. twl4030->rate,
  1442. twl4030->rate);
  1443. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1444. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1445. twl4030->sample_bits,
  1446. twl4030->sample_bits);
  1447. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1448. SNDRV_PCM_HW_PARAM_CHANNELS,
  1449. twl4030->channels,
  1450. twl4030->channels);
  1451. }
  1452. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1453. * capture has to be enabled/disabled. */
  1454. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1455. int enable)
  1456. {
  1457. u8 reg, mask;
  1458. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1459. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1460. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1461. else
  1462. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1463. if (enable)
  1464. reg |= mask;
  1465. else
  1466. reg &= ~mask;
  1467. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1468. }
  1469. static int twl4030_startup(struct snd_pcm_substream *substream,
  1470. struct snd_soc_dai *dai)
  1471. {
  1472. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1473. struct snd_soc_device *socdev = rtd->socdev;
  1474. struct snd_soc_codec *codec = socdev->card->codec;
  1475. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1476. if (twl4030->master_substream) {
  1477. twl4030->slave_substream = substream;
  1478. /* The DAI has one configuration for playback and capture, so
  1479. * if the DAI has been already configured then constrain this
  1480. * substream to match it. */
  1481. if (twl4030->configured)
  1482. twl4030_constraints(twl4030, twl4030->master_substream);
  1483. } else {
  1484. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1485. TWL4030_OPTION_1)) {
  1486. /* In option2 4 channel is not supported, set the
  1487. * constraint for the first stream for channels, the
  1488. * second stream will 'inherit' this cosntraint */
  1489. snd_pcm_hw_constraint_minmax(substream->runtime,
  1490. SNDRV_PCM_HW_PARAM_CHANNELS,
  1491. 2, 2);
  1492. }
  1493. twl4030->master_substream = substream;
  1494. }
  1495. return 0;
  1496. }
  1497. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1498. struct snd_soc_dai *dai)
  1499. {
  1500. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1501. struct snd_soc_device *socdev = rtd->socdev;
  1502. struct snd_soc_codec *codec = socdev->card->codec;
  1503. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1504. if (twl4030->master_substream == substream)
  1505. twl4030->master_substream = twl4030->slave_substream;
  1506. twl4030->slave_substream = NULL;
  1507. /* If all streams are closed, or the remaining stream has not yet
  1508. * been configured than set the DAI as not configured. */
  1509. if (!twl4030->master_substream)
  1510. twl4030->configured = 0;
  1511. else if (!twl4030->master_substream->runtime->channels)
  1512. twl4030->configured = 0;
  1513. /* If the closing substream had 4 channel, do the necessary cleanup */
  1514. if (substream->runtime->channels == 4)
  1515. twl4030_tdm_enable(codec, substream->stream, 0);
  1516. }
  1517. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1518. struct snd_pcm_hw_params *params,
  1519. struct snd_soc_dai *dai)
  1520. {
  1521. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1522. struct snd_soc_device *socdev = rtd->socdev;
  1523. struct snd_soc_codec *codec = socdev->card->codec;
  1524. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1525. u8 mode, old_mode, format, old_format;
  1526. /* If the substream has 4 channel, do the necessary setup */
  1527. if (params_channels(params) == 4) {
  1528. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1529. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1530. /* Safety check: are we in the correct operating mode and
  1531. * the interface is in TDM mode? */
  1532. if ((mode & TWL4030_OPTION_1) &&
  1533. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1534. twl4030_tdm_enable(codec, substream->stream, 1);
  1535. else
  1536. return -EINVAL;
  1537. }
  1538. if (twl4030->configured)
  1539. /* Ignoring hw_params for already configured DAI */
  1540. return 0;
  1541. /* bit rate */
  1542. old_mode = twl4030_read_reg_cache(codec,
  1543. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1544. mode = old_mode & ~TWL4030_APLL_RATE;
  1545. switch (params_rate(params)) {
  1546. case 8000:
  1547. mode |= TWL4030_APLL_RATE_8000;
  1548. break;
  1549. case 11025:
  1550. mode |= TWL4030_APLL_RATE_11025;
  1551. break;
  1552. case 12000:
  1553. mode |= TWL4030_APLL_RATE_12000;
  1554. break;
  1555. case 16000:
  1556. mode |= TWL4030_APLL_RATE_16000;
  1557. break;
  1558. case 22050:
  1559. mode |= TWL4030_APLL_RATE_22050;
  1560. break;
  1561. case 24000:
  1562. mode |= TWL4030_APLL_RATE_24000;
  1563. break;
  1564. case 32000:
  1565. mode |= TWL4030_APLL_RATE_32000;
  1566. break;
  1567. case 44100:
  1568. mode |= TWL4030_APLL_RATE_44100;
  1569. break;
  1570. case 48000:
  1571. mode |= TWL4030_APLL_RATE_48000;
  1572. break;
  1573. case 96000:
  1574. mode |= TWL4030_APLL_RATE_96000;
  1575. break;
  1576. default:
  1577. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1578. params_rate(params));
  1579. return -EINVAL;
  1580. }
  1581. if (mode != old_mode) {
  1582. /* change rate and set CODECPDZ */
  1583. twl4030_codec_enable(codec, 0);
  1584. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1585. twl4030_codec_enable(codec, 1);
  1586. }
  1587. /* sample size */
  1588. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1589. format = old_format;
  1590. format &= ~TWL4030_DATA_WIDTH;
  1591. switch (params_format(params)) {
  1592. case SNDRV_PCM_FORMAT_S16_LE:
  1593. format |= TWL4030_DATA_WIDTH_16S_16W;
  1594. break;
  1595. case SNDRV_PCM_FORMAT_S24_LE:
  1596. format |= TWL4030_DATA_WIDTH_32S_24W;
  1597. break;
  1598. default:
  1599. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1600. params_format(params));
  1601. return -EINVAL;
  1602. }
  1603. if (format != old_format) {
  1604. /* clear CODECPDZ before changing format (codec requirement) */
  1605. twl4030_codec_enable(codec, 0);
  1606. /* change format */
  1607. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1608. /* set CODECPDZ afterwards */
  1609. twl4030_codec_enable(codec, 1);
  1610. }
  1611. /* Store the important parameters for the DAI configuration and set
  1612. * the DAI as configured */
  1613. twl4030->configured = 1;
  1614. twl4030->rate = params_rate(params);
  1615. twl4030->sample_bits = hw_param_interval(params,
  1616. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1617. twl4030->channels = params_channels(params);
  1618. /* If both playback and capture streams are open, and one of them
  1619. * is setting the hw parameters right now (since we are here), set
  1620. * constraints to the other stream to match the current one. */
  1621. if (twl4030->slave_substream)
  1622. twl4030_constraints(twl4030, substream);
  1623. return 0;
  1624. }
  1625. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1626. int clk_id, unsigned int freq, int dir)
  1627. {
  1628. struct snd_soc_codec *codec = codec_dai->codec;
  1629. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1630. switch (freq) {
  1631. case 19200000:
  1632. case 26000000:
  1633. case 38400000:
  1634. break;
  1635. default:
  1636. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1637. return -EINVAL;
  1638. }
  1639. if ((freq / 1000) != twl4030->sysclk) {
  1640. dev_err(codec->dev,
  1641. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1642. freq, twl4030->sysclk * 1000);
  1643. return -EINVAL;
  1644. }
  1645. return 0;
  1646. }
  1647. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1648. unsigned int fmt)
  1649. {
  1650. struct snd_soc_codec *codec = codec_dai->codec;
  1651. u8 old_format, format;
  1652. /* get format */
  1653. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1654. format = old_format;
  1655. /* set master/slave audio interface */
  1656. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1657. case SND_SOC_DAIFMT_CBM_CFM:
  1658. format &= ~(TWL4030_AIF_SLAVE_EN);
  1659. format &= ~(TWL4030_CLK256FS_EN);
  1660. break;
  1661. case SND_SOC_DAIFMT_CBS_CFS:
  1662. format |= TWL4030_AIF_SLAVE_EN;
  1663. format |= TWL4030_CLK256FS_EN;
  1664. break;
  1665. default:
  1666. return -EINVAL;
  1667. }
  1668. /* interface format */
  1669. format &= ~TWL4030_AIF_FORMAT;
  1670. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1671. case SND_SOC_DAIFMT_I2S:
  1672. format |= TWL4030_AIF_FORMAT_CODEC;
  1673. break;
  1674. case SND_SOC_DAIFMT_DSP_A:
  1675. format |= TWL4030_AIF_FORMAT_TDM;
  1676. break;
  1677. default:
  1678. return -EINVAL;
  1679. }
  1680. if (format != old_format) {
  1681. /* clear CODECPDZ before changing format (codec requirement) */
  1682. twl4030_codec_enable(codec, 0);
  1683. /* change format */
  1684. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1685. /* set CODECPDZ afterwards */
  1686. twl4030_codec_enable(codec, 1);
  1687. }
  1688. return 0;
  1689. }
  1690. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1691. {
  1692. struct snd_soc_codec *codec = dai->codec;
  1693. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1694. if (tristate)
  1695. reg |= TWL4030_AIF_TRI_EN;
  1696. else
  1697. reg &= ~TWL4030_AIF_TRI_EN;
  1698. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1699. }
  1700. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1701. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1702. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1703. int enable)
  1704. {
  1705. u8 reg, mask;
  1706. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1707. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1708. mask = TWL4030_ARXL1_VRX_EN;
  1709. else
  1710. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1711. if (enable)
  1712. reg |= mask;
  1713. else
  1714. reg &= ~mask;
  1715. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1716. }
  1717. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1718. struct snd_soc_dai *dai)
  1719. {
  1720. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1721. struct snd_soc_device *socdev = rtd->socdev;
  1722. struct snd_soc_codec *codec = socdev->card->codec;
  1723. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1724. u8 mode;
  1725. /* If the system master clock is not 26MHz, the voice PCM interface is
  1726. * not avilable.
  1727. */
  1728. if (twl4030->sysclk != 26000) {
  1729. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1730. "the Voice interface needs 26MHz APLL mclk\n",
  1731. twl4030->sysclk * 1000);
  1732. return -EINVAL;
  1733. }
  1734. /* If the codec mode is not option2, the voice PCM interface is not
  1735. * avilable.
  1736. */
  1737. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1738. & TWL4030_OPT_MODE;
  1739. if (mode != TWL4030_OPTION_2) {
  1740. printk(KERN_ERR "TWL4030 voice startup: "
  1741. "the codec mode is not option2\n");
  1742. return -EINVAL;
  1743. }
  1744. return 0;
  1745. }
  1746. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1747. struct snd_soc_dai *dai)
  1748. {
  1749. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1750. struct snd_soc_device *socdev = rtd->socdev;
  1751. struct snd_soc_codec *codec = socdev->card->codec;
  1752. /* Enable voice digital filters */
  1753. twl4030_voice_enable(codec, substream->stream, 0);
  1754. }
  1755. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1756. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1757. {
  1758. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1759. struct snd_soc_device *socdev = rtd->socdev;
  1760. struct snd_soc_codec *codec = socdev->card->codec;
  1761. u8 old_mode, mode;
  1762. /* Enable voice digital filters */
  1763. twl4030_voice_enable(codec, substream->stream, 1);
  1764. /* bit rate */
  1765. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1766. & ~(TWL4030_CODECPDZ);
  1767. mode = old_mode;
  1768. switch (params_rate(params)) {
  1769. case 8000:
  1770. mode &= ~(TWL4030_SEL_16K);
  1771. break;
  1772. case 16000:
  1773. mode |= TWL4030_SEL_16K;
  1774. break;
  1775. default:
  1776. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1777. params_rate(params));
  1778. return -EINVAL;
  1779. }
  1780. if (mode != old_mode) {
  1781. /* change rate and set CODECPDZ */
  1782. twl4030_codec_enable(codec, 0);
  1783. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1784. twl4030_codec_enable(codec, 1);
  1785. }
  1786. return 0;
  1787. }
  1788. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1789. int clk_id, unsigned int freq, int dir)
  1790. {
  1791. struct snd_soc_codec *codec = codec_dai->codec;
  1792. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1793. if (freq != 26000000) {
  1794. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1795. "interface needs 26MHz APLL mclk\n", freq);
  1796. return -EINVAL;
  1797. }
  1798. if ((freq / 1000) != twl4030->sysclk) {
  1799. dev_err(codec->dev,
  1800. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1801. freq, twl4030->sysclk * 1000);
  1802. return -EINVAL;
  1803. }
  1804. return 0;
  1805. }
  1806. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1807. unsigned int fmt)
  1808. {
  1809. struct snd_soc_codec *codec = codec_dai->codec;
  1810. u8 old_format, format;
  1811. /* get format */
  1812. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1813. format = old_format;
  1814. /* set master/slave audio interface */
  1815. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1816. case SND_SOC_DAIFMT_CBM_CFM:
  1817. format &= ~(TWL4030_VIF_SLAVE_EN);
  1818. break;
  1819. case SND_SOC_DAIFMT_CBS_CFS:
  1820. format |= TWL4030_VIF_SLAVE_EN;
  1821. break;
  1822. default:
  1823. return -EINVAL;
  1824. }
  1825. /* clock inversion */
  1826. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1827. case SND_SOC_DAIFMT_IB_NF:
  1828. format &= ~(TWL4030_VIF_FORMAT);
  1829. break;
  1830. case SND_SOC_DAIFMT_NB_IF:
  1831. format |= TWL4030_VIF_FORMAT;
  1832. break;
  1833. default:
  1834. return -EINVAL;
  1835. }
  1836. if (format != old_format) {
  1837. /* change format and set CODECPDZ */
  1838. twl4030_codec_enable(codec, 0);
  1839. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1840. twl4030_codec_enable(codec, 1);
  1841. }
  1842. return 0;
  1843. }
  1844. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1845. {
  1846. struct snd_soc_codec *codec = dai->codec;
  1847. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1848. if (tristate)
  1849. reg |= TWL4030_VIF_TRI_EN;
  1850. else
  1851. reg &= ~TWL4030_VIF_TRI_EN;
  1852. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1853. }
  1854. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1855. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1856. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1857. .startup = twl4030_startup,
  1858. .shutdown = twl4030_shutdown,
  1859. .hw_params = twl4030_hw_params,
  1860. .set_sysclk = twl4030_set_dai_sysclk,
  1861. .set_fmt = twl4030_set_dai_fmt,
  1862. .set_tristate = twl4030_set_tristate,
  1863. };
  1864. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1865. .startup = twl4030_voice_startup,
  1866. .shutdown = twl4030_voice_shutdown,
  1867. .hw_params = twl4030_voice_hw_params,
  1868. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1869. .set_fmt = twl4030_voice_set_dai_fmt,
  1870. .set_tristate = twl4030_voice_set_tristate,
  1871. };
  1872. struct snd_soc_dai twl4030_dai[] = {
  1873. {
  1874. .name = "twl4030",
  1875. .playback = {
  1876. .stream_name = "HiFi Playback",
  1877. .channels_min = 2,
  1878. .channels_max = 4,
  1879. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1880. .formats = TWL4030_FORMATS,},
  1881. .capture = {
  1882. .stream_name = "Capture",
  1883. .channels_min = 2,
  1884. .channels_max = 4,
  1885. .rates = TWL4030_RATES,
  1886. .formats = TWL4030_FORMATS,},
  1887. .ops = &twl4030_dai_ops,
  1888. },
  1889. {
  1890. .name = "twl4030 Voice",
  1891. .playback = {
  1892. .stream_name = "Voice Playback",
  1893. .channels_min = 1,
  1894. .channels_max = 1,
  1895. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1896. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1897. .capture = {
  1898. .stream_name = "Capture",
  1899. .channels_min = 1,
  1900. .channels_max = 2,
  1901. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1902. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1903. .ops = &twl4030_dai_voice_ops,
  1904. },
  1905. };
  1906. EXPORT_SYMBOL_GPL(twl4030_dai);
  1907. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1908. {
  1909. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1910. struct snd_soc_codec *codec = socdev->card->codec;
  1911. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1912. return 0;
  1913. }
  1914. static int twl4030_soc_resume(struct platform_device *pdev)
  1915. {
  1916. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1917. struct snd_soc_codec *codec = socdev->card->codec;
  1918. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1919. return 0;
  1920. }
  1921. static struct snd_soc_codec *twl4030_codec;
  1922. static int twl4030_soc_probe(struct platform_device *pdev)
  1923. {
  1924. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1925. struct snd_soc_codec *codec;
  1926. int ret;
  1927. BUG_ON(!twl4030_codec);
  1928. codec = twl4030_codec;
  1929. socdev->card->codec = codec;
  1930. twl4030_init_chip(pdev);
  1931. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1932. /* register pcms */
  1933. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1934. if (ret < 0) {
  1935. dev_err(&pdev->dev, "failed to create pcms\n");
  1936. return ret;
  1937. }
  1938. snd_soc_add_controls(codec, twl4030_snd_controls,
  1939. ARRAY_SIZE(twl4030_snd_controls));
  1940. twl4030_add_widgets(codec);
  1941. return 0;
  1942. }
  1943. static int twl4030_soc_remove(struct platform_device *pdev)
  1944. {
  1945. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1946. struct snd_soc_codec *codec = socdev->card->codec;
  1947. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1948. snd_soc_free_pcms(socdev);
  1949. snd_soc_dapm_free(socdev);
  1950. return 0;
  1951. }
  1952. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1953. {
  1954. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1955. struct snd_soc_codec *codec;
  1956. struct twl4030_priv *twl4030;
  1957. int ret;
  1958. if (!pdata) {
  1959. dev_err(&pdev->dev, "platform_data is missing\n");
  1960. return -EINVAL;
  1961. }
  1962. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1963. if (twl4030 == NULL) {
  1964. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1965. return -ENOMEM;
  1966. }
  1967. codec = &twl4030->codec;
  1968. snd_soc_codec_set_drvdata(codec, twl4030);
  1969. codec->dev = &pdev->dev;
  1970. twl4030_dai[0].dev = &pdev->dev;
  1971. twl4030_dai[1].dev = &pdev->dev;
  1972. mutex_init(&codec->mutex);
  1973. INIT_LIST_HEAD(&codec->dapm_widgets);
  1974. INIT_LIST_HEAD(&codec->dapm_paths);
  1975. codec->name = "twl4030";
  1976. codec->owner = THIS_MODULE;
  1977. codec->read = twl4030_read_reg_cache;
  1978. codec->write = twl4030_write;
  1979. codec->set_bias_level = twl4030_set_bias_level;
  1980. codec->dai = twl4030_dai;
  1981. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  1982. codec->reg_cache_size = sizeof(twl4030_reg);
  1983. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1984. GFP_KERNEL);
  1985. if (codec->reg_cache == NULL) {
  1986. ret = -ENOMEM;
  1987. goto error_cache;
  1988. }
  1989. platform_set_drvdata(pdev, twl4030);
  1990. twl4030_codec = codec;
  1991. /* Set the defaults, and power up the codec */
  1992. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  1993. codec->bias_level = SND_SOC_BIAS_OFF;
  1994. ret = snd_soc_register_codec(codec);
  1995. if (ret != 0) {
  1996. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1997. goto error_codec;
  1998. }
  1999. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2000. if (ret != 0) {
  2001. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2002. snd_soc_unregister_codec(codec);
  2003. goto error_codec;
  2004. }
  2005. return 0;
  2006. error_codec:
  2007. twl4030_codec_enable(codec, 0);
  2008. kfree(codec->reg_cache);
  2009. error_cache:
  2010. kfree(twl4030);
  2011. return ret;
  2012. }
  2013. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2014. {
  2015. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2016. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2017. snd_soc_unregister_codec(&twl4030->codec);
  2018. kfree(twl4030->codec.reg_cache);
  2019. kfree(twl4030);
  2020. twl4030_codec = NULL;
  2021. return 0;
  2022. }
  2023. MODULE_ALIAS("platform:twl4030_codec_audio");
  2024. static struct platform_driver twl4030_codec_driver = {
  2025. .probe = twl4030_codec_probe,
  2026. .remove = __devexit_p(twl4030_codec_remove),
  2027. .driver = {
  2028. .name = "twl4030_codec_audio",
  2029. .owner = THIS_MODULE,
  2030. },
  2031. };
  2032. static int __init twl4030_modinit(void)
  2033. {
  2034. return platform_driver_register(&twl4030_codec_driver);
  2035. }
  2036. module_init(twl4030_modinit);
  2037. static void __exit twl4030_exit(void)
  2038. {
  2039. platform_driver_unregister(&twl4030_codec_driver);
  2040. }
  2041. module_exit(twl4030_exit);
  2042. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2043. .probe = twl4030_soc_probe,
  2044. .remove = twl4030_soc_remove,
  2045. .suspend = twl4030_soc_suspend,
  2046. .resume = twl4030_soc_resume,
  2047. };
  2048. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2049. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2050. MODULE_AUTHOR("Steve Sakoman");
  2051. MODULE_LICENSE("GPL");