wm8993.c 43 KB

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  1. /*
  2. * wm8993.c -- WM8993 ALSA SoC audio driver
  3. *
  4. * Copyright 2009, 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/tlv.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/wm8993.h>
  27. #include "wm8993.h"
  28. #include "wm_hubs.h"
  29. static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
  30. 0x8993, /* R0 - Software Reset */
  31. 0x0000, /* R1 - Power Management (1) */
  32. 0x6000, /* R2 - Power Management (2) */
  33. 0x0000, /* R3 - Power Management (3) */
  34. 0x4050, /* R4 - Audio Interface (1) */
  35. 0x4000, /* R5 - Audio Interface (2) */
  36. 0x01C8, /* R6 - Clocking 1 */
  37. 0x0000, /* R7 - Clocking 2 */
  38. 0x0000, /* R8 - Audio Interface (3) */
  39. 0x0040, /* R9 - Audio Interface (4) */
  40. 0x0004, /* R10 - DAC CTRL */
  41. 0x00C0, /* R11 - Left DAC Digital Volume */
  42. 0x00C0, /* R12 - Right DAC Digital Volume */
  43. 0x0000, /* R13 - Digital Side Tone */
  44. 0x0300, /* R14 - ADC CTRL */
  45. 0x00C0, /* R15 - Left ADC Digital Volume */
  46. 0x00C0, /* R16 - Right ADC Digital Volume */
  47. 0x0000, /* R17 */
  48. 0x0000, /* R18 - GPIO CTRL 1 */
  49. 0x0010, /* R19 - GPIO1 */
  50. 0x0000, /* R20 - IRQ_DEBOUNCE */
  51. 0x0000, /* R21 */
  52. 0x8000, /* R22 - GPIOCTRL 2 */
  53. 0x0800, /* R23 - GPIO_POL */
  54. 0x008B, /* R24 - Left Line Input 1&2 Volume */
  55. 0x008B, /* R25 - Left Line Input 3&4 Volume */
  56. 0x008B, /* R26 - Right Line Input 1&2 Volume */
  57. 0x008B, /* R27 - Right Line Input 3&4 Volume */
  58. 0x006D, /* R28 - Left Output Volume */
  59. 0x006D, /* R29 - Right Output Volume */
  60. 0x0066, /* R30 - Line Outputs Volume */
  61. 0x0020, /* R31 - HPOUT2 Volume */
  62. 0x0079, /* R32 - Left OPGA Volume */
  63. 0x0079, /* R33 - Right OPGA Volume */
  64. 0x0003, /* R34 - SPKMIXL Attenuation */
  65. 0x0003, /* R35 - SPKMIXR Attenuation */
  66. 0x0011, /* R36 - SPKOUT Mixers */
  67. 0x0100, /* R37 - SPKOUT Boost */
  68. 0x0079, /* R38 - Speaker Volume Left */
  69. 0x0079, /* R39 - Speaker Volume Right */
  70. 0x0000, /* R40 - Input Mixer2 */
  71. 0x0000, /* R41 - Input Mixer3 */
  72. 0x0000, /* R42 - Input Mixer4 */
  73. 0x0000, /* R43 - Input Mixer5 */
  74. 0x0000, /* R44 - Input Mixer6 */
  75. 0x0000, /* R45 - Output Mixer1 */
  76. 0x0000, /* R46 - Output Mixer2 */
  77. 0x0000, /* R47 - Output Mixer3 */
  78. 0x0000, /* R48 - Output Mixer4 */
  79. 0x0000, /* R49 - Output Mixer5 */
  80. 0x0000, /* R50 - Output Mixer6 */
  81. 0x0000, /* R51 - HPOUT2 Mixer */
  82. 0x0000, /* R52 - Line Mixer1 */
  83. 0x0000, /* R53 - Line Mixer2 */
  84. 0x0000, /* R54 - Speaker Mixer */
  85. 0x0000, /* R55 - Additional Control */
  86. 0x0000, /* R56 - AntiPOP1 */
  87. 0x0000, /* R57 - AntiPOP2 */
  88. 0x0000, /* R58 - MICBIAS */
  89. 0x0000, /* R59 */
  90. 0x0000, /* R60 - FLL Control 1 */
  91. 0x0000, /* R61 - FLL Control 2 */
  92. 0x0000, /* R62 - FLL Control 3 */
  93. 0x2EE0, /* R63 - FLL Control 4 */
  94. 0x0002, /* R64 - FLL Control 5 */
  95. 0x2287, /* R65 - Clocking 3 */
  96. 0x025F, /* R66 - Clocking 4 */
  97. 0x0000, /* R67 - MW Slave Control */
  98. 0x0000, /* R68 */
  99. 0x0002, /* R69 - Bus Control 1 */
  100. 0x0000, /* R70 - Write Sequencer 0 */
  101. 0x0000, /* R71 - Write Sequencer 1 */
  102. 0x0000, /* R72 - Write Sequencer 2 */
  103. 0x0000, /* R73 - Write Sequencer 3 */
  104. 0x0000, /* R74 - Write Sequencer 4 */
  105. 0x0000, /* R75 - Write Sequencer 5 */
  106. 0x1F25, /* R76 - Charge Pump 1 */
  107. 0x0000, /* R77 */
  108. 0x0000, /* R78 */
  109. 0x0000, /* R79 */
  110. 0x0000, /* R80 */
  111. 0x0000, /* R81 - Class W 0 */
  112. 0x0000, /* R82 */
  113. 0x0000, /* R83 */
  114. 0x0000, /* R84 - DC Servo 0 */
  115. 0x054A, /* R85 - DC Servo 1 */
  116. 0x0000, /* R86 */
  117. 0x0000, /* R87 - DC Servo 3 */
  118. 0x0000, /* R88 - DC Servo Readback 0 */
  119. 0x0000, /* R89 - DC Servo Readback 1 */
  120. 0x0000, /* R90 - DC Servo Readback 2 */
  121. 0x0000, /* R91 */
  122. 0x0000, /* R92 */
  123. 0x0000, /* R93 */
  124. 0x0000, /* R94 */
  125. 0x0000, /* R95 */
  126. 0x0100, /* R96 - Analogue HP 0 */
  127. 0x0000, /* R97 */
  128. 0x0000, /* R98 - EQ1 */
  129. 0x000C, /* R99 - EQ2 */
  130. 0x000C, /* R100 - EQ3 */
  131. 0x000C, /* R101 - EQ4 */
  132. 0x000C, /* R102 - EQ5 */
  133. 0x000C, /* R103 - EQ6 */
  134. 0x0FCA, /* R104 - EQ7 */
  135. 0x0400, /* R105 - EQ8 */
  136. 0x00D8, /* R106 - EQ9 */
  137. 0x1EB5, /* R107 - EQ10 */
  138. 0xF145, /* R108 - EQ11 */
  139. 0x0B75, /* R109 - EQ12 */
  140. 0x01C5, /* R110 - EQ13 */
  141. 0x1C58, /* R111 - EQ14 */
  142. 0xF373, /* R112 - EQ15 */
  143. 0x0A54, /* R113 - EQ16 */
  144. 0x0558, /* R114 - EQ17 */
  145. 0x168E, /* R115 - EQ18 */
  146. 0xF829, /* R116 - EQ19 */
  147. 0x07AD, /* R117 - EQ20 */
  148. 0x1103, /* R118 - EQ21 */
  149. 0x0564, /* R119 - EQ22 */
  150. 0x0559, /* R120 - EQ23 */
  151. 0x4000, /* R121 - EQ24 */
  152. 0x0000, /* R122 - Digital Pulls */
  153. 0x0F08, /* R123 - DRC Control 1 */
  154. 0x0000, /* R124 - DRC Control 2 */
  155. 0x0080, /* R125 - DRC Control 3 */
  156. 0x0000, /* R126 - DRC Control 4 */
  157. };
  158. static struct {
  159. int ratio;
  160. int clk_sys_rate;
  161. } clk_sys_rates[] = {
  162. { 64, 0 },
  163. { 128, 1 },
  164. { 192, 2 },
  165. { 256, 3 },
  166. { 384, 4 },
  167. { 512, 5 },
  168. { 768, 6 },
  169. { 1024, 7 },
  170. { 1408, 8 },
  171. { 1536, 9 },
  172. };
  173. static struct {
  174. int rate;
  175. int sample_rate;
  176. } sample_rates[] = {
  177. { 8000, 0 },
  178. { 11025, 1 },
  179. { 12000, 1 },
  180. { 16000, 2 },
  181. { 22050, 3 },
  182. { 24000, 3 },
  183. { 32000, 4 },
  184. { 44100, 5 },
  185. { 48000, 5 },
  186. };
  187. static struct {
  188. int div; /* *10 due to .5s */
  189. int bclk_div;
  190. } bclk_divs[] = {
  191. { 10, 0 },
  192. { 15, 1 },
  193. { 20, 2 },
  194. { 30, 3 },
  195. { 40, 4 },
  196. { 55, 5 },
  197. { 60, 6 },
  198. { 80, 7 },
  199. { 110, 8 },
  200. { 120, 9 },
  201. { 160, 10 },
  202. { 220, 11 },
  203. { 240, 12 },
  204. { 320, 13 },
  205. { 440, 14 },
  206. { 480, 15 },
  207. };
  208. struct wm8993_priv {
  209. struct wm_hubs_data hubs_data;
  210. u16 reg_cache[WM8993_REGISTER_COUNT];
  211. struct wm8993_platform_data pdata;
  212. struct snd_soc_codec codec;
  213. int master;
  214. int sysclk_source;
  215. int tdm_slots;
  216. int tdm_width;
  217. unsigned int mclk_rate;
  218. unsigned int sysclk_rate;
  219. unsigned int fs;
  220. unsigned int bclk;
  221. int class_w_users;
  222. unsigned int fll_fref;
  223. unsigned int fll_fout;
  224. int fll_src;
  225. };
  226. static int wm8993_volatile(unsigned int reg)
  227. {
  228. switch (reg) {
  229. case WM8993_SOFTWARE_RESET:
  230. case WM8993_DC_SERVO_0:
  231. case WM8993_DC_SERVO_READBACK_0:
  232. case WM8993_DC_SERVO_READBACK_1:
  233. case WM8993_DC_SERVO_READBACK_2:
  234. return 1;
  235. default:
  236. return 0;
  237. }
  238. }
  239. struct _fll_div {
  240. u16 fll_fratio;
  241. u16 fll_outdiv;
  242. u16 fll_clk_ref_div;
  243. u16 n;
  244. u16 k;
  245. };
  246. /* The size in bits of the FLL divide multiplied by 10
  247. * to allow rounding later */
  248. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  249. static struct {
  250. unsigned int min;
  251. unsigned int max;
  252. u16 fll_fratio;
  253. int ratio;
  254. } fll_fratios[] = {
  255. { 0, 64000, 4, 16 },
  256. { 64000, 128000, 3, 8 },
  257. { 128000, 256000, 2, 4 },
  258. { 256000, 1000000, 1, 2 },
  259. { 1000000, 13500000, 0, 1 },
  260. };
  261. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  262. unsigned int Fout)
  263. {
  264. u64 Kpart;
  265. unsigned int K, Ndiv, Nmod, target;
  266. unsigned int div;
  267. int i;
  268. /* Fref must be <=13.5MHz */
  269. div = 1;
  270. fll_div->fll_clk_ref_div = 0;
  271. while ((Fref / div) > 13500000) {
  272. div *= 2;
  273. fll_div->fll_clk_ref_div++;
  274. if (div > 8) {
  275. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  276. Fref);
  277. return -EINVAL;
  278. }
  279. }
  280. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  281. /* Apply the division for our remaining calculations */
  282. Fref /= div;
  283. /* Fvco should be 90-100MHz; don't check the upper bound */
  284. div = 0;
  285. target = Fout * 2;
  286. while (target < 90000000) {
  287. div++;
  288. target *= 2;
  289. if (div > 7) {
  290. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  291. Fout);
  292. return -EINVAL;
  293. }
  294. }
  295. fll_div->fll_outdiv = div;
  296. pr_debug("Fvco=%dHz\n", target);
  297. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  298. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  299. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  300. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  301. target /= fll_fratios[i].ratio;
  302. break;
  303. }
  304. }
  305. if (i == ARRAY_SIZE(fll_fratios)) {
  306. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  307. return -EINVAL;
  308. }
  309. /* Now, calculate N.K */
  310. Ndiv = target / Fref;
  311. fll_div->n = Ndiv;
  312. Nmod = target % Fref;
  313. pr_debug("Nmod=%d\n", Nmod);
  314. /* Calculate fractional part - scale up so we can round. */
  315. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  316. do_div(Kpart, Fref);
  317. K = Kpart & 0xFFFFFFFF;
  318. if ((K % 10) >= 5)
  319. K += 5;
  320. /* Move down to proper range now rounding is done */
  321. fll_div->k = K / 10;
  322. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  323. fll_div->n, fll_div->k,
  324. fll_div->fll_fratio, fll_div->fll_outdiv,
  325. fll_div->fll_clk_ref_div);
  326. return 0;
  327. }
  328. static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  329. unsigned int Fref, unsigned int Fout)
  330. {
  331. struct snd_soc_codec *codec = dai->codec;
  332. struct wm8993_priv *wm8993 = codec->private_data;
  333. u16 reg1, reg4, reg5;
  334. struct _fll_div fll_div;
  335. int ret;
  336. /* Any change? */
  337. if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
  338. return 0;
  339. /* Disable the FLL */
  340. if (Fout == 0) {
  341. dev_dbg(codec->dev, "FLL disabled\n");
  342. wm8993->fll_fref = 0;
  343. wm8993->fll_fout = 0;
  344. reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
  345. reg1 &= ~WM8993_FLL_ENA;
  346. snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
  347. return 0;
  348. }
  349. ret = fll_factors(&fll_div, Fref, Fout);
  350. if (ret != 0)
  351. return ret;
  352. reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
  353. reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
  354. switch (fll_id) {
  355. case WM8993_FLL_MCLK:
  356. break;
  357. case WM8993_FLL_LRCLK:
  358. reg5 |= 1;
  359. break;
  360. case WM8993_FLL_BCLK:
  361. reg5 |= 2;
  362. break;
  363. default:
  364. dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
  365. return -EINVAL;
  366. }
  367. /* Any FLL configuration change requires that the FLL be
  368. * disabled first. */
  369. reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
  370. reg1 &= ~WM8993_FLL_ENA;
  371. snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
  372. /* Apply the configuration */
  373. if (fll_div.k)
  374. reg1 |= WM8993_FLL_FRAC_MASK;
  375. else
  376. reg1 &= ~WM8993_FLL_FRAC_MASK;
  377. snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
  378. snd_soc_write(codec, WM8993_FLL_CONTROL_2,
  379. (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
  380. (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
  381. snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
  382. reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
  383. reg4 &= ~WM8993_FLL_N_MASK;
  384. reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
  385. snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
  386. reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
  387. reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
  388. snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
  389. /* Enable the FLL */
  390. snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
  391. dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
  392. wm8993->fll_fref = Fref;
  393. wm8993->fll_fout = Fout;
  394. wm8993->fll_src = source;
  395. return 0;
  396. }
  397. static int configure_clock(struct snd_soc_codec *codec)
  398. {
  399. struct wm8993_priv *wm8993 = codec->private_data;
  400. unsigned int reg;
  401. /* This should be done on init() for bypass paths */
  402. switch (wm8993->sysclk_source) {
  403. case WM8993_SYSCLK_MCLK:
  404. dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
  405. reg = snd_soc_read(codec, WM8993_CLOCKING_2);
  406. reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
  407. if (wm8993->mclk_rate > 13500000) {
  408. reg |= WM8993_MCLK_DIV;
  409. wm8993->sysclk_rate = wm8993->mclk_rate / 2;
  410. } else {
  411. reg &= ~WM8993_MCLK_DIV;
  412. wm8993->sysclk_rate = wm8993->mclk_rate;
  413. }
  414. snd_soc_write(codec, WM8993_CLOCKING_2, reg);
  415. break;
  416. case WM8993_SYSCLK_FLL:
  417. dev_dbg(codec->dev, "Using %dHz FLL clock\n",
  418. wm8993->fll_fout);
  419. reg = snd_soc_read(codec, WM8993_CLOCKING_2);
  420. reg |= WM8993_SYSCLK_SRC;
  421. if (wm8993->fll_fout > 13500000) {
  422. reg |= WM8993_MCLK_DIV;
  423. wm8993->sysclk_rate = wm8993->fll_fout / 2;
  424. } else {
  425. reg &= ~WM8993_MCLK_DIV;
  426. wm8993->sysclk_rate = wm8993->fll_fout;
  427. }
  428. snd_soc_write(codec, WM8993_CLOCKING_2, reg);
  429. break;
  430. default:
  431. dev_err(codec->dev, "System clock not configured\n");
  432. return -EINVAL;
  433. }
  434. dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
  435. return 0;
  436. }
  437. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  438. static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
  439. static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
  440. static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
  441. static const unsigned int drc_max_tlv[] = {
  442. TLV_DB_RANGE_HEAD(4),
  443. 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
  444. 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
  445. };
  446. static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
  447. static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
  448. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  449. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  450. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  451. static const char *dac_deemph_text[] = {
  452. "None",
  453. "32kHz",
  454. "44.1kHz",
  455. "48kHz",
  456. };
  457. static const struct soc_enum dac_deemph =
  458. SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
  459. static const char *adc_hpf_text[] = {
  460. "Hi-Fi",
  461. "Voice 1",
  462. "Voice 2",
  463. "Voice 3",
  464. };
  465. static const struct soc_enum adc_hpf =
  466. SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
  467. static const char *drc_path_text[] = {
  468. "ADC",
  469. "DAC"
  470. };
  471. static const struct soc_enum drc_path =
  472. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
  473. static const char *drc_r0_text[] = {
  474. "1",
  475. "1/2",
  476. "1/4",
  477. "1/8",
  478. "1/16",
  479. "0",
  480. };
  481. static const struct soc_enum drc_r0 =
  482. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
  483. static const char *drc_r1_text[] = {
  484. "1",
  485. "1/2",
  486. "1/4",
  487. "1/8",
  488. "0",
  489. };
  490. static const struct soc_enum drc_r1 =
  491. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
  492. static const char *drc_attack_text[] = {
  493. "Reserved",
  494. "181us",
  495. "363us",
  496. "726us",
  497. "1.45ms",
  498. "2.9ms",
  499. "5.8ms",
  500. "11.6ms",
  501. "23.2ms",
  502. "46.4ms",
  503. "92.8ms",
  504. "185.6ms",
  505. };
  506. static const struct soc_enum drc_attack =
  507. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
  508. static const char *drc_decay_text[] = {
  509. "186ms",
  510. "372ms",
  511. "743ms",
  512. "1.49s",
  513. "2.97ms",
  514. "5.94ms",
  515. "11.89ms",
  516. "23.78ms",
  517. "47.56ms",
  518. };
  519. static const struct soc_enum drc_decay =
  520. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
  521. static const char *drc_ff_text[] = {
  522. "5 samples",
  523. "9 samples",
  524. };
  525. static const struct soc_enum drc_ff =
  526. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
  527. static const char *drc_qr_rate_text[] = {
  528. "0.725ms",
  529. "1.45ms",
  530. "5.8ms",
  531. };
  532. static const struct soc_enum drc_qr_rate =
  533. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
  534. static const char *drc_smooth_text[] = {
  535. "Low",
  536. "Medium",
  537. "High",
  538. };
  539. static const struct soc_enum drc_smooth =
  540. SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
  541. static const struct snd_kcontrol_new wm8993_snd_controls[] = {
  542. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
  543. 5, 9, 12, 0, sidetone_tlv),
  544. SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
  545. SOC_ENUM("DRC Path", drc_path),
  546. SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
  547. 2, 60, 1, drc_comp_threash),
  548. SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
  549. 11, 30, 1, drc_comp_amp),
  550. SOC_ENUM("DRC R0", drc_r0),
  551. SOC_ENUM("DRC R1", drc_r1),
  552. SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
  553. drc_min_tlv),
  554. SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
  555. drc_max_tlv),
  556. SOC_ENUM("DRC Attack Rate", drc_attack),
  557. SOC_ENUM("DRC Decay Rate", drc_decay),
  558. SOC_ENUM("DRC FF Delay", drc_ff),
  559. SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
  560. SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
  561. SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
  562. drc_qr_tlv),
  563. SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
  564. SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
  565. SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
  566. SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
  567. SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
  568. drc_startup_tlv),
  569. SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
  570. SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
  571. WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
  572. SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
  573. SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
  574. SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
  575. WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
  576. SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
  577. dac_boost_tlv),
  578. SOC_ENUM("DAC Deemphasis", dac_deemph),
  579. SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
  580. 2, 1, 1, wm_hubs_spkmix_tlv),
  581. SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
  582. 2, 1, 1, wm_hubs_spkmix_tlv),
  583. };
  584. static const struct snd_kcontrol_new wm8993_eq_controls[] = {
  585. SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
  586. SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
  587. SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
  588. SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
  589. SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
  590. };
  591. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  592. struct snd_kcontrol *kcontrol, int event)
  593. {
  594. struct snd_soc_codec *codec = w->codec;
  595. switch (event) {
  596. case SND_SOC_DAPM_PRE_PMU:
  597. return configure_clock(codec);
  598. case SND_SOC_DAPM_POST_PMD:
  599. break;
  600. }
  601. return 0;
  602. }
  603. /*
  604. * When used with DAC outputs only the WM8993 charge pump supports
  605. * operation in class W mode, providing very low power consumption
  606. * when used with digital sources. Enable and disable this mode
  607. * automatically depending on the mixer configuration.
  608. *
  609. * Currently the only supported paths are the direct DAC->headphone
  610. * paths (which provide minimum power consumption anyway).
  611. */
  612. static int class_w_put(struct snd_kcontrol *kcontrol,
  613. struct snd_ctl_elem_value *ucontrol)
  614. {
  615. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  616. struct snd_soc_codec *codec = widget->codec;
  617. struct wm8993_priv *wm8993 = codec->private_data;
  618. int ret;
  619. /* Turn it off if we're using the main output mixer */
  620. if (ucontrol->value.integer.value[0] == 0) {
  621. if (wm8993->class_w_users == 0) {
  622. dev_dbg(codec->dev, "Disabling Class W\n");
  623. snd_soc_update_bits(codec, WM8993_CLASS_W_0,
  624. WM8993_CP_DYN_FREQ |
  625. WM8993_CP_DYN_V,
  626. 0);
  627. }
  628. wm8993->class_w_users++;
  629. }
  630. /* Implement the change */
  631. ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  632. /* Enable it if we're using the direct DAC path */
  633. if (ucontrol->value.integer.value[0] == 1) {
  634. if (wm8993->class_w_users == 1) {
  635. dev_dbg(codec->dev, "Enabling Class W\n");
  636. snd_soc_update_bits(codec, WM8993_CLASS_W_0,
  637. WM8993_CP_DYN_FREQ |
  638. WM8993_CP_DYN_V,
  639. WM8993_CP_DYN_FREQ |
  640. WM8993_CP_DYN_V);
  641. }
  642. wm8993->class_w_users--;
  643. }
  644. dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
  645. wm8993->class_w_users);
  646. return ret;
  647. }
  648. #define SOC_DAPM_ENUM_W(xname, xenum) \
  649. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  650. .info = snd_soc_info_enum_double, \
  651. .get = snd_soc_dapm_get_enum_double, \
  652. .put = class_w_put, \
  653. .private_value = (unsigned long)&xenum }
  654. static const char *hp_mux_text[] = {
  655. "Mixer",
  656. "DAC",
  657. };
  658. static const struct soc_enum hpl_enum =
  659. SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
  660. static const struct snd_kcontrol_new hpl_mux =
  661. SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
  662. static const struct soc_enum hpr_enum =
  663. SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
  664. static const struct snd_kcontrol_new hpr_mux =
  665. SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
  666. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  667. SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
  668. SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
  669. SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
  670. SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
  671. };
  672. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  673. SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
  674. SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
  675. SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
  676. SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
  677. };
  678. static const char *aif_text[] = {
  679. "Left", "Right"
  680. };
  681. static const struct soc_enum aifoutl_enum =
  682. SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
  683. static const struct snd_kcontrol_new aifoutl_mux =
  684. SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
  685. static const struct soc_enum aifoutr_enum =
  686. SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
  687. static const struct snd_kcontrol_new aifoutr_mux =
  688. SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
  689. static const struct soc_enum aifinl_enum =
  690. SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
  691. static const struct snd_kcontrol_new aifinl_mux =
  692. SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
  693. static const struct soc_enum aifinr_enum =
  694. SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
  695. static const struct snd_kcontrol_new aifinr_mux =
  696. SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
  697. static const char *sidetone_text[] = {
  698. "None", "Left", "Right"
  699. };
  700. static const struct soc_enum sidetonel_enum =
  701. SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
  702. static const struct snd_kcontrol_new sidetonel_mux =
  703. SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
  704. static const struct soc_enum sidetoner_enum =
  705. SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
  706. static const struct snd_kcontrol_new sidetoner_mux =
  707. SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
  708. static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
  709. SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
  710. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  711. SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
  712. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
  713. SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
  714. SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
  715. SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
  716. SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
  717. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  718. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  719. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  720. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  721. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
  722. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
  723. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
  724. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
  725. SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
  726. SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
  727. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  728. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  729. SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
  730. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  731. SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
  732. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  733. };
  734. static const struct snd_soc_dapm_route routes[] = {
  735. { "ADCL", NULL, "CLK_SYS" },
  736. { "ADCL", NULL, "CLK_DSP" },
  737. { "ADCR", NULL, "CLK_SYS" },
  738. { "ADCR", NULL, "CLK_DSP" },
  739. { "AIFOUTL Mux", "Left", "ADCL" },
  740. { "AIFOUTL Mux", "Right", "ADCR" },
  741. { "AIFOUTR Mux", "Left", "ADCL" },
  742. { "AIFOUTR Mux", "Right", "ADCR" },
  743. { "AIFOUTL", NULL, "AIFOUTL Mux" },
  744. { "AIFOUTR", NULL, "AIFOUTR Mux" },
  745. { "DACL Mux", "Left", "AIFINL" },
  746. { "DACL Mux", "Right", "AIFINR" },
  747. { "DACR Mux", "Left", "AIFINL" },
  748. { "DACR Mux", "Right", "AIFINR" },
  749. { "DACL Sidetone", "Left", "ADCL" },
  750. { "DACL Sidetone", "Right", "ADCR" },
  751. { "DACR Sidetone", "Left", "ADCL" },
  752. { "DACR Sidetone", "Right", "ADCR" },
  753. { "DACL", NULL, "CLK_SYS" },
  754. { "DACL", NULL, "CLK_DSP" },
  755. { "DACL", NULL, "DACL Mux" },
  756. { "DACL", NULL, "DACL Sidetone" },
  757. { "DACR", NULL, "CLK_SYS" },
  758. { "DACR", NULL, "CLK_DSP" },
  759. { "DACR", NULL, "DACR Mux" },
  760. { "DACR", NULL, "DACR Sidetone" },
  761. { "Left Output Mixer", "DAC Switch", "DACL" },
  762. { "Right Output Mixer", "DAC Switch", "DACR" },
  763. { "Left Output PGA", NULL, "CLK_SYS" },
  764. { "Right Output PGA", NULL, "CLK_SYS" },
  765. { "SPKL", "DAC Switch", "DACL" },
  766. { "SPKL", NULL, "CLK_SYS" },
  767. { "SPKR", "DAC Switch", "DACR" },
  768. { "SPKR", NULL, "CLK_SYS" },
  769. { "Left Headphone Mux", "DAC", "DACL" },
  770. { "Right Headphone Mux", "DAC", "DACR" },
  771. };
  772. static int wm8993_set_bias_level(struct snd_soc_codec *codec,
  773. enum snd_soc_bias_level level)
  774. {
  775. struct wm8993_priv *wm8993 = codec->private_data;
  776. switch (level) {
  777. case SND_SOC_BIAS_ON:
  778. case SND_SOC_BIAS_PREPARE:
  779. /* VMID=2*40k */
  780. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
  781. WM8993_VMID_SEL_MASK, 0x2);
  782. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
  783. WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
  784. break;
  785. case SND_SOC_BIAS_STANDBY:
  786. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  787. /* Tune DC servo configuration */
  788. snd_soc_write(codec, 0x44, 3);
  789. snd_soc_write(codec, 0x56, 3);
  790. snd_soc_write(codec, 0x44, 0);
  791. /* Bring up VMID with fast soft start */
  792. snd_soc_update_bits(codec, WM8993_ANTIPOP2,
  793. WM8993_STARTUP_BIAS_ENA |
  794. WM8993_VMID_BUF_ENA |
  795. WM8993_VMID_RAMP_MASK |
  796. WM8993_BIAS_SRC,
  797. WM8993_STARTUP_BIAS_ENA |
  798. WM8993_VMID_BUF_ENA |
  799. WM8993_VMID_RAMP_MASK |
  800. WM8993_BIAS_SRC);
  801. /* If either line output is single ended we
  802. * need the VMID buffer */
  803. if (!wm8993->pdata.lineout1_diff ||
  804. !wm8993->pdata.lineout2_diff)
  805. snd_soc_update_bits(codec, WM8993_ANTIPOP1,
  806. WM8993_LINEOUT_VMID_BUF_ENA,
  807. WM8993_LINEOUT_VMID_BUF_ENA);
  808. /* VMID=2*40k */
  809. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
  810. WM8993_VMID_SEL_MASK |
  811. WM8993_BIAS_ENA,
  812. WM8993_BIAS_ENA | 0x2);
  813. msleep(32);
  814. /* Switch to normal bias */
  815. snd_soc_update_bits(codec, WM8993_ANTIPOP2,
  816. WM8993_BIAS_SRC |
  817. WM8993_STARTUP_BIAS_ENA, 0);
  818. }
  819. /* VMID=2*240k */
  820. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
  821. WM8993_VMID_SEL_MASK, 0x4);
  822. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
  823. WM8993_TSHUT_ENA, 0);
  824. break;
  825. case SND_SOC_BIAS_OFF:
  826. snd_soc_update_bits(codec, WM8993_ANTIPOP1,
  827. WM8993_LINEOUT_VMID_BUF_ENA, 0);
  828. snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
  829. WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
  830. 0);
  831. break;
  832. }
  833. codec->bias_level = level;
  834. return 0;
  835. }
  836. static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
  837. int clk_id, unsigned int freq, int dir)
  838. {
  839. struct snd_soc_codec *codec = codec_dai->codec;
  840. struct wm8993_priv *wm8993 = codec->private_data;
  841. switch (clk_id) {
  842. case WM8993_SYSCLK_MCLK:
  843. wm8993->mclk_rate = freq;
  844. case WM8993_SYSCLK_FLL:
  845. wm8993->sysclk_source = clk_id;
  846. break;
  847. default:
  848. return -EINVAL;
  849. }
  850. return 0;
  851. }
  852. static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
  853. unsigned int fmt)
  854. {
  855. struct snd_soc_codec *codec = dai->codec;
  856. struct wm8993_priv *wm8993 = codec->private_data;
  857. unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
  858. unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
  859. aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
  860. WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
  861. aif4 &= ~WM8993_LRCLK_DIR;
  862. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  863. case SND_SOC_DAIFMT_CBS_CFS:
  864. wm8993->master = 0;
  865. break;
  866. case SND_SOC_DAIFMT_CBS_CFM:
  867. aif4 |= WM8993_LRCLK_DIR;
  868. wm8993->master = 1;
  869. break;
  870. case SND_SOC_DAIFMT_CBM_CFS:
  871. aif1 |= WM8993_BCLK_DIR;
  872. wm8993->master = 1;
  873. break;
  874. case SND_SOC_DAIFMT_CBM_CFM:
  875. aif1 |= WM8993_BCLK_DIR;
  876. aif4 |= WM8993_LRCLK_DIR;
  877. wm8993->master = 1;
  878. break;
  879. default:
  880. return -EINVAL;
  881. }
  882. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  883. case SND_SOC_DAIFMT_DSP_B:
  884. aif1 |= WM8993_AIF_LRCLK_INV;
  885. case SND_SOC_DAIFMT_DSP_A:
  886. aif1 |= 0x18;
  887. break;
  888. case SND_SOC_DAIFMT_I2S:
  889. aif1 |= 0x10;
  890. break;
  891. case SND_SOC_DAIFMT_RIGHT_J:
  892. break;
  893. case SND_SOC_DAIFMT_LEFT_J:
  894. aif1 |= 0x8;
  895. break;
  896. default:
  897. return -EINVAL;
  898. }
  899. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  900. case SND_SOC_DAIFMT_DSP_A:
  901. case SND_SOC_DAIFMT_DSP_B:
  902. /* frame inversion not valid for DSP modes */
  903. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  904. case SND_SOC_DAIFMT_NB_NF:
  905. break;
  906. case SND_SOC_DAIFMT_IB_NF:
  907. aif1 |= WM8993_AIF_BCLK_INV;
  908. break;
  909. default:
  910. return -EINVAL;
  911. }
  912. break;
  913. case SND_SOC_DAIFMT_I2S:
  914. case SND_SOC_DAIFMT_RIGHT_J:
  915. case SND_SOC_DAIFMT_LEFT_J:
  916. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  917. case SND_SOC_DAIFMT_NB_NF:
  918. break;
  919. case SND_SOC_DAIFMT_IB_IF:
  920. aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
  921. break;
  922. case SND_SOC_DAIFMT_IB_NF:
  923. aif1 |= WM8993_AIF_BCLK_INV;
  924. break;
  925. case SND_SOC_DAIFMT_NB_IF:
  926. aif1 |= WM8993_AIF_LRCLK_INV;
  927. break;
  928. default:
  929. return -EINVAL;
  930. }
  931. break;
  932. default:
  933. return -EINVAL;
  934. }
  935. snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
  936. snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
  937. return 0;
  938. }
  939. static int wm8993_hw_params(struct snd_pcm_substream *substream,
  940. struct snd_pcm_hw_params *params,
  941. struct snd_soc_dai *dai)
  942. {
  943. struct snd_soc_codec *codec = dai->codec;
  944. struct wm8993_priv *wm8993 = codec->private_data;
  945. int ret, i, best, best_val, cur_val;
  946. unsigned int clocking1, clocking3, aif1, aif4;
  947. clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
  948. clocking1 &= ~WM8993_BCLK_DIV_MASK;
  949. clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
  950. clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
  951. aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
  952. aif1 &= ~WM8993_AIF_WL_MASK;
  953. aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
  954. aif4 &= ~WM8993_LRCLK_RATE_MASK;
  955. /* What BCLK do we need? */
  956. wm8993->fs = params_rate(params);
  957. wm8993->bclk = 2 * wm8993->fs;
  958. if (wm8993->tdm_slots) {
  959. dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
  960. wm8993->tdm_slots, wm8993->tdm_width);
  961. wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
  962. } else {
  963. switch (params_format(params)) {
  964. case SNDRV_PCM_FORMAT_S16_LE:
  965. wm8993->bclk *= 16;
  966. break;
  967. case SNDRV_PCM_FORMAT_S20_3LE:
  968. wm8993->bclk *= 20;
  969. aif1 |= 0x8;
  970. break;
  971. case SNDRV_PCM_FORMAT_S24_LE:
  972. wm8993->bclk *= 24;
  973. aif1 |= 0x10;
  974. break;
  975. case SNDRV_PCM_FORMAT_S32_LE:
  976. wm8993->bclk *= 32;
  977. aif1 |= 0x18;
  978. break;
  979. default:
  980. return -EINVAL;
  981. }
  982. }
  983. dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
  984. ret = configure_clock(codec);
  985. if (ret != 0)
  986. return ret;
  987. /* Select nearest CLK_SYS_RATE */
  988. best = 0;
  989. best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
  990. - wm8993->fs);
  991. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  992. cur_val = abs((wm8993->sysclk_rate /
  993. clk_sys_rates[i].ratio) - wm8993->fs);;
  994. if (cur_val < best_val) {
  995. best = i;
  996. best_val = cur_val;
  997. }
  998. }
  999. dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
  1000. clk_sys_rates[best].ratio);
  1001. clocking3 |= (clk_sys_rates[best].clk_sys_rate
  1002. << WM8993_CLK_SYS_RATE_SHIFT);
  1003. /* SAMPLE_RATE */
  1004. best = 0;
  1005. best_val = abs(wm8993->fs - sample_rates[0].rate);
  1006. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1007. /* Closest match */
  1008. cur_val = abs(wm8993->fs - sample_rates[i].rate);
  1009. if (cur_val < best_val) {
  1010. best = i;
  1011. best_val = cur_val;
  1012. }
  1013. }
  1014. dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
  1015. sample_rates[best].rate);
  1016. clocking3 |= (sample_rates[best].sample_rate
  1017. << WM8993_SAMPLE_RATE_SHIFT);
  1018. /* BCLK_DIV */
  1019. best = 0;
  1020. best_val = INT_MAX;
  1021. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1022. cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
  1023. - wm8993->bclk;
  1024. if (cur_val < 0) /* Table is sorted */
  1025. break;
  1026. if (cur_val < best_val) {
  1027. best = i;
  1028. best_val = cur_val;
  1029. }
  1030. }
  1031. wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
  1032. dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  1033. bclk_divs[best].div, wm8993->bclk);
  1034. clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
  1035. /* LRCLK is a simple fraction of BCLK */
  1036. dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
  1037. aif4 |= wm8993->bclk / wm8993->fs;
  1038. snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
  1039. snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
  1040. snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
  1041. snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
  1042. /* ReTune Mobile? */
  1043. if (wm8993->pdata.num_retune_configs) {
  1044. u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
  1045. struct wm8993_retune_mobile_setting *s;
  1046. best = 0;
  1047. best_val = abs(wm8993->pdata.retune_configs[0].rate
  1048. - wm8993->fs);
  1049. for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
  1050. cur_val = abs(wm8993->pdata.retune_configs[i].rate
  1051. - wm8993->fs);
  1052. if (cur_val < best_val) {
  1053. best_val = cur_val;
  1054. best = i;
  1055. }
  1056. }
  1057. s = &wm8993->pdata.retune_configs[best];
  1058. dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
  1059. s->name, s->rate);
  1060. /* Disable EQ while we reconfigure */
  1061. snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
  1062. for (i = 1; i < ARRAY_SIZE(s->config); i++)
  1063. snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
  1064. snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
  1065. }
  1066. return 0;
  1067. }
  1068. static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  1069. {
  1070. struct snd_soc_codec *codec = codec_dai->codec;
  1071. unsigned int reg;
  1072. reg = snd_soc_read(codec, WM8993_DAC_CTRL);
  1073. if (mute)
  1074. reg |= WM8993_DAC_MUTE;
  1075. else
  1076. reg &= ~WM8993_DAC_MUTE;
  1077. snd_soc_write(codec, WM8993_DAC_CTRL, reg);
  1078. return 0;
  1079. }
  1080. static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1081. unsigned int rx_mask, int slots, int slot_width)
  1082. {
  1083. struct snd_soc_codec *codec = dai->codec;
  1084. struct wm8993_priv *wm8993 = codec->private_data;
  1085. int aif1 = 0;
  1086. int aif2 = 0;
  1087. /* Don't need to validate anything if we're turning off TDM */
  1088. if (slots == 0) {
  1089. wm8993->tdm_slots = 0;
  1090. goto out;
  1091. }
  1092. /* Note that we allow configurations we can't handle ourselves -
  1093. * for example, we can generate clocks for slots 2 and up even if
  1094. * we can't use those slots ourselves.
  1095. */
  1096. aif1 |= WM8993_AIFADC_TDM;
  1097. aif2 |= WM8993_AIFDAC_TDM;
  1098. switch (rx_mask) {
  1099. case 3:
  1100. break;
  1101. case 0xc:
  1102. aif1 |= WM8993_AIFADC_TDM_CHAN;
  1103. break;
  1104. default:
  1105. return -EINVAL;
  1106. }
  1107. switch (tx_mask) {
  1108. case 3:
  1109. break;
  1110. case 0xc:
  1111. aif2 |= WM8993_AIFDAC_TDM_CHAN;
  1112. break;
  1113. default:
  1114. return -EINVAL;
  1115. }
  1116. out:
  1117. wm8993->tdm_width = slot_width;
  1118. wm8993->tdm_slots = slots / 2;
  1119. snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
  1120. WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
  1121. snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
  1122. WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
  1123. return 0;
  1124. }
  1125. static struct snd_soc_dai_ops wm8993_ops = {
  1126. .set_sysclk = wm8993_set_sysclk,
  1127. .set_fmt = wm8993_set_dai_fmt,
  1128. .hw_params = wm8993_hw_params,
  1129. .digital_mute = wm8993_digital_mute,
  1130. .set_pll = wm8993_set_fll,
  1131. .set_tdm_slot = wm8993_set_tdm_slot,
  1132. };
  1133. #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
  1134. #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1135. SNDRV_PCM_FMTBIT_S20_3LE |\
  1136. SNDRV_PCM_FMTBIT_S24_LE |\
  1137. SNDRV_PCM_FMTBIT_S32_LE)
  1138. struct snd_soc_dai wm8993_dai = {
  1139. .name = "WM8993",
  1140. .playback = {
  1141. .stream_name = "Playback",
  1142. .channels_min = 1,
  1143. .channels_max = 2,
  1144. .rates = WM8993_RATES,
  1145. .formats = WM8993_FORMATS,
  1146. },
  1147. .capture = {
  1148. .stream_name = "Capture",
  1149. .channels_min = 1,
  1150. .channels_max = 2,
  1151. .rates = WM8993_RATES,
  1152. .formats = WM8993_FORMATS,
  1153. },
  1154. .ops = &wm8993_ops,
  1155. .symmetric_rates = 1,
  1156. };
  1157. EXPORT_SYMBOL_GPL(wm8993_dai);
  1158. static struct snd_soc_codec *wm8993_codec;
  1159. static int wm8993_probe(struct platform_device *pdev)
  1160. {
  1161. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1162. struct snd_soc_codec *codec;
  1163. struct wm8993_priv *wm8993;
  1164. int ret = 0;
  1165. if (!wm8993_codec) {
  1166. dev_err(&pdev->dev, "I2C device not yet probed\n");
  1167. goto err;
  1168. }
  1169. socdev->card->codec = wm8993_codec;
  1170. codec = wm8993_codec;
  1171. wm8993 = codec->private_data;
  1172. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1173. if (ret < 0) {
  1174. dev_err(codec->dev, "failed to create pcms\n");
  1175. goto err;
  1176. }
  1177. snd_soc_add_controls(codec, wm8993_snd_controls,
  1178. ARRAY_SIZE(wm8993_snd_controls));
  1179. if (wm8993->pdata.num_retune_configs != 0) {
  1180. dev_dbg(codec->dev, "Using ReTune Mobile\n");
  1181. } else {
  1182. dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
  1183. snd_soc_add_controls(codec, wm8993_eq_controls,
  1184. ARRAY_SIZE(wm8993_eq_controls));
  1185. }
  1186. snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
  1187. ARRAY_SIZE(wm8993_dapm_widgets));
  1188. wm_hubs_add_analogue_controls(codec);
  1189. snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
  1190. wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
  1191. wm8993->pdata.lineout2_diff);
  1192. return ret;
  1193. err:
  1194. return ret;
  1195. }
  1196. static int wm8993_remove(struct platform_device *pdev)
  1197. {
  1198. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1199. snd_soc_free_pcms(socdev);
  1200. snd_soc_dapm_free(socdev);
  1201. return 0;
  1202. }
  1203. #ifdef CONFIG_PM
  1204. static int wm8993_suspend(struct platform_device *pdev, pm_message_t state)
  1205. {
  1206. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1207. struct snd_soc_codec *codec = socdev->card->codec;
  1208. struct wm8993_priv *wm8993 = codec->private_data;
  1209. int fll_fout = wm8993->fll_fout;
  1210. int fll_fref = wm8993->fll_fref;
  1211. int ret;
  1212. /* Stop the FLL in an orderly fashion */
  1213. ret = wm8993_set_fll(codec->dai, 0, 0, 0, 0);
  1214. if (ret != 0) {
  1215. dev_err(&pdev->dev, "Failed to stop FLL\n");
  1216. return ret;
  1217. }
  1218. wm8993->fll_fout = fll_fout;
  1219. wm8993->fll_fref = fll_fref;
  1220. wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1221. return 0;
  1222. }
  1223. static int wm8993_resume(struct platform_device *pdev)
  1224. {
  1225. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1226. struct snd_soc_codec *codec = socdev->card->codec;
  1227. struct wm8993_priv *wm8993 = codec->private_data;
  1228. u16 *cache = wm8993->reg_cache;
  1229. int i, ret;
  1230. /* Restore the register settings */
  1231. for (i = 1; i < WM8993_MAX_REGISTER; i++) {
  1232. if (cache[i] == wm8993_reg_defaults[i])
  1233. continue;
  1234. snd_soc_write(codec, i, cache[i]);
  1235. }
  1236. wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1237. /* Restart the FLL? */
  1238. if (wm8993->fll_fout) {
  1239. int fll_fout = wm8993->fll_fout;
  1240. int fll_fref = wm8993->fll_fref;
  1241. wm8993->fll_fref = 0;
  1242. wm8993->fll_fout = 0;
  1243. ret = wm8993_set_fll(codec->dai, 0, wm8993->fll_src,
  1244. fll_fref, fll_fout);
  1245. if (ret != 0)
  1246. dev_err(codec->dev, "Failed to restart FLL\n");
  1247. }
  1248. return 0;
  1249. }
  1250. #else
  1251. #define wm8993_suspend NULL
  1252. #define wm8993_resume NULL
  1253. #endif
  1254. struct snd_soc_codec_device soc_codec_dev_wm8993 = {
  1255. .probe = wm8993_probe,
  1256. .remove = wm8993_remove,
  1257. .suspend = wm8993_suspend,
  1258. .resume = wm8993_resume,
  1259. };
  1260. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
  1261. static int wm8993_i2c_probe(struct i2c_client *i2c,
  1262. const struct i2c_device_id *id)
  1263. {
  1264. struct wm8993_priv *wm8993;
  1265. struct snd_soc_codec *codec;
  1266. unsigned int val;
  1267. int ret;
  1268. if (wm8993_codec) {
  1269. dev_err(&i2c->dev, "A WM8993 is already registered\n");
  1270. return -EINVAL;
  1271. }
  1272. wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
  1273. if (wm8993 == NULL)
  1274. return -ENOMEM;
  1275. codec = &wm8993->codec;
  1276. if (i2c->dev.platform_data)
  1277. memcpy(&wm8993->pdata, i2c->dev.platform_data,
  1278. sizeof(wm8993->pdata));
  1279. mutex_init(&codec->mutex);
  1280. INIT_LIST_HEAD(&codec->dapm_widgets);
  1281. INIT_LIST_HEAD(&codec->dapm_paths);
  1282. codec->name = "WM8993";
  1283. codec->volatile_register = wm8993_volatile;
  1284. codec->reg_cache = wm8993->reg_cache;
  1285. codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
  1286. codec->bias_level = SND_SOC_BIAS_OFF;
  1287. codec->set_bias_level = wm8993_set_bias_level;
  1288. codec->dai = &wm8993_dai;
  1289. codec->num_dai = 1;
  1290. codec->private_data = wm8993;
  1291. wm8993->hubs_data.hp_startup_mode = 1;
  1292. wm8993->hubs_data.dcs_codes = -2;
  1293. memcpy(wm8993->reg_cache, wm8993_reg_defaults,
  1294. sizeof(wm8993->reg_cache));
  1295. ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
  1296. if (ret != 0) {
  1297. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1298. goto err;
  1299. }
  1300. i2c_set_clientdata(i2c, wm8993);
  1301. codec->control_data = i2c;
  1302. wm8993_codec = codec;
  1303. codec->dev = &i2c->dev;
  1304. val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
  1305. if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
  1306. dev_err(codec->dev, "Invalid ID register value %x\n", val);
  1307. ret = -EINVAL;
  1308. goto err;
  1309. }
  1310. ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
  1311. if (ret != 0)
  1312. goto err;
  1313. /* By default we're using the output mixers */
  1314. wm8993->class_w_users = 2;
  1315. /* Latch volume update bits and default ZC on */
  1316. snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
  1317. WM8993_DAC_VU, WM8993_DAC_VU);
  1318. snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
  1319. WM8993_ADC_VU, WM8993_ADC_VU);
  1320. /* Manualy manage the HPOUT sequencing for independent stereo
  1321. * control. */
  1322. snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
  1323. WM8993_HPOUT1_AUTO_PU, 0);
  1324. /* Use automatic clock configuration */
  1325. snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
  1326. wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
  1327. wm8993->pdata.lineout2_diff,
  1328. wm8993->pdata.lineout1fb,
  1329. wm8993->pdata.lineout2fb,
  1330. wm8993->pdata.jd_scthr,
  1331. wm8993->pdata.jd_thr,
  1332. wm8993->pdata.micbias1_lvl,
  1333. wm8993->pdata.micbias2_lvl);
  1334. ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1335. if (ret != 0)
  1336. goto err;
  1337. wm8993_dai.dev = codec->dev;
  1338. ret = snd_soc_register_dai(&wm8993_dai);
  1339. if (ret != 0)
  1340. goto err_bias;
  1341. ret = snd_soc_register_codec(codec);
  1342. return 0;
  1343. err_bias:
  1344. wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1345. err:
  1346. wm8993_codec = NULL;
  1347. kfree(wm8993);
  1348. return ret;
  1349. }
  1350. static int wm8993_i2c_remove(struct i2c_client *client)
  1351. {
  1352. struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
  1353. snd_soc_unregister_codec(&wm8993->codec);
  1354. snd_soc_unregister_dai(&wm8993_dai);
  1355. wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
  1356. kfree(wm8993);
  1357. return 0;
  1358. }
  1359. static const struct i2c_device_id wm8993_i2c_id[] = {
  1360. { "wm8993", 0 },
  1361. { }
  1362. };
  1363. MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
  1364. static struct i2c_driver wm8993_i2c_driver = {
  1365. .driver = {
  1366. .name = "WM8993",
  1367. .owner = THIS_MODULE,
  1368. },
  1369. .probe = wm8993_i2c_probe,
  1370. .remove = wm8993_i2c_remove,
  1371. .id_table = wm8993_i2c_id,
  1372. };
  1373. static int __init wm8993_modinit(void)
  1374. {
  1375. int ret;
  1376. ret = i2c_add_driver(&wm8993_i2c_driver);
  1377. if (ret != 0)
  1378. pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
  1379. return ret;
  1380. }
  1381. module_init(wm8993_modinit);
  1382. static void __exit wm8993_exit(void)
  1383. {
  1384. i2c_del_driver(&wm8993_i2c_driver);
  1385. }
  1386. module_exit(wm8993_exit);
  1387. MODULE_DESCRIPTION("ASoC WM8993 driver");
  1388. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1389. MODULE_LICENSE("GPL");