board-fsample.c 8.3 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/board-fsample.c
  3. *
  4. * Modified from board-perseus2.c
  5. *
  6. * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
  7. * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/delay.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/nand.h>
  19. #include <linux/mtd/partitions.h>
  20. #include <linux/input.h>
  21. #include <linux/smc91x.h>
  22. #include <mach/hardware.h>
  23. #include <asm/mach-types.h>
  24. #include <asm/mach/arch.h>
  25. #include <asm/mach/flash.h>
  26. #include <asm/mach/map.h>
  27. #include <plat/tc.h>
  28. #include <mach/gpio.h>
  29. #include <plat/mux.h>
  30. #include <plat/fpga.h>
  31. #include <plat/nand.h>
  32. #include <plat/keypad.h>
  33. #include <plat/common.h>
  34. #include <plat/board.h>
  35. /* fsample is pretty close to p2-sample */
  36. #define fsample_cpld_read(reg) __raw_readb(reg)
  37. #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
  38. #define FSAMPLE_CPLD_BASE 0xE8100000
  39. #define FSAMPLE_CPLD_SIZE SZ_4K
  40. #define FSAMPLE_CPLD_START 0x05080000
  41. #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
  42. #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
  43. #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
  44. #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
  45. #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
  46. #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
  47. #define FSAMPLE_CPLD_BIT_BT_RESET 0
  48. #define FSAMPLE_CPLD_BIT_LCD_RESET 1
  49. #define FSAMPLE_CPLD_BIT_CAM_PWDN 2
  50. #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
  51. #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
  52. #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
  53. #define FSAMPLE_CPLD_BIT_BACKLIGHT 6
  54. #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
  55. #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
  56. #define FSAMPLE_CPLD_BIT_OTG_RESET 9
  57. #define fsample_cpld_set(bit) \
  58. fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
  59. #define fsample_cpld_clear(bit) \
  60. fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
  61. static int fsample_keymap[] = {
  62. KEY(0,0,KEY_UP),
  63. KEY(0,1,KEY_RIGHT),
  64. KEY(0,2,KEY_LEFT),
  65. KEY(0,3,KEY_DOWN),
  66. KEY(0,4,KEY_ENTER),
  67. KEY(1,0,KEY_F10),
  68. KEY(1,1,KEY_SEND),
  69. KEY(1,2,KEY_END),
  70. KEY(1,3,KEY_VOLUMEDOWN),
  71. KEY(1,4,KEY_VOLUMEUP),
  72. KEY(1,5,KEY_RECORD),
  73. KEY(2,0,KEY_F9),
  74. KEY(2,1,KEY_3),
  75. KEY(2,2,KEY_6),
  76. KEY(2,3,KEY_9),
  77. KEY(2,4,KEY_KPDOT),
  78. KEY(3,0,KEY_BACK),
  79. KEY(3,1,KEY_2),
  80. KEY(3,2,KEY_5),
  81. KEY(3,3,KEY_8),
  82. KEY(3,4,KEY_0),
  83. KEY(3,5,KEY_KPSLASH),
  84. KEY(4,0,KEY_HOME),
  85. KEY(4,1,KEY_1),
  86. KEY(4,2,KEY_4),
  87. KEY(4,3,KEY_7),
  88. KEY(4,4,KEY_KPASTERISK),
  89. KEY(4,5,KEY_POWER),
  90. 0
  91. };
  92. static struct smc91x_platdata smc91x_info = {
  93. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  94. .leda = RPC_LED_100_10,
  95. .ledb = RPC_LED_TX_RX,
  96. };
  97. static struct resource smc91x_resources[] = {
  98. [0] = {
  99. .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
  100. .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
  101. .flags = IORESOURCE_MEM,
  102. },
  103. [1] = {
  104. .start = INT_7XX_MPU_EXT_NIRQ,
  105. .end = 0,
  106. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  107. },
  108. };
  109. static struct mtd_partition nor_partitions[] = {
  110. /* bootloader (U-Boot, etc) in first sector */
  111. {
  112. .name = "bootloader",
  113. .offset = 0,
  114. .size = SZ_128K,
  115. .mask_flags = MTD_WRITEABLE, /* force read-only */
  116. },
  117. /* bootloader params in the next sector */
  118. {
  119. .name = "params",
  120. .offset = MTDPART_OFS_APPEND,
  121. .size = SZ_128K,
  122. .mask_flags = 0,
  123. },
  124. /* kernel */
  125. {
  126. .name = "kernel",
  127. .offset = MTDPART_OFS_APPEND,
  128. .size = SZ_2M,
  129. .mask_flags = 0
  130. },
  131. /* rest of flash is a file system */
  132. {
  133. .name = "rootfs",
  134. .offset = MTDPART_OFS_APPEND,
  135. .size = MTDPART_SIZ_FULL,
  136. .mask_flags = 0
  137. },
  138. };
  139. static struct flash_platform_data nor_data = {
  140. .map_name = "cfi_probe",
  141. .width = 2,
  142. .parts = nor_partitions,
  143. .nr_parts = ARRAY_SIZE(nor_partitions),
  144. };
  145. static struct resource nor_resource = {
  146. .start = OMAP_CS0_PHYS,
  147. .end = OMAP_CS0_PHYS + SZ_32M - 1,
  148. .flags = IORESOURCE_MEM,
  149. };
  150. static struct platform_device nor_device = {
  151. .name = "omapflash",
  152. .id = 0,
  153. .dev = {
  154. .platform_data = &nor_data,
  155. },
  156. .num_resources = 1,
  157. .resource = &nor_resource,
  158. };
  159. static struct omap_nand_platform_data nand_data = {
  160. .options = NAND_SAMSUNG_LP_OPTIONS,
  161. };
  162. static struct resource nand_resource = {
  163. .start = OMAP_CS3_PHYS,
  164. .end = OMAP_CS3_PHYS + SZ_4K - 1,
  165. .flags = IORESOURCE_MEM,
  166. };
  167. static struct platform_device nand_device = {
  168. .name = "omapnand",
  169. .id = 0,
  170. .dev = {
  171. .platform_data = &nand_data,
  172. },
  173. .num_resources = 1,
  174. .resource = &nand_resource,
  175. };
  176. static struct platform_device smc91x_device = {
  177. .name = "smc91x",
  178. .id = 0,
  179. .dev = {
  180. .platform_data = &smc91x_info,
  181. },
  182. .num_resources = ARRAY_SIZE(smc91x_resources),
  183. .resource = smc91x_resources,
  184. };
  185. static struct resource kp_resources[] = {
  186. [0] = {
  187. .start = INT_7XX_MPUIO_KEYPAD,
  188. .end = INT_7XX_MPUIO_KEYPAD,
  189. .flags = IORESOURCE_IRQ,
  190. },
  191. };
  192. static struct omap_kp_platform_data kp_data = {
  193. .rows = 8,
  194. .cols = 8,
  195. .keymap = fsample_keymap,
  196. .keymapsize = ARRAY_SIZE(fsample_keymap),
  197. .delay = 4,
  198. };
  199. static struct platform_device kp_device = {
  200. .name = "omap-keypad",
  201. .id = -1,
  202. .dev = {
  203. .platform_data = &kp_data,
  204. },
  205. .num_resources = ARRAY_SIZE(kp_resources),
  206. .resource = kp_resources,
  207. };
  208. static struct platform_device lcd_device = {
  209. .name = "lcd_p2",
  210. .id = -1,
  211. };
  212. static struct platform_device *devices[] __initdata = {
  213. &nor_device,
  214. &nand_device,
  215. &smc91x_device,
  216. &kp_device,
  217. &lcd_device,
  218. };
  219. #define P2_NAND_RB_GPIO_PIN 62
  220. static int nand_dev_ready(struct omap_nand_platform_data *data)
  221. {
  222. return gpio_get_value(P2_NAND_RB_GPIO_PIN);
  223. }
  224. static struct omap_lcd_config fsample_lcd_config __initdata = {
  225. .ctrl_name = "internal",
  226. };
  227. static struct omap_board_config_kernel fsample_config[] = {
  228. { OMAP_TAG_LCD, &fsample_lcd_config },
  229. };
  230. static void __init omap_fsample_init(void)
  231. {
  232. if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
  233. BUG();
  234. nand_data.dev_ready = nand_dev_ready;
  235. omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
  236. omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
  237. platform_add_devices(devices, ARRAY_SIZE(devices));
  238. omap_board_config = fsample_config;
  239. omap_board_config_size = ARRAY_SIZE(fsample_config);
  240. omap_serial_init();
  241. omap_register_i2c_bus(1, 100, NULL, 0);
  242. }
  243. static void __init fsample_init_smc91x(void)
  244. {
  245. fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
  246. mdelay(50);
  247. fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
  248. H2P2_DBG_FPGA_LAN_RESET);
  249. mdelay(50);
  250. }
  251. static void __init omap_fsample_init_irq(void)
  252. {
  253. omap1_init_common_hw();
  254. omap_init_irq();
  255. omap_gpio_init();
  256. fsample_init_smc91x();
  257. }
  258. /* Only FPGA needs to be mapped here. All others are done with ioremap */
  259. static struct map_desc omap_fsample_io_desc[] __initdata = {
  260. {
  261. .virtual = H2P2_DBG_FPGA_BASE,
  262. .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
  263. .length = H2P2_DBG_FPGA_SIZE,
  264. .type = MT_DEVICE
  265. },
  266. {
  267. .virtual = FSAMPLE_CPLD_BASE,
  268. .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
  269. .length = FSAMPLE_CPLD_SIZE,
  270. .type = MT_DEVICE
  271. }
  272. };
  273. static void __init omap_fsample_map_io(void)
  274. {
  275. omap1_map_common_io();
  276. iotable_init(omap_fsample_io_desc,
  277. ARRAY_SIZE(omap_fsample_io_desc));
  278. /* Early, board-dependent init */
  279. /*
  280. * Hold GSM Reset until needed
  281. */
  282. omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
  283. /*
  284. * UARTs -> done automagically by 8250 driver
  285. */
  286. /*
  287. * CSx timings, GPIO Mux ... setup
  288. */
  289. /* Flash: CS0 timings setup */
  290. omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
  291. omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
  292. /*
  293. * Ethernet support through the debug board
  294. * CS1 timings setup
  295. */
  296. omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
  297. omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
  298. /*
  299. * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
  300. * It is used as the Ethernet controller interrupt
  301. */
  302. omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
  303. }
  304. MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
  305. /* Maintainer: Brian Swetland <swetland@google.com> */
  306. .phys_io = 0xfff00000,
  307. .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
  308. .boot_params = 0x10000100,
  309. .map_io = omap_fsample_map_io,
  310. .init_irq = omap_fsample_init_irq,
  311. .init_machine = omap_fsample_init,
  312. .timer = &omap_timer,
  313. MACHINE_END