main.c 53 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. u32 txpow;
  52. if (sc->curtxpow != sc->config.txpowlimit) {
  53. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  54. /* read back in case value is clamped */
  55. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  56. sc->curtxpow = txpow;
  57. }
  58. }
  59. static u8 parse_mpdudensity(u8 mpdudensity)
  60. {
  61. /*
  62. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  63. * 0 for no restriction
  64. * 1 for 1/4 us
  65. * 2 for 1/2 us
  66. * 3 for 1 us
  67. * 4 for 2 us
  68. * 5 for 4 us
  69. * 6 for 8 us
  70. * 7 for 16 us
  71. */
  72. switch (mpdudensity) {
  73. case 0:
  74. return 0;
  75. case 1:
  76. case 2:
  77. case 3:
  78. /* Our lower layer calculations limit our precision to
  79. 1 microsecond */
  80. return 1;
  81. case 4:
  82. return 2;
  83. case 5:
  84. return 4;
  85. case 6:
  86. return 8;
  87. case 7:
  88. return 16;
  89. default:
  90. return 0;
  91. }
  92. }
  93. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  94. struct ieee80211_hw *hw)
  95. {
  96. struct ieee80211_channel *curchan = hw->conf.channel;
  97. struct ath9k_channel *channel;
  98. u8 chan_idx;
  99. chan_idx = curchan->hw_value;
  100. channel = &sc->sc_ah->channels[chan_idx];
  101. ath9k_update_ichannel(sc, hw, channel);
  102. return channel;
  103. }
  104. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  105. {
  106. unsigned long flags;
  107. bool ret;
  108. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  109. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  110. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  111. return ret;
  112. }
  113. void ath9k_ps_wakeup(struct ath_softc *sc)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  117. if (++sc->ps_usecount != 1)
  118. goto unlock;
  119. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  120. unlock:
  121. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  122. }
  123. void ath9k_ps_restore(struct ath_softc *sc)
  124. {
  125. unsigned long flags;
  126. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  127. if (--sc->ps_usecount != 0)
  128. goto unlock;
  129. if (sc->ps_idle)
  130. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  131. else if (sc->ps_enabled &&
  132. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  133. PS_WAIT_FOR_CAB |
  134. PS_WAIT_FOR_PSPOLL_DATA |
  135. PS_WAIT_FOR_TX_ACK)))
  136. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  137. unlock:
  138. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  139. }
  140. /*
  141. * Set/change channels. If the channel is really being changed, it's done
  142. * by reseting the chip. To accomplish this we must first cleanup any pending
  143. * DMA, then restart stuff.
  144. */
  145. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  146. struct ath9k_channel *hchan)
  147. {
  148. struct ath_hw *ah = sc->sc_ah;
  149. struct ath_common *common = ath9k_hw_common(ah);
  150. struct ieee80211_conf *conf = &common->hw->conf;
  151. bool fastcc = true, stopped;
  152. struct ieee80211_channel *channel = hw->conf.channel;
  153. int r;
  154. if (sc->sc_flags & SC_OP_INVALID)
  155. return -EIO;
  156. ath9k_ps_wakeup(sc);
  157. /*
  158. * This is only performed if the channel settings have
  159. * actually changed.
  160. *
  161. * To switch channels clear any pending DMA operations;
  162. * wait long enough for the RX fifo to drain, reset the
  163. * hardware at the new frequency, and then re-enable
  164. * the relevant bits of the h/w.
  165. */
  166. ath9k_hw_set_interrupts(ah, 0);
  167. ath_drain_all_txq(sc, false);
  168. stopped = ath_stoprecv(sc);
  169. /* XXX: do not flush receive queue here. We don't want
  170. * to flush data frames already in queue because of
  171. * changing channel. */
  172. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  173. fastcc = false;
  174. ath_print(common, ATH_DBG_CONFIG,
  175. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  176. sc->sc_ah->curchan->channel,
  177. channel->center_freq, conf_is_ht40(conf));
  178. spin_lock_bh(&sc->sc_resetlock);
  179. r = ath9k_hw_reset(ah, hchan, fastcc);
  180. if (r) {
  181. ath_print(common, ATH_DBG_FATAL,
  182. "Unable to reset channel (%u MHz), "
  183. "reset status %d\n",
  184. channel->center_freq, r);
  185. spin_unlock_bh(&sc->sc_resetlock);
  186. goto ps_restore;
  187. }
  188. spin_unlock_bh(&sc->sc_resetlock);
  189. sc->sc_flags &= ~SC_OP_FULL_RESET;
  190. if (ath_startrecv(sc) != 0) {
  191. ath_print(common, ATH_DBG_FATAL,
  192. "Unable to restart recv logic\n");
  193. r = -EIO;
  194. goto ps_restore;
  195. }
  196. ath_cache_conf_rate(sc, &hw->conf);
  197. ath_update_txpow(sc);
  198. ath9k_hw_set_interrupts(ah, ah->imask);
  199. ps_restore:
  200. ath9k_ps_restore(sc);
  201. return r;
  202. }
  203. /*
  204. * This routine performs the periodic noise floor calibration function
  205. * that is used to adjust and optimize the chip performance. This
  206. * takes environmental changes (location, temperature) into account.
  207. * When the task is complete, it reschedules itself depending on the
  208. * appropriate interval that was calculated.
  209. */
  210. void ath_ani_calibrate(unsigned long data)
  211. {
  212. struct ath_softc *sc = (struct ath_softc *)data;
  213. struct ath_hw *ah = sc->sc_ah;
  214. struct ath_common *common = ath9k_hw_common(ah);
  215. bool longcal = false;
  216. bool shortcal = false;
  217. bool aniflag = false;
  218. unsigned int timestamp = jiffies_to_msecs(jiffies);
  219. u32 cal_interval, short_cal_interval;
  220. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  221. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  222. /* Only calibrate if awake */
  223. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  224. goto set_timer;
  225. ath9k_ps_wakeup(sc);
  226. /* Long calibration runs independently of short calibration. */
  227. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  228. longcal = true;
  229. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  230. common->ani.longcal_timer = timestamp;
  231. }
  232. /* Short calibration applies only while caldone is false */
  233. if (!common->ani.caldone) {
  234. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  235. shortcal = true;
  236. ath_print(common, ATH_DBG_ANI,
  237. "shortcal @%lu\n", jiffies);
  238. common->ani.shortcal_timer = timestamp;
  239. common->ani.resetcal_timer = timestamp;
  240. }
  241. } else {
  242. if ((timestamp - common->ani.resetcal_timer) >=
  243. ATH_RESTART_CALINTERVAL) {
  244. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  245. if (common->ani.caldone)
  246. common->ani.resetcal_timer = timestamp;
  247. }
  248. }
  249. /* Verify whether we must check ANI */
  250. if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
  251. aniflag = true;
  252. common->ani.checkani_timer = timestamp;
  253. }
  254. /* Skip all processing if there's nothing to do. */
  255. if (longcal || shortcal || aniflag) {
  256. /* Call ANI routine if necessary */
  257. if (aniflag)
  258. ath9k_hw_ani_monitor(ah, ah->curchan);
  259. /* Perform calibration if necessary */
  260. if (longcal || shortcal) {
  261. common->ani.caldone =
  262. ath9k_hw_calibrate(ah,
  263. ah->curchan,
  264. common->rx_chainmask,
  265. longcal);
  266. if (longcal)
  267. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  268. ah->curchan);
  269. ath_print(common, ATH_DBG_ANI,
  270. " calibrate chan %u/%x nf: %d\n",
  271. ah->curchan->channel,
  272. ah->curchan->channelFlags,
  273. common->ani.noise_floor);
  274. }
  275. }
  276. ath9k_ps_restore(sc);
  277. set_timer:
  278. /*
  279. * Set timer interval based on previous results.
  280. * The interval must be the shortest necessary to satisfy ANI,
  281. * short calibration and long calibration.
  282. */
  283. cal_interval = ATH_LONG_CALINTERVAL;
  284. if (sc->sc_ah->config.enable_ani)
  285. cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
  286. if (!common->ani.caldone)
  287. cal_interval = min(cal_interval, (u32)short_cal_interval);
  288. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  289. }
  290. static void ath_start_ani(struct ath_common *common)
  291. {
  292. unsigned long timestamp = jiffies_to_msecs(jiffies);
  293. common->ani.longcal_timer = timestamp;
  294. common->ani.shortcal_timer = timestamp;
  295. common->ani.checkani_timer = timestamp;
  296. mod_timer(&common->ani.timer,
  297. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  298. }
  299. /*
  300. * Update tx/rx chainmask. For legacy association,
  301. * hard code chainmask to 1x1, for 11n association, use
  302. * the chainmask configuration, for bt coexistence, use
  303. * the chainmask configuration even in legacy mode.
  304. */
  305. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  306. {
  307. struct ath_hw *ah = sc->sc_ah;
  308. struct ath_common *common = ath9k_hw_common(ah);
  309. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  310. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  311. common->tx_chainmask = ah->caps.tx_chainmask;
  312. common->rx_chainmask = ah->caps.rx_chainmask;
  313. } else {
  314. common->tx_chainmask = 1;
  315. common->rx_chainmask = 1;
  316. }
  317. ath_print(common, ATH_DBG_CONFIG,
  318. "tx chmask: %d, rx chmask: %d\n",
  319. common->tx_chainmask,
  320. common->rx_chainmask);
  321. }
  322. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  323. {
  324. struct ath_node *an;
  325. an = (struct ath_node *)sta->drv_priv;
  326. if (sc->sc_flags & SC_OP_TXAGGR) {
  327. ath_tx_node_init(sc, an);
  328. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  329. sta->ht_cap.ampdu_factor);
  330. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  331. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  332. }
  333. }
  334. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  335. {
  336. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  337. if (sc->sc_flags & SC_OP_TXAGGR)
  338. ath_tx_node_cleanup(sc, an);
  339. }
  340. void ath9k_tasklet(unsigned long data)
  341. {
  342. struct ath_softc *sc = (struct ath_softc *)data;
  343. struct ath_hw *ah = sc->sc_ah;
  344. struct ath_common *common = ath9k_hw_common(ah);
  345. u32 status = sc->intrstatus;
  346. u32 rxmask;
  347. ath9k_ps_wakeup(sc);
  348. if ((status & ATH9K_INT_FATAL) ||
  349. !ath9k_hw_check_alive(ah)) {
  350. ath_reset(sc, false);
  351. ath9k_ps_restore(sc);
  352. return;
  353. }
  354. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  355. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  356. ATH9K_INT_RXORN);
  357. else
  358. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  359. if (status & rxmask) {
  360. spin_lock_bh(&sc->rx.rxflushlock);
  361. /* Check for high priority Rx first */
  362. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  363. (status & ATH9K_INT_RXHP))
  364. ath_rx_tasklet(sc, 0, true);
  365. ath_rx_tasklet(sc, 0, false);
  366. spin_unlock_bh(&sc->rx.rxflushlock);
  367. }
  368. if (status & ATH9K_INT_TX) {
  369. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  370. ath_tx_edma_tasklet(sc);
  371. else
  372. ath_tx_tasklet(sc);
  373. }
  374. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  375. /*
  376. * TSF sync does not look correct; remain awake to sync with
  377. * the next Beacon.
  378. */
  379. ath_print(common, ATH_DBG_PS,
  380. "TSFOOR - Sync with next Beacon\n");
  381. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  382. }
  383. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  384. if (status & ATH9K_INT_GENTIMER)
  385. ath_gen_timer_isr(sc->sc_ah);
  386. /* re-enable hardware interrupt */
  387. ath9k_hw_set_interrupts(ah, ah->imask);
  388. ath9k_ps_restore(sc);
  389. }
  390. irqreturn_t ath_isr(int irq, void *dev)
  391. {
  392. #define SCHED_INTR ( \
  393. ATH9K_INT_FATAL | \
  394. ATH9K_INT_RXORN | \
  395. ATH9K_INT_RXEOL | \
  396. ATH9K_INT_RX | \
  397. ATH9K_INT_RXLP | \
  398. ATH9K_INT_RXHP | \
  399. ATH9K_INT_TX | \
  400. ATH9K_INT_BMISS | \
  401. ATH9K_INT_CST | \
  402. ATH9K_INT_TSFOOR | \
  403. ATH9K_INT_GENTIMER)
  404. struct ath_softc *sc = dev;
  405. struct ath_hw *ah = sc->sc_ah;
  406. enum ath9k_int status;
  407. bool sched = false;
  408. /*
  409. * The hardware is not ready/present, don't
  410. * touch anything. Note this can happen early
  411. * on if the IRQ is shared.
  412. */
  413. if (sc->sc_flags & SC_OP_INVALID)
  414. return IRQ_NONE;
  415. /* shared irq, not for us */
  416. if (!ath9k_hw_intrpend(ah))
  417. return IRQ_NONE;
  418. /*
  419. * Figure out the reason(s) for the interrupt. Note
  420. * that the hal returns a pseudo-ISR that may include
  421. * bits we haven't explicitly enabled so we mask the
  422. * value to insure we only process bits we requested.
  423. */
  424. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  425. status &= ah->imask; /* discard unasked-for bits */
  426. /*
  427. * If there are no status bits set, then this interrupt was not
  428. * for me (should have been caught above).
  429. */
  430. if (!status)
  431. return IRQ_NONE;
  432. /* Cache the status */
  433. sc->intrstatus = status;
  434. if (status & SCHED_INTR)
  435. sched = true;
  436. /*
  437. * If a FATAL or RXORN interrupt is received, we have to reset the
  438. * chip immediately.
  439. */
  440. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  441. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  442. goto chip_reset;
  443. if (status & ATH9K_INT_SWBA)
  444. tasklet_schedule(&sc->bcon_tasklet);
  445. if (status & ATH9K_INT_TXURN)
  446. ath9k_hw_updatetxtriglevel(ah, true);
  447. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  448. if (status & ATH9K_INT_RXEOL) {
  449. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  450. ath9k_hw_set_interrupts(ah, ah->imask);
  451. }
  452. }
  453. if (status & ATH9K_INT_MIB) {
  454. /*
  455. * Disable interrupts until we service the MIB
  456. * interrupt; otherwise it will continue to
  457. * fire.
  458. */
  459. ath9k_hw_set_interrupts(ah, 0);
  460. /*
  461. * Let the hal handle the event. We assume
  462. * it will clear whatever condition caused
  463. * the interrupt.
  464. */
  465. ath9k_hw_procmibevent(ah);
  466. ath9k_hw_set_interrupts(ah, ah->imask);
  467. }
  468. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  469. if (status & ATH9K_INT_TIM_TIMER) {
  470. /* Clear RxAbort bit so that we can
  471. * receive frames */
  472. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  473. ath9k_hw_setrxabort(sc->sc_ah, 0);
  474. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  475. }
  476. chip_reset:
  477. ath_debug_stat_interrupt(sc, status);
  478. if (sched) {
  479. /* turn off every interrupt except SWBA */
  480. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  481. tasklet_schedule(&sc->intr_tq);
  482. }
  483. return IRQ_HANDLED;
  484. #undef SCHED_INTR
  485. }
  486. static u32 ath_get_extchanmode(struct ath_softc *sc,
  487. struct ieee80211_channel *chan,
  488. enum nl80211_channel_type channel_type)
  489. {
  490. u32 chanmode = 0;
  491. switch (chan->band) {
  492. case IEEE80211_BAND_2GHZ:
  493. switch(channel_type) {
  494. case NL80211_CHAN_NO_HT:
  495. case NL80211_CHAN_HT20:
  496. chanmode = CHANNEL_G_HT20;
  497. break;
  498. case NL80211_CHAN_HT40PLUS:
  499. chanmode = CHANNEL_G_HT40PLUS;
  500. break;
  501. case NL80211_CHAN_HT40MINUS:
  502. chanmode = CHANNEL_G_HT40MINUS;
  503. break;
  504. }
  505. break;
  506. case IEEE80211_BAND_5GHZ:
  507. switch(channel_type) {
  508. case NL80211_CHAN_NO_HT:
  509. case NL80211_CHAN_HT20:
  510. chanmode = CHANNEL_A_HT20;
  511. break;
  512. case NL80211_CHAN_HT40PLUS:
  513. chanmode = CHANNEL_A_HT40PLUS;
  514. break;
  515. case NL80211_CHAN_HT40MINUS:
  516. chanmode = CHANNEL_A_HT40MINUS;
  517. break;
  518. }
  519. break;
  520. default:
  521. break;
  522. }
  523. return chanmode;
  524. }
  525. static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
  526. struct ath9k_keyval *hk, const u8 *addr,
  527. bool authenticator)
  528. {
  529. struct ath_hw *ah = common->ah;
  530. const u8 *key_rxmic;
  531. const u8 *key_txmic;
  532. key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  533. key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  534. if (addr == NULL) {
  535. /*
  536. * Group key installation - only two key cache entries are used
  537. * regardless of splitmic capability since group key is only
  538. * used either for TX or RX.
  539. */
  540. if (authenticator) {
  541. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  542. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
  543. } else {
  544. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  545. memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
  546. }
  547. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  548. }
  549. if (!common->splitmic) {
  550. /* TX and RX keys share the same key cache entry. */
  551. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  552. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  553. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  554. }
  555. /* Separate key cache entries for TX and RX */
  556. /* TX key goes at first index, RX key at +32. */
  557. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  558. if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
  559. /* TX MIC entry failed. No need to proceed further */
  560. ath_print(common, ATH_DBG_FATAL,
  561. "Setting TX MIC Key Failed\n");
  562. return 0;
  563. }
  564. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  565. /* XXX delete tx key on failure? */
  566. return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
  567. }
  568. static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
  569. {
  570. int i;
  571. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  572. if (test_bit(i, common->keymap) ||
  573. test_bit(i + 64, common->keymap))
  574. continue; /* At least one part of TKIP key allocated */
  575. if (common->splitmic &&
  576. (test_bit(i + 32, common->keymap) ||
  577. test_bit(i + 64 + 32, common->keymap)))
  578. continue; /* At least one part of TKIP key allocated */
  579. /* Found a free slot for a TKIP key */
  580. return i;
  581. }
  582. return -1;
  583. }
  584. static int ath_reserve_key_cache_slot(struct ath_common *common)
  585. {
  586. int i;
  587. /* First, try to find slots that would not be available for TKIP. */
  588. if (common->splitmic) {
  589. for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
  590. if (!test_bit(i, common->keymap) &&
  591. (test_bit(i + 32, common->keymap) ||
  592. test_bit(i + 64, common->keymap) ||
  593. test_bit(i + 64 + 32, common->keymap)))
  594. return i;
  595. if (!test_bit(i + 32, common->keymap) &&
  596. (test_bit(i, common->keymap) ||
  597. test_bit(i + 64, common->keymap) ||
  598. test_bit(i + 64 + 32, common->keymap)))
  599. return i + 32;
  600. if (!test_bit(i + 64, common->keymap) &&
  601. (test_bit(i , common->keymap) ||
  602. test_bit(i + 32, common->keymap) ||
  603. test_bit(i + 64 + 32, common->keymap)))
  604. return i + 64;
  605. if (!test_bit(i + 64 + 32, common->keymap) &&
  606. (test_bit(i, common->keymap) ||
  607. test_bit(i + 32, common->keymap) ||
  608. test_bit(i + 64, common->keymap)))
  609. return i + 64 + 32;
  610. }
  611. } else {
  612. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  613. if (!test_bit(i, common->keymap) &&
  614. test_bit(i + 64, common->keymap))
  615. return i;
  616. if (test_bit(i, common->keymap) &&
  617. !test_bit(i + 64, common->keymap))
  618. return i + 64;
  619. }
  620. }
  621. /* No partially used TKIP slots, pick any available slot */
  622. for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
  623. /* Do not allow slots that could be needed for TKIP group keys
  624. * to be used. This limitation could be removed if we know that
  625. * TKIP will not be used. */
  626. if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
  627. continue;
  628. if (common->splitmic) {
  629. if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
  630. continue;
  631. if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
  632. continue;
  633. }
  634. if (!test_bit(i, common->keymap))
  635. return i; /* Found a free slot for a key */
  636. }
  637. /* No free slot found */
  638. return -1;
  639. }
  640. static int ath_key_config(struct ath_common *common,
  641. struct ieee80211_vif *vif,
  642. struct ieee80211_sta *sta,
  643. struct ieee80211_key_conf *key)
  644. {
  645. struct ath_hw *ah = common->ah;
  646. struct ath9k_keyval hk;
  647. const u8 *mac = NULL;
  648. u8 gmac[ETH_ALEN];
  649. int ret = 0;
  650. int idx;
  651. memset(&hk, 0, sizeof(hk));
  652. switch (key->alg) {
  653. case ALG_WEP:
  654. hk.kv_type = ATH9K_CIPHER_WEP;
  655. break;
  656. case ALG_TKIP:
  657. hk.kv_type = ATH9K_CIPHER_TKIP;
  658. break;
  659. case ALG_CCMP:
  660. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  661. break;
  662. default:
  663. return -EOPNOTSUPP;
  664. }
  665. hk.kv_len = key->keylen;
  666. memcpy(hk.kv_val, key->key, key->keylen);
  667. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  668. if (key->ap_addr) {
  669. /*
  670. * Group keys on hardware that supports multicast frame
  671. * key search use a mac that is the sender's address with
  672. * the high bit set instead of the app-specified address.
  673. */
  674. memcpy(gmac, key->ap_addr, ETH_ALEN);
  675. gmac[0] |= 0x80;
  676. mac = gmac;
  677. if (key->alg == ALG_TKIP)
  678. idx = ath_reserve_key_cache_slot_tkip(common);
  679. else
  680. idx = ath_reserve_key_cache_slot(common);
  681. if (idx < 0)
  682. mac = NULL; /* no free key cache entries */
  683. }
  684. if (!mac) {
  685. /* For now, use the default keys for broadcast keys. This may
  686. * need to change with virtual interfaces. */
  687. idx = key->keyidx;
  688. }
  689. } else if (key->keyidx) {
  690. if (WARN_ON(!sta))
  691. return -EOPNOTSUPP;
  692. mac = sta->addr;
  693. if (vif->type != NL80211_IFTYPE_AP) {
  694. /* Only keyidx 0 should be used with unicast key, but
  695. * allow this for client mode for now. */
  696. idx = key->keyidx;
  697. } else
  698. return -EIO;
  699. } else {
  700. if (WARN_ON(!sta))
  701. return -EOPNOTSUPP;
  702. mac = sta->addr;
  703. if (key->alg == ALG_TKIP)
  704. idx = ath_reserve_key_cache_slot_tkip(common);
  705. else
  706. idx = ath_reserve_key_cache_slot(common);
  707. if (idx < 0)
  708. return -ENOSPC; /* no free key cache entries */
  709. }
  710. if (key->alg == ALG_TKIP)
  711. ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
  712. vif->type == NL80211_IFTYPE_AP);
  713. else
  714. ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
  715. if (!ret)
  716. return -EIO;
  717. set_bit(idx, common->keymap);
  718. if (key->alg == ALG_TKIP) {
  719. set_bit(idx + 64, common->keymap);
  720. if (common->splitmic) {
  721. set_bit(idx + 32, common->keymap);
  722. set_bit(idx + 64 + 32, common->keymap);
  723. }
  724. }
  725. return idx;
  726. }
  727. static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
  728. {
  729. struct ath_hw *ah = common->ah;
  730. ath9k_hw_keyreset(ah, key->hw_key_idx);
  731. if (key->hw_key_idx < IEEE80211_WEP_NKID)
  732. return;
  733. clear_bit(key->hw_key_idx, common->keymap);
  734. if (key->alg != ALG_TKIP)
  735. return;
  736. clear_bit(key->hw_key_idx + 64, common->keymap);
  737. if (common->splitmic) {
  738. ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
  739. clear_bit(key->hw_key_idx + 32, common->keymap);
  740. clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
  741. }
  742. }
  743. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  744. struct ieee80211_vif *vif,
  745. struct ieee80211_bss_conf *bss_conf)
  746. {
  747. struct ath_hw *ah = sc->sc_ah;
  748. struct ath_common *common = ath9k_hw_common(ah);
  749. if (bss_conf->assoc) {
  750. ath_print(common, ATH_DBG_CONFIG,
  751. "Bss Info ASSOC %d, bssid: %pM\n",
  752. bss_conf->aid, common->curbssid);
  753. /* New association, store aid */
  754. common->curaid = bss_conf->aid;
  755. ath9k_hw_write_associd(ah);
  756. /*
  757. * Request a re-configuration of Beacon related timers
  758. * on the receipt of the first Beacon frame (i.e.,
  759. * after time sync with the AP).
  760. */
  761. sc->ps_flags |= PS_BEACON_SYNC;
  762. /* Configure the beacon */
  763. ath_beacon_config(sc, vif);
  764. /* Reset rssi stats */
  765. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  766. ath_start_ani(common);
  767. } else {
  768. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  769. common->curaid = 0;
  770. /* Stop ANI */
  771. del_timer_sync(&common->ani.timer);
  772. }
  773. }
  774. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  775. {
  776. struct ath_hw *ah = sc->sc_ah;
  777. struct ath_common *common = ath9k_hw_common(ah);
  778. struct ieee80211_channel *channel = hw->conf.channel;
  779. int r;
  780. ath9k_ps_wakeup(sc);
  781. ath9k_hw_configpcipowersave(ah, 0, 0);
  782. if (!ah->curchan)
  783. ah->curchan = ath_get_curchannel(sc, sc->hw);
  784. spin_lock_bh(&sc->sc_resetlock);
  785. r = ath9k_hw_reset(ah, ah->curchan, false);
  786. if (r) {
  787. ath_print(common, ATH_DBG_FATAL,
  788. "Unable to reset channel (%u MHz), "
  789. "reset status %d\n",
  790. channel->center_freq, r);
  791. }
  792. spin_unlock_bh(&sc->sc_resetlock);
  793. ath_update_txpow(sc);
  794. if (ath_startrecv(sc) != 0) {
  795. ath_print(common, ATH_DBG_FATAL,
  796. "Unable to restart recv logic\n");
  797. return;
  798. }
  799. if (sc->sc_flags & SC_OP_BEACONS)
  800. ath_beacon_config(sc, NULL); /* restart beacons */
  801. /* Re-Enable interrupts */
  802. ath9k_hw_set_interrupts(ah, ah->imask);
  803. /* Enable LED */
  804. ath9k_hw_cfg_output(ah, ah->led_pin,
  805. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  806. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  807. ieee80211_wake_queues(hw);
  808. ath9k_ps_restore(sc);
  809. }
  810. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  811. {
  812. struct ath_hw *ah = sc->sc_ah;
  813. struct ieee80211_channel *channel = hw->conf.channel;
  814. int r;
  815. ath9k_ps_wakeup(sc);
  816. ieee80211_stop_queues(hw);
  817. /* Disable LED */
  818. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  819. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  820. /* Disable interrupts */
  821. ath9k_hw_set_interrupts(ah, 0);
  822. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  823. ath_stoprecv(sc); /* turn off frame recv */
  824. ath_flushrecv(sc); /* flush recv queue */
  825. if (!ah->curchan)
  826. ah->curchan = ath_get_curchannel(sc, hw);
  827. spin_lock_bh(&sc->sc_resetlock);
  828. r = ath9k_hw_reset(ah, ah->curchan, false);
  829. if (r) {
  830. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  831. "Unable to reset channel (%u MHz), "
  832. "reset status %d\n",
  833. channel->center_freq, r);
  834. }
  835. spin_unlock_bh(&sc->sc_resetlock);
  836. ath9k_hw_phy_disable(ah);
  837. ath9k_hw_configpcipowersave(ah, 1, 1);
  838. ath9k_ps_restore(sc);
  839. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  840. }
  841. int ath_reset(struct ath_softc *sc, bool retry_tx)
  842. {
  843. struct ath_hw *ah = sc->sc_ah;
  844. struct ath_common *common = ath9k_hw_common(ah);
  845. struct ieee80211_hw *hw = sc->hw;
  846. int r;
  847. /* Stop ANI */
  848. del_timer_sync(&common->ani.timer);
  849. ieee80211_stop_queues(hw);
  850. ath9k_hw_set_interrupts(ah, 0);
  851. ath_drain_all_txq(sc, retry_tx);
  852. ath_stoprecv(sc);
  853. ath_flushrecv(sc);
  854. spin_lock_bh(&sc->sc_resetlock);
  855. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  856. if (r)
  857. ath_print(common, ATH_DBG_FATAL,
  858. "Unable to reset hardware; reset status %d\n", r);
  859. spin_unlock_bh(&sc->sc_resetlock);
  860. if (ath_startrecv(sc) != 0)
  861. ath_print(common, ATH_DBG_FATAL,
  862. "Unable to start recv logic\n");
  863. /*
  864. * We may be doing a reset in response to a request
  865. * that changes the channel so update any state that
  866. * might change as a result.
  867. */
  868. ath_cache_conf_rate(sc, &hw->conf);
  869. ath_update_txpow(sc);
  870. if (sc->sc_flags & SC_OP_BEACONS)
  871. ath_beacon_config(sc, NULL); /* restart beacons */
  872. ath9k_hw_set_interrupts(ah, ah->imask);
  873. if (retry_tx) {
  874. int i;
  875. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  876. if (ATH_TXQ_SETUP(sc, i)) {
  877. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  878. ath_txq_schedule(sc, &sc->tx.txq[i]);
  879. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  880. }
  881. }
  882. }
  883. ieee80211_wake_queues(hw);
  884. /* Start ANI */
  885. ath_start_ani(common);
  886. return r;
  887. }
  888. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  889. {
  890. int qnum;
  891. switch (queue) {
  892. case 0:
  893. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
  894. break;
  895. case 1:
  896. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
  897. break;
  898. case 2:
  899. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  900. break;
  901. case 3:
  902. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
  903. break;
  904. default:
  905. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  906. break;
  907. }
  908. return qnum;
  909. }
  910. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  911. {
  912. int qnum;
  913. switch (queue) {
  914. case ATH9K_WME_AC_VO:
  915. qnum = 0;
  916. break;
  917. case ATH9K_WME_AC_VI:
  918. qnum = 1;
  919. break;
  920. case ATH9K_WME_AC_BE:
  921. qnum = 2;
  922. break;
  923. case ATH9K_WME_AC_BK:
  924. qnum = 3;
  925. break;
  926. default:
  927. qnum = -1;
  928. break;
  929. }
  930. return qnum;
  931. }
  932. /* XXX: Remove me once we don't depend on ath9k_channel for all
  933. * this redundant data */
  934. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  935. struct ath9k_channel *ichan)
  936. {
  937. struct ieee80211_channel *chan = hw->conf.channel;
  938. struct ieee80211_conf *conf = &hw->conf;
  939. ichan->channel = chan->center_freq;
  940. ichan->chan = chan;
  941. if (chan->band == IEEE80211_BAND_2GHZ) {
  942. ichan->chanmode = CHANNEL_G;
  943. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  944. } else {
  945. ichan->chanmode = CHANNEL_A;
  946. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  947. }
  948. if (conf_is_ht(conf))
  949. ichan->chanmode = ath_get_extchanmode(sc, chan,
  950. conf->channel_type);
  951. }
  952. /**********************/
  953. /* mac80211 callbacks */
  954. /**********************/
  955. static int ath9k_start(struct ieee80211_hw *hw)
  956. {
  957. struct ath_wiphy *aphy = hw->priv;
  958. struct ath_softc *sc = aphy->sc;
  959. struct ath_hw *ah = sc->sc_ah;
  960. struct ath_common *common = ath9k_hw_common(ah);
  961. struct ieee80211_channel *curchan = hw->conf.channel;
  962. struct ath9k_channel *init_channel;
  963. int r;
  964. ath_print(common, ATH_DBG_CONFIG,
  965. "Starting driver with initial channel: %d MHz\n",
  966. curchan->center_freq);
  967. mutex_lock(&sc->mutex);
  968. if (ath9k_wiphy_started(sc)) {
  969. if (sc->chan_idx == curchan->hw_value) {
  970. /*
  971. * Already on the operational channel, the new wiphy
  972. * can be marked active.
  973. */
  974. aphy->state = ATH_WIPHY_ACTIVE;
  975. ieee80211_wake_queues(hw);
  976. } else {
  977. /*
  978. * Another wiphy is on another channel, start the new
  979. * wiphy in paused state.
  980. */
  981. aphy->state = ATH_WIPHY_PAUSED;
  982. ieee80211_stop_queues(hw);
  983. }
  984. mutex_unlock(&sc->mutex);
  985. return 0;
  986. }
  987. aphy->state = ATH_WIPHY_ACTIVE;
  988. /* setup initial channel */
  989. sc->chan_idx = curchan->hw_value;
  990. init_channel = ath_get_curchannel(sc, hw);
  991. /* Reset SERDES registers */
  992. ath9k_hw_configpcipowersave(ah, 0, 0);
  993. /*
  994. * The basic interface to setting the hardware in a good
  995. * state is ``reset''. On return the hardware is known to
  996. * be powered up and with interrupts disabled. This must
  997. * be followed by initialization of the appropriate bits
  998. * and then setup of the interrupt mask.
  999. */
  1000. spin_lock_bh(&sc->sc_resetlock);
  1001. r = ath9k_hw_reset(ah, init_channel, false);
  1002. if (r) {
  1003. ath_print(common, ATH_DBG_FATAL,
  1004. "Unable to reset hardware; reset status %d "
  1005. "(freq %u MHz)\n", r,
  1006. curchan->center_freq);
  1007. spin_unlock_bh(&sc->sc_resetlock);
  1008. goto mutex_unlock;
  1009. }
  1010. spin_unlock_bh(&sc->sc_resetlock);
  1011. /*
  1012. * This is needed only to setup initial state
  1013. * but it's best done after a reset.
  1014. */
  1015. ath_update_txpow(sc);
  1016. /*
  1017. * Setup the hardware after reset:
  1018. * The receive engine is set going.
  1019. * Frame transmit is handled entirely
  1020. * in the frame output path; there's nothing to do
  1021. * here except setup the interrupt mask.
  1022. */
  1023. if (ath_startrecv(sc) != 0) {
  1024. ath_print(common, ATH_DBG_FATAL,
  1025. "Unable to start recv logic\n");
  1026. r = -EIO;
  1027. goto mutex_unlock;
  1028. }
  1029. /* Setup our intr mask. */
  1030. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  1031. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  1032. ATH9K_INT_GLOBAL;
  1033. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  1034. ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
  1035. else
  1036. ah->imask |= ATH9K_INT_RX;
  1037. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  1038. ah->imask |= ATH9K_INT_GTT;
  1039. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  1040. ah->imask |= ATH9K_INT_CST;
  1041. ath_cache_conf_rate(sc, &hw->conf);
  1042. sc->sc_flags &= ~SC_OP_INVALID;
  1043. /* Disable BMISS interrupt when we're not associated */
  1044. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1045. ath9k_hw_set_interrupts(ah, ah->imask);
  1046. ieee80211_wake_queues(hw);
  1047. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1048. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  1049. !ah->btcoex_hw.enabled) {
  1050. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  1051. AR_STOMP_LOW_WLAN_WGHT);
  1052. ath9k_hw_btcoex_enable(ah);
  1053. if (common->bus_ops->bt_coex_prep)
  1054. common->bus_ops->bt_coex_prep(common);
  1055. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1056. ath9k_btcoex_timer_resume(sc);
  1057. }
  1058. mutex_unlock:
  1059. mutex_unlock(&sc->mutex);
  1060. return r;
  1061. }
  1062. static int ath9k_tx(struct ieee80211_hw *hw,
  1063. struct sk_buff *skb)
  1064. {
  1065. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1066. struct ath_wiphy *aphy = hw->priv;
  1067. struct ath_softc *sc = aphy->sc;
  1068. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1069. struct ath_tx_control txctl;
  1070. int padpos, padsize;
  1071. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1072. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1073. ath_print(common, ATH_DBG_XMIT,
  1074. "ath9k: %s: TX in unexpected wiphy state "
  1075. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1076. goto exit;
  1077. }
  1078. if (sc->ps_enabled) {
  1079. /*
  1080. * mac80211 does not set PM field for normal data frames, so we
  1081. * need to update that based on the current PS mode.
  1082. */
  1083. if (ieee80211_is_data(hdr->frame_control) &&
  1084. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1085. !ieee80211_has_pm(hdr->frame_control)) {
  1086. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1087. "while in PS mode\n");
  1088. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1089. }
  1090. }
  1091. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1092. /*
  1093. * We are using PS-Poll and mac80211 can request TX while in
  1094. * power save mode. Need to wake up hardware for the TX to be
  1095. * completed and if needed, also for RX of buffered frames.
  1096. */
  1097. ath9k_ps_wakeup(sc);
  1098. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1099. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1100. ath_print(common, ATH_DBG_PS,
  1101. "Sending PS-Poll to pick a buffered frame\n");
  1102. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1103. } else {
  1104. ath_print(common, ATH_DBG_PS,
  1105. "Wake up to complete TX\n");
  1106. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1107. }
  1108. /*
  1109. * The actual restore operation will happen only after
  1110. * the sc_flags bit is cleared. We are just dropping
  1111. * the ps_usecount here.
  1112. */
  1113. ath9k_ps_restore(sc);
  1114. }
  1115. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1116. /*
  1117. * As a temporary workaround, assign seq# here; this will likely need
  1118. * to be cleaned up to work better with Beacon transmission and virtual
  1119. * BSSes.
  1120. */
  1121. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1122. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1123. sc->tx.seq_no += 0x10;
  1124. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1125. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1126. }
  1127. /* Add the padding after the header if this is not already done */
  1128. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1129. padsize = padpos & 3;
  1130. if (padsize && skb->len>padpos) {
  1131. if (skb_headroom(skb) < padsize)
  1132. return -1;
  1133. skb_push(skb, padsize);
  1134. memmove(skb->data, skb->data + padsize, padpos);
  1135. }
  1136. /* Check if a tx queue is available */
  1137. txctl.txq = ath_test_get_txq(sc, skb);
  1138. if (!txctl.txq)
  1139. goto exit;
  1140. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1141. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1142. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1143. goto exit;
  1144. }
  1145. return 0;
  1146. exit:
  1147. dev_kfree_skb_any(skb);
  1148. return 0;
  1149. }
  1150. static void ath9k_stop(struct ieee80211_hw *hw)
  1151. {
  1152. struct ath_wiphy *aphy = hw->priv;
  1153. struct ath_softc *sc = aphy->sc;
  1154. struct ath_hw *ah = sc->sc_ah;
  1155. struct ath_common *common = ath9k_hw_common(ah);
  1156. mutex_lock(&sc->mutex);
  1157. aphy->state = ATH_WIPHY_INACTIVE;
  1158. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1159. cancel_delayed_work_sync(&sc->tx_complete_work);
  1160. if (!sc->num_sec_wiphy) {
  1161. cancel_delayed_work_sync(&sc->wiphy_work);
  1162. cancel_work_sync(&sc->chan_work);
  1163. }
  1164. if (sc->sc_flags & SC_OP_INVALID) {
  1165. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1166. mutex_unlock(&sc->mutex);
  1167. return;
  1168. }
  1169. if (ath9k_wiphy_started(sc)) {
  1170. mutex_unlock(&sc->mutex);
  1171. return; /* another wiphy still in use */
  1172. }
  1173. /* Ensure HW is awake when we try to shut it down. */
  1174. ath9k_ps_wakeup(sc);
  1175. if (ah->btcoex_hw.enabled) {
  1176. ath9k_hw_btcoex_disable(ah);
  1177. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1178. ath9k_btcoex_timer_pause(sc);
  1179. }
  1180. /* make sure h/w will not generate any interrupt
  1181. * before setting the invalid flag. */
  1182. ath9k_hw_set_interrupts(ah, 0);
  1183. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1184. ath_drain_all_txq(sc, false);
  1185. ath_stoprecv(sc);
  1186. ath9k_hw_phy_disable(ah);
  1187. } else
  1188. sc->rx.rxlink = NULL;
  1189. /* disable HAL and put h/w to sleep */
  1190. ath9k_hw_disable(ah);
  1191. ath9k_hw_configpcipowersave(ah, 1, 1);
  1192. ath9k_ps_restore(sc);
  1193. /* Finally, put the chip in FULL SLEEP mode */
  1194. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1195. sc->sc_flags |= SC_OP_INVALID;
  1196. mutex_unlock(&sc->mutex);
  1197. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1198. }
  1199. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1200. struct ieee80211_vif *vif)
  1201. {
  1202. struct ath_wiphy *aphy = hw->priv;
  1203. struct ath_softc *sc = aphy->sc;
  1204. struct ath_hw *ah = sc->sc_ah;
  1205. struct ath_common *common = ath9k_hw_common(ah);
  1206. struct ath_vif *avp = (void *)vif->drv_priv;
  1207. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1208. int ret = 0;
  1209. mutex_lock(&sc->mutex);
  1210. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1211. sc->nvifs > 0) {
  1212. ret = -ENOBUFS;
  1213. goto out;
  1214. }
  1215. switch (vif->type) {
  1216. case NL80211_IFTYPE_STATION:
  1217. ic_opmode = NL80211_IFTYPE_STATION;
  1218. break;
  1219. case NL80211_IFTYPE_ADHOC:
  1220. case NL80211_IFTYPE_AP:
  1221. case NL80211_IFTYPE_MESH_POINT:
  1222. if (sc->nbcnvifs >= ATH_BCBUF) {
  1223. ret = -ENOBUFS;
  1224. goto out;
  1225. }
  1226. ic_opmode = vif->type;
  1227. break;
  1228. default:
  1229. ath_print(common, ATH_DBG_FATAL,
  1230. "Interface type %d not yet supported\n", vif->type);
  1231. ret = -EOPNOTSUPP;
  1232. goto out;
  1233. }
  1234. ath_print(common, ATH_DBG_CONFIG,
  1235. "Attach a VIF of type: %d\n", ic_opmode);
  1236. /* Set the VIF opmode */
  1237. avp->av_opmode = ic_opmode;
  1238. avp->av_bslot = -1;
  1239. sc->nvifs++;
  1240. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1241. ath9k_set_bssid_mask(hw);
  1242. if (sc->nvifs > 1)
  1243. goto out; /* skip global settings for secondary vif */
  1244. if (ic_opmode == NL80211_IFTYPE_AP) {
  1245. ath9k_hw_set_tsfadjust(ah, 1);
  1246. sc->sc_flags |= SC_OP_TSF_RESET;
  1247. }
  1248. /* Set the device opmode */
  1249. ah->opmode = ic_opmode;
  1250. /*
  1251. * Enable MIB interrupts when there are hardware phy counters.
  1252. * Note we only do this (at the moment) for station mode.
  1253. */
  1254. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1255. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1256. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1257. if (ah->config.enable_ani)
  1258. ah->imask |= ATH9K_INT_MIB;
  1259. ah->imask |= ATH9K_INT_TSFOOR;
  1260. }
  1261. ath9k_hw_set_interrupts(ah, ah->imask);
  1262. if (vif->type == NL80211_IFTYPE_AP ||
  1263. vif->type == NL80211_IFTYPE_ADHOC ||
  1264. vif->type == NL80211_IFTYPE_MONITOR)
  1265. ath_start_ani(common);
  1266. out:
  1267. mutex_unlock(&sc->mutex);
  1268. return ret;
  1269. }
  1270. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1271. struct ieee80211_vif *vif)
  1272. {
  1273. struct ath_wiphy *aphy = hw->priv;
  1274. struct ath_softc *sc = aphy->sc;
  1275. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1276. struct ath_vif *avp = (void *)vif->drv_priv;
  1277. int i;
  1278. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1279. mutex_lock(&sc->mutex);
  1280. /* Stop ANI */
  1281. del_timer_sync(&common->ani.timer);
  1282. /* Reclaim beacon resources */
  1283. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1284. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1285. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1286. ath9k_ps_wakeup(sc);
  1287. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1288. ath9k_ps_restore(sc);
  1289. }
  1290. ath_beacon_return(sc, avp);
  1291. sc->sc_flags &= ~SC_OP_BEACONS;
  1292. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1293. if (sc->beacon.bslot[i] == vif) {
  1294. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1295. "slot\n", __func__);
  1296. sc->beacon.bslot[i] = NULL;
  1297. sc->beacon.bslot_aphy[i] = NULL;
  1298. }
  1299. }
  1300. sc->nvifs--;
  1301. mutex_unlock(&sc->mutex);
  1302. }
  1303. void ath9k_enable_ps(struct ath_softc *sc)
  1304. {
  1305. struct ath_hw *ah = sc->sc_ah;
  1306. sc->ps_enabled = true;
  1307. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1308. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1309. ah->imask |= ATH9K_INT_TIM_TIMER;
  1310. ath9k_hw_set_interrupts(ah, ah->imask);
  1311. }
  1312. }
  1313. ath9k_hw_setrxabort(ah, 1);
  1314. }
  1315. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1316. {
  1317. struct ath_wiphy *aphy = hw->priv;
  1318. struct ath_softc *sc = aphy->sc;
  1319. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1320. struct ieee80211_conf *conf = &hw->conf;
  1321. struct ath_hw *ah = sc->sc_ah;
  1322. bool disable_radio;
  1323. mutex_lock(&sc->mutex);
  1324. /*
  1325. * Leave this as the first check because we need to turn on the
  1326. * radio if it was disabled before prior to processing the rest
  1327. * of the changes. Likewise we must only disable the radio towards
  1328. * the end.
  1329. */
  1330. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1331. bool enable_radio;
  1332. bool all_wiphys_idle;
  1333. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1334. spin_lock_bh(&sc->wiphy_lock);
  1335. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1336. ath9k_set_wiphy_idle(aphy, idle);
  1337. enable_radio = (!idle && all_wiphys_idle);
  1338. /*
  1339. * After we unlock here its possible another wiphy
  1340. * can be re-renabled so to account for that we will
  1341. * only disable the radio toward the end of this routine
  1342. * if by then all wiphys are still idle.
  1343. */
  1344. spin_unlock_bh(&sc->wiphy_lock);
  1345. if (enable_radio) {
  1346. sc->ps_idle = false;
  1347. ath_radio_enable(sc, hw);
  1348. ath_print(common, ATH_DBG_CONFIG,
  1349. "not-idle: enabling radio\n");
  1350. }
  1351. }
  1352. /*
  1353. * We just prepare to enable PS. We have to wait until our AP has
  1354. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1355. * those ACKs and end up retransmitting the same null data frames.
  1356. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1357. */
  1358. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1359. if (conf->flags & IEEE80211_CONF_PS) {
  1360. sc->ps_flags |= PS_ENABLED;
  1361. /*
  1362. * At this point we know hardware has received an ACK
  1363. * of a previously sent null data frame.
  1364. */
  1365. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1366. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1367. ath9k_enable_ps(sc);
  1368. }
  1369. } else {
  1370. sc->ps_enabled = false;
  1371. sc->ps_flags &= ~(PS_ENABLED |
  1372. PS_NULLFUNC_COMPLETED);
  1373. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1374. if (!(ah->caps.hw_caps &
  1375. ATH9K_HW_CAP_AUTOSLEEP)) {
  1376. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1377. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1378. PS_WAIT_FOR_CAB |
  1379. PS_WAIT_FOR_PSPOLL_DATA |
  1380. PS_WAIT_FOR_TX_ACK);
  1381. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1382. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1383. ath9k_hw_set_interrupts(sc->sc_ah,
  1384. ah->imask);
  1385. }
  1386. }
  1387. }
  1388. }
  1389. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1390. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1391. ath_print(common, ATH_DBG_CONFIG,
  1392. "HW opmode set to Monitor mode\n");
  1393. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1394. }
  1395. }
  1396. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1397. struct ieee80211_channel *curchan = hw->conf.channel;
  1398. int pos = curchan->hw_value;
  1399. aphy->chan_idx = pos;
  1400. aphy->chan_is_ht = conf_is_ht(conf);
  1401. if (aphy->state == ATH_WIPHY_SCAN ||
  1402. aphy->state == ATH_WIPHY_ACTIVE)
  1403. ath9k_wiphy_pause_all_forced(sc, aphy);
  1404. else {
  1405. /*
  1406. * Do not change operational channel based on a paused
  1407. * wiphy changes.
  1408. */
  1409. goto skip_chan_change;
  1410. }
  1411. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1412. curchan->center_freq);
  1413. /* XXX: remove me eventualy */
  1414. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1415. ath_update_chainmask(sc, conf_is_ht(conf));
  1416. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1417. ath_print(common, ATH_DBG_FATAL,
  1418. "Unable to set channel\n");
  1419. mutex_unlock(&sc->mutex);
  1420. return -EINVAL;
  1421. }
  1422. }
  1423. skip_chan_change:
  1424. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1425. sc->config.txpowlimit = 2 * conf->power_level;
  1426. ath_update_txpow(sc);
  1427. }
  1428. spin_lock_bh(&sc->wiphy_lock);
  1429. disable_radio = ath9k_all_wiphys_idle(sc);
  1430. spin_unlock_bh(&sc->wiphy_lock);
  1431. if (disable_radio) {
  1432. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1433. sc->ps_idle = true;
  1434. ath_radio_disable(sc, hw);
  1435. }
  1436. mutex_unlock(&sc->mutex);
  1437. return 0;
  1438. }
  1439. #define SUPPORTED_FILTERS \
  1440. (FIF_PROMISC_IN_BSS | \
  1441. FIF_ALLMULTI | \
  1442. FIF_CONTROL | \
  1443. FIF_PSPOLL | \
  1444. FIF_OTHER_BSS | \
  1445. FIF_BCN_PRBRESP_PROMISC | \
  1446. FIF_FCSFAIL)
  1447. /* FIXME: sc->sc_full_reset ? */
  1448. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1449. unsigned int changed_flags,
  1450. unsigned int *total_flags,
  1451. u64 multicast)
  1452. {
  1453. struct ath_wiphy *aphy = hw->priv;
  1454. struct ath_softc *sc = aphy->sc;
  1455. u32 rfilt;
  1456. changed_flags &= SUPPORTED_FILTERS;
  1457. *total_flags &= SUPPORTED_FILTERS;
  1458. sc->rx.rxfilter = *total_flags;
  1459. ath9k_ps_wakeup(sc);
  1460. rfilt = ath_calcrxfilter(sc);
  1461. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1462. ath9k_ps_restore(sc);
  1463. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1464. "Set HW RX filter: 0x%x\n", rfilt);
  1465. }
  1466. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1467. struct ieee80211_vif *vif,
  1468. struct ieee80211_sta *sta)
  1469. {
  1470. struct ath_wiphy *aphy = hw->priv;
  1471. struct ath_softc *sc = aphy->sc;
  1472. ath_node_attach(sc, sta);
  1473. return 0;
  1474. }
  1475. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1476. struct ieee80211_vif *vif,
  1477. struct ieee80211_sta *sta)
  1478. {
  1479. struct ath_wiphy *aphy = hw->priv;
  1480. struct ath_softc *sc = aphy->sc;
  1481. ath_node_detach(sc, sta);
  1482. return 0;
  1483. }
  1484. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1485. const struct ieee80211_tx_queue_params *params)
  1486. {
  1487. struct ath_wiphy *aphy = hw->priv;
  1488. struct ath_softc *sc = aphy->sc;
  1489. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1490. struct ath9k_tx_queue_info qi;
  1491. int ret = 0, qnum;
  1492. if (queue >= WME_NUM_AC)
  1493. return 0;
  1494. mutex_lock(&sc->mutex);
  1495. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1496. qi.tqi_aifs = params->aifs;
  1497. qi.tqi_cwmin = params->cw_min;
  1498. qi.tqi_cwmax = params->cw_max;
  1499. qi.tqi_burstTime = params->txop;
  1500. qnum = ath_get_hal_qnum(queue, sc);
  1501. ath_print(common, ATH_DBG_CONFIG,
  1502. "Configure tx [queue/halq] [%d/%d], "
  1503. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1504. queue, qnum, params->aifs, params->cw_min,
  1505. params->cw_max, params->txop);
  1506. ret = ath_txq_update(sc, qnum, &qi);
  1507. if (ret)
  1508. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1509. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1510. if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
  1511. ath_beaconq_config(sc);
  1512. mutex_unlock(&sc->mutex);
  1513. return ret;
  1514. }
  1515. static int ath9k_set_key(struct ieee80211_hw *hw,
  1516. enum set_key_cmd cmd,
  1517. struct ieee80211_vif *vif,
  1518. struct ieee80211_sta *sta,
  1519. struct ieee80211_key_conf *key)
  1520. {
  1521. struct ath_wiphy *aphy = hw->priv;
  1522. struct ath_softc *sc = aphy->sc;
  1523. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1524. int ret = 0;
  1525. if (modparam_nohwcrypt)
  1526. return -ENOSPC;
  1527. mutex_lock(&sc->mutex);
  1528. ath9k_ps_wakeup(sc);
  1529. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1530. switch (cmd) {
  1531. case SET_KEY:
  1532. ret = ath_key_config(common, vif, sta, key);
  1533. if (ret >= 0) {
  1534. key->hw_key_idx = ret;
  1535. /* push IV and Michael MIC generation to stack */
  1536. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1537. if (key->alg == ALG_TKIP)
  1538. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1539. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1540. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1541. ret = 0;
  1542. }
  1543. break;
  1544. case DISABLE_KEY:
  1545. ath_key_delete(common, key);
  1546. break;
  1547. default:
  1548. ret = -EINVAL;
  1549. }
  1550. ath9k_ps_restore(sc);
  1551. mutex_unlock(&sc->mutex);
  1552. return ret;
  1553. }
  1554. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1555. struct ieee80211_vif *vif,
  1556. struct ieee80211_bss_conf *bss_conf,
  1557. u32 changed)
  1558. {
  1559. struct ath_wiphy *aphy = hw->priv;
  1560. struct ath_softc *sc = aphy->sc;
  1561. struct ath_hw *ah = sc->sc_ah;
  1562. struct ath_common *common = ath9k_hw_common(ah);
  1563. struct ath_vif *avp = (void *)vif->drv_priv;
  1564. int slottime;
  1565. int error;
  1566. mutex_lock(&sc->mutex);
  1567. if (changed & BSS_CHANGED_BSSID) {
  1568. /* Set BSSID */
  1569. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1570. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1571. common->curaid = 0;
  1572. ath9k_hw_write_associd(ah);
  1573. /* Set aggregation protection mode parameters */
  1574. sc->config.ath_aggr_prot = 0;
  1575. /* Only legacy IBSS for now */
  1576. if (vif->type == NL80211_IFTYPE_ADHOC)
  1577. ath_update_chainmask(sc, 0);
  1578. ath_print(common, ATH_DBG_CONFIG,
  1579. "BSSID: %pM aid: 0x%x\n",
  1580. common->curbssid, common->curaid);
  1581. /* need to reconfigure the beacon */
  1582. sc->sc_flags &= ~SC_OP_BEACONS ;
  1583. }
  1584. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1585. if ((changed & BSS_CHANGED_BEACON) ||
  1586. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1587. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1588. error = ath_beacon_alloc(aphy, vif);
  1589. if (!error)
  1590. ath_beacon_config(sc, vif);
  1591. }
  1592. if (changed & BSS_CHANGED_ERP_SLOT) {
  1593. if (bss_conf->use_short_slot)
  1594. slottime = 9;
  1595. else
  1596. slottime = 20;
  1597. if (vif->type == NL80211_IFTYPE_AP) {
  1598. /*
  1599. * Defer update, so that connected stations can adjust
  1600. * their settings at the same time.
  1601. * See beacon.c for more details
  1602. */
  1603. sc->beacon.slottime = slottime;
  1604. sc->beacon.updateslot = UPDATE;
  1605. } else {
  1606. ah->slottime = slottime;
  1607. ath9k_hw_init_global_settings(ah);
  1608. }
  1609. }
  1610. /* Disable transmission of beacons */
  1611. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1612. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1613. if (changed & BSS_CHANGED_BEACON_INT) {
  1614. sc->beacon_interval = bss_conf->beacon_int;
  1615. /*
  1616. * In case of AP mode, the HW TSF has to be reset
  1617. * when the beacon interval changes.
  1618. */
  1619. if (vif->type == NL80211_IFTYPE_AP) {
  1620. sc->sc_flags |= SC_OP_TSF_RESET;
  1621. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1622. error = ath_beacon_alloc(aphy, vif);
  1623. if (!error)
  1624. ath_beacon_config(sc, vif);
  1625. } else {
  1626. ath_beacon_config(sc, vif);
  1627. }
  1628. }
  1629. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1630. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1631. bss_conf->use_short_preamble);
  1632. if (bss_conf->use_short_preamble)
  1633. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1634. else
  1635. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1636. }
  1637. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1638. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1639. bss_conf->use_cts_prot);
  1640. if (bss_conf->use_cts_prot &&
  1641. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1642. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1643. else
  1644. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1645. }
  1646. if (changed & BSS_CHANGED_ASSOC) {
  1647. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1648. bss_conf->assoc);
  1649. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1650. }
  1651. mutex_unlock(&sc->mutex);
  1652. }
  1653. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1654. {
  1655. u64 tsf;
  1656. struct ath_wiphy *aphy = hw->priv;
  1657. struct ath_softc *sc = aphy->sc;
  1658. mutex_lock(&sc->mutex);
  1659. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1660. mutex_unlock(&sc->mutex);
  1661. return tsf;
  1662. }
  1663. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1664. {
  1665. struct ath_wiphy *aphy = hw->priv;
  1666. struct ath_softc *sc = aphy->sc;
  1667. mutex_lock(&sc->mutex);
  1668. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1669. mutex_unlock(&sc->mutex);
  1670. }
  1671. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1672. {
  1673. struct ath_wiphy *aphy = hw->priv;
  1674. struct ath_softc *sc = aphy->sc;
  1675. mutex_lock(&sc->mutex);
  1676. ath9k_ps_wakeup(sc);
  1677. ath9k_hw_reset_tsf(sc->sc_ah);
  1678. ath9k_ps_restore(sc);
  1679. mutex_unlock(&sc->mutex);
  1680. }
  1681. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1682. struct ieee80211_vif *vif,
  1683. enum ieee80211_ampdu_mlme_action action,
  1684. struct ieee80211_sta *sta,
  1685. u16 tid, u16 *ssn)
  1686. {
  1687. struct ath_wiphy *aphy = hw->priv;
  1688. struct ath_softc *sc = aphy->sc;
  1689. int ret = 0;
  1690. switch (action) {
  1691. case IEEE80211_AMPDU_RX_START:
  1692. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1693. ret = -ENOTSUPP;
  1694. break;
  1695. case IEEE80211_AMPDU_RX_STOP:
  1696. break;
  1697. case IEEE80211_AMPDU_TX_START:
  1698. ath9k_ps_wakeup(sc);
  1699. ath_tx_aggr_start(sc, sta, tid, ssn);
  1700. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1701. ath9k_ps_restore(sc);
  1702. break;
  1703. case IEEE80211_AMPDU_TX_STOP:
  1704. ath9k_ps_wakeup(sc);
  1705. ath_tx_aggr_stop(sc, sta, tid);
  1706. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1707. ath9k_ps_restore(sc);
  1708. break;
  1709. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1710. ath9k_ps_wakeup(sc);
  1711. ath_tx_aggr_resume(sc, sta, tid);
  1712. ath9k_ps_restore(sc);
  1713. break;
  1714. default:
  1715. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1716. "Unknown AMPDU action\n");
  1717. }
  1718. return ret;
  1719. }
  1720. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1721. {
  1722. struct ath_wiphy *aphy = hw->priv;
  1723. struct ath_softc *sc = aphy->sc;
  1724. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1725. mutex_lock(&sc->mutex);
  1726. if (ath9k_wiphy_scanning(sc)) {
  1727. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1728. "same time\n");
  1729. /*
  1730. * Do not allow the concurrent scanning state for now. This
  1731. * could be improved with scanning control moved into ath9k.
  1732. */
  1733. mutex_unlock(&sc->mutex);
  1734. return;
  1735. }
  1736. aphy->state = ATH_WIPHY_SCAN;
  1737. ath9k_wiphy_pause_all_forced(sc, aphy);
  1738. sc->sc_flags |= SC_OP_SCANNING;
  1739. del_timer_sync(&common->ani.timer);
  1740. cancel_delayed_work_sync(&sc->tx_complete_work);
  1741. mutex_unlock(&sc->mutex);
  1742. }
  1743. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1744. {
  1745. struct ath_wiphy *aphy = hw->priv;
  1746. struct ath_softc *sc = aphy->sc;
  1747. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1748. mutex_lock(&sc->mutex);
  1749. aphy->state = ATH_WIPHY_ACTIVE;
  1750. sc->sc_flags &= ~SC_OP_SCANNING;
  1751. sc->sc_flags |= SC_OP_FULL_RESET;
  1752. ath_start_ani(common);
  1753. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1754. ath_beacon_config(sc, NULL);
  1755. mutex_unlock(&sc->mutex);
  1756. }
  1757. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1758. {
  1759. struct ath_wiphy *aphy = hw->priv;
  1760. struct ath_softc *sc = aphy->sc;
  1761. struct ath_hw *ah = sc->sc_ah;
  1762. mutex_lock(&sc->mutex);
  1763. ah->coverage_class = coverage_class;
  1764. ath9k_hw_init_global_settings(ah);
  1765. mutex_unlock(&sc->mutex);
  1766. }
  1767. struct ieee80211_ops ath9k_ops = {
  1768. .tx = ath9k_tx,
  1769. .start = ath9k_start,
  1770. .stop = ath9k_stop,
  1771. .add_interface = ath9k_add_interface,
  1772. .remove_interface = ath9k_remove_interface,
  1773. .config = ath9k_config,
  1774. .configure_filter = ath9k_configure_filter,
  1775. .sta_add = ath9k_sta_add,
  1776. .sta_remove = ath9k_sta_remove,
  1777. .conf_tx = ath9k_conf_tx,
  1778. .bss_info_changed = ath9k_bss_info_changed,
  1779. .set_key = ath9k_set_key,
  1780. .get_tsf = ath9k_get_tsf,
  1781. .set_tsf = ath9k_set_tsf,
  1782. .reset_tsf = ath9k_reset_tsf,
  1783. .ampdu_action = ath9k_ampdu_action,
  1784. .sw_scan_start = ath9k_sw_scan_start,
  1785. .sw_scan_complete = ath9k_sw_scan_complete,
  1786. .rfkill_poll = ath9k_rfkill_poll_state,
  1787. .set_coverage_class = ath9k_set_coverage_class,
  1788. };