sdhci.h 4.9 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * PCI registers
  12. */
  13. #define PCI_SLOT_INFO 0x40 /* 8 bits */
  14. #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
  15. #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
  16. /*
  17. * Controller registers
  18. */
  19. #define SDHCI_DMA_ADDRESS 0x00
  20. #define SDHCI_BLOCK_SIZE 0x04
  21. #define SDHCI_BLOCK_COUNT 0x06
  22. #define SDHCI_ARGUMENT 0x08
  23. #define SDHCI_TRANSFER_MODE 0x0C
  24. #define SDHCI_TRNS_DMA 0x01
  25. #define SDHCI_TRNS_BLK_CNT_EN 0x02
  26. #define SDHCI_TRNS_ACMD12 0x04
  27. #define SDHCI_TRNS_READ 0x10
  28. #define SDHCI_TRNS_MULTI 0x20
  29. #define SDHCI_COMMAND 0x0E
  30. #define SDHCI_CMD_RESP_MASK 0x03
  31. #define SDHCI_CMD_CRC 0x08
  32. #define SDHCI_CMD_INDEX 0x10
  33. #define SDHCI_CMD_DATA 0x20
  34. #define SDHCI_CMD_RESP_NONE 0x00
  35. #define SDHCI_CMD_RESP_LONG 0x01
  36. #define SDHCI_CMD_RESP_SHORT 0x02
  37. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  38. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  39. #define SDHCI_RESPONSE 0x10
  40. #define SDHCI_BUFFER 0x20
  41. #define SDHCI_PRESENT_STATE 0x24
  42. #define SDHCI_CMD_INHIBIT 0x00000001
  43. #define SDHCI_DATA_INHIBIT 0x00000002
  44. #define SDHCI_DOING_WRITE 0x00000100
  45. #define SDHCI_DOING_READ 0x00000200
  46. #define SDHCI_SPACE_AVAILABLE 0x00000400
  47. #define SDHCI_DATA_AVAILABLE 0x00000800
  48. #define SDHCI_CARD_PRESENT 0x00010000
  49. #define SDHCI_WRITE_PROTECT 0x00080000
  50. #define SDHCI_HOST_CONTROL 0x28
  51. #define SDHCI_CTRL_LED 0x01
  52. #define SDHCI_CTRL_4BITBUS 0x02
  53. #define SDHCI_POWER_CONTROL 0x29
  54. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  55. #define SDHCI_WALK_UP_CONTROL 0x2B
  56. #define SDHCI_CLOCK_CONTROL 0x2C
  57. #define SDHCI_DIVIDER_SHIFT 8
  58. #define SDHCI_CLOCK_CARD_EN 0x0004
  59. #define SDHCI_CLOCK_INT_STABLE 0x0002
  60. #define SDHCI_CLOCK_INT_EN 0x0001
  61. #define SDHCI_TIMEOUT_CONTROL 0x2E
  62. #define SDHCI_SOFTWARE_RESET 0x2F
  63. #define SDHCI_RESET_ALL 0x01
  64. #define SDHCI_RESET_CMD 0x02
  65. #define SDHCI_RESET_DATA 0x04
  66. #define SDHCI_INT_STATUS 0x30
  67. #define SDHCI_INT_ENABLE 0x34
  68. #define SDHCI_SIGNAL_ENABLE 0x38
  69. #define SDHCI_INT_RESPONSE 0x00000001
  70. #define SDHCI_INT_DATA_END 0x00000002
  71. #define SDHCI_INT_DMA_END 0x00000008
  72. #define SDHCI_INT_BUF_EMPTY 0x00000010
  73. #define SDHCI_INT_BUF_FULL 0x00000020
  74. #define SDHCI_INT_CARD_INSERT 0x00000040
  75. #define SDHCI_INT_CARD_REMOVE 0x00000080
  76. #define SDHCI_INT_CARD_INT 0x00000100
  77. #define SDHCI_INT_TIMEOUT 0x00010000
  78. #define SDHCI_INT_CRC 0x00020000
  79. #define SDHCI_INT_END_BIT 0x00040000
  80. #define SDHCI_INT_INDEX 0x00080000
  81. #define SDHCI_INT_DATA_TIMEOUT 0x00100000
  82. #define SDHCI_INT_DATA_CRC 0x00200000
  83. #define SDHCI_INT_DATA_END_BIT 0x00400000
  84. #define SDHCI_INT_BUS_POWER 0x00800000
  85. #define SDHCI_INT_ACMD12ERR 0x01000000
  86. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  87. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  88. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
  89. SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
  90. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
  91. SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL | \
  92. SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
  93. SDHCI_INT_DATA_END_BIT)
  94. #define SDHCI_ACMD12_ERR 0x3C
  95. /* 3E-3F reserved */
  96. #define SDHCI_CAPABILITIES 0x40
  97. #define SDHCI_CAN_DO_DMA 0x00400000
  98. #define SDHCI_CLOCK_BASE_MASK 0x00003F00
  99. #define SDHCI_CLOCK_BASE_SHIFT 8
  100. /* 44-47 reserved for more caps */
  101. #define SDHCI_MAX_CURRENT 0x48
  102. /* 4C-4F reserved for more max current */
  103. /* 50-FB reserved */
  104. #define SDHCI_SLOT_INT_STATUS 0xFC
  105. #define SDHCI_HOST_VERSION 0xFE
  106. struct sdhci_chip;
  107. struct sdhci_host {
  108. struct sdhci_chip *chip;
  109. struct mmc_host *mmc; /* MMC structure */
  110. spinlock_t lock; /* Mutex */
  111. int flags; /* Host attributes */
  112. #define SDHCI_USE_DMA (1<<0)
  113. unsigned int max_clk; /* Max possible freq (MHz) */
  114. unsigned int clock; /* Current clock (MHz) */
  115. struct mmc_request *mrq; /* Current request */
  116. struct mmc_command *cmd; /* Current command */
  117. struct mmc_data *data; /* Current data request */
  118. struct scatterlist *cur_sg; /* We're working on this */
  119. char *mapped_sg; /* This is where it's mapped */
  120. int num_sg; /* Entries left */
  121. int offset; /* Offset into current sg */
  122. int remain; /* Bytes left in current */
  123. int size; /* Remaining bytes in transfer */
  124. char slot_descr[20]; /* Name for reservations */
  125. int irq; /* Device IRQ */
  126. int bar; /* PCI BAR index */
  127. unsigned long addr; /* Bus address */
  128. void __iomem * ioaddr; /* Mapped address */
  129. struct tasklet_struct card_tasklet; /* Tasklet structures */
  130. struct tasklet_struct finish_tasklet;
  131. struct timer_list timer; /* Timer for timeouts */
  132. };
  133. struct sdhci_chip {
  134. struct pci_dev *pdev;
  135. int num_slots; /* Slots on controller */
  136. struct sdhci_host *hosts[0]; /* Pointers to hosts */
  137. };