ucb1400_ts.c 15 KB

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  1. /*
  2. * Philips UCB1400 touchscreen driver
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: September 25, 2006
  6. * Copyright: MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
  13. * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has
  14. * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/completion.h>
  19. #include <linux/delay.h>
  20. #include <linux/input.h>
  21. #include <linux/device.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/suspend.h>
  24. #include <linux/slab.h>
  25. #include <linux/kthread.h>
  26. #include <linux/freezer.h>
  27. #include <sound/driver.h>
  28. #include <sound/core.h>
  29. #include <sound/ac97_codec.h>
  30. /*
  31. * Interesting UCB1400 AC-link registers
  32. */
  33. #define UCB_IE_RIS 0x5e
  34. #define UCB_IE_FAL 0x60
  35. #define UCB_IE_STATUS 0x62
  36. #define UCB_IE_CLEAR 0x62
  37. #define UCB_IE_ADC (1 << 11)
  38. #define UCB_IE_TSPX (1 << 12)
  39. #define UCB_TS_CR 0x64
  40. #define UCB_TS_CR_TSMX_POW (1 << 0)
  41. #define UCB_TS_CR_TSPX_POW (1 << 1)
  42. #define UCB_TS_CR_TSMY_POW (1 << 2)
  43. #define UCB_TS_CR_TSPY_POW (1 << 3)
  44. #define UCB_TS_CR_TSMX_GND (1 << 4)
  45. #define UCB_TS_CR_TSPX_GND (1 << 5)
  46. #define UCB_TS_CR_TSMY_GND (1 << 6)
  47. #define UCB_TS_CR_TSPY_GND (1 << 7)
  48. #define UCB_TS_CR_MODE_INT (0 << 8)
  49. #define UCB_TS_CR_MODE_PRES (1 << 8)
  50. #define UCB_TS_CR_MODE_POS (2 << 8)
  51. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  52. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  53. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  54. #define UCB_ADC_CR 0x66
  55. #define UCB_ADC_SYNC_ENA (1 << 0)
  56. #define UCB_ADC_VREFBYP_CON (1 << 1)
  57. #define UCB_ADC_INP_TSPX (0 << 2)
  58. #define UCB_ADC_INP_TSMX (1 << 2)
  59. #define UCB_ADC_INP_TSPY (2 << 2)
  60. #define UCB_ADC_INP_TSMY (3 << 2)
  61. #define UCB_ADC_INP_AD0 (4 << 2)
  62. #define UCB_ADC_INP_AD1 (5 << 2)
  63. #define UCB_ADC_INP_AD2 (6 << 2)
  64. #define UCB_ADC_INP_AD3 (7 << 2)
  65. #define UCB_ADC_EXT_REF (1 << 5)
  66. #define UCB_ADC_START (1 << 7)
  67. #define UCB_ADC_ENA (1 << 15)
  68. #define UCB_ADC_DATA 0x68
  69. #define UCB_ADC_DAT_VALID (1 << 15)
  70. #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff)
  71. #define UCB_ID 0x7e
  72. #define UCB_ID_1400 0x4304
  73. struct ucb1400 {
  74. struct snd_ac97 *ac97;
  75. struct input_dev *ts_idev;
  76. int irq;
  77. wait_queue_head_t ts_wait;
  78. struct task_struct *ts_task;
  79. unsigned int irq_pending; /* not bit field shared */
  80. unsigned int ts_restart:1;
  81. unsigned int adcsync:1;
  82. };
  83. static int adcsync;
  84. static int ts_delay = 55; /* us */
  85. static int ts_delay_pressure; /* us */
  86. static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg)
  87. {
  88. return ucb->ac97->bus->ops->read(ucb->ac97, reg);
  89. }
  90. static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val)
  91. {
  92. ucb->ac97->bus->ops->write(ucb->ac97, reg, val);
  93. }
  94. static inline void ucb1400_adc_enable(struct ucb1400 *ucb)
  95. {
  96. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  97. }
  98. static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel)
  99. {
  100. unsigned int val;
  101. if (ucb->adcsync)
  102. adc_channel |= UCB_ADC_SYNC_ENA;
  103. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
  104. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START);
  105. for (;;) {
  106. val = ucb1400_reg_read(ucb, UCB_ADC_DATA);
  107. if (val & UCB_ADC_DAT_VALID)
  108. break;
  109. /* yield to other processes */
  110. schedule_timeout_uninterruptible(1);
  111. }
  112. return UCB_ADC_DAT_VALUE(val);
  113. }
  114. static inline void ucb1400_adc_disable(struct ucb1400 *ucb)
  115. {
  116. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  117. }
  118. /* Switch to interrupt mode. */
  119. static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb)
  120. {
  121. ucb1400_reg_write(ucb, UCB_TS_CR,
  122. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  123. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  124. UCB_TS_CR_MODE_INT);
  125. }
  126. /*
  127. * Switch to pressure mode, and read pressure. We don't need to wait
  128. * here, since both plates are being driven.
  129. */
  130. static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb)
  131. {
  132. ucb1400_reg_write(ucb, UCB_TS_CR,
  133. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  134. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  135. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  136. udelay(ts_delay_pressure);
  137. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  138. }
  139. /*
  140. * Switch to X position mode and measure Y plate. We switch the plate
  141. * configuration in pressure mode, then switch to position mode. This
  142. * gives a faster response time. Even so, we need to wait about 55us
  143. * for things to stabilise.
  144. */
  145. static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb)
  146. {
  147. ucb1400_reg_write(ucb, UCB_TS_CR,
  148. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  149. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  150. ucb1400_reg_write(ucb, UCB_TS_CR,
  151. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  152. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  153. ucb1400_reg_write(ucb, UCB_TS_CR,
  154. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  155. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  156. udelay(ts_delay);
  157. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  158. }
  159. /*
  160. * Switch to Y position mode and measure X plate. We switch the plate
  161. * configuration in pressure mode, then switch to position mode. This
  162. * gives a faster response time. Even so, we need to wait about 55us
  163. * for things to stabilise.
  164. */
  165. static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb)
  166. {
  167. ucb1400_reg_write(ucb, UCB_TS_CR,
  168. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  169. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  170. ucb1400_reg_write(ucb, UCB_TS_CR,
  171. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  172. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  173. ucb1400_reg_write(ucb, UCB_TS_CR,
  174. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  175. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  176. udelay(ts_delay);
  177. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX);
  178. }
  179. /*
  180. * Switch to X plate resistance mode. Set MX to ground, PX to
  181. * supply. Measure current.
  182. */
  183. static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb)
  184. {
  185. ucb1400_reg_write(ucb, UCB_TS_CR,
  186. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  187. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  188. return ucb1400_adc_read(ucb, 0);
  189. }
  190. /*
  191. * Switch to Y plate resistance mode. Set MY to ground, PY to
  192. * supply. Measure current.
  193. */
  194. static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb)
  195. {
  196. ucb1400_reg_write(ucb, UCB_TS_CR,
  197. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  198. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  199. return ucb1400_adc_read(ucb, 0);
  200. }
  201. static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb)
  202. {
  203. unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR);
  204. return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
  205. }
  206. static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb)
  207. {
  208. ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX);
  209. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  210. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX);
  211. }
  212. static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb)
  213. {
  214. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  215. }
  216. static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y)
  217. {
  218. input_report_abs(idev, ABS_X, x);
  219. input_report_abs(idev, ABS_Y, y);
  220. input_report_abs(idev, ABS_PRESSURE, pressure);
  221. input_sync(idev);
  222. }
  223. static void ucb1400_ts_event_release(struct input_dev *idev)
  224. {
  225. input_report_abs(idev, ABS_PRESSURE, 0);
  226. input_sync(idev);
  227. }
  228. static void ucb1400_handle_pending_irq(struct ucb1400 *ucb)
  229. {
  230. unsigned int isr;
  231. isr = ucb1400_reg_read(ucb, UCB_IE_STATUS);
  232. ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr);
  233. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  234. if (isr & UCB_IE_TSPX)
  235. ucb1400_ts_irq_disable(ucb);
  236. else
  237. printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr);
  238. enable_irq(ucb->irq);
  239. }
  240. static int ucb1400_ts_thread(void *_ucb)
  241. {
  242. struct ucb1400 *ucb = _ucb;
  243. struct task_struct *tsk = current;
  244. int valid = 0;
  245. struct sched_param param = { .sched_priority = 1 };
  246. sched_setscheduler(tsk, SCHED_FIFO, &param);
  247. set_freezable();
  248. while (!kthread_should_stop()) {
  249. unsigned int x, y, p;
  250. long timeout;
  251. ucb->ts_restart = 0;
  252. if (ucb->irq_pending) {
  253. ucb->irq_pending = 0;
  254. ucb1400_handle_pending_irq(ucb);
  255. }
  256. ucb1400_adc_enable(ucb);
  257. x = ucb1400_ts_read_xpos(ucb);
  258. y = ucb1400_ts_read_ypos(ucb);
  259. p = ucb1400_ts_read_pressure(ucb);
  260. ucb1400_adc_disable(ucb);
  261. /* Switch back to interrupt mode. */
  262. ucb1400_ts_mode_int(ucb);
  263. msleep(10);
  264. if (ucb1400_ts_pen_down(ucb)) {
  265. ucb1400_ts_irq_enable(ucb);
  266. /*
  267. * If we spat out a valid sample set last time,
  268. * spit out a "pen off" sample here.
  269. */
  270. if (valid) {
  271. ucb1400_ts_event_release(ucb->ts_idev);
  272. valid = 0;
  273. }
  274. timeout = MAX_SCHEDULE_TIMEOUT;
  275. } else {
  276. valid = 1;
  277. ucb1400_ts_evt_add(ucb->ts_idev, p, x, y);
  278. timeout = msecs_to_jiffies(10);
  279. }
  280. wait_event_freezable_timeout(ucb->ts_wait,
  281. ucb->irq_pending || ucb->ts_restart || kthread_should_stop(),
  282. timeout);
  283. }
  284. /* Send the "pen off" if we are stopping with the pen still active */
  285. if (valid)
  286. ucb1400_ts_event_release(ucb->ts_idev);
  287. ucb->ts_task = NULL;
  288. return 0;
  289. }
  290. /*
  291. * A restriction with interrupts exists when using the ucb1400, as
  292. * the codec read/write routines may sleep while waiting for codec
  293. * access completion and uses semaphores for access control to the
  294. * AC97 bus. A complete codec read cycle could take anywhere from
  295. * 60 to 100uSec so we *definitely* don't want to spin inside the
  296. * interrupt handler waiting for codec access. So, we handle the
  297. * interrupt by scheduling a RT kernel thread to run in process
  298. * context instead of interrupt context.
  299. */
  300. static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid)
  301. {
  302. struct ucb1400 *ucb = devid;
  303. if (irqnr == ucb->irq) {
  304. disable_irq(ucb->irq);
  305. ucb->irq_pending = 1;
  306. wake_up(&ucb->ts_wait);
  307. return IRQ_HANDLED;
  308. }
  309. return IRQ_NONE;
  310. }
  311. static int ucb1400_ts_open(struct input_dev *idev)
  312. {
  313. struct ucb1400 *ucb = input_get_drvdata(idev);
  314. int ret = 0;
  315. BUG_ON(ucb->ts_task);
  316. ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts");
  317. if (IS_ERR(ucb->ts_task)) {
  318. ret = PTR_ERR(ucb->ts_task);
  319. ucb->ts_task = NULL;
  320. }
  321. return ret;
  322. }
  323. static void ucb1400_ts_close(struct input_dev *idev)
  324. {
  325. struct ucb1400 *ucb = input_get_drvdata(idev);
  326. if (ucb->ts_task)
  327. kthread_stop(ucb->ts_task);
  328. ucb1400_ts_irq_disable(ucb);
  329. ucb1400_reg_write(ucb, UCB_TS_CR, 0);
  330. }
  331. #ifdef CONFIG_PM
  332. static int ucb1400_ts_resume(struct device *dev)
  333. {
  334. struct ucb1400 *ucb = dev_get_drvdata(dev);
  335. if (ucb->ts_task) {
  336. /*
  337. * Restart the TS thread to ensure the
  338. * TS interrupt mode is set up again
  339. * after sleep.
  340. */
  341. ucb->ts_restart = 1;
  342. wake_up(&ucb->ts_wait);
  343. }
  344. return 0;
  345. }
  346. #else
  347. #define ucb1400_ts_resume NULL
  348. #endif
  349. #ifndef NO_IRQ
  350. #define NO_IRQ 0
  351. #endif
  352. /*
  353. * Try to probe our interrupt, rather than relying on lots of
  354. * hard-coded machine dependencies.
  355. */
  356. static int ucb1400_detect_irq(struct ucb1400 *ucb)
  357. {
  358. unsigned long mask, timeout;
  359. mask = probe_irq_on();
  360. if (!mask) {
  361. probe_irq_off(mask);
  362. return -EBUSY;
  363. }
  364. /* Enable the ADC interrupt. */
  365. ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  366. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  367. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  368. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  369. /* Cause an ADC interrupt. */
  370. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  371. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  372. /* Wait for the conversion to complete. */
  373. timeout = jiffies + HZ/2;
  374. while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) {
  375. cpu_relax();
  376. if (time_after(jiffies, timeout)) {
  377. printk(KERN_ERR "ucb1400: timed out in IRQ probe\n");
  378. probe_irq_off(mask);
  379. return -ENODEV;
  380. }
  381. }
  382. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  383. /* Disable and clear interrupt. */
  384. ucb1400_reg_write(ucb, UCB_IE_RIS, 0);
  385. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  386. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  387. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  388. /* Read triggered interrupt. */
  389. ucb->irq = probe_irq_off(mask);
  390. if (ucb->irq < 0 || ucb->irq == NO_IRQ)
  391. return -ENODEV;
  392. return 0;
  393. }
  394. static int ucb1400_ts_probe(struct device *dev)
  395. {
  396. struct ucb1400 *ucb;
  397. struct input_dev *idev;
  398. int error, id, x_res, y_res;
  399. ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL);
  400. idev = input_allocate_device();
  401. if (!ucb || !idev) {
  402. error = -ENOMEM;
  403. goto err_free_devs;
  404. }
  405. ucb->ts_idev = idev;
  406. ucb->adcsync = adcsync;
  407. ucb->ac97 = to_ac97_t(dev);
  408. init_waitqueue_head(&ucb->ts_wait);
  409. id = ucb1400_reg_read(ucb, UCB_ID);
  410. if (id != UCB_ID_1400) {
  411. error = -ENODEV;
  412. goto err_free_devs;
  413. }
  414. error = ucb1400_detect_irq(ucb);
  415. if (error) {
  416. printk(KERN_ERR "UCB1400: IRQ probe failed\n");
  417. goto err_free_devs;
  418. }
  419. error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING,
  420. "UCB1400", ucb);
  421. if (error) {
  422. printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n",
  423. ucb->irq, error);
  424. goto err_free_devs;
  425. }
  426. printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq);
  427. input_set_drvdata(idev, ucb);
  428. idev->dev.parent = dev;
  429. idev->name = "UCB1400 touchscreen interface";
  430. idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1);
  431. idev->id.product = id;
  432. idev->open = ucb1400_ts_open;
  433. idev->close = ucb1400_ts_close;
  434. idev->evbit[0] = BIT_MASK(EV_ABS);
  435. ucb1400_adc_enable(ucb);
  436. x_res = ucb1400_ts_read_xres(ucb);
  437. y_res = ucb1400_ts_read_yres(ucb);
  438. ucb1400_adc_disable(ucb);
  439. printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res);
  440. input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0);
  441. input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0);
  442. input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
  443. error = input_register_device(idev);
  444. if (error)
  445. goto err_free_irq;
  446. dev_set_drvdata(dev, ucb);
  447. return 0;
  448. err_free_irq:
  449. free_irq(ucb->irq, ucb);
  450. err_free_devs:
  451. input_free_device(idev);
  452. kfree(ucb);
  453. return error;
  454. }
  455. static int ucb1400_ts_remove(struct device *dev)
  456. {
  457. struct ucb1400 *ucb = dev_get_drvdata(dev);
  458. free_irq(ucb->irq, ucb);
  459. input_unregister_device(ucb->ts_idev);
  460. dev_set_drvdata(dev, NULL);
  461. kfree(ucb);
  462. return 0;
  463. }
  464. static struct device_driver ucb1400_ts_driver = {
  465. .name = "ucb1400_ts",
  466. .owner = THIS_MODULE,
  467. .bus = &ac97_bus_type,
  468. .probe = ucb1400_ts_probe,
  469. .remove = ucb1400_ts_remove,
  470. .resume = ucb1400_ts_resume,
  471. };
  472. static int __init ucb1400_ts_init(void)
  473. {
  474. return driver_register(&ucb1400_ts_driver);
  475. }
  476. static void __exit ucb1400_ts_exit(void)
  477. {
  478. driver_unregister(&ucb1400_ts_driver);
  479. }
  480. module_param(adcsync, bool, 0444);
  481. MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
  482. module_param(ts_delay, int, 0444);
  483. MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us.");
  484. module_param(ts_delay_pressure, int, 0444);
  485. MODULE_PARM_DESC(ts_delay_pressure,
  486. "delay between panel setup and pressure read. Default = 0us.");
  487. module_init(ucb1400_ts_init);
  488. module_exit(ucb1400_ts_exit);
  489. MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
  490. MODULE_LICENSE("GPL");