i8042.c 28 KB

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  1. /*
  2. * i8042 keyboard and mouse controller driver for Linux
  3. *
  4. * Copyright (c) 1999-2004 Vojtech Pavlik
  5. */
  6. /*
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/init.h>
  16. #include <linux/serio.h>
  17. #include <linux/err.h>
  18. #include <linux/rcupdate.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/i8042.h>
  21. #include <asm/io.h>
  22. MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
  23. MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int i8042_nokbd;
  26. module_param_named(nokbd, i8042_nokbd, bool, 0);
  27. MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
  28. static unsigned int i8042_noaux;
  29. module_param_named(noaux, i8042_noaux, bool, 0);
  30. MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
  31. static unsigned int i8042_nomux;
  32. module_param_named(nomux, i8042_nomux, bool, 0);
  33. MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
  34. static unsigned int i8042_unlock;
  35. module_param_named(unlock, i8042_unlock, bool, 0);
  36. MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
  37. static unsigned int i8042_reset;
  38. module_param_named(reset, i8042_reset, bool, 0);
  39. MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
  40. static unsigned int i8042_direct;
  41. module_param_named(direct, i8042_direct, bool, 0);
  42. MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
  43. static unsigned int i8042_dumbkbd;
  44. module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
  45. MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
  46. static unsigned int i8042_noloop;
  47. module_param_named(noloop, i8042_noloop, bool, 0);
  48. MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
  49. static unsigned int i8042_blink_frequency = 500;
  50. module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
  51. MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
  52. #ifdef CONFIG_PNP
  53. static int i8042_nopnp;
  54. module_param_named(nopnp, i8042_nopnp, bool, 0);
  55. MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
  56. #endif
  57. #define DEBUG
  58. #ifdef DEBUG
  59. static int i8042_debug;
  60. module_param_named(debug, i8042_debug, bool, 0600);
  61. MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
  62. #endif
  63. #include "i8042.h"
  64. static DEFINE_SPINLOCK(i8042_lock);
  65. struct i8042_port {
  66. struct serio *serio;
  67. int irq;
  68. unsigned char exists;
  69. signed char mux;
  70. };
  71. #define I8042_KBD_PORT_NO 0
  72. #define I8042_AUX_PORT_NO 1
  73. #define I8042_MUX_PORT_NO 2
  74. #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
  75. static struct i8042_port i8042_ports[I8042_NUM_PORTS];
  76. static unsigned char i8042_initial_ctr;
  77. static unsigned char i8042_ctr;
  78. static unsigned char i8042_mux_present;
  79. static unsigned char i8042_kbd_irq_registered;
  80. static unsigned char i8042_aux_irq_registered;
  81. static unsigned char i8042_suppress_kbd_ack;
  82. static struct platform_device *i8042_platform_device;
  83. static irqreturn_t i8042_interrupt(int irq, void *dev_id);
  84. /*
  85. * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
  86. * be ready for reading values from it / writing values to it.
  87. * Called always with i8042_lock held.
  88. */
  89. static int i8042_wait_read(void)
  90. {
  91. int i = 0;
  92. while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
  93. udelay(50);
  94. i++;
  95. }
  96. return -(i == I8042_CTL_TIMEOUT);
  97. }
  98. static int i8042_wait_write(void)
  99. {
  100. int i = 0;
  101. while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
  102. udelay(50);
  103. i++;
  104. }
  105. return -(i == I8042_CTL_TIMEOUT);
  106. }
  107. /*
  108. * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
  109. * of the i8042 down the toilet.
  110. */
  111. static int i8042_flush(void)
  112. {
  113. unsigned long flags;
  114. unsigned char data, str;
  115. int i = 0;
  116. spin_lock_irqsave(&i8042_lock, flags);
  117. while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
  118. udelay(50);
  119. data = i8042_read_data();
  120. i++;
  121. dbg("%02x <- i8042 (flush, %s)", data,
  122. str & I8042_STR_AUXDATA ? "aux" : "kbd");
  123. }
  124. spin_unlock_irqrestore(&i8042_lock, flags);
  125. return i;
  126. }
  127. /*
  128. * i8042_command() executes a command on the i8042. It also sends the input
  129. * parameter(s) of the commands to it, and receives the output value(s). The
  130. * parameters are to be stored in the param array, and the output is placed
  131. * into the same array. The number of the parameters and output values is
  132. * encoded in bits 8-11 of the command number.
  133. */
  134. static int __i8042_command(unsigned char *param, int command)
  135. {
  136. int i, error;
  137. if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
  138. return -1;
  139. error = i8042_wait_write();
  140. if (error)
  141. return error;
  142. dbg("%02x -> i8042 (command)", command & 0xff);
  143. i8042_write_command(command & 0xff);
  144. for (i = 0; i < ((command >> 12) & 0xf); i++) {
  145. error = i8042_wait_write();
  146. if (error)
  147. return error;
  148. dbg("%02x -> i8042 (parameter)", param[i]);
  149. i8042_write_data(param[i]);
  150. }
  151. for (i = 0; i < ((command >> 8) & 0xf); i++) {
  152. error = i8042_wait_read();
  153. if (error) {
  154. dbg(" -- i8042 (timeout)");
  155. return error;
  156. }
  157. if (command == I8042_CMD_AUX_LOOP &&
  158. !(i8042_read_status() & I8042_STR_AUXDATA)) {
  159. dbg(" -- i8042 (auxerr)");
  160. return -1;
  161. }
  162. param[i] = i8042_read_data();
  163. dbg("%02x <- i8042 (return)", param[i]);
  164. }
  165. return 0;
  166. }
  167. int i8042_command(unsigned char *param, int command)
  168. {
  169. unsigned long flags;
  170. int retval;
  171. spin_lock_irqsave(&i8042_lock, flags);
  172. retval = __i8042_command(param, command);
  173. spin_unlock_irqrestore(&i8042_lock, flags);
  174. return retval;
  175. }
  176. EXPORT_SYMBOL(i8042_command);
  177. /*
  178. * i8042_kbd_write() sends a byte out through the keyboard interface.
  179. */
  180. static int i8042_kbd_write(struct serio *port, unsigned char c)
  181. {
  182. unsigned long flags;
  183. int retval = 0;
  184. spin_lock_irqsave(&i8042_lock, flags);
  185. if (!(retval = i8042_wait_write())) {
  186. dbg("%02x -> i8042 (kbd-data)", c);
  187. i8042_write_data(c);
  188. }
  189. spin_unlock_irqrestore(&i8042_lock, flags);
  190. return retval;
  191. }
  192. /*
  193. * i8042_aux_write() sends a byte out through the aux interface.
  194. */
  195. static int i8042_aux_write(struct serio *serio, unsigned char c)
  196. {
  197. struct i8042_port *port = serio->port_data;
  198. return i8042_command(&c, port->mux == -1 ?
  199. I8042_CMD_AUX_SEND :
  200. I8042_CMD_MUX_SEND + port->mux);
  201. }
  202. /*
  203. * i8042_start() is called by serio core when port is about to finish
  204. * registering. It will mark port as existing so i8042_interrupt can
  205. * start sending data through it.
  206. */
  207. static int i8042_start(struct serio *serio)
  208. {
  209. struct i8042_port *port = serio->port_data;
  210. port->exists = 1;
  211. mb();
  212. return 0;
  213. }
  214. /*
  215. * i8042_stop() marks serio port as non-existing so i8042_interrupt
  216. * will not try to send data to the port that is about to go away.
  217. * The function is called by serio core as part of unregister procedure.
  218. */
  219. static void i8042_stop(struct serio *serio)
  220. {
  221. struct i8042_port *port = serio->port_data;
  222. port->exists = 0;
  223. /*
  224. * We synchronize with both AUX and KBD IRQs because there is
  225. * a (very unlikely) chance that AUX IRQ is raised for KBD port
  226. * and vice versa.
  227. */
  228. synchronize_irq(I8042_AUX_IRQ);
  229. synchronize_irq(I8042_KBD_IRQ);
  230. port->serio = NULL;
  231. }
  232. /*
  233. * i8042_interrupt() is the most important function in this driver -
  234. * it handles the interrupts from the i8042, and sends incoming bytes
  235. * to the upper layers.
  236. */
  237. static irqreturn_t i8042_interrupt(int irq, void *dev_id)
  238. {
  239. struct i8042_port *port;
  240. unsigned long flags;
  241. unsigned char str, data;
  242. unsigned int dfl;
  243. unsigned int port_no;
  244. int ret = 1;
  245. spin_lock_irqsave(&i8042_lock, flags);
  246. str = i8042_read_status();
  247. if (unlikely(~str & I8042_STR_OBF)) {
  248. spin_unlock_irqrestore(&i8042_lock, flags);
  249. if (irq) dbg("Interrupt %d, without any data", irq);
  250. ret = 0;
  251. goto out;
  252. }
  253. data = i8042_read_data();
  254. spin_unlock_irqrestore(&i8042_lock, flags);
  255. if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
  256. static unsigned long last_transmit;
  257. static unsigned char last_str;
  258. dfl = 0;
  259. if (str & I8042_STR_MUXERR) {
  260. dbg("MUX error, status is %02x, data is %02x", str, data);
  261. /*
  262. * When MUXERR condition is signalled the data register can only contain
  263. * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
  264. * it is not always the case. Some KBCs also report 0xfc when there is
  265. * nothing connected to the port while others sometimes get confused which
  266. * port the data came from and signal error leaving the data intact. They
  267. * _do not_ revert to legacy mode (actually I've never seen KBC reverting
  268. * to legacy mode yet, when we see one we'll add proper handling).
  269. * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
  270. * rest assume that the data came from the same serio last byte
  271. * was transmitted (if transmission happened not too long ago).
  272. */
  273. switch (data) {
  274. default:
  275. if (time_before(jiffies, last_transmit + HZ/10)) {
  276. str = last_str;
  277. break;
  278. }
  279. /* fall through - report timeout */
  280. case 0xfc:
  281. case 0xfd:
  282. case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
  283. case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
  284. }
  285. }
  286. port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
  287. last_str = str;
  288. last_transmit = jiffies;
  289. } else {
  290. dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
  291. ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
  292. port_no = (str & I8042_STR_AUXDATA) ?
  293. I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
  294. }
  295. port = &i8042_ports[port_no];
  296. dbg("%02x <- i8042 (interrupt, %d, %d%s%s)",
  297. data, port_no, irq,
  298. dfl & SERIO_PARITY ? ", bad parity" : "",
  299. dfl & SERIO_TIMEOUT ? ", timeout" : "");
  300. if (unlikely(i8042_suppress_kbd_ack))
  301. if (port_no == I8042_KBD_PORT_NO &&
  302. (data == 0xfa || data == 0xfe)) {
  303. i8042_suppress_kbd_ack--;
  304. goto out;
  305. }
  306. if (likely(port->exists))
  307. serio_interrupt(port->serio, data, dfl);
  308. out:
  309. return IRQ_RETVAL(ret);
  310. }
  311. /*
  312. * i8042_enable_kbd_port enables keybaord port on chip
  313. */
  314. static int i8042_enable_kbd_port(void)
  315. {
  316. i8042_ctr &= ~I8042_CTR_KBDDIS;
  317. i8042_ctr |= I8042_CTR_KBDINT;
  318. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  319. i8042_ctr &= ~I8042_CTR_KBDINT;
  320. i8042_ctr |= I8042_CTR_KBDDIS;
  321. printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n");
  322. return -EIO;
  323. }
  324. return 0;
  325. }
  326. /*
  327. * i8042_enable_aux_port enables AUX (mouse) port on chip
  328. */
  329. static int i8042_enable_aux_port(void)
  330. {
  331. i8042_ctr &= ~I8042_CTR_AUXDIS;
  332. i8042_ctr |= I8042_CTR_AUXINT;
  333. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  334. i8042_ctr &= ~I8042_CTR_AUXINT;
  335. i8042_ctr |= I8042_CTR_AUXDIS;
  336. printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n");
  337. return -EIO;
  338. }
  339. return 0;
  340. }
  341. /*
  342. * i8042_enable_mux_ports enables 4 individual AUX ports after
  343. * the controller has been switched into Multiplexed mode
  344. */
  345. static int i8042_enable_mux_ports(void)
  346. {
  347. unsigned char param;
  348. int i;
  349. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  350. i8042_command(&param, I8042_CMD_MUX_PFX + i);
  351. i8042_command(&param, I8042_CMD_AUX_ENABLE);
  352. }
  353. return i8042_enable_aux_port();
  354. }
  355. /*
  356. * i8042_set_mux_mode checks whether the controller has an active
  357. * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode.
  358. */
  359. static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
  360. {
  361. unsigned char param;
  362. /*
  363. * Get rid of bytes in the queue.
  364. */
  365. i8042_flush();
  366. /*
  367. * Internal loopback test - send three bytes, they should come back from the
  368. * mouse interface, the last should be version.
  369. */
  370. param = 0xf0;
  371. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xf0)
  372. return -1;
  373. param = mode ? 0x56 : 0xf6;
  374. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6))
  375. return -1;
  376. param = mode ? 0xa4 : 0xa5;
  377. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5))
  378. return -1;
  379. if (mux_version)
  380. *mux_version = param;
  381. return 0;
  382. }
  383. /*
  384. * i8042_check_mux() checks whether the controller supports the PS/2 Active
  385. * Multiplexing specification by Synaptics, Phoenix, Insyde and
  386. * LCS/Telegraphics.
  387. */
  388. static int __devinit i8042_check_mux(void)
  389. {
  390. unsigned char mux_version;
  391. if (i8042_set_mux_mode(1, &mux_version))
  392. return -1;
  393. /*
  394. * Workaround for interference with USB Legacy emulation
  395. * that causes a v10.12 MUX to be found.
  396. */
  397. if (mux_version == 0xAC)
  398. return -1;
  399. printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
  400. (mux_version >> 4) & 0xf, mux_version & 0xf);
  401. /*
  402. * Disable all muxed ports by disabling AUX.
  403. */
  404. i8042_ctr |= I8042_CTR_AUXDIS;
  405. i8042_ctr &= ~I8042_CTR_AUXINT;
  406. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  407. printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
  408. return -EIO;
  409. }
  410. i8042_mux_present = 1;
  411. return 0;
  412. }
  413. /*
  414. * The following is used to test AUX IRQ delivery.
  415. */
  416. static struct completion i8042_aux_irq_delivered __devinitdata;
  417. static int i8042_irq_being_tested __devinitdata;
  418. static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id)
  419. {
  420. unsigned long flags;
  421. unsigned char str, data;
  422. int ret = 0;
  423. spin_lock_irqsave(&i8042_lock, flags);
  424. str = i8042_read_status();
  425. if (str & I8042_STR_OBF) {
  426. data = i8042_read_data();
  427. if (i8042_irq_being_tested &&
  428. data == 0xa5 && (str & I8042_STR_AUXDATA))
  429. complete(&i8042_aux_irq_delivered);
  430. ret = 1;
  431. }
  432. spin_unlock_irqrestore(&i8042_lock, flags);
  433. return IRQ_RETVAL(ret);
  434. }
  435. /*
  436. * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
  437. * verifies success by readinng CTR. Used when testing for presence of AUX
  438. * port.
  439. */
  440. static int __devinit i8042_toggle_aux(int on)
  441. {
  442. unsigned char param;
  443. int i;
  444. if (i8042_command(&param,
  445. on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
  446. return -1;
  447. /* some chips need some time to set the I8042_CTR_AUXDIS bit */
  448. for (i = 0; i < 100; i++) {
  449. udelay(50);
  450. if (i8042_command(&param, I8042_CMD_CTL_RCTR))
  451. return -1;
  452. if (!(param & I8042_CTR_AUXDIS) == on)
  453. return 0;
  454. }
  455. return -1;
  456. }
  457. /*
  458. * i8042_check_aux() applies as much paranoia as it can at detecting
  459. * the presence of an AUX interface.
  460. */
  461. static int __devinit i8042_check_aux(void)
  462. {
  463. int retval = -1;
  464. int irq_registered = 0;
  465. int aux_loop_broken = 0;
  466. unsigned long flags;
  467. unsigned char param;
  468. /*
  469. * Get rid of bytes in the queue.
  470. */
  471. i8042_flush();
  472. /*
  473. * Internal loopback test - filters out AT-type i8042's. Unfortunately
  474. * SiS screwed up and their 5597 doesn't support the LOOP command even
  475. * though it has an AUX port.
  476. */
  477. param = 0x5a;
  478. retval = i8042_command(&param, I8042_CMD_AUX_LOOP);
  479. if (retval || param != 0x5a) {
  480. /*
  481. * External connection test - filters out AT-soldered PS/2 i8042's
  482. * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
  483. * 0xfa - no error on some notebooks which ignore the spec
  484. * Because it's common for chipsets to return error on perfectly functioning
  485. * AUX ports, we test for this only when the LOOP command failed.
  486. */
  487. if (i8042_command(&param, I8042_CMD_AUX_TEST) ||
  488. (param && param != 0xfa && param != 0xff))
  489. return -1;
  490. /*
  491. * If AUX_LOOP completed without error but returned unexpected data
  492. * mark it as broken
  493. */
  494. if (!retval)
  495. aux_loop_broken = 1;
  496. }
  497. /*
  498. * Bit assignment test - filters out PS/2 i8042's in AT mode
  499. */
  500. if (i8042_toggle_aux(0)) {
  501. printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
  502. printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
  503. }
  504. if (i8042_toggle_aux(1))
  505. return -1;
  506. /*
  507. * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
  508. * used it for a PCI card or somethig else.
  509. */
  510. if (i8042_noloop || aux_loop_broken) {
  511. /*
  512. * Without LOOP command we can't test AUX IRQ delivery. Assume the port
  513. * is working and hope we are right.
  514. */
  515. retval = 0;
  516. goto out;
  517. }
  518. if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
  519. "i8042", i8042_platform_device))
  520. goto out;
  521. irq_registered = 1;
  522. if (i8042_enable_aux_port())
  523. goto out;
  524. spin_lock_irqsave(&i8042_lock, flags);
  525. init_completion(&i8042_aux_irq_delivered);
  526. i8042_irq_being_tested = 1;
  527. param = 0xa5;
  528. retval = __i8042_command(&param, I8042_CMD_AUX_LOOP & 0xf0ff);
  529. spin_unlock_irqrestore(&i8042_lock, flags);
  530. if (retval)
  531. goto out;
  532. if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
  533. msecs_to_jiffies(250)) == 0) {
  534. /*
  535. * AUX IRQ was never delivered so we need to flush the controller to
  536. * get rid of the byte we put there; otherwise keyboard may not work.
  537. */
  538. i8042_flush();
  539. retval = -1;
  540. }
  541. out:
  542. /*
  543. * Disable the interface.
  544. */
  545. i8042_ctr |= I8042_CTR_AUXDIS;
  546. i8042_ctr &= ~I8042_CTR_AUXINT;
  547. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  548. retval = -1;
  549. if (irq_registered)
  550. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  551. return retval;
  552. }
  553. static int i8042_controller_check(void)
  554. {
  555. if (i8042_flush() == I8042_BUFFER_SIZE) {
  556. printk(KERN_ERR "i8042.c: No controller found.\n");
  557. return -ENODEV;
  558. }
  559. return 0;
  560. }
  561. static int i8042_controller_selftest(void)
  562. {
  563. unsigned char param;
  564. if (!i8042_reset)
  565. return 0;
  566. if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
  567. printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
  568. return -ENODEV;
  569. }
  570. if (param != I8042_RET_CTL_TEST) {
  571. printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
  572. param, I8042_RET_CTL_TEST);
  573. return -EIO;
  574. }
  575. return 0;
  576. }
  577. /*
  578. * i8042_controller init initializes the i8042 controller, and,
  579. * most importantly, sets it into non-xlated mode if that's
  580. * desired.
  581. */
  582. static int i8042_controller_init(void)
  583. {
  584. unsigned long flags;
  585. /*
  586. * Save the CTR for restoral on unload / reboot.
  587. */
  588. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
  589. printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
  590. return -EIO;
  591. }
  592. i8042_initial_ctr = i8042_ctr;
  593. /*
  594. * Disable the keyboard interface and interrupt.
  595. */
  596. i8042_ctr |= I8042_CTR_KBDDIS;
  597. i8042_ctr &= ~I8042_CTR_KBDINT;
  598. /*
  599. * Handle keylock.
  600. */
  601. spin_lock_irqsave(&i8042_lock, flags);
  602. if (~i8042_read_status() & I8042_STR_KEYLOCK) {
  603. if (i8042_unlock)
  604. i8042_ctr |= I8042_CTR_IGNKEYLOCK;
  605. else
  606. printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
  607. }
  608. spin_unlock_irqrestore(&i8042_lock, flags);
  609. /*
  610. * If the chip is configured into nontranslated mode by the BIOS, don't
  611. * bother enabling translating and be happy.
  612. */
  613. if (~i8042_ctr & I8042_CTR_XLATE)
  614. i8042_direct = 1;
  615. /*
  616. * Set nontranslated mode for the kbd interface if requested by an option.
  617. * After this the kbd interface becomes a simple serial in/out, like the aux
  618. * interface is. We don't do this by default, since it can confuse notebook
  619. * BIOSes.
  620. */
  621. if (i8042_direct)
  622. i8042_ctr &= ~I8042_CTR_XLATE;
  623. /*
  624. * Write CTR back.
  625. */
  626. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  627. printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
  628. return -EIO;
  629. }
  630. return 0;
  631. }
  632. /*
  633. * Reset the controller and reset CRT to the original value set by BIOS.
  634. */
  635. static void i8042_controller_reset(void)
  636. {
  637. i8042_flush();
  638. /*
  639. * Disable both KBD and AUX interfaces so they don't get in the way
  640. */
  641. i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
  642. i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
  643. /*
  644. * Disable MUX mode if present.
  645. */
  646. if (i8042_mux_present)
  647. i8042_set_mux_mode(0, NULL);
  648. /*
  649. * Reset the controller if requested.
  650. */
  651. i8042_controller_selftest();
  652. /*
  653. * Restore the original control register setting.
  654. */
  655. if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
  656. printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
  657. }
  658. /*
  659. * i8042_panic_blink() will flash the keyboard LEDs and is called when
  660. * kernel panics. Flashing LEDs is useful for users running X who may
  661. * not see the console and will help distingushing panics from "real"
  662. * lockups.
  663. *
  664. * Note that DELAY has a limit of 10ms so we will not get stuck here
  665. * waiting for KBC to free up even if KBD interrupt is off
  666. */
  667. #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
  668. static long i8042_panic_blink(long count)
  669. {
  670. long delay = 0;
  671. static long last_blink;
  672. static char led;
  673. /*
  674. * We expect frequency to be about 1/2s. KDB uses about 1s.
  675. * Make sure they are different.
  676. */
  677. if (!i8042_blink_frequency)
  678. return 0;
  679. if (count - last_blink < i8042_blink_frequency)
  680. return 0;
  681. led ^= 0x01 | 0x04;
  682. while (i8042_read_status() & I8042_STR_IBF)
  683. DELAY;
  684. dbg("%02x -> i8042 (panic blink)", 0xed);
  685. i8042_suppress_kbd_ack = 2;
  686. i8042_write_data(0xed); /* set leds */
  687. DELAY;
  688. while (i8042_read_status() & I8042_STR_IBF)
  689. DELAY;
  690. DELAY;
  691. dbg("%02x -> i8042 (panic blink)", led);
  692. i8042_write_data(led);
  693. DELAY;
  694. last_blink = count;
  695. return delay;
  696. }
  697. #undef DELAY
  698. #ifdef CONFIG_PM
  699. /*
  700. * Here we try to restore the original BIOS settings. We only want to
  701. * do that once, when we really suspend, not when we taking memory
  702. * snapshot for swsusp (in this case we'll perform required cleanup
  703. * as part of shutdown process).
  704. */
  705. static int i8042_suspend(struct platform_device *dev, pm_message_t state)
  706. {
  707. if (dev->dev.power.power_state.event != state.event) {
  708. if (state.event == PM_EVENT_SUSPEND)
  709. i8042_controller_reset();
  710. dev->dev.power.power_state = state;
  711. }
  712. return 0;
  713. }
  714. /*
  715. * Here we try to reset everything back to a state in which suspended
  716. */
  717. static int i8042_resume(struct platform_device *dev)
  718. {
  719. int error;
  720. /*
  721. * Do not bother with restoring state if we haven't suspened yet
  722. */
  723. if (dev->dev.power.power_state.event == PM_EVENT_ON)
  724. return 0;
  725. error = i8042_controller_check();
  726. if (error)
  727. return error;
  728. error = i8042_controller_selftest();
  729. if (error)
  730. return error;
  731. /*
  732. * Restore original CTR value and disable all ports
  733. */
  734. i8042_ctr = i8042_initial_ctr;
  735. if (i8042_direct)
  736. i8042_ctr &= ~I8042_CTR_XLATE;
  737. i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
  738. i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
  739. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  740. printk(KERN_ERR "i8042: Can't write CTR to resume\n");
  741. return -EIO;
  742. }
  743. if (i8042_mux_present) {
  744. if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports())
  745. printk(KERN_WARNING
  746. "i8042: failed to resume active multiplexor, "
  747. "mouse won't work.\n");
  748. } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
  749. i8042_enable_aux_port();
  750. if (i8042_ports[I8042_KBD_PORT_NO].serio)
  751. i8042_enable_kbd_port();
  752. i8042_interrupt(0, NULL);
  753. dev->dev.power.power_state = PMSG_ON;
  754. return 0;
  755. }
  756. #endif /* CONFIG_PM */
  757. /*
  758. * We need to reset the 8042 back to original mode on system shutdown,
  759. * because otherwise BIOSes will be confused.
  760. */
  761. static void i8042_shutdown(struct platform_device *dev)
  762. {
  763. i8042_controller_reset();
  764. }
  765. static int __devinit i8042_create_kbd_port(void)
  766. {
  767. struct serio *serio;
  768. struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
  769. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  770. if (!serio)
  771. return -ENOMEM;
  772. serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
  773. serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
  774. serio->start = i8042_start;
  775. serio->stop = i8042_stop;
  776. serio->port_data = port;
  777. serio->dev.parent = &i8042_platform_device->dev;
  778. strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
  779. strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
  780. port->serio = serio;
  781. port->irq = I8042_KBD_IRQ;
  782. return 0;
  783. }
  784. static int __devinit i8042_create_aux_port(int idx)
  785. {
  786. struct serio *serio;
  787. int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
  788. struct i8042_port *port = &i8042_ports[port_no];
  789. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  790. if (!serio)
  791. return -ENOMEM;
  792. serio->id.type = SERIO_8042;
  793. serio->write = i8042_aux_write;
  794. serio->start = i8042_start;
  795. serio->stop = i8042_stop;
  796. serio->port_data = port;
  797. serio->dev.parent = &i8042_platform_device->dev;
  798. if (idx < 0) {
  799. strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
  800. strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
  801. } else {
  802. snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
  803. snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
  804. }
  805. port->serio = serio;
  806. port->mux = idx;
  807. port->irq = I8042_AUX_IRQ;
  808. return 0;
  809. }
  810. static void __devinit i8042_free_kbd_port(void)
  811. {
  812. kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
  813. i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
  814. }
  815. static void __devinit i8042_free_aux_ports(void)
  816. {
  817. int i;
  818. for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
  819. kfree(i8042_ports[i].serio);
  820. i8042_ports[i].serio = NULL;
  821. }
  822. }
  823. static void __devinit i8042_register_ports(void)
  824. {
  825. int i;
  826. for (i = 0; i < I8042_NUM_PORTS; i++) {
  827. if (i8042_ports[i].serio) {
  828. printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
  829. i8042_ports[i].serio->name,
  830. (unsigned long) I8042_DATA_REG,
  831. (unsigned long) I8042_COMMAND_REG,
  832. i8042_ports[i].irq);
  833. serio_register_port(i8042_ports[i].serio);
  834. }
  835. }
  836. }
  837. static void __devexit i8042_unregister_ports(void)
  838. {
  839. int i;
  840. for (i = 0; i < I8042_NUM_PORTS; i++) {
  841. if (i8042_ports[i].serio) {
  842. serio_unregister_port(i8042_ports[i].serio);
  843. i8042_ports[i].serio = NULL;
  844. }
  845. }
  846. }
  847. static void i8042_free_irqs(void)
  848. {
  849. if (i8042_aux_irq_registered)
  850. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  851. if (i8042_kbd_irq_registered)
  852. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  853. i8042_aux_irq_registered = i8042_kbd_irq_registered = 0;
  854. }
  855. static int __devinit i8042_setup_aux(void)
  856. {
  857. int (*aux_enable)(void);
  858. int error;
  859. int i;
  860. if (i8042_check_aux())
  861. return -ENODEV;
  862. if (i8042_nomux || i8042_check_mux()) {
  863. error = i8042_create_aux_port(-1);
  864. if (error)
  865. goto err_free_ports;
  866. aux_enable = i8042_enable_aux_port;
  867. } else {
  868. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  869. error = i8042_create_aux_port(i);
  870. if (error)
  871. goto err_free_ports;
  872. }
  873. aux_enable = i8042_enable_mux_ports;
  874. }
  875. error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
  876. "i8042", i8042_platform_device);
  877. if (error)
  878. goto err_free_ports;
  879. if (aux_enable())
  880. goto err_free_irq;
  881. i8042_aux_irq_registered = 1;
  882. return 0;
  883. err_free_irq:
  884. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  885. err_free_ports:
  886. i8042_free_aux_ports();
  887. return error;
  888. }
  889. static int __devinit i8042_setup_kbd(void)
  890. {
  891. int error;
  892. error = i8042_create_kbd_port();
  893. if (error)
  894. return error;
  895. error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
  896. "i8042", i8042_platform_device);
  897. if (error)
  898. goto err_free_port;
  899. error = i8042_enable_kbd_port();
  900. if (error)
  901. goto err_free_irq;
  902. i8042_kbd_irq_registered = 1;
  903. return 0;
  904. err_free_irq:
  905. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  906. err_free_port:
  907. i8042_free_kbd_port();
  908. return error;
  909. }
  910. static int __devinit i8042_probe(struct platform_device *dev)
  911. {
  912. int error;
  913. error = i8042_controller_selftest();
  914. if (error)
  915. return error;
  916. error = i8042_controller_init();
  917. if (error)
  918. return error;
  919. if (!i8042_noaux) {
  920. error = i8042_setup_aux();
  921. if (error && error != -ENODEV && error != -EBUSY)
  922. goto out_fail;
  923. }
  924. if (!i8042_nokbd) {
  925. error = i8042_setup_kbd();
  926. if (error)
  927. goto out_fail;
  928. }
  929. /*
  930. * Ok, everything is ready, let's register all serio ports
  931. */
  932. i8042_register_ports();
  933. return 0;
  934. out_fail:
  935. i8042_free_aux_ports(); /* in case KBD failed but AUX not */
  936. i8042_free_irqs();
  937. i8042_controller_reset();
  938. return error;
  939. }
  940. static int __devexit i8042_remove(struct platform_device *dev)
  941. {
  942. i8042_unregister_ports();
  943. i8042_free_irqs();
  944. i8042_controller_reset();
  945. return 0;
  946. }
  947. static struct platform_driver i8042_driver = {
  948. .driver = {
  949. .name = "i8042",
  950. .owner = THIS_MODULE,
  951. },
  952. .probe = i8042_probe,
  953. .remove = __devexit_p(i8042_remove),
  954. .shutdown = i8042_shutdown,
  955. #ifdef CONFIG_PM
  956. .suspend = i8042_suspend,
  957. .resume = i8042_resume,
  958. #endif
  959. };
  960. static int __init i8042_init(void)
  961. {
  962. int err;
  963. dbg_init();
  964. err = i8042_platform_init();
  965. if (err)
  966. return err;
  967. err = i8042_controller_check();
  968. if (err)
  969. goto err_platform_exit;
  970. err = platform_driver_register(&i8042_driver);
  971. if (err)
  972. goto err_platform_exit;
  973. i8042_platform_device = platform_device_alloc("i8042", -1);
  974. if (!i8042_platform_device) {
  975. err = -ENOMEM;
  976. goto err_unregister_driver;
  977. }
  978. err = platform_device_add(i8042_platform_device);
  979. if (err)
  980. goto err_free_device;
  981. panic_blink = i8042_panic_blink;
  982. return 0;
  983. err_free_device:
  984. platform_device_put(i8042_platform_device);
  985. err_unregister_driver:
  986. platform_driver_unregister(&i8042_driver);
  987. err_platform_exit:
  988. i8042_platform_exit();
  989. return err;
  990. }
  991. static void __exit i8042_exit(void)
  992. {
  993. platform_device_unregister(i8042_platform_device);
  994. platform_driver_unregister(&i8042_driver);
  995. i8042_platform_exit();
  996. panic_blink = NULL;
  997. }
  998. module_init(i8042_init);
  999. module_exit(i8042_exit);