iwl-agn.c 105 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  67. #define VS "s"
  68. #else
  69. #define VS
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD VS
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. MODULE_ALIAS("iwl4965");
  77. /*************** STATION TABLE MANAGEMENT ****
  78. * mac80211 should be examined to determine if sta_info is duplicating
  79. * the functionality provided here
  80. */
  81. /**************************************************************/
  82. /**
  83. * iwl_commit_rxon - commit staging_rxon to hardware
  84. *
  85. * The RXON command in staging_rxon is committed to the hardware and
  86. * the active_rxon structure is updated with the new data. This
  87. * function correctly transitions out of the RXON_ASSOC_MSK state if
  88. * a HW tune is required based on the RXON structure changes.
  89. */
  90. int iwl_commit_rxon(struct iwl_priv *priv)
  91. {
  92. /* cast away the const for active_rxon in this function */
  93. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  94. int ret;
  95. bool new_assoc =
  96. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  97. if (!iwl_is_alive(priv))
  98. return -EBUSY;
  99. /* always get timestamp with Rx frame */
  100. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  101. ret = iwl_check_rxon_cmd(priv);
  102. if (ret) {
  103. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  104. return -EINVAL;
  105. }
  106. /*
  107. * receive commit_rxon request
  108. * abort any previous channel switch if still in process
  109. */
  110. if (priv->switch_rxon.switch_in_progress &&
  111. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  112. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  113. le16_to_cpu(priv->switch_rxon.channel));
  114. priv->switch_rxon.switch_in_progress = false;
  115. }
  116. /* If we don't need to send a full RXON, we can use
  117. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  118. * and other flags for the current radio configuration. */
  119. if (!iwl_full_rxon_required(priv)) {
  120. ret = iwl_send_rxon_assoc(priv);
  121. if (ret) {
  122. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  123. return ret;
  124. }
  125. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  126. iwl_print_rx_config_cmd(priv);
  127. return 0;
  128. }
  129. /* station table will be cleared */
  130. priv->assoc_station_added = 0;
  131. /* If we are currently associated and the new config requires
  132. * an RXON_ASSOC and the new config wants the associated mask enabled,
  133. * we must clear the associated from the active configuration
  134. * before we apply the new config */
  135. if (iwl_is_associated(priv) && new_assoc) {
  136. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  137. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  138. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  139. sizeof(struct iwl_rxon_cmd),
  140. &priv->active_rxon);
  141. /* If the mask clearing failed then we set
  142. * active_rxon back to what it was previously */
  143. if (ret) {
  144. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  145. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  146. return ret;
  147. }
  148. }
  149. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  150. "* with%s RXON_FILTER_ASSOC_MSK\n"
  151. "* channel = %d\n"
  152. "* bssid = %pM\n",
  153. (new_assoc ? "" : "out"),
  154. le16_to_cpu(priv->staging_rxon.channel),
  155. priv->staging_rxon.bssid_addr);
  156. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  157. /* Apply the new configuration
  158. * RXON unassoc clears the station table in uCode, send it before
  159. * we add the bcast station. If assoc bit is set, we will send RXON
  160. * after having added the bcast and bssid station.
  161. */
  162. if (!new_assoc) {
  163. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  164. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  165. if (ret) {
  166. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  167. return ret;
  168. }
  169. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  170. }
  171. iwl_clear_stations_table(priv);
  172. priv->start_calib = 0;
  173. /* Add the broadcast address so we can send broadcast frames */
  174. iwl_add_bcast_station(priv);
  175. /* If we have set the ASSOC_MSK and we are in BSS mode then
  176. * add the IWL_AP_ID to the station rate table */
  177. if (new_assoc) {
  178. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  179. ret = iwl_rxon_add_station(priv,
  180. priv->active_rxon.bssid_addr, 1);
  181. if (ret == IWL_INVALID_STATION) {
  182. IWL_ERR(priv,
  183. "Error adding AP address for TX.\n");
  184. return -EIO;
  185. }
  186. priv->assoc_station_added = 1;
  187. if (priv->default_wep_key &&
  188. iwl_send_static_wepkey_cmd(priv, 0))
  189. IWL_ERR(priv,
  190. "Could not send WEP static key.\n");
  191. }
  192. /*
  193. * allow CTS-to-self if possible for new association.
  194. * this is relevant only for 5000 series and up,
  195. * but will not damage 4965
  196. */
  197. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  198. /* Apply the new configuration
  199. * RXON assoc doesn't clear the station table in uCode,
  200. */
  201. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  202. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  203. if (ret) {
  204. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  205. return ret;
  206. }
  207. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  208. }
  209. iwl_print_rx_config_cmd(priv);
  210. iwl_init_sensitivity(priv);
  211. /* If we issue a new RXON command which required a tune then we must
  212. * send a new TXPOWER command or we won't be able to Tx any frames */
  213. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  214. if (ret) {
  215. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  216. return ret;
  217. }
  218. return 0;
  219. }
  220. void iwl_update_chain_flags(struct iwl_priv *priv)
  221. {
  222. if (priv->cfg->ops->hcmd->set_rxon_chain)
  223. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  224. iwlcore_commit_rxon(priv);
  225. }
  226. static void iwl_clear_free_frames(struct iwl_priv *priv)
  227. {
  228. struct list_head *element;
  229. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  230. priv->frames_count);
  231. while (!list_empty(&priv->free_frames)) {
  232. element = priv->free_frames.next;
  233. list_del(element);
  234. kfree(list_entry(element, struct iwl_frame, list));
  235. priv->frames_count--;
  236. }
  237. if (priv->frames_count) {
  238. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  239. priv->frames_count);
  240. priv->frames_count = 0;
  241. }
  242. }
  243. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  244. {
  245. struct iwl_frame *frame;
  246. struct list_head *element;
  247. if (list_empty(&priv->free_frames)) {
  248. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  249. if (!frame) {
  250. IWL_ERR(priv, "Could not allocate frame!\n");
  251. return NULL;
  252. }
  253. priv->frames_count++;
  254. return frame;
  255. }
  256. element = priv->free_frames.next;
  257. list_del(element);
  258. return list_entry(element, struct iwl_frame, list);
  259. }
  260. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  261. {
  262. memset(frame, 0, sizeof(*frame));
  263. list_add(&frame->list, &priv->free_frames);
  264. }
  265. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  266. struct ieee80211_hdr *hdr,
  267. int left)
  268. {
  269. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  270. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  271. (priv->iw_mode != NL80211_IFTYPE_AP)))
  272. return 0;
  273. if (priv->ibss_beacon->len > left)
  274. return 0;
  275. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  276. return priv->ibss_beacon->len;
  277. }
  278. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  279. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  280. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  281. u8 *beacon, u32 frame_size)
  282. {
  283. u16 tim_idx;
  284. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  285. /*
  286. * The index is relative to frame start but we start looking at the
  287. * variable-length part of the beacon.
  288. */
  289. tim_idx = mgmt->u.beacon.variable - beacon;
  290. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  291. while ((tim_idx < (frame_size - 2)) &&
  292. (beacon[tim_idx] != WLAN_EID_TIM))
  293. tim_idx += beacon[tim_idx+1] + 2;
  294. /* If TIM field was found, set variables */
  295. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  296. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  297. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  298. } else
  299. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  300. }
  301. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  302. struct iwl_frame *frame)
  303. {
  304. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  305. u32 frame_size;
  306. u32 rate_flags;
  307. u32 rate;
  308. /*
  309. * We have to set up the TX command, the TX Beacon command, and the
  310. * beacon contents.
  311. */
  312. /* Initialize memory */
  313. tx_beacon_cmd = &frame->u.beacon;
  314. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  315. /* Set up TX beacon contents */
  316. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  317. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  318. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  319. return 0;
  320. /* Set up TX command fields */
  321. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  322. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  323. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  324. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  325. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  326. /* Set up TX beacon command fields */
  327. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  328. frame_size);
  329. /* Set up packet rate and flags */
  330. rate = iwl_rate_get_lowest_plcp(priv);
  331. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  332. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  333. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  334. rate_flags |= RATE_MCS_CCK_MSK;
  335. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  336. rate_flags);
  337. return sizeof(*tx_beacon_cmd) + frame_size;
  338. }
  339. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  340. {
  341. struct iwl_frame *frame;
  342. unsigned int frame_size;
  343. int rc;
  344. frame = iwl_get_free_frame(priv);
  345. if (!frame) {
  346. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  347. "command.\n");
  348. return -ENOMEM;
  349. }
  350. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  351. if (!frame_size) {
  352. IWL_ERR(priv, "Error configuring the beacon command\n");
  353. iwl_free_frame(priv, frame);
  354. return -EINVAL;
  355. }
  356. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  357. &frame->u.cmd[0]);
  358. iwl_free_frame(priv, frame);
  359. return rc;
  360. }
  361. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  362. {
  363. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  364. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  365. if (sizeof(dma_addr_t) > sizeof(u32))
  366. addr |=
  367. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  368. return addr;
  369. }
  370. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  371. {
  372. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  373. return le16_to_cpu(tb->hi_n_len) >> 4;
  374. }
  375. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  376. dma_addr_t addr, u16 len)
  377. {
  378. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  379. u16 hi_n_len = len << 4;
  380. put_unaligned_le32(addr, &tb->lo);
  381. if (sizeof(dma_addr_t) > sizeof(u32))
  382. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  383. tb->hi_n_len = cpu_to_le16(hi_n_len);
  384. tfd->num_tbs = idx + 1;
  385. }
  386. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  387. {
  388. return tfd->num_tbs & 0x1f;
  389. }
  390. /**
  391. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  392. * @priv - driver private data
  393. * @txq - tx queue
  394. *
  395. * Does NOT advance any TFD circular buffer read/write indexes
  396. * Does NOT free the TFD itself (which is within circular buffer)
  397. */
  398. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  399. {
  400. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  401. struct iwl_tfd *tfd;
  402. struct pci_dev *dev = priv->pci_dev;
  403. int index = txq->q.read_ptr;
  404. int i;
  405. int num_tbs;
  406. tfd = &tfd_tmp[index];
  407. /* Sanity check on number of chunks */
  408. num_tbs = iwl_tfd_get_num_tbs(tfd);
  409. if (num_tbs >= IWL_NUM_OF_TBS) {
  410. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  411. /* @todo issue fatal error, it is quite serious situation */
  412. return;
  413. }
  414. /* Unmap tx_cmd */
  415. if (num_tbs)
  416. pci_unmap_single(dev,
  417. pci_unmap_addr(&txq->meta[index], mapping),
  418. pci_unmap_len(&txq->meta[index], len),
  419. PCI_DMA_BIDIRECTIONAL);
  420. /* Unmap chunks, if any. */
  421. for (i = 1; i < num_tbs; i++) {
  422. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  423. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  424. if (txq->txb) {
  425. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  426. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  427. }
  428. }
  429. }
  430. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  431. struct iwl_tx_queue *txq,
  432. dma_addr_t addr, u16 len,
  433. u8 reset, u8 pad)
  434. {
  435. struct iwl_queue *q;
  436. struct iwl_tfd *tfd, *tfd_tmp;
  437. u32 num_tbs;
  438. q = &txq->q;
  439. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  440. tfd = &tfd_tmp[q->write_ptr];
  441. if (reset)
  442. memset(tfd, 0, sizeof(*tfd));
  443. num_tbs = iwl_tfd_get_num_tbs(tfd);
  444. /* Each TFD can point to a maximum 20 Tx buffers */
  445. if (num_tbs >= IWL_NUM_OF_TBS) {
  446. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  447. IWL_NUM_OF_TBS);
  448. return -EINVAL;
  449. }
  450. BUG_ON(addr & ~DMA_BIT_MASK(36));
  451. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  452. IWL_ERR(priv, "Unaligned address = %llx\n",
  453. (unsigned long long)addr);
  454. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  455. return 0;
  456. }
  457. /*
  458. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  459. * given Tx queue, and enable the DMA channel used for that queue.
  460. *
  461. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  462. * channels supported in hardware.
  463. */
  464. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  465. struct iwl_tx_queue *txq)
  466. {
  467. int txq_id = txq->q.id;
  468. /* Circular buffer (TFD queue in DRAM) physical base address */
  469. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  470. txq->q.dma_addr >> 8);
  471. return 0;
  472. }
  473. /******************************************************************************
  474. *
  475. * Generic RX handler implementations
  476. *
  477. ******************************************************************************/
  478. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  479. struct iwl_rx_mem_buffer *rxb)
  480. {
  481. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  482. struct iwl_alive_resp *palive;
  483. struct delayed_work *pwork;
  484. palive = &pkt->u.alive_frame;
  485. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  486. "0x%01X 0x%01X\n",
  487. palive->is_valid, palive->ver_type,
  488. palive->ver_subtype);
  489. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  490. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  491. memcpy(&priv->card_alive_init,
  492. &pkt->u.alive_frame,
  493. sizeof(struct iwl_init_alive_resp));
  494. pwork = &priv->init_alive_start;
  495. } else {
  496. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  497. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  498. sizeof(struct iwl_alive_resp));
  499. pwork = &priv->alive_start;
  500. }
  501. /* We delay the ALIVE response by 5ms to
  502. * give the HW RF Kill time to activate... */
  503. if (palive->is_valid == UCODE_VALID_OK)
  504. queue_delayed_work(priv->workqueue, pwork,
  505. msecs_to_jiffies(5));
  506. else
  507. IWL_WARN(priv, "uCode did not respond OK.\n");
  508. }
  509. static void iwl_bg_beacon_update(struct work_struct *work)
  510. {
  511. struct iwl_priv *priv =
  512. container_of(work, struct iwl_priv, beacon_update);
  513. struct sk_buff *beacon;
  514. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  515. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  516. if (!beacon) {
  517. IWL_ERR(priv, "update beacon failed\n");
  518. return;
  519. }
  520. mutex_lock(&priv->mutex);
  521. /* new beacon skb is allocated every time; dispose previous.*/
  522. if (priv->ibss_beacon)
  523. dev_kfree_skb(priv->ibss_beacon);
  524. priv->ibss_beacon = beacon;
  525. mutex_unlock(&priv->mutex);
  526. iwl_send_beacon_cmd(priv);
  527. }
  528. /**
  529. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  530. *
  531. * This callback is provided in order to send a statistics request.
  532. *
  533. * This timer function is continually reset to execute within
  534. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  535. * was received. We need to ensure we receive the statistics in order
  536. * to update the temperature used for calibrating the TXPOWER.
  537. */
  538. static void iwl_bg_statistics_periodic(unsigned long data)
  539. {
  540. struct iwl_priv *priv = (struct iwl_priv *)data;
  541. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  542. return;
  543. /* dont send host command if rf-kill is on */
  544. if (!iwl_is_ready_rf(priv))
  545. return;
  546. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  547. }
  548. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  549. struct iwl_rx_mem_buffer *rxb)
  550. {
  551. #ifdef CONFIG_IWLWIFI_DEBUG
  552. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  553. struct iwl4965_beacon_notif *beacon =
  554. (struct iwl4965_beacon_notif *)pkt->u.raw;
  555. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  556. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  557. "tsf %d %d rate %d\n",
  558. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  559. beacon->beacon_notify_hdr.failure_frame,
  560. le32_to_cpu(beacon->ibss_mgr_status),
  561. le32_to_cpu(beacon->high_tsf),
  562. le32_to_cpu(beacon->low_tsf), rate);
  563. #endif
  564. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  565. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  566. queue_work(priv->workqueue, &priv->beacon_update);
  567. }
  568. /* Handle notification from uCode that card's power state is changing
  569. * due to software, hardware, or critical temperature RFKILL */
  570. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  571. struct iwl_rx_mem_buffer *rxb)
  572. {
  573. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  574. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  575. unsigned long status = priv->status;
  576. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  577. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  578. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  579. (flags & CT_CARD_DISABLED) ?
  580. "Reached" : "Not reached");
  581. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  582. CT_CARD_DISABLED)) {
  583. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  584. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  585. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  586. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  587. if (!(flags & RXON_CARD_DISABLED)) {
  588. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  589. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  590. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  591. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  592. }
  593. if (flags & CT_CARD_DISABLED)
  594. iwl_tt_enter_ct_kill(priv);
  595. }
  596. if (!(flags & CT_CARD_DISABLED))
  597. iwl_tt_exit_ct_kill(priv);
  598. if (flags & HW_CARD_DISABLED)
  599. set_bit(STATUS_RF_KILL_HW, &priv->status);
  600. else
  601. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  602. if (!(flags & RXON_CARD_DISABLED))
  603. iwl_scan_cancel(priv);
  604. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  605. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  606. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  607. test_bit(STATUS_RF_KILL_HW, &priv->status));
  608. else
  609. wake_up_interruptible(&priv->wait_command_queue);
  610. }
  611. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  612. {
  613. if (src == IWL_PWR_SRC_VAUX) {
  614. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  615. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  616. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  617. ~APMG_PS_CTRL_MSK_PWR_SRC);
  618. } else {
  619. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  620. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  621. ~APMG_PS_CTRL_MSK_PWR_SRC);
  622. }
  623. return 0;
  624. }
  625. /**
  626. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  627. *
  628. * Setup the RX handlers for each of the reply types sent from the uCode
  629. * to the host.
  630. *
  631. * This function chains into the hardware specific files for them to setup
  632. * any hardware specific handlers as well.
  633. */
  634. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  635. {
  636. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  637. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  638. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  639. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  640. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  641. iwl_rx_pm_debug_statistics_notif;
  642. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  643. /*
  644. * The same handler is used for both the REPLY to a discrete
  645. * statistics request from the host as well as for the periodic
  646. * statistics notifications (after received beacons) from the uCode.
  647. */
  648. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  649. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  650. iwl_setup_spectrum_handlers(priv);
  651. iwl_setup_rx_scan_handlers(priv);
  652. /* status change handler */
  653. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  654. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  655. iwl_rx_missed_beacon_notif;
  656. /* Rx handlers */
  657. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  658. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  659. /* block ack */
  660. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  661. /* Set up hardware specific Rx handlers */
  662. priv->cfg->ops->lib->rx_handler_setup(priv);
  663. }
  664. /**
  665. * iwl_rx_handle - Main entry function for receiving responses from uCode
  666. *
  667. * Uses the priv->rx_handlers callback function array to invoke
  668. * the appropriate handlers, including command responses,
  669. * frame-received notifications, and other notifications.
  670. */
  671. void iwl_rx_handle(struct iwl_priv *priv)
  672. {
  673. struct iwl_rx_mem_buffer *rxb;
  674. struct iwl_rx_packet *pkt;
  675. struct iwl_rx_queue *rxq = &priv->rxq;
  676. u32 r, i;
  677. int reclaim;
  678. unsigned long flags;
  679. u8 fill_rx = 0;
  680. u32 count = 8;
  681. int total_empty;
  682. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  683. * buffer that the driver may process (last buffer filled by ucode). */
  684. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  685. i = rxq->read;
  686. /* Rx interrupt, but nothing sent from uCode */
  687. if (i == r)
  688. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  689. /* calculate total frames need to be restock after handling RX */
  690. total_empty = r - rxq->write_actual;
  691. if (total_empty < 0)
  692. total_empty += RX_QUEUE_SIZE;
  693. if (total_empty > (RX_QUEUE_SIZE / 2))
  694. fill_rx = 1;
  695. while (i != r) {
  696. rxb = rxq->queue[i];
  697. /* If an RXB doesn't have a Rx queue slot associated with it,
  698. * then a bug has been introduced in the queue refilling
  699. * routines -- catch it here */
  700. BUG_ON(rxb == NULL);
  701. rxq->queue[i] = NULL;
  702. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  703. PAGE_SIZE << priv->hw_params.rx_page_order,
  704. PCI_DMA_FROMDEVICE);
  705. pkt = rxb_addr(rxb);
  706. trace_iwlwifi_dev_rx(priv, pkt,
  707. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  708. /* Reclaim a command buffer only if this packet is a response
  709. * to a (driver-originated) command.
  710. * If the packet (e.g. Rx frame) originated from uCode,
  711. * there is no command buffer to reclaim.
  712. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  713. * but apparently a few don't get set; catch them here. */
  714. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  715. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  716. (pkt->hdr.cmd != REPLY_RX) &&
  717. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  718. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  719. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  720. (pkt->hdr.cmd != REPLY_TX);
  721. /* Based on type of command response or notification,
  722. * handle those that need handling via function in
  723. * rx_handlers table. See iwl_setup_rx_handlers() */
  724. if (priv->rx_handlers[pkt->hdr.cmd]) {
  725. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  726. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  727. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  728. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  729. } else {
  730. /* No handling needed */
  731. IWL_DEBUG_RX(priv,
  732. "r %d i %d No handler needed for %s, 0x%02x\n",
  733. r, i, get_cmd_string(pkt->hdr.cmd),
  734. pkt->hdr.cmd);
  735. }
  736. /*
  737. * XXX: After here, we should always check rxb->page
  738. * against NULL before touching it or its virtual
  739. * memory (pkt). Because some rx_handler might have
  740. * already taken or freed the pages.
  741. */
  742. if (reclaim) {
  743. /* Invoke any callbacks, transfer the buffer to caller,
  744. * and fire off the (possibly) blocking iwl_send_cmd()
  745. * as we reclaim the driver command queue */
  746. if (rxb->page)
  747. iwl_tx_cmd_complete(priv, rxb);
  748. else
  749. IWL_WARN(priv, "Claim null rxb?\n");
  750. }
  751. /* Reuse the page if possible. For notification packets and
  752. * SKBs that fail to Rx correctly, add them back into the
  753. * rx_free list for reuse later. */
  754. spin_lock_irqsave(&rxq->lock, flags);
  755. if (rxb->page != NULL) {
  756. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  757. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  758. PCI_DMA_FROMDEVICE);
  759. list_add_tail(&rxb->list, &rxq->rx_free);
  760. rxq->free_count++;
  761. } else
  762. list_add_tail(&rxb->list, &rxq->rx_used);
  763. spin_unlock_irqrestore(&rxq->lock, flags);
  764. i = (i + 1) & RX_QUEUE_MASK;
  765. /* If there are a lot of unused frames,
  766. * restock the Rx queue so ucode wont assert. */
  767. if (fill_rx) {
  768. count++;
  769. if (count >= 8) {
  770. rxq->read = i;
  771. iwl_rx_replenish_now(priv);
  772. count = 0;
  773. }
  774. }
  775. }
  776. /* Backtrack one entry */
  777. rxq->read = i;
  778. if (fill_rx)
  779. iwl_rx_replenish_now(priv);
  780. else
  781. iwl_rx_queue_restock(priv);
  782. }
  783. /* call this function to flush any scheduled tasklet */
  784. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  785. {
  786. /* wait to make sure we flush pending tasklet*/
  787. synchronize_irq(priv->pci_dev->irq);
  788. tasklet_kill(&priv->irq_tasklet);
  789. }
  790. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  791. {
  792. u32 inta, handled = 0;
  793. u32 inta_fh;
  794. unsigned long flags;
  795. u32 i;
  796. #ifdef CONFIG_IWLWIFI_DEBUG
  797. u32 inta_mask;
  798. #endif
  799. spin_lock_irqsave(&priv->lock, flags);
  800. /* Ack/clear/reset pending uCode interrupts.
  801. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  802. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  803. inta = iwl_read32(priv, CSR_INT);
  804. iwl_write32(priv, CSR_INT, inta);
  805. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  806. * Any new interrupts that happen after this, either while we're
  807. * in this tasklet, or later, will show up in next ISR/tasklet. */
  808. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  809. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  810. #ifdef CONFIG_IWLWIFI_DEBUG
  811. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  812. /* just for debug */
  813. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  814. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  815. inta, inta_mask, inta_fh);
  816. }
  817. #endif
  818. spin_unlock_irqrestore(&priv->lock, flags);
  819. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  820. * atomic, make sure that inta covers all the interrupts that
  821. * we've discovered, even if FH interrupt came in just after
  822. * reading CSR_INT. */
  823. if (inta_fh & CSR49_FH_INT_RX_MASK)
  824. inta |= CSR_INT_BIT_FH_RX;
  825. if (inta_fh & CSR49_FH_INT_TX_MASK)
  826. inta |= CSR_INT_BIT_FH_TX;
  827. /* Now service all interrupt bits discovered above. */
  828. if (inta & CSR_INT_BIT_HW_ERR) {
  829. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  830. /* Tell the device to stop sending interrupts */
  831. iwl_disable_interrupts(priv);
  832. priv->isr_stats.hw++;
  833. iwl_irq_handle_error(priv);
  834. handled |= CSR_INT_BIT_HW_ERR;
  835. return;
  836. }
  837. #ifdef CONFIG_IWLWIFI_DEBUG
  838. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  839. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  840. if (inta & CSR_INT_BIT_SCD) {
  841. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  842. "the frame/frames.\n");
  843. priv->isr_stats.sch++;
  844. }
  845. /* Alive notification via Rx interrupt will do the real work */
  846. if (inta & CSR_INT_BIT_ALIVE) {
  847. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  848. priv->isr_stats.alive++;
  849. }
  850. }
  851. #endif
  852. /* Safely ignore these bits for debug checks below */
  853. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  854. /* HW RF KILL switch toggled */
  855. if (inta & CSR_INT_BIT_RF_KILL) {
  856. int hw_rf_kill = 0;
  857. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  858. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  859. hw_rf_kill = 1;
  860. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  861. hw_rf_kill ? "disable radio" : "enable radio");
  862. priv->isr_stats.rfkill++;
  863. /* driver only loads ucode once setting the interface up.
  864. * the driver allows loading the ucode even if the radio
  865. * is killed. Hence update the killswitch state here. The
  866. * rfkill handler will care about restarting if needed.
  867. */
  868. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  869. if (hw_rf_kill)
  870. set_bit(STATUS_RF_KILL_HW, &priv->status);
  871. else
  872. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  873. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  874. }
  875. handled |= CSR_INT_BIT_RF_KILL;
  876. }
  877. /* Chip got too hot and stopped itself */
  878. if (inta & CSR_INT_BIT_CT_KILL) {
  879. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  880. priv->isr_stats.ctkill++;
  881. handled |= CSR_INT_BIT_CT_KILL;
  882. }
  883. /* Error detected by uCode */
  884. if (inta & CSR_INT_BIT_SW_ERR) {
  885. IWL_ERR(priv, "Microcode SW error detected. "
  886. " Restarting 0x%X.\n", inta);
  887. priv->isr_stats.sw++;
  888. priv->isr_stats.sw_err = inta;
  889. iwl_irq_handle_error(priv);
  890. handled |= CSR_INT_BIT_SW_ERR;
  891. }
  892. /*
  893. * uCode wakes up after power-down sleep.
  894. * Tell device about any new tx or host commands enqueued,
  895. * and about any Rx buffers made available while asleep.
  896. */
  897. if (inta & CSR_INT_BIT_WAKEUP) {
  898. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  899. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  900. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  901. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  902. priv->isr_stats.wakeup++;
  903. handled |= CSR_INT_BIT_WAKEUP;
  904. }
  905. /* All uCode command responses, including Tx command responses,
  906. * Rx "responses" (frame-received notification), and other
  907. * notifications from uCode come through here*/
  908. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  909. iwl_rx_handle(priv);
  910. priv->isr_stats.rx++;
  911. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  912. }
  913. /* This "Tx" DMA channel is used only for loading uCode */
  914. if (inta & CSR_INT_BIT_FH_TX) {
  915. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  916. priv->isr_stats.tx++;
  917. handled |= CSR_INT_BIT_FH_TX;
  918. /* Wake up uCode load routine, now that load is complete */
  919. priv->ucode_write_complete = 1;
  920. wake_up_interruptible(&priv->wait_command_queue);
  921. }
  922. if (inta & ~handled) {
  923. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  924. priv->isr_stats.unhandled++;
  925. }
  926. if (inta & ~(priv->inta_mask)) {
  927. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  928. inta & ~priv->inta_mask);
  929. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  930. }
  931. /* Re-enable all interrupts */
  932. /* only Re-enable if diabled by irq */
  933. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  934. iwl_enable_interrupts(priv);
  935. #ifdef CONFIG_IWLWIFI_DEBUG
  936. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  937. inta = iwl_read32(priv, CSR_INT);
  938. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  939. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  940. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  941. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  942. }
  943. #endif
  944. }
  945. /* tasklet for iwlagn interrupt */
  946. static void iwl_irq_tasklet(struct iwl_priv *priv)
  947. {
  948. u32 inta = 0;
  949. u32 handled = 0;
  950. unsigned long flags;
  951. u32 i;
  952. #ifdef CONFIG_IWLWIFI_DEBUG
  953. u32 inta_mask;
  954. #endif
  955. spin_lock_irqsave(&priv->lock, flags);
  956. /* Ack/clear/reset pending uCode interrupts.
  957. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  958. */
  959. iwl_write32(priv, CSR_INT, priv->inta);
  960. inta = priv->inta;
  961. #ifdef CONFIG_IWLWIFI_DEBUG
  962. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  963. /* just for debug */
  964. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  965. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  966. inta, inta_mask);
  967. }
  968. #endif
  969. spin_unlock_irqrestore(&priv->lock, flags);
  970. /* saved interrupt in inta variable now we can reset priv->inta */
  971. priv->inta = 0;
  972. /* Now service all interrupt bits discovered above. */
  973. if (inta & CSR_INT_BIT_HW_ERR) {
  974. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  975. /* Tell the device to stop sending interrupts */
  976. iwl_disable_interrupts(priv);
  977. priv->isr_stats.hw++;
  978. iwl_irq_handle_error(priv);
  979. handled |= CSR_INT_BIT_HW_ERR;
  980. return;
  981. }
  982. #ifdef CONFIG_IWLWIFI_DEBUG
  983. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  984. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  985. if (inta & CSR_INT_BIT_SCD) {
  986. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  987. "the frame/frames.\n");
  988. priv->isr_stats.sch++;
  989. }
  990. /* Alive notification via Rx interrupt will do the real work */
  991. if (inta & CSR_INT_BIT_ALIVE) {
  992. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  993. priv->isr_stats.alive++;
  994. }
  995. }
  996. #endif
  997. /* Safely ignore these bits for debug checks below */
  998. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  999. /* HW RF KILL switch toggled */
  1000. if (inta & CSR_INT_BIT_RF_KILL) {
  1001. int hw_rf_kill = 0;
  1002. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1003. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1004. hw_rf_kill = 1;
  1005. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1006. hw_rf_kill ? "disable radio" : "enable radio");
  1007. priv->isr_stats.rfkill++;
  1008. /* driver only loads ucode once setting the interface up.
  1009. * the driver allows loading the ucode even if the radio
  1010. * is killed. Hence update the killswitch state here. The
  1011. * rfkill handler will care about restarting if needed.
  1012. */
  1013. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1014. if (hw_rf_kill)
  1015. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1016. else
  1017. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1018. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1019. }
  1020. handled |= CSR_INT_BIT_RF_KILL;
  1021. }
  1022. /* Chip got too hot and stopped itself */
  1023. if (inta & CSR_INT_BIT_CT_KILL) {
  1024. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1025. priv->isr_stats.ctkill++;
  1026. handled |= CSR_INT_BIT_CT_KILL;
  1027. }
  1028. /* Error detected by uCode */
  1029. if (inta & CSR_INT_BIT_SW_ERR) {
  1030. IWL_ERR(priv, "Microcode SW error detected. "
  1031. " Restarting 0x%X.\n", inta);
  1032. priv->isr_stats.sw++;
  1033. priv->isr_stats.sw_err = inta;
  1034. iwl_irq_handle_error(priv);
  1035. handled |= CSR_INT_BIT_SW_ERR;
  1036. }
  1037. /* uCode wakes up after power-down sleep */
  1038. if (inta & CSR_INT_BIT_WAKEUP) {
  1039. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1040. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1041. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1042. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1043. priv->isr_stats.wakeup++;
  1044. handled |= CSR_INT_BIT_WAKEUP;
  1045. }
  1046. /* All uCode command responses, including Tx command responses,
  1047. * Rx "responses" (frame-received notification), and other
  1048. * notifications from uCode come through here*/
  1049. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1050. CSR_INT_BIT_RX_PERIODIC)) {
  1051. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1052. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1053. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1054. iwl_write32(priv, CSR_FH_INT_STATUS,
  1055. CSR49_FH_INT_RX_MASK);
  1056. }
  1057. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1058. handled |= CSR_INT_BIT_RX_PERIODIC;
  1059. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1060. }
  1061. /* Sending RX interrupt require many steps to be done in the
  1062. * the device:
  1063. * 1- write interrupt to current index in ICT table.
  1064. * 2- dma RX frame.
  1065. * 3- update RX shared data to indicate last write index.
  1066. * 4- send interrupt.
  1067. * This could lead to RX race, driver could receive RX interrupt
  1068. * but the shared data changes does not reflect this;
  1069. * periodic interrupt will detect any dangling Rx activity.
  1070. */
  1071. /* Disable periodic interrupt; we use it as just a one-shot. */
  1072. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1073. CSR_INT_PERIODIC_DIS);
  1074. iwl_rx_handle(priv);
  1075. /*
  1076. * Enable periodic interrupt in 8 msec only if we received
  1077. * real RX interrupt (instead of just periodic int), to catch
  1078. * any dangling Rx interrupt. If it was just the periodic
  1079. * interrupt, there was no dangling Rx activity, and no need
  1080. * to extend the periodic interrupt; one-shot is enough.
  1081. */
  1082. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1083. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1084. CSR_INT_PERIODIC_ENA);
  1085. priv->isr_stats.rx++;
  1086. }
  1087. /* This "Tx" DMA channel is used only for loading uCode */
  1088. if (inta & CSR_INT_BIT_FH_TX) {
  1089. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1090. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1091. priv->isr_stats.tx++;
  1092. handled |= CSR_INT_BIT_FH_TX;
  1093. /* Wake up uCode load routine, now that load is complete */
  1094. priv->ucode_write_complete = 1;
  1095. wake_up_interruptible(&priv->wait_command_queue);
  1096. }
  1097. if (inta & ~handled) {
  1098. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1099. priv->isr_stats.unhandled++;
  1100. }
  1101. if (inta & ~(priv->inta_mask)) {
  1102. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1103. inta & ~priv->inta_mask);
  1104. }
  1105. /* Re-enable all interrupts */
  1106. /* only Re-enable if diabled by irq */
  1107. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1108. iwl_enable_interrupts(priv);
  1109. }
  1110. /******************************************************************************
  1111. *
  1112. * uCode download functions
  1113. *
  1114. ******************************************************************************/
  1115. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1116. {
  1117. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1118. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1119. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1120. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1121. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1122. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1123. }
  1124. static void iwl_nic_start(struct iwl_priv *priv)
  1125. {
  1126. /* Remove all resets to allow NIC to operate */
  1127. iwl_write32(priv, CSR_RESET, 0);
  1128. }
  1129. /**
  1130. * iwl_read_ucode - Read uCode images from disk file.
  1131. *
  1132. * Copy into buffers for card to fetch via bus-mastering
  1133. */
  1134. static int iwl_read_ucode(struct iwl_priv *priv)
  1135. {
  1136. struct iwl_ucode_header *ucode;
  1137. int ret = -EINVAL, index;
  1138. const struct firmware *ucode_raw;
  1139. const char *name_pre = priv->cfg->fw_name_pre;
  1140. const unsigned int api_max = priv->cfg->ucode_api_max;
  1141. const unsigned int api_min = priv->cfg->ucode_api_min;
  1142. char buf[25];
  1143. u8 *src;
  1144. size_t len;
  1145. u32 api_ver, build;
  1146. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1147. u16 eeprom_ver;
  1148. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1149. * request_firmware() is synchronous, file is in memory on return. */
  1150. for (index = api_max; index >= api_min; index--) {
  1151. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1152. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1153. if (ret < 0) {
  1154. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1155. buf, ret);
  1156. if (ret == -ENOENT)
  1157. continue;
  1158. else
  1159. goto error;
  1160. } else {
  1161. if (index < api_max)
  1162. IWL_ERR(priv, "Loaded firmware %s, "
  1163. "which is deprecated. "
  1164. "Please use API v%u instead.\n",
  1165. buf, api_max);
  1166. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1167. buf, ucode_raw->size);
  1168. break;
  1169. }
  1170. }
  1171. if (ret < 0)
  1172. goto error;
  1173. /* Make sure that we got at least the v1 header! */
  1174. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1175. IWL_ERR(priv, "File size way too small!\n");
  1176. ret = -EINVAL;
  1177. goto err_release;
  1178. }
  1179. /* Data from ucode file: header followed by uCode images */
  1180. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1181. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1182. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1183. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1184. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1185. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1186. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1187. init_data_size =
  1188. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1189. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1190. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1191. /* api_ver should match the api version forming part of the
  1192. * firmware filename ... but we don't check for that and only rely
  1193. * on the API version read from firmware header from here on forward */
  1194. if (api_ver < api_min || api_ver > api_max) {
  1195. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1196. "Driver supports v%u, firmware is v%u.\n",
  1197. api_max, api_ver);
  1198. priv->ucode_ver = 0;
  1199. ret = -EINVAL;
  1200. goto err_release;
  1201. }
  1202. if (api_ver != api_max)
  1203. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1204. "got v%u. New firmware can be obtained "
  1205. "from http://www.intellinuxwireless.org.\n",
  1206. api_max, api_ver);
  1207. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1208. IWL_UCODE_MAJOR(priv->ucode_ver),
  1209. IWL_UCODE_MINOR(priv->ucode_ver),
  1210. IWL_UCODE_API(priv->ucode_ver),
  1211. IWL_UCODE_SERIAL(priv->ucode_ver));
  1212. snprintf(priv->hw->wiphy->fw_version,
  1213. sizeof(priv->hw->wiphy->fw_version),
  1214. "%u.%u.%u.%u",
  1215. IWL_UCODE_MAJOR(priv->ucode_ver),
  1216. IWL_UCODE_MINOR(priv->ucode_ver),
  1217. IWL_UCODE_API(priv->ucode_ver),
  1218. IWL_UCODE_SERIAL(priv->ucode_ver));
  1219. if (build)
  1220. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1221. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1222. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1223. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1224. ? "OTP" : "EEPROM", eeprom_ver);
  1225. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1226. priv->ucode_ver);
  1227. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1228. inst_size);
  1229. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1230. data_size);
  1231. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1232. init_size);
  1233. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1234. init_data_size);
  1235. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1236. boot_size);
  1237. /* Verify size of file vs. image size info in file's header */
  1238. if (ucode_raw->size !=
  1239. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1240. inst_size + data_size + init_size +
  1241. init_data_size + boot_size) {
  1242. IWL_DEBUG_INFO(priv,
  1243. "uCode file size %d does not match expected size\n",
  1244. (int)ucode_raw->size);
  1245. ret = -EINVAL;
  1246. goto err_release;
  1247. }
  1248. /* Verify that uCode images will fit in card's SRAM */
  1249. if (inst_size > priv->hw_params.max_inst_size) {
  1250. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1251. inst_size);
  1252. ret = -EINVAL;
  1253. goto err_release;
  1254. }
  1255. if (data_size > priv->hw_params.max_data_size) {
  1256. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1257. data_size);
  1258. ret = -EINVAL;
  1259. goto err_release;
  1260. }
  1261. if (init_size > priv->hw_params.max_inst_size) {
  1262. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1263. init_size);
  1264. ret = -EINVAL;
  1265. goto err_release;
  1266. }
  1267. if (init_data_size > priv->hw_params.max_data_size) {
  1268. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1269. init_data_size);
  1270. ret = -EINVAL;
  1271. goto err_release;
  1272. }
  1273. if (boot_size > priv->hw_params.max_bsm_size) {
  1274. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1275. boot_size);
  1276. ret = -EINVAL;
  1277. goto err_release;
  1278. }
  1279. /* Allocate ucode buffers for card's bus-master loading ... */
  1280. /* Runtime instructions and 2 copies of data:
  1281. * 1) unmodified from disk
  1282. * 2) backup cache for save/restore during power-downs */
  1283. priv->ucode_code.len = inst_size;
  1284. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1285. priv->ucode_data.len = data_size;
  1286. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1287. priv->ucode_data_backup.len = data_size;
  1288. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1289. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1290. !priv->ucode_data_backup.v_addr)
  1291. goto err_pci_alloc;
  1292. /* Initialization instructions and data */
  1293. if (init_size && init_data_size) {
  1294. priv->ucode_init.len = init_size;
  1295. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1296. priv->ucode_init_data.len = init_data_size;
  1297. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1298. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1299. goto err_pci_alloc;
  1300. }
  1301. /* Bootstrap (instructions only, no data) */
  1302. if (boot_size) {
  1303. priv->ucode_boot.len = boot_size;
  1304. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1305. if (!priv->ucode_boot.v_addr)
  1306. goto err_pci_alloc;
  1307. }
  1308. /* Copy images into buffers for card's bus-master reads ... */
  1309. /* Runtime instructions (first block of data in file) */
  1310. len = inst_size;
  1311. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1312. memcpy(priv->ucode_code.v_addr, src, len);
  1313. src += len;
  1314. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1315. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1316. /* Runtime data (2nd block)
  1317. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1318. len = data_size;
  1319. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1320. memcpy(priv->ucode_data.v_addr, src, len);
  1321. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1322. src += len;
  1323. /* Initialization instructions (3rd block) */
  1324. if (init_size) {
  1325. len = init_size;
  1326. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1327. len);
  1328. memcpy(priv->ucode_init.v_addr, src, len);
  1329. src += len;
  1330. }
  1331. /* Initialization data (4th block) */
  1332. if (init_data_size) {
  1333. len = init_data_size;
  1334. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1335. len);
  1336. memcpy(priv->ucode_init_data.v_addr, src, len);
  1337. src += len;
  1338. }
  1339. /* Bootstrap instructions (5th block) */
  1340. len = boot_size;
  1341. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1342. memcpy(priv->ucode_boot.v_addr, src, len);
  1343. /* We have our copies now, allow OS release its copies */
  1344. release_firmware(ucode_raw);
  1345. return 0;
  1346. err_pci_alloc:
  1347. IWL_ERR(priv, "failed to allocate pci memory\n");
  1348. ret = -ENOMEM;
  1349. iwl_dealloc_ucode_pci(priv);
  1350. err_release:
  1351. release_firmware(ucode_raw);
  1352. error:
  1353. return ret;
  1354. }
  1355. static const char *desc_lookup_text[] = {
  1356. "OK",
  1357. "FAIL",
  1358. "BAD_PARAM",
  1359. "BAD_CHECKSUM",
  1360. "NMI_INTERRUPT_WDG",
  1361. "SYSASSERT",
  1362. "FATAL_ERROR",
  1363. "BAD_COMMAND",
  1364. "HW_ERROR_TUNE_LOCK",
  1365. "HW_ERROR_TEMPERATURE",
  1366. "ILLEGAL_CHAN_FREQ",
  1367. "VCC_NOT_STABLE",
  1368. "FH_ERROR",
  1369. "NMI_INTERRUPT_HOST",
  1370. "NMI_INTERRUPT_ACTION_PT",
  1371. "NMI_INTERRUPT_UNKNOWN",
  1372. "UCODE_VERSION_MISMATCH",
  1373. "HW_ERROR_ABS_LOCK",
  1374. "HW_ERROR_CAL_LOCK_FAIL",
  1375. "NMI_INTERRUPT_INST_ACTION_PT",
  1376. "NMI_INTERRUPT_DATA_ACTION_PT",
  1377. "NMI_TRM_HW_ER",
  1378. "NMI_INTERRUPT_TRM",
  1379. "NMI_INTERRUPT_BREAK_POINT"
  1380. "DEBUG_0",
  1381. "DEBUG_1",
  1382. "DEBUG_2",
  1383. "DEBUG_3",
  1384. "UNKNOWN"
  1385. };
  1386. static const char *desc_lookup(int i)
  1387. {
  1388. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1389. if (i < 0 || i > max)
  1390. i = max;
  1391. return desc_lookup_text[i];
  1392. }
  1393. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1394. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1395. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1396. {
  1397. u32 data2, line;
  1398. u32 desc, time, count, base, data1;
  1399. u32 blink1, blink2, ilink1, ilink2;
  1400. if (priv->ucode_type == UCODE_INIT)
  1401. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1402. else
  1403. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1404. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1405. IWL_ERR(priv,
  1406. "Not valid error log pointer 0x%08X for %s uCode\n",
  1407. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1408. return;
  1409. }
  1410. count = iwl_read_targ_mem(priv, base);
  1411. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1412. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1413. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1414. priv->status, count);
  1415. }
  1416. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1417. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1418. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1419. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1420. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1421. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1422. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1423. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1424. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1425. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1426. blink1, blink2, ilink1, ilink2);
  1427. IWL_ERR(priv, "Desc Time "
  1428. "data1 data2 line\n");
  1429. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1430. desc_lookup(desc), desc, time, data1, data2, line);
  1431. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1432. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1433. ilink1, ilink2);
  1434. }
  1435. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1436. /**
  1437. * iwl_print_event_log - Dump error event log to syslog
  1438. *
  1439. */
  1440. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1441. u32 num_events, u32 mode)
  1442. {
  1443. u32 i;
  1444. u32 base; /* SRAM byte address of event log header */
  1445. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1446. u32 ptr; /* SRAM byte address of log data */
  1447. u32 ev, time, data; /* event log data */
  1448. unsigned long reg_flags;
  1449. if (num_events == 0)
  1450. return;
  1451. if (priv->ucode_type == UCODE_INIT)
  1452. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1453. else
  1454. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1455. if (mode == 0)
  1456. event_size = 2 * sizeof(u32);
  1457. else
  1458. event_size = 3 * sizeof(u32);
  1459. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1460. /* Make sure device is powered up for SRAM reads */
  1461. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1462. iwl_grab_nic_access(priv);
  1463. /* Set starting address; reads will auto-increment */
  1464. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1465. rmb();
  1466. /* "time" is actually "data" for mode 0 (no timestamp).
  1467. * place event id # at far right for easier visual parsing. */
  1468. for (i = 0; i < num_events; i++) {
  1469. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1470. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1471. if (mode == 0) {
  1472. /* data, ev */
  1473. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1474. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1475. } else {
  1476. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1477. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1478. time, data, ev);
  1479. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1480. }
  1481. }
  1482. /* Allow device to power down */
  1483. iwl_release_nic_access(priv);
  1484. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1485. }
  1486. /**
  1487. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1488. */
  1489. static void iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1490. u32 num_wraps, u32 next_entry,
  1491. u32 size, u32 mode)
  1492. {
  1493. /*
  1494. * display the newest DEFAULT_LOG_ENTRIES entries
  1495. * i.e the entries just before the next ont that uCode would fill.
  1496. */
  1497. if (num_wraps) {
  1498. if (next_entry < size) {
  1499. iwl_print_event_log(priv,
  1500. capacity - (size - next_entry),
  1501. size - next_entry, mode);
  1502. iwl_print_event_log(priv, 0,
  1503. next_entry, mode);
  1504. } else
  1505. iwl_print_event_log(priv, next_entry - size,
  1506. size, mode);
  1507. } else {
  1508. if (next_entry < size)
  1509. iwl_print_event_log(priv, 0, next_entry, mode);
  1510. else
  1511. iwl_print_event_log(priv, next_entry - size,
  1512. size, mode);
  1513. }
  1514. }
  1515. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1516. #define MAX_EVENT_LOG_SIZE (512)
  1517. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1518. void iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log)
  1519. {
  1520. u32 base; /* SRAM byte address of event log header */
  1521. u32 capacity; /* event log capacity in # entries */
  1522. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1523. u32 num_wraps; /* # times uCode wrapped to top of log */
  1524. u32 next_entry; /* index of next entry to be written by uCode */
  1525. u32 size; /* # entries that we'll print */
  1526. if (priv->ucode_type == UCODE_INIT)
  1527. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1528. else
  1529. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1530. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1531. IWL_ERR(priv,
  1532. "Invalid event log pointer 0x%08X for %s uCode\n",
  1533. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1534. return;
  1535. }
  1536. /* event log header */
  1537. capacity = iwl_read_targ_mem(priv, base);
  1538. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1539. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1540. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1541. if (capacity > MAX_EVENT_LOG_SIZE) {
  1542. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1543. capacity, MAX_EVENT_LOG_SIZE);
  1544. capacity = MAX_EVENT_LOG_SIZE;
  1545. }
  1546. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1547. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1548. next_entry, MAX_EVENT_LOG_SIZE);
  1549. next_entry = MAX_EVENT_LOG_SIZE;
  1550. }
  1551. size = num_wraps ? capacity : next_entry;
  1552. /* bail out if nothing in log */
  1553. if (size == 0) {
  1554. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1555. return;
  1556. }
  1557. #ifdef CONFIG_IWLWIFI_DEBUG
  1558. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS))
  1559. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1560. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1561. #else
  1562. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1563. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1564. #endif
  1565. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1566. size);
  1567. #ifdef CONFIG_IWLWIFI_DEBUG
  1568. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1569. /*
  1570. * if uCode has wrapped back to top of log,
  1571. * start at the oldest entry,
  1572. * i.e the next one that uCode would fill.
  1573. */
  1574. if (num_wraps)
  1575. iwl_print_event_log(priv, next_entry,
  1576. capacity - next_entry, mode);
  1577. /* (then/else) start at top of log */
  1578. iwl_print_event_log(priv, 0, next_entry, mode);
  1579. } else
  1580. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1581. next_entry, size, mode);
  1582. #else
  1583. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1584. next_entry, size, mode);
  1585. #endif
  1586. }
  1587. /**
  1588. * iwl_alive_start - called after REPLY_ALIVE notification received
  1589. * from protocol/runtime uCode (initialization uCode's
  1590. * Alive gets handled by iwl_init_alive_start()).
  1591. */
  1592. static void iwl_alive_start(struct iwl_priv *priv)
  1593. {
  1594. int ret = 0;
  1595. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1596. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1597. /* We had an error bringing up the hardware, so take it
  1598. * all the way back down so we can try again */
  1599. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1600. goto restart;
  1601. }
  1602. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1603. * This is a paranoid check, because we would not have gotten the
  1604. * "runtime" alive if code weren't properly loaded. */
  1605. if (iwl_verify_ucode(priv)) {
  1606. /* Runtime instruction load was bad;
  1607. * take it all the way back down so we can try again */
  1608. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1609. goto restart;
  1610. }
  1611. iwl_clear_stations_table(priv);
  1612. ret = priv->cfg->ops->lib->alive_notify(priv);
  1613. if (ret) {
  1614. IWL_WARN(priv,
  1615. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1616. goto restart;
  1617. }
  1618. /* After the ALIVE response, we can send host commands to the uCode */
  1619. set_bit(STATUS_ALIVE, &priv->status);
  1620. if (iwl_is_rfkill(priv))
  1621. return;
  1622. ieee80211_wake_queues(priv->hw);
  1623. priv->active_rate = priv->rates_mask;
  1624. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1625. /* Configure Tx antenna selection based on H/W config */
  1626. if (priv->cfg->ops->hcmd->set_tx_ant)
  1627. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1628. if (iwl_is_associated(priv)) {
  1629. struct iwl_rxon_cmd *active_rxon =
  1630. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1631. /* apply any changes in staging */
  1632. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1633. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1634. } else {
  1635. /* Initialize our rx_config data */
  1636. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1637. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1638. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1639. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1640. }
  1641. /* Configure Bluetooth device coexistence support */
  1642. iwl_send_bt_config(priv);
  1643. iwl_reset_run_time_calib(priv);
  1644. /* Configure the adapter for unassociated operation */
  1645. iwlcore_commit_rxon(priv);
  1646. /* At this point, the NIC is initialized and operational */
  1647. iwl_rf_kill_ct_config(priv);
  1648. iwl_leds_init(priv);
  1649. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1650. set_bit(STATUS_READY, &priv->status);
  1651. wake_up_interruptible(&priv->wait_command_queue);
  1652. iwl_power_update_mode(priv, true);
  1653. /* reassociate for ADHOC mode */
  1654. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1655. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1656. priv->vif);
  1657. if (beacon)
  1658. iwl_mac_beacon_update(priv->hw, beacon);
  1659. }
  1660. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1661. iwl_set_mode(priv, priv->iw_mode);
  1662. return;
  1663. restart:
  1664. queue_work(priv->workqueue, &priv->restart);
  1665. }
  1666. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1667. static void __iwl_down(struct iwl_priv *priv)
  1668. {
  1669. unsigned long flags;
  1670. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1671. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1672. if (!exit_pending)
  1673. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1674. iwl_clear_stations_table(priv);
  1675. /* Unblock any waiting calls */
  1676. wake_up_interruptible_all(&priv->wait_command_queue);
  1677. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1678. * exiting the module */
  1679. if (!exit_pending)
  1680. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1681. /* stop and reset the on-board processor */
  1682. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1683. /* tell the device to stop sending interrupts */
  1684. spin_lock_irqsave(&priv->lock, flags);
  1685. iwl_disable_interrupts(priv);
  1686. spin_unlock_irqrestore(&priv->lock, flags);
  1687. iwl_synchronize_irq(priv);
  1688. if (priv->mac80211_registered)
  1689. ieee80211_stop_queues(priv->hw);
  1690. /* If we have not previously called iwl_init() then
  1691. * clear all bits but the RF Kill bit and return */
  1692. if (!iwl_is_init(priv)) {
  1693. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1694. STATUS_RF_KILL_HW |
  1695. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1696. STATUS_GEO_CONFIGURED |
  1697. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1698. STATUS_EXIT_PENDING;
  1699. goto exit;
  1700. }
  1701. /* ...otherwise clear out all the status bits but the RF Kill
  1702. * bit and continue taking the NIC down. */
  1703. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1704. STATUS_RF_KILL_HW |
  1705. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1706. STATUS_GEO_CONFIGURED |
  1707. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1708. STATUS_FW_ERROR |
  1709. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1710. STATUS_EXIT_PENDING;
  1711. /* device going down, Stop using ICT table */
  1712. iwl_disable_ict(priv);
  1713. iwl_txq_ctx_stop(priv);
  1714. iwl_rxq_stop(priv);
  1715. /* Power-down device's busmaster DMA clocks */
  1716. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1717. udelay(5);
  1718. /* Make sure (redundant) we've released our request to stay awake */
  1719. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1720. /* Stop the device, and put it in low power state */
  1721. priv->cfg->ops->lib->apm_ops.stop(priv);
  1722. exit:
  1723. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1724. if (priv->ibss_beacon)
  1725. dev_kfree_skb(priv->ibss_beacon);
  1726. priv->ibss_beacon = NULL;
  1727. /* clear out any free frames */
  1728. iwl_clear_free_frames(priv);
  1729. }
  1730. static void iwl_down(struct iwl_priv *priv)
  1731. {
  1732. mutex_lock(&priv->mutex);
  1733. __iwl_down(priv);
  1734. mutex_unlock(&priv->mutex);
  1735. iwl_cancel_deferred_work(priv);
  1736. }
  1737. #define HW_READY_TIMEOUT (50)
  1738. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1739. {
  1740. int ret = 0;
  1741. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1742. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1743. /* See if we got it */
  1744. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1745. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1746. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1747. HW_READY_TIMEOUT);
  1748. if (ret != -ETIMEDOUT)
  1749. priv->hw_ready = true;
  1750. else
  1751. priv->hw_ready = false;
  1752. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1753. (priv->hw_ready == 1) ? "ready" : "not ready");
  1754. return ret;
  1755. }
  1756. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1757. {
  1758. int ret = 0;
  1759. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1760. ret = iwl_set_hw_ready(priv);
  1761. if (priv->hw_ready)
  1762. return ret;
  1763. /* If HW is not ready, prepare the conditions to check again */
  1764. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1765. CSR_HW_IF_CONFIG_REG_PREPARE);
  1766. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1767. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1768. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1769. /* HW should be ready by now, check again. */
  1770. if (ret != -ETIMEDOUT)
  1771. iwl_set_hw_ready(priv);
  1772. return ret;
  1773. }
  1774. #define MAX_HW_RESTARTS 5
  1775. static int __iwl_up(struct iwl_priv *priv)
  1776. {
  1777. int i;
  1778. int ret;
  1779. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1780. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1781. return -EIO;
  1782. }
  1783. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1784. IWL_ERR(priv, "ucode not available for device bringup\n");
  1785. return -EIO;
  1786. }
  1787. iwl_prepare_card_hw(priv);
  1788. if (!priv->hw_ready) {
  1789. IWL_WARN(priv, "Exit HW not ready\n");
  1790. return -EIO;
  1791. }
  1792. /* If platform's RF_KILL switch is NOT set to KILL */
  1793. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1794. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1795. else
  1796. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1797. if (iwl_is_rfkill(priv)) {
  1798. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1799. iwl_enable_interrupts(priv);
  1800. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1801. return 0;
  1802. }
  1803. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1804. ret = iwl_hw_nic_init(priv);
  1805. if (ret) {
  1806. IWL_ERR(priv, "Unable to init nic\n");
  1807. return ret;
  1808. }
  1809. /* make sure rfkill handshake bits are cleared */
  1810. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1811. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1812. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1813. /* clear (again), then enable host interrupts */
  1814. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1815. iwl_enable_interrupts(priv);
  1816. /* really make sure rfkill handshake bits are cleared */
  1817. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1818. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1819. /* Copy original ucode data image from disk into backup cache.
  1820. * This will be used to initialize the on-board processor's
  1821. * data SRAM for a clean start when the runtime program first loads. */
  1822. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1823. priv->ucode_data.len);
  1824. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1825. iwl_clear_stations_table(priv);
  1826. /* load bootstrap state machine,
  1827. * load bootstrap program into processor's memory,
  1828. * prepare to load the "initialize" uCode */
  1829. ret = priv->cfg->ops->lib->load_ucode(priv);
  1830. if (ret) {
  1831. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1832. ret);
  1833. continue;
  1834. }
  1835. /* start card; "initialize" will load runtime ucode */
  1836. iwl_nic_start(priv);
  1837. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1838. return 0;
  1839. }
  1840. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1841. __iwl_down(priv);
  1842. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1843. /* tried to restart and config the device for as long as our
  1844. * patience could withstand */
  1845. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1846. return -EIO;
  1847. }
  1848. /*****************************************************************************
  1849. *
  1850. * Workqueue callbacks
  1851. *
  1852. *****************************************************************************/
  1853. static void iwl_bg_init_alive_start(struct work_struct *data)
  1854. {
  1855. struct iwl_priv *priv =
  1856. container_of(data, struct iwl_priv, init_alive_start.work);
  1857. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1858. return;
  1859. mutex_lock(&priv->mutex);
  1860. priv->cfg->ops->lib->init_alive_start(priv);
  1861. mutex_unlock(&priv->mutex);
  1862. }
  1863. static void iwl_bg_alive_start(struct work_struct *data)
  1864. {
  1865. struct iwl_priv *priv =
  1866. container_of(data, struct iwl_priv, alive_start.work);
  1867. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1868. return;
  1869. /* enable dram interrupt */
  1870. iwl_reset_ict(priv);
  1871. mutex_lock(&priv->mutex);
  1872. iwl_alive_start(priv);
  1873. mutex_unlock(&priv->mutex);
  1874. }
  1875. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1876. {
  1877. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1878. run_time_calib_work);
  1879. mutex_lock(&priv->mutex);
  1880. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1881. test_bit(STATUS_SCANNING, &priv->status)) {
  1882. mutex_unlock(&priv->mutex);
  1883. return;
  1884. }
  1885. if (priv->start_calib) {
  1886. iwl_chain_noise_calibration(priv, &priv->statistics);
  1887. iwl_sensitivity_calibration(priv, &priv->statistics);
  1888. }
  1889. mutex_unlock(&priv->mutex);
  1890. return;
  1891. }
  1892. static void iwl_bg_up(struct work_struct *data)
  1893. {
  1894. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1895. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1896. return;
  1897. mutex_lock(&priv->mutex);
  1898. __iwl_up(priv);
  1899. mutex_unlock(&priv->mutex);
  1900. }
  1901. static void iwl_bg_restart(struct work_struct *data)
  1902. {
  1903. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1904. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1905. return;
  1906. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1907. mutex_lock(&priv->mutex);
  1908. priv->vif = NULL;
  1909. priv->is_open = 0;
  1910. mutex_unlock(&priv->mutex);
  1911. iwl_down(priv);
  1912. ieee80211_restart_hw(priv->hw);
  1913. } else {
  1914. iwl_down(priv);
  1915. queue_work(priv->workqueue, &priv->up);
  1916. }
  1917. }
  1918. static void iwl_bg_rx_replenish(struct work_struct *data)
  1919. {
  1920. struct iwl_priv *priv =
  1921. container_of(data, struct iwl_priv, rx_replenish);
  1922. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1923. return;
  1924. mutex_lock(&priv->mutex);
  1925. iwl_rx_replenish(priv);
  1926. mutex_unlock(&priv->mutex);
  1927. }
  1928. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1929. void iwl_post_associate(struct iwl_priv *priv)
  1930. {
  1931. struct ieee80211_conf *conf = NULL;
  1932. int ret = 0;
  1933. unsigned long flags;
  1934. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1935. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1936. return;
  1937. }
  1938. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1939. priv->assoc_id, priv->active_rxon.bssid_addr);
  1940. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1941. return;
  1942. if (!priv->vif || !priv->is_open)
  1943. return;
  1944. iwl_scan_cancel_timeout(priv, 200);
  1945. conf = ieee80211_get_hw_conf(priv->hw);
  1946. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1947. iwlcore_commit_rxon(priv);
  1948. iwl_setup_rxon_timing(priv);
  1949. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1950. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1951. if (ret)
  1952. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1953. "Attempting to continue.\n");
  1954. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1955. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1956. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1957. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1958. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1959. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1960. priv->assoc_id, priv->beacon_int);
  1961. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1962. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1963. else
  1964. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1965. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1966. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1967. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1968. else
  1969. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1970. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1971. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1972. }
  1973. iwlcore_commit_rxon(priv);
  1974. switch (priv->iw_mode) {
  1975. case NL80211_IFTYPE_STATION:
  1976. break;
  1977. case NL80211_IFTYPE_ADHOC:
  1978. /* assume default assoc id */
  1979. priv->assoc_id = 1;
  1980. iwl_rxon_add_station(priv, priv->bssid, 0);
  1981. iwl_send_beacon_cmd(priv);
  1982. break;
  1983. default:
  1984. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1985. __func__, priv->iw_mode);
  1986. break;
  1987. }
  1988. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1989. priv->assoc_station_added = 1;
  1990. spin_lock_irqsave(&priv->lock, flags);
  1991. iwl_activate_qos(priv, 0);
  1992. spin_unlock_irqrestore(&priv->lock, flags);
  1993. /* the chain noise calibration will enabled PM upon completion
  1994. * If chain noise has already been run, then we need to enable
  1995. * power management here */
  1996. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1997. iwl_power_update_mode(priv, false);
  1998. /* Enable Rx differential gain and sensitivity calibrations */
  1999. iwl_chain_noise_reset(priv);
  2000. priv->start_calib = 1;
  2001. }
  2002. /*****************************************************************************
  2003. *
  2004. * mac80211 entry point functions
  2005. *
  2006. *****************************************************************************/
  2007. #define UCODE_READY_TIMEOUT (4 * HZ)
  2008. /*
  2009. * Not a mac80211 entry point function, but it fits in with all the
  2010. * other mac80211 functions grouped here.
  2011. */
  2012. static int iwl_setup_mac(struct iwl_priv *priv)
  2013. {
  2014. int ret;
  2015. struct ieee80211_hw *hw = priv->hw;
  2016. hw->rate_control_algorithm = "iwl-agn-rs";
  2017. /* Tell mac80211 our characteristics */
  2018. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2019. IEEE80211_HW_NOISE_DBM |
  2020. IEEE80211_HW_AMPDU_AGGREGATION |
  2021. IEEE80211_HW_SPECTRUM_MGMT;
  2022. if (!priv->cfg->broken_powersave)
  2023. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2024. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2025. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2026. hw->wiphy->interface_modes =
  2027. BIT(NL80211_IFTYPE_STATION) |
  2028. BIT(NL80211_IFTYPE_ADHOC);
  2029. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2030. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2031. /*
  2032. * For now, disable PS by default because it affects
  2033. * RX performance significantly.
  2034. */
  2035. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2036. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2037. /* we create the 802.11 header and a zero-length SSID element */
  2038. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2039. /* Default value; 4 EDCA QOS priorities */
  2040. hw->queues = 4;
  2041. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2042. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2043. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2044. &priv->bands[IEEE80211_BAND_2GHZ];
  2045. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2046. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2047. &priv->bands[IEEE80211_BAND_5GHZ];
  2048. ret = ieee80211_register_hw(priv->hw);
  2049. if (ret) {
  2050. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2051. return ret;
  2052. }
  2053. priv->mac80211_registered = 1;
  2054. return 0;
  2055. }
  2056. static int iwl_mac_start(struct ieee80211_hw *hw)
  2057. {
  2058. struct iwl_priv *priv = hw->priv;
  2059. int ret;
  2060. IWL_DEBUG_MAC80211(priv, "enter\n");
  2061. /* we should be verifying the device is ready to be opened */
  2062. mutex_lock(&priv->mutex);
  2063. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2064. * ucode filename and max sizes are card-specific. */
  2065. if (!priv->ucode_code.len) {
  2066. ret = iwl_read_ucode(priv);
  2067. if (ret) {
  2068. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2069. mutex_unlock(&priv->mutex);
  2070. return ret;
  2071. }
  2072. }
  2073. ret = __iwl_up(priv);
  2074. mutex_unlock(&priv->mutex);
  2075. if (ret)
  2076. return ret;
  2077. if (iwl_is_rfkill(priv))
  2078. goto out;
  2079. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2080. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2081. * mac80211 will not be run successfully. */
  2082. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2083. test_bit(STATUS_READY, &priv->status),
  2084. UCODE_READY_TIMEOUT);
  2085. if (!ret) {
  2086. if (!test_bit(STATUS_READY, &priv->status)) {
  2087. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2088. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2089. return -ETIMEDOUT;
  2090. }
  2091. }
  2092. iwl_led_start(priv);
  2093. out:
  2094. priv->is_open = 1;
  2095. IWL_DEBUG_MAC80211(priv, "leave\n");
  2096. return 0;
  2097. }
  2098. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2099. {
  2100. struct iwl_priv *priv = hw->priv;
  2101. IWL_DEBUG_MAC80211(priv, "enter\n");
  2102. if (!priv->is_open)
  2103. return;
  2104. priv->is_open = 0;
  2105. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2106. /* stop mac, cancel any scan request and clear
  2107. * RXON_FILTER_ASSOC_MSK BIT
  2108. */
  2109. mutex_lock(&priv->mutex);
  2110. iwl_scan_cancel_timeout(priv, 100);
  2111. mutex_unlock(&priv->mutex);
  2112. }
  2113. iwl_down(priv);
  2114. flush_workqueue(priv->workqueue);
  2115. /* enable interrupts again in order to receive rfkill changes */
  2116. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2117. iwl_enable_interrupts(priv);
  2118. IWL_DEBUG_MAC80211(priv, "leave\n");
  2119. }
  2120. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2121. {
  2122. struct iwl_priv *priv = hw->priv;
  2123. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2124. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2125. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2126. if (iwl_tx_skb(priv, skb))
  2127. dev_kfree_skb_any(skb);
  2128. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2129. return NETDEV_TX_OK;
  2130. }
  2131. void iwl_config_ap(struct iwl_priv *priv)
  2132. {
  2133. int ret = 0;
  2134. unsigned long flags;
  2135. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2136. return;
  2137. /* The following should be done only at AP bring up */
  2138. if (!iwl_is_associated(priv)) {
  2139. /* RXON - unassoc (to set timing command) */
  2140. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2141. iwlcore_commit_rxon(priv);
  2142. /* RXON Timing */
  2143. iwl_setup_rxon_timing(priv);
  2144. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2145. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2146. if (ret)
  2147. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2148. "Attempting to continue.\n");
  2149. /* AP has all antennas */
  2150. priv->chain_noise_data.active_chains =
  2151. priv->hw_params.valid_rx_ant;
  2152. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2153. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2154. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2155. /* FIXME: what should be the assoc_id for AP? */
  2156. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2157. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2158. priv->staging_rxon.flags |=
  2159. RXON_FLG_SHORT_PREAMBLE_MSK;
  2160. else
  2161. priv->staging_rxon.flags &=
  2162. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2163. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2164. if (priv->assoc_capability &
  2165. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2166. priv->staging_rxon.flags |=
  2167. RXON_FLG_SHORT_SLOT_MSK;
  2168. else
  2169. priv->staging_rxon.flags &=
  2170. ~RXON_FLG_SHORT_SLOT_MSK;
  2171. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2172. priv->staging_rxon.flags &=
  2173. ~RXON_FLG_SHORT_SLOT_MSK;
  2174. }
  2175. /* restore RXON assoc */
  2176. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2177. iwlcore_commit_rxon(priv);
  2178. iwl_reset_qos(priv);
  2179. spin_lock_irqsave(&priv->lock, flags);
  2180. iwl_activate_qos(priv, 1);
  2181. spin_unlock_irqrestore(&priv->lock, flags);
  2182. iwl_add_bcast_station(priv);
  2183. }
  2184. iwl_send_beacon_cmd(priv);
  2185. /* FIXME - we need to add code here to detect a totally new
  2186. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2187. * clear sta table, add BCAST sta... */
  2188. }
  2189. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2190. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2191. u32 iv32, u16 *phase1key)
  2192. {
  2193. struct iwl_priv *priv = hw->priv;
  2194. IWL_DEBUG_MAC80211(priv, "enter\n");
  2195. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2196. IWL_DEBUG_MAC80211(priv, "leave\n");
  2197. }
  2198. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2199. struct ieee80211_vif *vif,
  2200. struct ieee80211_sta *sta,
  2201. struct ieee80211_key_conf *key)
  2202. {
  2203. struct iwl_priv *priv = hw->priv;
  2204. const u8 *addr;
  2205. int ret;
  2206. u8 sta_id;
  2207. bool is_default_wep_key = false;
  2208. IWL_DEBUG_MAC80211(priv, "enter\n");
  2209. if (priv->cfg->mod_params->sw_crypto) {
  2210. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2211. return -EOPNOTSUPP;
  2212. }
  2213. addr = sta ? sta->addr : iwl_bcast_addr;
  2214. sta_id = iwl_find_station(priv, addr);
  2215. if (sta_id == IWL_INVALID_STATION) {
  2216. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2217. addr);
  2218. return -EINVAL;
  2219. }
  2220. mutex_lock(&priv->mutex);
  2221. iwl_scan_cancel_timeout(priv, 100);
  2222. mutex_unlock(&priv->mutex);
  2223. /* If we are getting WEP group key and we didn't receive any key mapping
  2224. * so far, we are in legacy wep mode (group key only), otherwise we are
  2225. * in 1X mode.
  2226. * In legacy wep mode, we use another host command to the uCode */
  2227. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2228. priv->iw_mode != NL80211_IFTYPE_AP) {
  2229. if (cmd == SET_KEY)
  2230. is_default_wep_key = !priv->key_mapping_key;
  2231. else
  2232. is_default_wep_key =
  2233. (key->hw_key_idx == HW_KEY_DEFAULT);
  2234. }
  2235. switch (cmd) {
  2236. case SET_KEY:
  2237. if (is_default_wep_key)
  2238. ret = iwl_set_default_wep_key(priv, key);
  2239. else
  2240. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2241. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2242. break;
  2243. case DISABLE_KEY:
  2244. if (is_default_wep_key)
  2245. ret = iwl_remove_default_wep_key(priv, key);
  2246. else
  2247. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2248. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2249. break;
  2250. default:
  2251. ret = -EINVAL;
  2252. }
  2253. IWL_DEBUG_MAC80211(priv, "leave\n");
  2254. return ret;
  2255. }
  2256. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2257. struct ieee80211_vif *vif,
  2258. enum ieee80211_ampdu_mlme_action action,
  2259. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2260. {
  2261. struct iwl_priv *priv = hw->priv;
  2262. int ret;
  2263. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2264. sta->addr, tid);
  2265. if (!(priv->cfg->sku & IWL_SKU_N))
  2266. return -EACCES;
  2267. switch (action) {
  2268. case IEEE80211_AMPDU_RX_START:
  2269. IWL_DEBUG_HT(priv, "start Rx\n");
  2270. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2271. case IEEE80211_AMPDU_RX_STOP:
  2272. IWL_DEBUG_HT(priv, "stop Rx\n");
  2273. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2274. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2275. return 0;
  2276. else
  2277. return ret;
  2278. case IEEE80211_AMPDU_TX_START:
  2279. IWL_DEBUG_HT(priv, "start Tx\n");
  2280. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2281. case IEEE80211_AMPDU_TX_STOP:
  2282. IWL_DEBUG_HT(priv, "stop Tx\n");
  2283. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2284. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2285. return 0;
  2286. else
  2287. return ret;
  2288. default:
  2289. IWL_DEBUG_HT(priv, "unknown\n");
  2290. return -EINVAL;
  2291. break;
  2292. }
  2293. return 0;
  2294. }
  2295. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2296. struct ieee80211_low_level_stats *stats)
  2297. {
  2298. struct iwl_priv *priv = hw->priv;
  2299. priv = hw->priv;
  2300. IWL_DEBUG_MAC80211(priv, "enter\n");
  2301. IWL_DEBUG_MAC80211(priv, "leave\n");
  2302. return 0;
  2303. }
  2304. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2305. struct ieee80211_vif *vif,
  2306. enum sta_notify_cmd cmd,
  2307. struct ieee80211_sta *sta)
  2308. {
  2309. struct iwl_priv *priv = hw->priv;
  2310. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2311. int sta_id;
  2312. /*
  2313. * TODO: We really should use this callback to
  2314. * actually maintain the station table in
  2315. * the device.
  2316. */
  2317. switch (cmd) {
  2318. case STA_NOTIFY_ADD:
  2319. atomic_set(&sta_priv->pending_frames, 0);
  2320. if (vif->type == NL80211_IFTYPE_AP)
  2321. sta_priv->client = true;
  2322. break;
  2323. case STA_NOTIFY_SLEEP:
  2324. WARN_ON(!sta_priv->client);
  2325. sta_priv->asleep = true;
  2326. if (atomic_read(&sta_priv->pending_frames) > 0)
  2327. ieee80211_sta_block_awake(hw, sta, true);
  2328. break;
  2329. case STA_NOTIFY_AWAKE:
  2330. WARN_ON(!sta_priv->client);
  2331. sta_priv->asleep = false;
  2332. sta_id = iwl_find_station(priv, sta->addr);
  2333. if (sta_id != IWL_INVALID_STATION)
  2334. iwl_sta_modify_ps_wake(priv, sta_id);
  2335. break;
  2336. default:
  2337. break;
  2338. }
  2339. }
  2340. /*****************************************************************************
  2341. *
  2342. * sysfs attributes
  2343. *
  2344. *****************************************************************************/
  2345. #ifdef CONFIG_IWLWIFI_DEBUG
  2346. /*
  2347. * The following adds a new attribute to the sysfs representation
  2348. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2349. * used for controlling the debug level.
  2350. *
  2351. * See the level definitions in iwl for details.
  2352. *
  2353. * The debug_level being managed using sysfs below is a per device debug
  2354. * level that is used instead of the global debug level if it (the per
  2355. * device debug level) is set.
  2356. */
  2357. static ssize_t show_debug_level(struct device *d,
  2358. struct device_attribute *attr, char *buf)
  2359. {
  2360. struct iwl_priv *priv = dev_get_drvdata(d);
  2361. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2362. }
  2363. static ssize_t store_debug_level(struct device *d,
  2364. struct device_attribute *attr,
  2365. const char *buf, size_t count)
  2366. {
  2367. struct iwl_priv *priv = dev_get_drvdata(d);
  2368. unsigned long val;
  2369. int ret;
  2370. ret = strict_strtoul(buf, 0, &val);
  2371. if (ret)
  2372. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2373. else {
  2374. priv->debug_level = val;
  2375. if (iwl_alloc_traffic_mem(priv))
  2376. IWL_ERR(priv,
  2377. "Not enough memory to generate traffic log\n");
  2378. }
  2379. return strnlen(buf, count);
  2380. }
  2381. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2382. show_debug_level, store_debug_level);
  2383. #endif /* CONFIG_IWLWIFI_DEBUG */
  2384. static ssize_t show_temperature(struct device *d,
  2385. struct device_attribute *attr, char *buf)
  2386. {
  2387. struct iwl_priv *priv = dev_get_drvdata(d);
  2388. if (!iwl_is_alive(priv))
  2389. return -EAGAIN;
  2390. return sprintf(buf, "%d\n", priv->temperature);
  2391. }
  2392. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2393. static ssize_t show_tx_power(struct device *d,
  2394. struct device_attribute *attr, char *buf)
  2395. {
  2396. struct iwl_priv *priv = dev_get_drvdata(d);
  2397. if (!iwl_is_ready_rf(priv))
  2398. return sprintf(buf, "off\n");
  2399. else
  2400. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2401. }
  2402. static ssize_t store_tx_power(struct device *d,
  2403. struct device_attribute *attr,
  2404. const char *buf, size_t count)
  2405. {
  2406. struct iwl_priv *priv = dev_get_drvdata(d);
  2407. unsigned long val;
  2408. int ret;
  2409. ret = strict_strtoul(buf, 10, &val);
  2410. if (ret)
  2411. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2412. else {
  2413. ret = iwl_set_tx_power(priv, val, false);
  2414. if (ret)
  2415. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2416. ret);
  2417. else
  2418. ret = count;
  2419. }
  2420. return ret;
  2421. }
  2422. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2423. static ssize_t show_flags(struct device *d,
  2424. struct device_attribute *attr, char *buf)
  2425. {
  2426. struct iwl_priv *priv = dev_get_drvdata(d);
  2427. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2428. }
  2429. static ssize_t store_flags(struct device *d,
  2430. struct device_attribute *attr,
  2431. const char *buf, size_t count)
  2432. {
  2433. struct iwl_priv *priv = dev_get_drvdata(d);
  2434. unsigned long val;
  2435. u32 flags;
  2436. int ret = strict_strtoul(buf, 0, &val);
  2437. if (ret)
  2438. return ret;
  2439. flags = (u32)val;
  2440. mutex_lock(&priv->mutex);
  2441. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2442. /* Cancel any currently running scans... */
  2443. if (iwl_scan_cancel_timeout(priv, 100))
  2444. IWL_WARN(priv, "Could not cancel scan.\n");
  2445. else {
  2446. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2447. priv->staging_rxon.flags = cpu_to_le32(flags);
  2448. iwlcore_commit_rxon(priv);
  2449. }
  2450. }
  2451. mutex_unlock(&priv->mutex);
  2452. return count;
  2453. }
  2454. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2455. static ssize_t show_filter_flags(struct device *d,
  2456. struct device_attribute *attr, char *buf)
  2457. {
  2458. struct iwl_priv *priv = dev_get_drvdata(d);
  2459. return sprintf(buf, "0x%04X\n",
  2460. le32_to_cpu(priv->active_rxon.filter_flags));
  2461. }
  2462. static ssize_t store_filter_flags(struct device *d,
  2463. struct device_attribute *attr,
  2464. const char *buf, size_t count)
  2465. {
  2466. struct iwl_priv *priv = dev_get_drvdata(d);
  2467. unsigned long val;
  2468. u32 filter_flags;
  2469. int ret = strict_strtoul(buf, 0, &val);
  2470. if (ret)
  2471. return ret;
  2472. filter_flags = (u32)val;
  2473. mutex_lock(&priv->mutex);
  2474. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2475. /* Cancel any currently running scans... */
  2476. if (iwl_scan_cancel_timeout(priv, 100))
  2477. IWL_WARN(priv, "Could not cancel scan.\n");
  2478. else {
  2479. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2480. "0x%04X\n", filter_flags);
  2481. priv->staging_rxon.filter_flags =
  2482. cpu_to_le32(filter_flags);
  2483. iwlcore_commit_rxon(priv);
  2484. }
  2485. }
  2486. mutex_unlock(&priv->mutex);
  2487. return count;
  2488. }
  2489. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2490. store_filter_flags);
  2491. static ssize_t show_statistics(struct device *d,
  2492. struct device_attribute *attr, char *buf)
  2493. {
  2494. struct iwl_priv *priv = dev_get_drvdata(d);
  2495. u32 size = sizeof(struct iwl_notif_statistics);
  2496. u32 len = 0, ofs = 0;
  2497. u8 *data = (u8 *)&priv->statistics;
  2498. int rc = 0;
  2499. if (!iwl_is_alive(priv))
  2500. return -EAGAIN;
  2501. mutex_lock(&priv->mutex);
  2502. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2503. mutex_unlock(&priv->mutex);
  2504. if (rc) {
  2505. len = sprintf(buf,
  2506. "Error sending statistics request: 0x%08X\n", rc);
  2507. return len;
  2508. }
  2509. while (size && (PAGE_SIZE - len)) {
  2510. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2511. PAGE_SIZE - len, 1);
  2512. len = strlen(buf);
  2513. if (PAGE_SIZE - len)
  2514. buf[len++] = '\n';
  2515. ofs += 16;
  2516. size -= min(size, 16U);
  2517. }
  2518. return len;
  2519. }
  2520. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2521. static ssize_t show_rts_ht_protection(struct device *d,
  2522. struct device_attribute *attr, char *buf)
  2523. {
  2524. struct iwl_priv *priv = dev_get_drvdata(d);
  2525. return sprintf(buf, "%s\n",
  2526. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2527. }
  2528. static ssize_t store_rts_ht_protection(struct device *d,
  2529. struct device_attribute *attr,
  2530. const char *buf, size_t count)
  2531. {
  2532. struct iwl_priv *priv = dev_get_drvdata(d);
  2533. unsigned long val;
  2534. int ret;
  2535. ret = strict_strtoul(buf, 10, &val);
  2536. if (ret)
  2537. IWL_INFO(priv, "Input is not in decimal form.\n");
  2538. else {
  2539. if (!iwl_is_associated(priv))
  2540. priv->cfg->use_rts_for_ht = val ? true : false;
  2541. else
  2542. IWL_ERR(priv, "Sta associated with AP - "
  2543. "Change protection mechanism is not allowed\n");
  2544. ret = count;
  2545. }
  2546. return ret;
  2547. }
  2548. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2549. show_rts_ht_protection, store_rts_ht_protection);
  2550. /*****************************************************************************
  2551. *
  2552. * driver setup and teardown
  2553. *
  2554. *****************************************************************************/
  2555. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2556. {
  2557. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2558. init_waitqueue_head(&priv->wait_command_queue);
  2559. INIT_WORK(&priv->up, iwl_bg_up);
  2560. INIT_WORK(&priv->restart, iwl_bg_restart);
  2561. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2562. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2563. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2564. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2565. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2566. iwl_setup_scan_deferred_work(priv);
  2567. if (priv->cfg->ops->lib->setup_deferred_work)
  2568. priv->cfg->ops->lib->setup_deferred_work(priv);
  2569. init_timer(&priv->statistics_periodic);
  2570. priv->statistics_periodic.data = (unsigned long)priv;
  2571. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2572. if (!priv->cfg->use_isr_legacy)
  2573. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2574. iwl_irq_tasklet, (unsigned long)priv);
  2575. else
  2576. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2577. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2578. }
  2579. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2580. {
  2581. if (priv->cfg->ops->lib->cancel_deferred_work)
  2582. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2583. cancel_delayed_work_sync(&priv->init_alive_start);
  2584. cancel_delayed_work(&priv->scan_check);
  2585. cancel_delayed_work(&priv->alive_start);
  2586. cancel_work_sync(&priv->beacon_update);
  2587. del_timer_sync(&priv->statistics_periodic);
  2588. }
  2589. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2590. struct ieee80211_rate *rates)
  2591. {
  2592. int i;
  2593. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2594. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2595. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2596. rates[i].hw_value_short = i;
  2597. rates[i].flags = 0;
  2598. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2599. /*
  2600. * If CCK != 1M then set short preamble rate flag.
  2601. */
  2602. rates[i].flags |=
  2603. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2604. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2605. }
  2606. }
  2607. }
  2608. static int iwl_init_drv(struct iwl_priv *priv)
  2609. {
  2610. int ret;
  2611. priv->ibss_beacon = NULL;
  2612. spin_lock_init(&priv->lock);
  2613. spin_lock_init(&priv->sta_lock);
  2614. spin_lock_init(&priv->hcmd_lock);
  2615. INIT_LIST_HEAD(&priv->free_frames);
  2616. mutex_init(&priv->mutex);
  2617. /* Clear the driver's (not device's) station table */
  2618. iwl_clear_stations_table(priv);
  2619. priv->ieee_channels = NULL;
  2620. priv->ieee_rates = NULL;
  2621. priv->band = IEEE80211_BAND_2GHZ;
  2622. priv->iw_mode = NL80211_IFTYPE_STATION;
  2623. /* Choose which receivers/antennas to use */
  2624. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2625. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2626. iwl_init_scan_params(priv);
  2627. iwl_reset_qos(priv);
  2628. priv->qos_data.qos_active = 0;
  2629. priv->qos_data.qos_cap.val = 0;
  2630. priv->rates_mask = IWL_RATES_MASK;
  2631. /* Set the tx_power_user_lmt to the lowest power level
  2632. * this value will get overwritten by channel max power avg
  2633. * from eeprom */
  2634. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2635. ret = iwl_init_channel_map(priv);
  2636. if (ret) {
  2637. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2638. goto err;
  2639. }
  2640. ret = iwlcore_init_geos(priv);
  2641. if (ret) {
  2642. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2643. goto err_free_channel_map;
  2644. }
  2645. iwl_init_hw_rates(priv, priv->ieee_rates);
  2646. return 0;
  2647. err_free_channel_map:
  2648. iwl_free_channel_map(priv);
  2649. err:
  2650. return ret;
  2651. }
  2652. static void iwl_uninit_drv(struct iwl_priv *priv)
  2653. {
  2654. iwl_calib_free_results(priv);
  2655. iwlcore_free_geos(priv);
  2656. iwl_free_channel_map(priv);
  2657. kfree(priv->scan);
  2658. }
  2659. static struct attribute *iwl_sysfs_entries[] = {
  2660. &dev_attr_flags.attr,
  2661. &dev_attr_filter_flags.attr,
  2662. &dev_attr_statistics.attr,
  2663. &dev_attr_temperature.attr,
  2664. &dev_attr_tx_power.attr,
  2665. &dev_attr_rts_ht_protection.attr,
  2666. #ifdef CONFIG_IWLWIFI_DEBUG
  2667. &dev_attr_debug_level.attr,
  2668. #endif
  2669. NULL
  2670. };
  2671. static struct attribute_group iwl_attribute_group = {
  2672. .name = NULL, /* put in device directory */
  2673. .attrs = iwl_sysfs_entries,
  2674. };
  2675. static struct ieee80211_ops iwl_hw_ops = {
  2676. .tx = iwl_mac_tx,
  2677. .start = iwl_mac_start,
  2678. .stop = iwl_mac_stop,
  2679. .add_interface = iwl_mac_add_interface,
  2680. .remove_interface = iwl_mac_remove_interface,
  2681. .config = iwl_mac_config,
  2682. .configure_filter = iwl_configure_filter,
  2683. .set_key = iwl_mac_set_key,
  2684. .update_tkip_key = iwl_mac_update_tkip_key,
  2685. .get_stats = iwl_mac_get_stats,
  2686. .get_tx_stats = iwl_mac_get_tx_stats,
  2687. .conf_tx = iwl_mac_conf_tx,
  2688. .reset_tsf = iwl_mac_reset_tsf,
  2689. .bss_info_changed = iwl_bss_info_changed,
  2690. .ampdu_action = iwl_mac_ampdu_action,
  2691. .hw_scan = iwl_mac_hw_scan,
  2692. .sta_notify = iwl_mac_sta_notify,
  2693. };
  2694. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2695. {
  2696. int err = 0;
  2697. struct iwl_priv *priv;
  2698. struct ieee80211_hw *hw;
  2699. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2700. unsigned long flags;
  2701. u16 pci_cmd;
  2702. /************************
  2703. * 1. Allocating HW data
  2704. ************************/
  2705. /* Disabling hardware scan means that mac80211 will perform scans
  2706. * "the hard way", rather than using device's scan. */
  2707. if (cfg->mod_params->disable_hw_scan) {
  2708. if (iwl_debug_level & IWL_DL_INFO)
  2709. dev_printk(KERN_DEBUG, &(pdev->dev),
  2710. "Disabling hw_scan\n");
  2711. iwl_hw_ops.hw_scan = NULL;
  2712. }
  2713. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2714. if (!hw) {
  2715. err = -ENOMEM;
  2716. goto out;
  2717. }
  2718. priv = hw->priv;
  2719. /* At this point both hw and priv are allocated. */
  2720. SET_IEEE80211_DEV(hw, &pdev->dev);
  2721. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2722. priv->cfg = cfg;
  2723. priv->pci_dev = pdev;
  2724. priv->inta_mask = CSR_INI_SET_MASK;
  2725. #ifdef CONFIG_IWLWIFI_DEBUG
  2726. atomic_set(&priv->restrict_refcnt, 0);
  2727. #endif
  2728. if (iwl_alloc_traffic_mem(priv))
  2729. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2730. /**************************
  2731. * 2. Initializing PCI bus
  2732. **************************/
  2733. if (pci_enable_device(pdev)) {
  2734. err = -ENODEV;
  2735. goto out_ieee80211_free_hw;
  2736. }
  2737. pci_set_master(pdev);
  2738. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2739. if (!err)
  2740. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2741. if (err) {
  2742. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2743. if (!err)
  2744. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2745. /* both attempts failed: */
  2746. if (err) {
  2747. IWL_WARN(priv, "No suitable DMA available.\n");
  2748. goto out_pci_disable_device;
  2749. }
  2750. }
  2751. err = pci_request_regions(pdev, DRV_NAME);
  2752. if (err)
  2753. goto out_pci_disable_device;
  2754. pci_set_drvdata(pdev, priv);
  2755. /***********************
  2756. * 3. Read REV register
  2757. ***********************/
  2758. priv->hw_base = pci_iomap(pdev, 0, 0);
  2759. if (!priv->hw_base) {
  2760. err = -ENODEV;
  2761. goto out_pci_release_regions;
  2762. }
  2763. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2764. (unsigned long long) pci_resource_len(pdev, 0));
  2765. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2766. /* this spin lock will be used in apm_ops.init and EEPROM access
  2767. * we should init now
  2768. */
  2769. spin_lock_init(&priv->reg_lock);
  2770. iwl_hw_detect(priv);
  2771. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2772. priv->cfg->name, priv->hw_rev);
  2773. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2774. * PCI Tx retries from interfering with C3 CPU state */
  2775. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2776. iwl_prepare_card_hw(priv);
  2777. if (!priv->hw_ready) {
  2778. IWL_WARN(priv, "Failed, HW not ready\n");
  2779. goto out_iounmap;
  2780. }
  2781. /*****************
  2782. * 4. Read EEPROM
  2783. *****************/
  2784. /* Read the EEPROM */
  2785. err = iwl_eeprom_init(priv);
  2786. if (err) {
  2787. IWL_ERR(priv, "Unable to init EEPROM\n");
  2788. goto out_iounmap;
  2789. }
  2790. err = iwl_eeprom_check_version(priv);
  2791. if (err)
  2792. goto out_free_eeprom;
  2793. /* extract MAC Address */
  2794. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2795. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2796. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2797. /************************
  2798. * 5. Setup HW constants
  2799. ************************/
  2800. if (iwl_set_hw_params(priv)) {
  2801. IWL_ERR(priv, "failed to set hw parameters\n");
  2802. goto out_free_eeprom;
  2803. }
  2804. /*******************
  2805. * 6. Setup priv
  2806. *******************/
  2807. err = iwl_init_drv(priv);
  2808. if (err)
  2809. goto out_free_eeprom;
  2810. /* At this point both hw and priv are initialized. */
  2811. /********************
  2812. * 7. Setup services
  2813. ********************/
  2814. spin_lock_irqsave(&priv->lock, flags);
  2815. iwl_disable_interrupts(priv);
  2816. spin_unlock_irqrestore(&priv->lock, flags);
  2817. pci_enable_msi(priv->pci_dev);
  2818. iwl_alloc_isr_ict(priv);
  2819. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2820. IRQF_SHARED, DRV_NAME, priv);
  2821. if (err) {
  2822. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2823. goto out_disable_msi;
  2824. }
  2825. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2826. if (err) {
  2827. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2828. goto out_free_irq;
  2829. }
  2830. iwl_setup_deferred_work(priv);
  2831. iwl_setup_rx_handlers(priv);
  2832. /**********************************
  2833. * 8. Setup and register mac80211
  2834. **********************************/
  2835. /* enable interrupts if needed: hw bug w/a */
  2836. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2837. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2838. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2839. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2840. }
  2841. iwl_enable_interrupts(priv);
  2842. err = iwl_setup_mac(priv);
  2843. if (err)
  2844. goto out_remove_sysfs;
  2845. err = iwl_dbgfs_register(priv, DRV_NAME);
  2846. if (err)
  2847. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2848. /* If platform's RF_KILL switch is NOT set to KILL */
  2849. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2850. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2851. else
  2852. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2853. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2854. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2855. iwl_power_initialize(priv);
  2856. iwl_tt_initialize(priv);
  2857. return 0;
  2858. out_remove_sysfs:
  2859. destroy_workqueue(priv->workqueue);
  2860. priv->workqueue = NULL;
  2861. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2862. out_free_irq:
  2863. free_irq(priv->pci_dev->irq, priv);
  2864. iwl_free_isr_ict(priv);
  2865. out_disable_msi:
  2866. pci_disable_msi(priv->pci_dev);
  2867. iwl_uninit_drv(priv);
  2868. out_free_eeprom:
  2869. iwl_eeprom_free(priv);
  2870. out_iounmap:
  2871. pci_iounmap(pdev, priv->hw_base);
  2872. out_pci_release_regions:
  2873. pci_set_drvdata(pdev, NULL);
  2874. pci_release_regions(pdev);
  2875. out_pci_disable_device:
  2876. pci_disable_device(pdev);
  2877. out_ieee80211_free_hw:
  2878. iwl_free_traffic_mem(priv);
  2879. ieee80211_free_hw(priv->hw);
  2880. out:
  2881. return err;
  2882. }
  2883. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2884. {
  2885. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2886. unsigned long flags;
  2887. if (!priv)
  2888. return;
  2889. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2890. iwl_dbgfs_unregister(priv);
  2891. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2892. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2893. * to be called and iwl_down since we are removing the device
  2894. * we need to set STATUS_EXIT_PENDING bit.
  2895. */
  2896. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2897. if (priv->mac80211_registered) {
  2898. ieee80211_unregister_hw(priv->hw);
  2899. priv->mac80211_registered = 0;
  2900. } else {
  2901. iwl_down(priv);
  2902. }
  2903. /*
  2904. * Make sure device is reset to low power before unloading driver.
  2905. * This may be redundant with iwl_down(), but there are paths to
  2906. * run iwl_down() without calling apm_ops.stop(), and there are
  2907. * paths to avoid running iwl_down() at all before leaving driver.
  2908. * This (inexpensive) call *makes sure* device is reset.
  2909. */
  2910. priv->cfg->ops->lib->apm_ops.stop(priv);
  2911. iwl_tt_exit(priv);
  2912. /* make sure we flush any pending irq or
  2913. * tasklet for the driver
  2914. */
  2915. spin_lock_irqsave(&priv->lock, flags);
  2916. iwl_disable_interrupts(priv);
  2917. spin_unlock_irqrestore(&priv->lock, flags);
  2918. iwl_synchronize_irq(priv);
  2919. iwl_dealloc_ucode_pci(priv);
  2920. if (priv->rxq.bd)
  2921. iwl_rx_queue_free(priv, &priv->rxq);
  2922. iwl_hw_txq_ctx_free(priv);
  2923. iwl_clear_stations_table(priv);
  2924. iwl_eeprom_free(priv);
  2925. /*netif_stop_queue(dev); */
  2926. flush_workqueue(priv->workqueue);
  2927. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2928. * priv->workqueue... so we can't take down the workqueue
  2929. * until now... */
  2930. destroy_workqueue(priv->workqueue);
  2931. priv->workqueue = NULL;
  2932. iwl_free_traffic_mem(priv);
  2933. free_irq(priv->pci_dev->irq, priv);
  2934. pci_disable_msi(priv->pci_dev);
  2935. pci_iounmap(pdev, priv->hw_base);
  2936. pci_release_regions(pdev);
  2937. pci_disable_device(pdev);
  2938. pci_set_drvdata(pdev, NULL);
  2939. iwl_uninit_drv(priv);
  2940. iwl_free_isr_ict(priv);
  2941. if (priv->ibss_beacon)
  2942. dev_kfree_skb(priv->ibss_beacon);
  2943. ieee80211_free_hw(priv->hw);
  2944. }
  2945. /*****************************************************************************
  2946. *
  2947. * driver and module entry point
  2948. *
  2949. *****************************************************************************/
  2950. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2951. static struct pci_device_id iwl_hw_card_ids[] = {
  2952. #ifdef CONFIG_IWL4965
  2953. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2954. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2955. #endif /* CONFIG_IWL4965 */
  2956. #ifdef CONFIG_IWL5000
  2957. /* 5100 Series WiFi */
  2958. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  2959. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  2960. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  2961. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  2962. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  2963. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2964. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  2965. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  2966. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  2967. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  2968. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  2969. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  2970. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  2971. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2972. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  2973. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  2974. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  2975. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  2976. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  2977. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  2978. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  2979. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2980. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  2981. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  2982. /* 5300 Series WiFi */
  2983. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  2984. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  2985. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  2986. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  2987. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  2988. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  2989. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  2990. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  2991. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  2992. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  2993. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  2994. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  2995. /* 5350 Series WiFi/WiMax */
  2996. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  2997. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  2998. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  2999. /* 5150 Series Wifi/WiMax */
  3000. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3001. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3002. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3003. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3004. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3005. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3006. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3007. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3008. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3009. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3010. /* 6x00 Series */
  3011. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3012. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3013. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3014. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3015. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3016. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3017. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3018. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3019. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3020. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3021. /* 6x50 WiFi/WiMax Series */
  3022. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3023. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3024. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3025. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3026. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3027. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3028. /* 1000 Series WiFi */
  3029. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3030. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3031. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3032. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3033. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3034. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3035. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3036. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3037. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3038. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3039. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3040. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3041. #endif /* CONFIG_IWL5000 */
  3042. {0}
  3043. };
  3044. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3045. static struct pci_driver iwl_driver = {
  3046. .name = DRV_NAME,
  3047. .id_table = iwl_hw_card_ids,
  3048. .probe = iwl_pci_probe,
  3049. .remove = __devexit_p(iwl_pci_remove),
  3050. #ifdef CONFIG_PM
  3051. .suspend = iwl_pci_suspend,
  3052. .resume = iwl_pci_resume,
  3053. #endif
  3054. };
  3055. static int __init iwl_init(void)
  3056. {
  3057. int ret;
  3058. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3059. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3060. ret = iwlagn_rate_control_register();
  3061. if (ret) {
  3062. printk(KERN_ERR DRV_NAME
  3063. "Unable to register rate control algorithm: %d\n", ret);
  3064. return ret;
  3065. }
  3066. ret = pci_register_driver(&iwl_driver);
  3067. if (ret) {
  3068. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3069. goto error_register;
  3070. }
  3071. return ret;
  3072. error_register:
  3073. iwlagn_rate_control_unregister();
  3074. return ret;
  3075. }
  3076. static void __exit iwl_exit(void)
  3077. {
  3078. pci_unregister_driver(&iwl_driver);
  3079. iwlagn_rate_control_unregister();
  3080. }
  3081. module_exit(iwl_exit);
  3082. module_init(iwl_init);
  3083. #ifdef CONFIG_IWLWIFI_DEBUG
  3084. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3085. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3086. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3087. MODULE_PARM_DESC(debug, "debug output mask");
  3088. #endif