iwl-agn.c 103 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /*
  106. * receive commit_rxon request
  107. * abort any previous channel switch if still in process
  108. */
  109. if (priv->switch_rxon.switch_in_progress &&
  110. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  111. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  112. le16_to_cpu(priv->switch_rxon.channel));
  113. priv->switch_rxon.switch_in_progress = false;
  114. }
  115. /* If we don't need to send a full RXON, we can use
  116. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  117. * and other flags for the current radio configuration. */
  118. if (!iwl_full_rxon_required(priv)) {
  119. ret = iwl_send_rxon_assoc(priv);
  120. if (ret) {
  121. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  122. return ret;
  123. }
  124. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  125. iwl_print_rx_config_cmd(priv);
  126. return 0;
  127. }
  128. /* station table will be cleared */
  129. priv->assoc_station_added = 0;
  130. /* If we are currently associated and the new config requires
  131. * an RXON_ASSOC and the new config wants the associated mask enabled,
  132. * we must clear the associated from the active configuration
  133. * before we apply the new config */
  134. if (iwl_is_associated(priv) && new_assoc) {
  135. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  136. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  137. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  138. sizeof(struct iwl_rxon_cmd),
  139. &priv->active_rxon);
  140. /* If the mask clearing failed then we set
  141. * active_rxon back to what it was previously */
  142. if (ret) {
  143. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  144. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  145. return ret;
  146. }
  147. }
  148. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  149. "* with%s RXON_FILTER_ASSOC_MSK\n"
  150. "* channel = %d\n"
  151. "* bssid = %pM\n",
  152. (new_assoc ? "" : "out"),
  153. le16_to_cpu(priv->staging_rxon.channel),
  154. priv->staging_rxon.bssid_addr);
  155. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  156. /* Apply the new configuration
  157. * RXON unassoc clears the station table in uCode, send it before
  158. * we add the bcast station. If assoc bit is set, we will send RXON
  159. * after having added the bcast and bssid station.
  160. */
  161. if (!new_assoc) {
  162. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  163. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  164. if (ret) {
  165. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  166. return ret;
  167. }
  168. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  169. }
  170. iwl_clear_stations_table(priv);
  171. priv->start_calib = 0;
  172. /* Add the broadcast address so we can send broadcast frames */
  173. iwl_add_bcast_station(priv);
  174. /* If we have set the ASSOC_MSK and we are in BSS mode then
  175. * add the IWL_AP_ID to the station rate table */
  176. if (new_assoc) {
  177. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  178. ret = iwl_rxon_add_station(priv,
  179. priv->active_rxon.bssid_addr, 1);
  180. if (ret == IWL_INVALID_STATION) {
  181. IWL_ERR(priv,
  182. "Error adding AP address for TX.\n");
  183. return -EIO;
  184. }
  185. priv->assoc_station_added = 1;
  186. if (priv->default_wep_key &&
  187. iwl_send_static_wepkey_cmd(priv, 0))
  188. IWL_ERR(priv,
  189. "Could not send WEP static key.\n");
  190. }
  191. /*
  192. * allow CTS-to-self if possible for new association.
  193. * this is relevant only for 5000 series and up,
  194. * but will not damage 4965
  195. */
  196. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  197. /* Apply the new configuration
  198. * RXON assoc doesn't clear the station table in uCode,
  199. */
  200. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  201. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  202. if (ret) {
  203. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  204. return ret;
  205. }
  206. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  207. }
  208. iwl_print_rx_config_cmd(priv);
  209. iwl_init_sensitivity(priv);
  210. /* If we issue a new RXON command which required a tune then we must
  211. * send a new TXPOWER command or we won't be able to Tx any frames */
  212. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  213. if (ret) {
  214. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. void iwl_update_chain_flags(struct iwl_priv *priv)
  220. {
  221. if (priv->cfg->ops->hcmd->set_rxon_chain)
  222. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  223. iwlcore_commit_rxon(priv);
  224. }
  225. static void iwl_clear_free_frames(struct iwl_priv *priv)
  226. {
  227. struct list_head *element;
  228. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  229. priv->frames_count);
  230. while (!list_empty(&priv->free_frames)) {
  231. element = priv->free_frames.next;
  232. list_del(element);
  233. kfree(list_entry(element, struct iwl_frame, list));
  234. priv->frames_count--;
  235. }
  236. if (priv->frames_count) {
  237. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  238. priv->frames_count);
  239. priv->frames_count = 0;
  240. }
  241. }
  242. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  243. {
  244. struct iwl_frame *frame;
  245. struct list_head *element;
  246. if (list_empty(&priv->free_frames)) {
  247. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  248. if (!frame) {
  249. IWL_ERR(priv, "Could not allocate frame!\n");
  250. return NULL;
  251. }
  252. priv->frames_count++;
  253. return frame;
  254. }
  255. element = priv->free_frames.next;
  256. list_del(element);
  257. return list_entry(element, struct iwl_frame, list);
  258. }
  259. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  260. {
  261. memset(frame, 0, sizeof(*frame));
  262. list_add(&frame->list, &priv->free_frames);
  263. }
  264. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  265. struct ieee80211_hdr *hdr,
  266. int left)
  267. {
  268. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  269. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  270. (priv->iw_mode != NL80211_IFTYPE_AP)))
  271. return 0;
  272. if (priv->ibss_beacon->len > left)
  273. return 0;
  274. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  275. return priv->ibss_beacon->len;
  276. }
  277. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  278. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  279. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  280. u8 *beacon, u32 frame_size)
  281. {
  282. u16 tim_idx;
  283. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  284. /*
  285. * The index is relative to frame start but we start looking at the
  286. * variable-length part of the beacon.
  287. */
  288. tim_idx = mgmt->u.beacon.variable - beacon;
  289. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  290. while ((tim_idx < (frame_size - 2)) &&
  291. (beacon[tim_idx] != WLAN_EID_TIM))
  292. tim_idx += beacon[tim_idx+1] + 2;
  293. /* If TIM field was found, set variables */
  294. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  295. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  296. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  297. } else
  298. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  299. }
  300. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  301. struct iwl_frame *frame)
  302. {
  303. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  304. u32 frame_size;
  305. u32 rate_flags;
  306. u32 rate;
  307. /*
  308. * We have to set up the TX command, the TX Beacon command, and the
  309. * beacon contents.
  310. */
  311. /* Initialize memory */
  312. tx_beacon_cmd = &frame->u.beacon;
  313. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  314. /* Set up TX beacon contents */
  315. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  316. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  317. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  318. return 0;
  319. /* Set up TX command fields */
  320. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  321. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  322. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  323. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  324. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  325. /* Set up TX beacon command fields */
  326. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  327. frame_size);
  328. /* Set up packet rate and flags */
  329. rate = iwl_rate_get_lowest_plcp(priv);
  330. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  331. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  332. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  333. rate_flags |= RATE_MCS_CCK_MSK;
  334. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  335. rate_flags);
  336. return sizeof(*tx_beacon_cmd) + frame_size;
  337. }
  338. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  339. {
  340. struct iwl_frame *frame;
  341. unsigned int frame_size;
  342. int rc;
  343. frame = iwl_get_free_frame(priv);
  344. if (!frame) {
  345. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  346. "command.\n");
  347. return -ENOMEM;
  348. }
  349. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  350. if (!frame_size) {
  351. IWL_ERR(priv, "Error configuring the beacon command\n");
  352. iwl_free_frame(priv, frame);
  353. return -EINVAL;
  354. }
  355. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  356. &frame->u.cmd[0]);
  357. iwl_free_frame(priv, frame);
  358. return rc;
  359. }
  360. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  361. {
  362. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  363. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  364. if (sizeof(dma_addr_t) > sizeof(u32))
  365. addr |=
  366. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  367. return addr;
  368. }
  369. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  370. {
  371. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  372. return le16_to_cpu(tb->hi_n_len) >> 4;
  373. }
  374. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  375. dma_addr_t addr, u16 len)
  376. {
  377. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  378. u16 hi_n_len = len << 4;
  379. put_unaligned_le32(addr, &tb->lo);
  380. if (sizeof(dma_addr_t) > sizeof(u32))
  381. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  382. tb->hi_n_len = cpu_to_le16(hi_n_len);
  383. tfd->num_tbs = idx + 1;
  384. }
  385. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  386. {
  387. return tfd->num_tbs & 0x1f;
  388. }
  389. /**
  390. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  391. * @priv - driver private data
  392. * @txq - tx queue
  393. *
  394. * Does NOT advance any TFD circular buffer read/write indexes
  395. * Does NOT free the TFD itself (which is within circular buffer)
  396. */
  397. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  398. {
  399. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  400. struct iwl_tfd *tfd;
  401. struct pci_dev *dev = priv->pci_dev;
  402. int index = txq->q.read_ptr;
  403. int i;
  404. int num_tbs;
  405. tfd = &tfd_tmp[index];
  406. /* Sanity check on number of chunks */
  407. num_tbs = iwl_tfd_get_num_tbs(tfd);
  408. if (num_tbs >= IWL_NUM_OF_TBS) {
  409. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  410. /* @todo issue fatal error, it is quite serious situation */
  411. return;
  412. }
  413. /* Unmap tx_cmd */
  414. if (num_tbs)
  415. pci_unmap_single(dev,
  416. pci_unmap_addr(&txq->meta[index], mapping),
  417. pci_unmap_len(&txq->meta[index], len),
  418. PCI_DMA_BIDIRECTIONAL);
  419. /* Unmap chunks, if any. */
  420. for (i = 1; i < num_tbs; i++) {
  421. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  422. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  423. if (txq->txb) {
  424. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  425. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  426. }
  427. }
  428. }
  429. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  430. struct iwl_tx_queue *txq,
  431. dma_addr_t addr, u16 len,
  432. u8 reset, u8 pad)
  433. {
  434. struct iwl_queue *q;
  435. struct iwl_tfd *tfd, *tfd_tmp;
  436. u32 num_tbs;
  437. q = &txq->q;
  438. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  439. tfd = &tfd_tmp[q->write_ptr];
  440. if (reset)
  441. memset(tfd, 0, sizeof(*tfd));
  442. num_tbs = iwl_tfd_get_num_tbs(tfd);
  443. /* Each TFD can point to a maximum 20 Tx buffers */
  444. if (num_tbs >= IWL_NUM_OF_TBS) {
  445. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  446. IWL_NUM_OF_TBS);
  447. return -EINVAL;
  448. }
  449. BUG_ON(addr & ~DMA_BIT_MASK(36));
  450. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  451. IWL_ERR(priv, "Unaligned address = %llx\n",
  452. (unsigned long long)addr);
  453. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  454. return 0;
  455. }
  456. /*
  457. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  458. * given Tx queue, and enable the DMA channel used for that queue.
  459. *
  460. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  461. * channels supported in hardware.
  462. */
  463. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  464. struct iwl_tx_queue *txq)
  465. {
  466. int txq_id = txq->q.id;
  467. /* Circular buffer (TFD queue in DRAM) physical base address */
  468. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  469. txq->q.dma_addr >> 8);
  470. return 0;
  471. }
  472. /******************************************************************************
  473. *
  474. * Generic RX handler implementations
  475. *
  476. ******************************************************************************/
  477. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  478. struct iwl_rx_mem_buffer *rxb)
  479. {
  480. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  481. struct iwl_alive_resp *palive;
  482. struct delayed_work *pwork;
  483. palive = &pkt->u.alive_frame;
  484. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  485. "0x%01X 0x%01X\n",
  486. palive->is_valid, palive->ver_type,
  487. palive->ver_subtype);
  488. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  489. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  490. memcpy(&priv->card_alive_init,
  491. &pkt->u.alive_frame,
  492. sizeof(struct iwl_init_alive_resp));
  493. pwork = &priv->init_alive_start;
  494. } else {
  495. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  496. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  497. sizeof(struct iwl_alive_resp));
  498. pwork = &priv->alive_start;
  499. }
  500. /* We delay the ALIVE response by 5ms to
  501. * give the HW RF Kill time to activate... */
  502. if (palive->is_valid == UCODE_VALID_OK)
  503. queue_delayed_work(priv->workqueue, pwork,
  504. msecs_to_jiffies(5));
  505. else
  506. IWL_WARN(priv, "uCode did not respond OK.\n");
  507. }
  508. static void iwl_bg_beacon_update(struct work_struct *work)
  509. {
  510. struct iwl_priv *priv =
  511. container_of(work, struct iwl_priv, beacon_update);
  512. struct sk_buff *beacon;
  513. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  514. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  515. if (!beacon) {
  516. IWL_ERR(priv, "update beacon failed\n");
  517. return;
  518. }
  519. mutex_lock(&priv->mutex);
  520. /* new beacon skb is allocated every time; dispose previous.*/
  521. if (priv->ibss_beacon)
  522. dev_kfree_skb(priv->ibss_beacon);
  523. priv->ibss_beacon = beacon;
  524. mutex_unlock(&priv->mutex);
  525. iwl_send_beacon_cmd(priv);
  526. }
  527. /**
  528. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  529. *
  530. * This callback is provided in order to send a statistics request.
  531. *
  532. * This timer function is continually reset to execute within
  533. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  534. * was received. We need to ensure we receive the statistics in order
  535. * to update the temperature used for calibrating the TXPOWER.
  536. */
  537. static void iwl_bg_statistics_periodic(unsigned long data)
  538. {
  539. struct iwl_priv *priv = (struct iwl_priv *)data;
  540. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  541. return;
  542. /* dont send host command if rf-kill is on */
  543. if (!iwl_is_ready_rf(priv))
  544. return;
  545. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  546. }
  547. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  548. struct iwl_rx_mem_buffer *rxb)
  549. {
  550. #ifdef CONFIG_IWLWIFI_DEBUG
  551. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  552. struct iwl4965_beacon_notif *beacon =
  553. (struct iwl4965_beacon_notif *)pkt->u.raw;
  554. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  555. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  556. "tsf %d %d rate %d\n",
  557. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  558. beacon->beacon_notify_hdr.failure_frame,
  559. le32_to_cpu(beacon->ibss_mgr_status),
  560. le32_to_cpu(beacon->high_tsf),
  561. le32_to_cpu(beacon->low_tsf), rate);
  562. #endif
  563. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  564. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  565. queue_work(priv->workqueue, &priv->beacon_update);
  566. }
  567. /* Handle notification from uCode that card's power state is changing
  568. * due to software, hardware, or critical temperature RFKILL */
  569. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  570. struct iwl_rx_mem_buffer *rxb)
  571. {
  572. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  573. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  574. unsigned long status = priv->status;
  575. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  576. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  577. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  578. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  579. RF_CARD_DISABLED)) {
  580. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  581. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  582. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  583. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  584. if (!(flags & RXON_CARD_DISABLED)) {
  585. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  586. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  587. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  588. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  589. }
  590. if (flags & RF_CARD_DISABLED)
  591. iwl_tt_enter_ct_kill(priv);
  592. }
  593. if (!(flags & RF_CARD_DISABLED))
  594. iwl_tt_exit_ct_kill(priv);
  595. if (flags & HW_CARD_DISABLED)
  596. set_bit(STATUS_RF_KILL_HW, &priv->status);
  597. else
  598. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  599. if (!(flags & RXON_CARD_DISABLED))
  600. iwl_scan_cancel(priv);
  601. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  602. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  603. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  604. test_bit(STATUS_RF_KILL_HW, &priv->status));
  605. else
  606. wake_up_interruptible(&priv->wait_command_queue);
  607. }
  608. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  609. {
  610. if (src == IWL_PWR_SRC_VAUX) {
  611. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  612. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  613. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  614. ~APMG_PS_CTRL_MSK_PWR_SRC);
  615. } else {
  616. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  617. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  618. ~APMG_PS_CTRL_MSK_PWR_SRC);
  619. }
  620. return 0;
  621. }
  622. /**
  623. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  624. *
  625. * Setup the RX handlers for each of the reply types sent from the uCode
  626. * to the host.
  627. *
  628. * This function chains into the hardware specific files for them to setup
  629. * any hardware specific handlers as well.
  630. */
  631. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  632. {
  633. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  634. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  635. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  636. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  637. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  638. iwl_rx_pm_debug_statistics_notif;
  639. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  640. /*
  641. * The same handler is used for both the REPLY to a discrete
  642. * statistics request from the host as well as for the periodic
  643. * statistics notifications (after received beacons) from the uCode.
  644. */
  645. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  646. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  647. iwl_setup_spectrum_handlers(priv);
  648. iwl_setup_rx_scan_handlers(priv);
  649. /* status change handler */
  650. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  651. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  652. iwl_rx_missed_beacon_notif;
  653. /* Rx handlers */
  654. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  655. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  656. /* block ack */
  657. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  658. /* Set up hardware specific Rx handlers */
  659. priv->cfg->ops->lib->rx_handler_setup(priv);
  660. }
  661. /**
  662. * iwl_rx_handle - Main entry function for receiving responses from uCode
  663. *
  664. * Uses the priv->rx_handlers callback function array to invoke
  665. * the appropriate handlers, including command responses,
  666. * frame-received notifications, and other notifications.
  667. */
  668. void iwl_rx_handle(struct iwl_priv *priv)
  669. {
  670. struct iwl_rx_mem_buffer *rxb;
  671. struct iwl_rx_packet *pkt;
  672. struct iwl_rx_queue *rxq = &priv->rxq;
  673. u32 r, i;
  674. int reclaim;
  675. unsigned long flags;
  676. u8 fill_rx = 0;
  677. u32 count = 8;
  678. int total_empty;
  679. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  680. * buffer that the driver may process (last buffer filled by ucode). */
  681. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  682. i = rxq->read;
  683. /* Rx interrupt, but nothing sent from uCode */
  684. if (i == r)
  685. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  686. /* calculate total frames need to be restock after handling RX */
  687. total_empty = r - rxq->write_actual;
  688. if (total_empty < 0)
  689. total_empty += RX_QUEUE_SIZE;
  690. if (total_empty > (RX_QUEUE_SIZE / 2))
  691. fill_rx = 1;
  692. while (i != r) {
  693. rxb = rxq->queue[i];
  694. /* If an RXB doesn't have a Rx queue slot associated with it,
  695. * then a bug has been introduced in the queue refilling
  696. * routines -- catch it here */
  697. BUG_ON(rxb == NULL);
  698. rxq->queue[i] = NULL;
  699. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  700. PAGE_SIZE << priv->hw_params.rx_page_order,
  701. PCI_DMA_FROMDEVICE);
  702. pkt = rxb_addr(rxb);
  703. trace_iwlwifi_dev_rx(priv, pkt,
  704. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  705. /* Reclaim a command buffer only if this packet is a response
  706. * to a (driver-originated) command.
  707. * If the packet (e.g. Rx frame) originated from uCode,
  708. * there is no command buffer to reclaim.
  709. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  710. * but apparently a few don't get set; catch them here. */
  711. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  712. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  713. (pkt->hdr.cmd != REPLY_RX) &&
  714. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  715. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  716. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  717. (pkt->hdr.cmd != REPLY_TX);
  718. /* Based on type of command response or notification,
  719. * handle those that need handling via function in
  720. * rx_handlers table. See iwl_setup_rx_handlers() */
  721. if (priv->rx_handlers[pkt->hdr.cmd]) {
  722. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  723. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  724. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  725. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  726. } else {
  727. /* No handling needed */
  728. IWL_DEBUG_RX(priv,
  729. "r %d i %d No handler needed for %s, 0x%02x\n",
  730. r, i, get_cmd_string(pkt->hdr.cmd),
  731. pkt->hdr.cmd);
  732. }
  733. /*
  734. * XXX: After here, we should always check rxb->page
  735. * against NULL before touching it or its virtual
  736. * memory (pkt). Because some rx_handler might have
  737. * already taken or freed the pages.
  738. */
  739. if (reclaim) {
  740. /* Invoke any callbacks, transfer the buffer to caller,
  741. * and fire off the (possibly) blocking iwl_send_cmd()
  742. * as we reclaim the driver command queue */
  743. if (rxb->page)
  744. iwl_tx_cmd_complete(priv, rxb);
  745. else
  746. IWL_WARN(priv, "Claim null rxb?\n");
  747. }
  748. /* Reuse the page if possible. For notification packets and
  749. * SKBs that fail to Rx correctly, add them back into the
  750. * rx_free list for reuse later. */
  751. spin_lock_irqsave(&rxq->lock, flags);
  752. if (rxb->page != NULL) {
  753. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  754. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  755. PCI_DMA_FROMDEVICE);
  756. list_add_tail(&rxb->list, &rxq->rx_free);
  757. rxq->free_count++;
  758. } else
  759. list_add_tail(&rxb->list, &rxq->rx_used);
  760. spin_unlock_irqrestore(&rxq->lock, flags);
  761. i = (i + 1) & RX_QUEUE_MASK;
  762. /* If there are a lot of unused frames,
  763. * restock the Rx queue so ucode wont assert. */
  764. if (fill_rx) {
  765. count++;
  766. if (count >= 8) {
  767. rxq->read = i;
  768. iwl_rx_replenish_now(priv);
  769. count = 0;
  770. }
  771. }
  772. }
  773. /* Backtrack one entry */
  774. rxq->read = i;
  775. if (fill_rx)
  776. iwl_rx_replenish_now(priv);
  777. else
  778. iwl_rx_queue_restock(priv);
  779. }
  780. /* call this function to flush any scheduled tasklet */
  781. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  782. {
  783. /* wait to make sure we flush pending tasklet*/
  784. synchronize_irq(priv->pci_dev->irq);
  785. tasklet_kill(&priv->irq_tasklet);
  786. }
  787. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  788. {
  789. u32 inta, handled = 0;
  790. u32 inta_fh;
  791. unsigned long flags;
  792. u32 i;
  793. #ifdef CONFIG_IWLWIFI_DEBUG
  794. u32 inta_mask;
  795. #endif
  796. spin_lock_irqsave(&priv->lock, flags);
  797. /* Ack/clear/reset pending uCode interrupts.
  798. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  799. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  800. inta = iwl_read32(priv, CSR_INT);
  801. iwl_write32(priv, CSR_INT, inta);
  802. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  803. * Any new interrupts that happen after this, either while we're
  804. * in this tasklet, or later, will show up in next ISR/tasklet. */
  805. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  806. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  807. #ifdef CONFIG_IWLWIFI_DEBUG
  808. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  809. /* just for debug */
  810. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  811. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  812. inta, inta_mask, inta_fh);
  813. }
  814. #endif
  815. spin_unlock_irqrestore(&priv->lock, flags);
  816. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  817. * atomic, make sure that inta covers all the interrupts that
  818. * we've discovered, even if FH interrupt came in just after
  819. * reading CSR_INT. */
  820. if (inta_fh & CSR49_FH_INT_RX_MASK)
  821. inta |= CSR_INT_BIT_FH_RX;
  822. if (inta_fh & CSR49_FH_INT_TX_MASK)
  823. inta |= CSR_INT_BIT_FH_TX;
  824. /* Now service all interrupt bits discovered above. */
  825. if (inta & CSR_INT_BIT_HW_ERR) {
  826. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  827. /* Tell the device to stop sending interrupts */
  828. iwl_disable_interrupts(priv);
  829. priv->isr_stats.hw++;
  830. iwl_irq_handle_error(priv);
  831. handled |= CSR_INT_BIT_HW_ERR;
  832. return;
  833. }
  834. #ifdef CONFIG_IWLWIFI_DEBUG
  835. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  836. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  837. if (inta & CSR_INT_BIT_SCD) {
  838. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  839. "the frame/frames.\n");
  840. priv->isr_stats.sch++;
  841. }
  842. /* Alive notification via Rx interrupt will do the real work */
  843. if (inta & CSR_INT_BIT_ALIVE) {
  844. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  845. priv->isr_stats.alive++;
  846. }
  847. }
  848. #endif
  849. /* Safely ignore these bits for debug checks below */
  850. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  851. /* HW RF KILL switch toggled */
  852. if (inta & CSR_INT_BIT_RF_KILL) {
  853. int hw_rf_kill = 0;
  854. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  855. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  856. hw_rf_kill = 1;
  857. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  858. hw_rf_kill ? "disable radio" : "enable radio");
  859. priv->isr_stats.rfkill++;
  860. /* driver only loads ucode once setting the interface up.
  861. * the driver allows loading the ucode even if the radio
  862. * is killed. Hence update the killswitch state here. The
  863. * rfkill handler will care about restarting if needed.
  864. */
  865. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  866. if (hw_rf_kill)
  867. set_bit(STATUS_RF_KILL_HW, &priv->status);
  868. else
  869. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  870. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  871. }
  872. handled |= CSR_INT_BIT_RF_KILL;
  873. }
  874. /* Chip got too hot and stopped itself */
  875. if (inta & CSR_INT_BIT_CT_KILL) {
  876. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  877. priv->isr_stats.ctkill++;
  878. handled |= CSR_INT_BIT_CT_KILL;
  879. }
  880. /* Error detected by uCode */
  881. if (inta & CSR_INT_BIT_SW_ERR) {
  882. IWL_ERR(priv, "Microcode SW error detected. "
  883. " Restarting 0x%X.\n", inta);
  884. priv->isr_stats.sw++;
  885. priv->isr_stats.sw_err = inta;
  886. iwl_irq_handle_error(priv);
  887. handled |= CSR_INT_BIT_SW_ERR;
  888. }
  889. /*
  890. * uCode wakes up after power-down sleep.
  891. * Tell device about any new tx or host commands enqueued,
  892. * and about any Rx buffers made available while asleep.
  893. */
  894. if (inta & CSR_INT_BIT_WAKEUP) {
  895. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  896. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  897. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  898. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  899. priv->isr_stats.wakeup++;
  900. handled |= CSR_INT_BIT_WAKEUP;
  901. }
  902. /* All uCode command responses, including Tx command responses,
  903. * Rx "responses" (frame-received notification), and other
  904. * notifications from uCode come through here*/
  905. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  906. iwl_rx_handle(priv);
  907. priv->isr_stats.rx++;
  908. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  909. }
  910. /* This "Tx" DMA channel is used only for loading uCode */
  911. if (inta & CSR_INT_BIT_FH_TX) {
  912. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  913. priv->isr_stats.tx++;
  914. handled |= CSR_INT_BIT_FH_TX;
  915. /* Wake up uCode load routine, now that load is complete */
  916. priv->ucode_write_complete = 1;
  917. wake_up_interruptible(&priv->wait_command_queue);
  918. }
  919. if (inta & ~handled) {
  920. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  921. priv->isr_stats.unhandled++;
  922. }
  923. if (inta & ~(priv->inta_mask)) {
  924. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  925. inta & ~priv->inta_mask);
  926. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  927. }
  928. /* Re-enable all interrupts */
  929. /* only Re-enable if diabled by irq */
  930. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  931. iwl_enable_interrupts(priv);
  932. #ifdef CONFIG_IWLWIFI_DEBUG
  933. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  934. inta = iwl_read32(priv, CSR_INT);
  935. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  936. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  937. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  938. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  939. }
  940. #endif
  941. }
  942. /* tasklet for iwlagn interrupt */
  943. static void iwl_irq_tasklet(struct iwl_priv *priv)
  944. {
  945. u32 inta = 0;
  946. u32 handled = 0;
  947. unsigned long flags;
  948. u32 i;
  949. #ifdef CONFIG_IWLWIFI_DEBUG
  950. u32 inta_mask;
  951. #endif
  952. spin_lock_irqsave(&priv->lock, flags);
  953. /* Ack/clear/reset pending uCode interrupts.
  954. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  955. */
  956. iwl_write32(priv, CSR_INT, priv->inta);
  957. inta = priv->inta;
  958. #ifdef CONFIG_IWLWIFI_DEBUG
  959. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  960. /* just for debug */
  961. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  962. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  963. inta, inta_mask);
  964. }
  965. #endif
  966. spin_unlock_irqrestore(&priv->lock, flags);
  967. /* saved interrupt in inta variable now we can reset priv->inta */
  968. priv->inta = 0;
  969. /* Now service all interrupt bits discovered above. */
  970. if (inta & CSR_INT_BIT_HW_ERR) {
  971. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  972. /* Tell the device to stop sending interrupts */
  973. iwl_disable_interrupts(priv);
  974. priv->isr_stats.hw++;
  975. iwl_irq_handle_error(priv);
  976. handled |= CSR_INT_BIT_HW_ERR;
  977. return;
  978. }
  979. #ifdef CONFIG_IWLWIFI_DEBUG
  980. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  981. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  982. if (inta & CSR_INT_BIT_SCD) {
  983. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  984. "the frame/frames.\n");
  985. priv->isr_stats.sch++;
  986. }
  987. /* Alive notification via Rx interrupt will do the real work */
  988. if (inta & CSR_INT_BIT_ALIVE) {
  989. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  990. priv->isr_stats.alive++;
  991. }
  992. }
  993. #endif
  994. /* Safely ignore these bits for debug checks below */
  995. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  996. /* HW RF KILL switch toggled */
  997. if (inta & CSR_INT_BIT_RF_KILL) {
  998. int hw_rf_kill = 0;
  999. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1000. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1001. hw_rf_kill = 1;
  1002. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1003. hw_rf_kill ? "disable radio" : "enable radio");
  1004. priv->isr_stats.rfkill++;
  1005. /* driver only loads ucode once setting the interface up.
  1006. * the driver allows loading the ucode even if the radio
  1007. * is killed. Hence update the killswitch state here. The
  1008. * rfkill handler will care about restarting if needed.
  1009. */
  1010. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1011. if (hw_rf_kill)
  1012. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1013. else
  1014. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1015. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1016. }
  1017. handled |= CSR_INT_BIT_RF_KILL;
  1018. }
  1019. /* Chip got too hot and stopped itself */
  1020. if (inta & CSR_INT_BIT_CT_KILL) {
  1021. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1022. priv->isr_stats.ctkill++;
  1023. handled |= CSR_INT_BIT_CT_KILL;
  1024. }
  1025. /* Error detected by uCode */
  1026. if (inta & CSR_INT_BIT_SW_ERR) {
  1027. IWL_ERR(priv, "Microcode SW error detected. "
  1028. " Restarting 0x%X.\n", inta);
  1029. priv->isr_stats.sw++;
  1030. priv->isr_stats.sw_err = inta;
  1031. iwl_irq_handle_error(priv);
  1032. handled |= CSR_INT_BIT_SW_ERR;
  1033. }
  1034. /* uCode wakes up after power-down sleep */
  1035. if (inta & CSR_INT_BIT_WAKEUP) {
  1036. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1037. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1038. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1039. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1040. priv->isr_stats.wakeup++;
  1041. handled |= CSR_INT_BIT_WAKEUP;
  1042. }
  1043. /* All uCode command responses, including Tx command responses,
  1044. * Rx "responses" (frame-received notification), and other
  1045. * notifications from uCode come through here*/
  1046. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1047. CSR_INT_BIT_RX_PERIODIC)) {
  1048. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1049. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1050. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1051. iwl_write32(priv, CSR_FH_INT_STATUS,
  1052. CSR49_FH_INT_RX_MASK);
  1053. }
  1054. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1055. handled |= CSR_INT_BIT_RX_PERIODIC;
  1056. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1057. }
  1058. /* Sending RX interrupt require many steps to be done in the
  1059. * the device:
  1060. * 1- write interrupt to current index in ICT table.
  1061. * 2- dma RX frame.
  1062. * 3- update RX shared data to indicate last write index.
  1063. * 4- send interrupt.
  1064. * This could lead to RX race, driver could receive RX interrupt
  1065. * but the shared data changes does not reflect this;
  1066. * periodic interrupt will detect any dangling Rx activity.
  1067. */
  1068. /* Disable periodic interrupt; we use it as just a one-shot. */
  1069. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1070. CSR_INT_PERIODIC_DIS);
  1071. iwl_rx_handle(priv);
  1072. /*
  1073. * Enable periodic interrupt in 8 msec only if we received
  1074. * real RX interrupt (instead of just periodic int), to catch
  1075. * any dangling Rx interrupt. If it was just the periodic
  1076. * interrupt, there was no dangling Rx activity, and no need
  1077. * to extend the periodic interrupt; one-shot is enough.
  1078. */
  1079. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1080. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1081. CSR_INT_PERIODIC_ENA);
  1082. priv->isr_stats.rx++;
  1083. }
  1084. /* This "Tx" DMA channel is used only for loading uCode */
  1085. if (inta & CSR_INT_BIT_FH_TX) {
  1086. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1087. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1088. priv->isr_stats.tx++;
  1089. handled |= CSR_INT_BIT_FH_TX;
  1090. /* Wake up uCode load routine, now that load is complete */
  1091. priv->ucode_write_complete = 1;
  1092. wake_up_interruptible(&priv->wait_command_queue);
  1093. }
  1094. if (inta & ~handled) {
  1095. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1096. priv->isr_stats.unhandled++;
  1097. }
  1098. if (inta & ~(priv->inta_mask)) {
  1099. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1100. inta & ~priv->inta_mask);
  1101. }
  1102. /* Re-enable all interrupts */
  1103. /* only Re-enable if diabled by irq */
  1104. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1105. iwl_enable_interrupts(priv);
  1106. }
  1107. /******************************************************************************
  1108. *
  1109. * uCode download functions
  1110. *
  1111. ******************************************************************************/
  1112. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1113. {
  1114. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1115. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1116. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1117. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1118. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1119. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1120. }
  1121. static void iwl_nic_start(struct iwl_priv *priv)
  1122. {
  1123. /* Remove all resets to allow NIC to operate */
  1124. iwl_write32(priv, CSR_RESET, 0);
  1125. }
  1126. /**
  1127. * iwl_read_ucode - Read uCode images from disk file.
  1128. *
  1129. * Copy into buffers for card to fetch via bus-mastering
  1130. */
  1131. static int iwl_read_ucode(struct iwl_priv *priv)
  1132. {
  1133. struct iwl_ucode_header *ucode;
  1134. int ret = -EINVAL, index;
  1135. const struct firmware *ucode_raw;
  1136. const char *name_pre = priv->cfg->fw_name_pre;
  1137. const unsigned int api_max = priv->cfg->ucode_api_max;
  1138. const unsigned int api_min = priv->cfg->ucode_api_min;
  1139. char buf[25];
  1140. u8 *src;
  1141. size_t len;
  1142. u32 api_ver, build;
  1143. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1144. u16 eeprom_ver;
  1145. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1146. * request_firmware() is synchronous, file is in memory on return. */
  1147. for (index = api_max; index >= api_min; index--) {
  1148. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1149. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1150. if (ret < 0) {
  1151. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1152. buf, ret);
  1153. if (ret == -ENOENT)
  1154. continue;
  1155. else
  1156. goto error;
  1157. } else {
  1158. if (index < api_max)
  1159. IWL_ERR(priv, "Loaded firmware %s, "
  1160. "which is deprecated. "
  1161. "Please use API v%u instead.\n",
  1162. buf, api_max);
  1163. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1164. buf, ucode_raw->size);
  1165. break;
  1166. }
  1167. }
  1168. if (ret < 0)
  1169. goto error;
  1170. /* Make sure that we got at least the v1 header! */
  1171. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1172. IWL_ERR(priv, "File size way too small!\n");
  1173. ret = -EINVAL;
  1174. goto err_release;
  1175. }
  1176. /* Data from ucode file: header followed by uCode images */
  1177. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1178. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1179. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1180. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1181. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1182. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1183. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1184. init_data_size =
  1185. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1186. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1187. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1188. /* api_ver should match the api version forming part of the
  1189. * firmware filename ... but we don't check for that and only rely
  1190. * on the API version read from firmware header from here on forward */
  1191. if (api_ver < api_min || api_ver > api_max) {
  1192. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1193. "Driver supports v%u, firmware is v%u.\n",
  1194. api_max, api_ver);
  1195. priv->ucode_ver = 0;
  1196. ret = -EINVAL;
  1197. goto err_release;
  1198. }
  1199. if (api_ver != api_max)
  1200. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1201. "got v%u. New firmware can be obtained "
  1202. "from http://www.intellinuxwireless.org.\n",
  1203. api_max, api_ver);
  1204. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1205. IWL_UCODE_MAJOR(priv->ucode_ver),
  1206. IWL_UCODE_MINOR(priv->ucode_ver),
  1207. IWL_UCODE_API(priv->ucode_ver),
  1208. IWL_UCODE_SERIAL(priv->ucode_ver));
  1209. snprintf(priv->hw->wiphy->fw_version,
  1210. sizeof(priv->hw->wiphy->fw_version),
  1211. "%u.%u.%u.%u",
  1212. IWL_UCODE_MAJOR(priv->ucode_ver),
  1213. IWL_UCODE_MINOR(priv->ucode_ver),
  1214. IWL_UCODE_API(priv->ucode_ver),
  1215. IWL_UCODE_SERIAL(priv->ucode_ver));
  1216. if (build)
  1217. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1218. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1219. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1220. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1221. ? "OTP" : "EEPROM", eeprom_ver);
  1222. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1223. priv->ucode_ver);
  1224. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1225. inst_size);
  1226. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1227. data_size);
  1228. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1229. init_size);
  1230. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1231. init_data_size);
  1232. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1233. boot_size);
  1234. /* Verify size of file vs. image size info in file's header */
  1235. if (ucode_raw->size !=
  1236. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1237. inst_size + data_size + init_size +
  1238. init_data_size + boot_size) {
  1239. IWL_DEBUG_INFO(priv,
  1240. "uCode file size %d does not match expected size\n",
  1241. (int)ucode_raw->size);
  1242. ret = -EINVAL;
  1243. goto err_release;
  1244. }
  1245. /* Verify that uCode images will fit in card's SRAM */
  1246. if (inst_size > priv->hw_params.max_inst_size) {
  1247. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1248. inst_size);
  1249. ret = -EINVAL;
  1250. goto err_release;
  1251. }
  1252. if (data_size > priv->hw_params.max_data_size) {
  1253. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1254. data_size);
  1255. ret = -EINVAL;
  1256. goto err_release;
  1257. }
  1258. if (init_size > priv->hw_params.max_inst_size) {
  1259. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1260. init_size);
  1261. ret = -EINVAL;
  1262. goto err_release;
  1263. }
  1264. if (init_data_size > priv->hw_params.max_data_size) {
  1265. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1266. init_data_size);
  1267. ret = -EINVAL;
  1268. goto err_release;
  1269. }
  1270. if (boot_size > priv->hw_params.max_bsm_size) {
  1271. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1272. boot_size);
  1273. ret = -EINVAL;
  1274. goto err_release;
  1275. }
  1276. /* Allocate ucode buffers for card's bus-master loading ... */
  1277. /* Runtime instructions and 2 copies of data:
  1278. * 1) unmodified from disk
  1279. * 2) backup cache for save/restore during power-downs */
  1280. priv->ucode_code.len = inst_size;
  1281. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1282. priv->ucode_data.len = data_size;
  1283. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1284. priv->ucode_data_backup.len = data_size;
  1285. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1286. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1287. !priv->ucode_data_backup.v_addr)
  1288. goto err_pci_alloc;
  1289. /* Initialization instructions and data */
  1290. if (init_size && init_data_size) {
  1291. priv->ucode_init.len = init_size;
  1292. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1293. priv->ucode_init_data.len = init_data_size;
  1294. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1295. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1296. goto err_pci_alloc;
  1297. }
  1298. /* Bootstrap (instructions only, no data) */
  1299. if (boot_size) {
  1300. priv->ucode_boot.len = boot_size;
  1301. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1302. if (!priv->ucode_boot.v_addr)
  1303. goto err_pci_alloc;
  1304. }
  1305. /* Copy images into buffers for card's bus-master reads ... */
  1306. /* Runtime instructions (first block of data in file) */
  1307. len = inst_size;
  1308. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1309. memcpy(priv->ucode_code.v_addr, src, len);
  1310. src += len;
  1311. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1312. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1313. /* Runtime data (2nd block)
  1314. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1315. len = data_size;
  1316. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1317. memcpy(priv->ucode_data.v_addr, src, len);
  1318. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1319. src += len;
  1320. /* Initialization instructions (3rd block) */
  1321. if (init_size) {
  1322. len = init_size;
  1323. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1324. len);
  1325. memcpy(priv->ucode_init.v_addr, src, len);
  1326. src += len;
  1327. }
  1328. /* Initialization data (4th block) */
  1329. if (init_data_size) {
  1330. len = init_data_size;
  1331. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1332. len);
  1333. memcpy(priv->ucode_init_data.v_addr, src, len);
  1334. src += len;
  1335. }
  1336. /* Bootstrap instructions (5th block) */
  1337. len = boot_size;
  1338. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1339. memcpy(priv->ucode_boot.v_addr, src, len);
  1340. /* We have our copies now, allow OS release its copies */
  1341. release_firmware(ucode_raw);
  1342. return 0;
  1343. err_pci_alloc:
  1344. IWL_ERR(priv, "failed to allocate pci memory\n");
  1345. ret = -ENOMEM;
  1346. iwl_dealloc_ucode_pci(priv);
  1347. err_release:
  1348. release_firmware(ucode_raw);
  1349. error:
  1350. return ret;
  1351. }
  1352. static const char *desc_lookup_text[] = {
  1353. "OK",
  1354. "FAIL",
  1355. "BAD_PARAM",
  1356. "BAD_CHECKSUM",
  1357. "NMI_INTERRUPT_WDG",
  1358. "SYSASSERT",
  1359. "FATAL_ERROR",
  1360. "BAD_COMMAND",
  1361. "HW_ERROR_TUNE_LOCK",
  1362. "HW_ERROR_TEMPERATURE",
  1363. "ILLEGAL_CHAN_FREQ",
  1364. "VCC_NOT_STABLE",
  1365. "FH_ERROR",
  1366. "NMI_INTERRUPT_HOST",
  1367. "NMI_INTERRUPT_ACTION_PT",
  1368. "NMI_INTERRUPT_UNKNOWN",
  1369. "UCODE_VERSION_MISMATCH",
  1370. "HW_ERROR_ABS_LOCK",
  1371. "HW_ERROR_CAL_LOCK_FAIL",
  1372. "NMI_INTERRUPT_INST_ACTION_PT",
  1373. "NMI_INTERRUPT_DATA_ACTION_PT",
  1374. "NMI_TRM_HW_ER",
  1375. "NMI_INTERRUPT_TRM",
  1376. "NMI_INTERRUPT_BREAK_POINT"
  1377. "DEBUG_0",
  1378. "DEBUG_1",
  1379. "DEBUG_2",
  1380. "DEBUG_3",
  1381. "UNKNOWN"
  1382. };
  1383. static const char *desc_lookup(int i)
  1384. {
  1385. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1386. if (i < 0 || i > max)
  1387. i = max;
  1388. return desc_lookup_text[i];
  1389. }
  1390. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1391. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1392. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1393. {
  1394. u32 data2, line;
  1395. u32 desc, time, count, base, data1;
  1396. u32 blink1, blink2, ilink1, ilink2;
  1397. if (priv->ucode_type == UCODE_INIT)
  1398. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1399. else
  1400. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1401. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1402. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1403. return;
  1404. }
  1405. count = iwl_read_targ_mem(priv, base);
  1406. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1407. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1408. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1409. priv->status, count);
  1410. }
  1411. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1412. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1413. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1414. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1415. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1416. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1417. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1418. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1419. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1420. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1421. blink1, blink2, ilink1, ilink2);
  1422. IWL_ERR(priv, "Desc Time "
  1423. "data1 data2 line\n");
  1424. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1425. desc_lookup(desc), desc, time, data1, data2, line);
  1426. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1427. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1428. ilink1, ilink2);
  1429. }
  1430. #ifdef CONFIG_IWLWIFI_DEBUG
  1431. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1432. /**
  1433. * iwl_print_event_log - Dump error event log to syslog
  1434. *
  1435. */
  1436. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1437. u32 num_events, u32 mode)
  1438. {
  1439. u32 i;
  1440. u32 base; /* SRAM byte address of event log header */
  1441. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1442. u32 ptr; /* SRAM byte address of log data */
  1443. u32 ev, time, data; /* event log data */
  1444. unsigned long reg_flags;
  1445. if (num_events == 0)
  1446. return;
  1447. if (priv->ucode_type == UCODE_INIT)
  1448. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1449. else
  1450. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1451. if (mode == 0)
  1452. event_size = 2 * sizeof(u32);
  1453. else
  1454. event_size = 3 * sizeof(u32);
  1455. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1456. /* Make sure device is powered up for SRAM reads */
  1457. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1458. iwl_grab_nic_access(priv);
  1459. /* Set starting address; reads will auto-increment */
  1460. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1461. rmb();
  1462. /* "time" is actually "data" for mode 0 (no timestamp).
  1463. * place event id # at far right for easier visual parsing. */
  1464. for (i = 0; i < num_events; i++) {
  1465. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1466. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1467. if (mode == 0) {
  1468. /* data, ev */
  1469. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1470. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1471. } else {
  1472. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1473. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1474. time, data, ev);
  1475. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1476. }
  1477. }
  1478. /* Allow device to power down */
  1479. iwl_release_nic_access(priv);
  1480. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1481. }
  1482. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1483. #define MAX_EVENT_LOG_SIZE (512)
  1484. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1485. {
  1486. u32 base; /* SRAM byte address of event log header */
  1487. u32 capacity; /* event log capacity in # entries */
  1488. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1489. u32 num_wraps; /* # times uCode wrapped to top of log */
  1490. u32 next_entry; /* index of next entry to be written by uCode */
  1491. u32 size; /* # entries that we'll print */
  1492. if (priv->ucode_type == UCODE_INIT)
  1493. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1494. else
  1495. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1496. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1497. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1498. return;
  1499. }
  1500. /* event log header */
  1501. capacity = iwl_read_targ_mem(priv, base);
  1502. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1503. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1504. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1505. if (capacity > MAX_EVENT_LOG_SIZE) {
  1506. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1507. capacity, MAX_EVENT_LOG_SIZE);
  1508. capacity = MAX_EVENT_LOG_SIZE;
  1509. }
  1510. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1511. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1512. next_entry, MAX_EVENT_LOG_SIZE);
  1513. next_entry = MAX_EVENT_LOG_SIZE;
  1514. }
  1515. size = num_wraps ? capacity : next_entry;
  1516. /* bail out if nothing in log */
  1517. if (size == 0) {
  1518. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1519. return;
  1520. }
  1521. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1522. size, num_wraps);
  1523. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1524. * i.e the next one that uCode would fill. */
  1525. if (num_wraps)
  1526. iwl_print_event_log(priv, next_entry,
  1527. capacity - next_entry, mode);
  1528. /* (then/else) start at top of log */
  1529. iwl_print_event_log(priv, 0, next_entry, mode);
  1530. }
  1531. #endif
  1532. /**
  1533. * iwl_alive_start - called after REPLY_ALIVE notification received
  1534. * from protocol/runtime uCode (initialization uCode's
  1535. * Alive gets handled by iwl_init_alive_start()).
  1536. */
  1537. static void iwl_alive_start(struct iwl_priv *priv)
  1538. {
  1539. int ret = 0;
  1540. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1541. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1542. /* We had an error bringing up the hardware, so take it
  1543. * all the way back down so we can try again */
  1544. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1545. goto restart;
  1546. }
  1547. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1548. * This is a paranoid check, because we would not have gotten the
  1549. * "runtime" alive if code weren't properly loaded. */
  1550. if (iwl_verify_ucode(priv)) {
  1551. /* Runtime instruction load was bad;
  1552. * take it all the way back down so we can try again */
  1553. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1554. goto restart;
  1555. }
  1556. iwl_clear_stations_table(priv);
  1557. ret = priv->cfg->ops->lib->alive_notify(priv);
  1558. if (ret) {
  1559. IWL_WARN(priv,
  1560. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1561. goto restart;
  1562. }
  1563. /* After the ALIVE response, we can send host commands to the uCode */
  1564. set_bit(STATUS_ALIVE, &priv->status);
  1565. if (iwl_is_rfkill(priv))
  1566. return;
  1567. ieee80211_wake_queues(priv->hw);
  1568. priv->active_rate = priv->rates_mask;
  1569. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1570. /* Configure Tx antenna selection based on H/W config */
  1571. if (priv->cfg->ops->hcmd->set_tx_ant)
  1572. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1573. if (iwl_is_associated(priv)) {
  1574. struct iwl_rxon_cmd *active_rxon =
  1575. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1576. /* apply any changes in staging */
  1577. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1578. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1579. } else {
  1580. /* Initialize our rx_config data */
  1581. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1582. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1583. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1584. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1585. }
  1586. /* Configure Bluetooth device coexistence support */
  1587. iwl_send_bt_config(priv);
  1588. iwl_reset_run_time_calib(priv);
  1589. /* Configure the adapter for unassociated operation */
  1590. iwlcore_commit_rxon(priv);
  1591. /* At this point, the NIC is initialized and operational */
  1592. iwl_rf_kill_ct_config(priv);
  1593. iwl_leds_init(priv);
  1594. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1595. set_bit(STATUS_READY, &priv->status);
  1596. wake_up_interruptible(&priv->wait_command_queue);
  1597. iwl_power_update_mode(priv, true);
  1598. /* reassociate for ADHOC mode */
  1599. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1600. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1601. priv->vif);
  1602. if (beacon)
  1603. iwl_mac_beacon_update(priv->hw, beacon);
  1604. }
  1605. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1606. iwl_set_mode(priv, priv->iw_mode);
  1607. return;
  1608. restart:
  1609. queue_work(priv->workqueue, &priv->restart);
  1610. }
  1611. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1612. static void __iwl_down(struct iwl_priv *priv)
  1613. {
  1614. unsigned long flags;
  1615. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1616. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1617. if (!exit_pending)
  1618. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1619. iwl_clear_stations_table(priv);
  1620. /* Unblock any waiting calls */
  1621. wake_up_interruptible_all(&priv->wait_command_queue);
  1622. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1623. * exiting the module */
  1624. if (!exit_pending)
  1625. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1626. /* stop and reset the on-board processor */
  1627. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1628. /* tell the device to stop sending interrupts */
  1629. spin_lock_irqsave(&priv->lock, flags);
  1630. iwl_disable_interrupts(priv);
  1631. spin_unlock_irqrestore(&priv->lock, flags);
  1632. iwl_synchronize_irq(priv);
  1633. if (priv->mac80211_registered)
  1634. ieee80211_stop_queues(priv->hw);
  1635. /* If we have not previously called iwl_init() then
  1636. * clear all bits but the RF Kill bit and return */
  1637. if (!iwl_is_init(priv)) {
  1638. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1639. STATUS_RF_KILL_HW |
  1640. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1641. STATUS_GEO_CONFIGURED |
  1642. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1643. STATUS_EXIT_PENDING;
  1644. goto exit;
  1645. }
  1646. /* ...otherwise clear out all the status bits but the RF Kill
  1647. * bit and continue taking the NIC down. */
  1648. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1649. STATUS_RF_KILL_HW |
  1650. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1651. STATUS_GEO_CONFIGURED |
  1652. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1653. STATUS_FW_ERROR |
  1654. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1655. STATUS_EXIT_PENDING;
  1656. /* device going down, Stop using ICT table */
  1657. iwl_disable_ict(priv);
  1658. iwl_txq_ctx_stop(priv);
  1659. iwl_rxq_stop(priv);
  1660. /* Power-down device's busmaster DMA clocks */
  1661. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1662. udelay(5);
  1663. /* Make sure (redundant) we've released our request to stay awake */
  1664. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1665. /* Stop the device, and put it in low power state */
  1666. priv->cfg->ops->lib->apm_ops.stop(priv);
  1667. exit:
  1668. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1669. if (priv->ibss_beacon)
  1670. dev_kfree_skb(priv->ibss_beacon);
  1671. priv->ibss_beacon = NULL;
  1672. /* clear out any free frames */
  1673. iwl_clear_free_frames(priv);
  1674. }
  1675. static void iwl_down(struct iwl_priv *priv)
  1676. {
  1677. mutex_lock(&priv->mutex);
  1678. __iwl_down(priv);
  1679. mutex_unlock(&priv->mutex);
  1680. iwl_cancel_deferred_work(priv);
  1681. }
  1682. #define HW_READY_TIMEOUT (50)
  1683. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1684. {
  1685. int ret = 0;
  1686. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1687. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1688. /* See if we got it */
  1689. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1690. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1691. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1692. HW_READY_TIMEOUT);
  1693. if (ret != -ETIMEDOUT)
  1694. priv->hw_ready = true;
  1695. else
  1696. priv->hw_ready = false;
  1697. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1698. (priv->hw_ready == 1) ? "ready" : "not ready");
  1699. return ret;
  1700. }
  1701. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1702. {
  1703. int ret = 0;
  1704. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1705. ret = iwl_set_hw_ready(priv);
  1706. if (priv->hw_ready)
  1707. return ret;
  1708. /* If HW is not ready, prepare the conditions to check again */
  1709. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1710. CSR_HW_IF_CONFIG_REG_PREPARE);
  1711. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1712. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1713. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1714. /* HW should be ready by now, check again. */
  1715. if (ret != -ETIMEDOUT)
  1716. iwl_set_hw_ready(priv);
  1717. return ret;
  1718. }
  1719. #define MAX_HW_RESTARTS 5
  1720. static int __iwl_up(struct iwl_priv *priv)
  1721. {
  1722. int i;
  1723. int ret;
  1724. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1725. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1726. return -EIO;
  1727. }
  1728. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1729. IWL_ERR(priv, "ucode not available for device bringup\n");
  1730. return -EIO;
  1731. }
  1732. iwl_prepare_card_hw(priv);
  1733. if (!priv->hw_ready) {
  1734. IWL_WARN(priv, "Exit HW not ready\n");
  1735. return -EIO;
  1736. }
  1737. /* If platform's RF_KILL switch is NOT set to KILL */
  1738. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1739. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1740. else
  1741. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1742. if (iwl_is_rfkill(priv)) {
  1743. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1744. iwl_enable_interrupts(priv);
  1745. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1746. return 0;
  1747. }
  1748. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1749. ret = iwl_hw_nic_init(priv);
  1750. if (ret) {
  1751. IWL_ERR(priv, "Unable to init nic\n");
  1752. return ret;
  1753. }
  1754. /* make sure rfkill handshake bits are cleared */
  1755. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1756. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1757. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1758. /* clear (again), then enable host interrupts */
  1759. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1760. iwl_enable_interrupts(priv);
  1761. /* really make sure rfkill handshake bits are cleared */
  1762. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1763. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1764. /* Copy original ucode data image from disk into backup cache.
  1765. * This will be used to initialize the on-board processor's
  1766. * data SRAM for a clean start when the runtime program first loads. */
  1767. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1768. priv->ucode_data.len);
  1769. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1770. iwl_clear_stations_table(priv);
  1771. /* load bootstrap state machine,
  1772. * load bootstrap program into processor's memory,
  1773. * prepare to load the "initialize" uCode */
  1774. ret = priv->cfg->ops->lib->load_ucode(priv);
  1775. if (ret) {
  1776. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1777. ret);
  1778. continue;
  1779. }
  1780. /* start card; "initialize" will load runtime ucode */
  1781. iwl_nic_start(priv);
  1782. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1783. return 0;
  1784. }
  1785. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1786. __iwl_down(priv);
  1787. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1788. /* tried to restart and config the device for as long as our
  1789. * patience could withstand */
  1790. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1791. return -EIO;
  1792. }
  1793. /*****************************************************************************
  1794. *
  1795. * Workqueue callbacks
  1796. *
  1797. *****************************************************************************/
  1798. static void iwl_bg_init_alive_start(struct work_struct *data)
  1799. {
  1800. struct iwl_priv *priv =
  1801. container_of(data, struct iwl_priv, init_alive_start.work);
  1802. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1803. return;
  1804. mutex_lock(&priv->mutex);
  1805. priv->cfg->ops->lib->init_alive_start(priv);
  1806. mutex_unlock(&priv->mutex);
  1807. }
  1808. static void iwl_bg_alive_start(struct work_struct *data)
  1809. {
  1810. struct iwl_priv *priv =
  1811. container_of(data, struct iwl_priv, alive_start.work);
  1812. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1813. return;
  1814. /* enable dram interrupt */
  1815. iwl_reset_ict(priv);
  1816. mutex_lock(&priv->mutex);
  1817. iwl_alive_start(priv);
  1818. mutex_unlock(&priv->mutex);
  1819. }
  1820. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1821. {
  1822. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1823. run_time_calib_work);
  1824. mutex_lock(&priv->mutex);
  1825. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1826. test_bit(STATUS_SCANNING, &priv->status)) {
  1827. mutex_unlock(&priv->mutex);
  1828. return;
  1829. }
  1830. if (priv->start_calib) {
  1831. iwl_chain_noise_calibration(priv, &priv->statistics);
  1832. iwl_sensitivity_calibration(priv, &priv->statistics);
  1833. }
  1834. mutex_unlock(&priv->mutex);
  1835. return;
  1836. }
  1837. static void iwl_bg_up(struct work_struct *data)
  1838. {
  1839. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1840. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1841. return;
  1842. mutex_lock(&priv->mutex);
  1843. __iwl_up(priv);
  1844. mutex_unlock(&priv->mutex);
  1845. }
  1846. static void iwl_bg_restart(struct work_struct *data)
  1847. {
  1848. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1849. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1850. return;
  1851. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1852. mutex_lock(&priv->mutex);
  1853. priv->vif = NULL;
  1854. priv->is_open = 0;
  1855. mutex_unlock(&priv->mutex);
  1856. iwl_down(priv);
  1857. ieee80211_restart_hw(priv->hw);
  1858. } else {
  1859. iwl_down(priv);
  1860. queue_work(priv->workqueue, &priv->up);
  1861. }
  1862. }
  1863. static void iwl_bg_rx_replenish(struct work_struct *data)
  1864. {
  1865. struct iwl_priv *priv =
  1866. container_of(data, struct iwl_priv, rx_replenish);
  1867. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1868. return;
  1869. mutex_lock(&priv->mutex);
  1870. iwl_rx_replenish(priv);
  1871. mutex_unlock(&priv->mutex);
  1872. }
  1873. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1874. void iwl_post_associate(struct iwl_priv *priv)
  1875. {
  1876. struct ieee80211_conf *conf = NULL;
  1877. int ret = 0;
  1878. unsigned long flags;
  1879. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1880. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1881. return;
  1882. }
  1883. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1884. priv->assoc_id, priv->active_rxon.bssid_addr);
  1885. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1886. return;
  1887. if (!priv->vif || !priv->is_open)
  1888. return;
  1889. iwl_scan_cancel_timeout(priv, 200);
  1890. conf = ieee80211_get_hw_conf(priv->hw);
  1891. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1892. iwlcore_commit_rxon(priv);
  1893. iwl_setup_rxon_timing(priv);
  1894. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1895. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1896. if (ret)
  1897. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1898. "Attempting to continue.\n");
  1899. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1900. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1901. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1902. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1903. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1904. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1905. priv->assoc_id, priv->beacon_int);
  1906. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1907. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1908. else
  1909. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1910. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1911. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1912. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1913. else
  1914. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1915. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1916. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1917. }
  1918. iwlcore_commit_rxon(priv);
  1919. switch (priv->iw_mode) {
  1920. case NL80211_IFTYPE_STATION:
  1921. break;
  1922. case NL80211_IFTYPE_ADHOC:
  1923. /* assume default assoc id */
  1924. priv->assoc_id = 1;
  1925. iwl_rxon_add_station(priv, priv->bssid, 0);
  1926. iwl_send_beacon_cmd(priv);
  1927. break;
  1928. default:
  1929. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1930. __func__, priv->iw_mode);
  1931. break;
  1932. }
  1933. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1934. priv->assoc_station_added = 1;
  1935. spin_lock_irqsave(&priv->lock, flags);
  1936. iwl_activate_qos(priv, 0);
  1937. spin_unlock_irqrestore(&priv->lock, flags);
  1938. /* the chain noise calibration will enabled PM upon completion
  1939. * If chain noise has already been run, then we need to enable
  1940. * power management here */
  1941. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1942. iwl_power_update_mode(priv, false);
  1943. /* Enable Rx differential gain and sensitivity calibrations */
  1944. iwl_chain_noise_reset(priv);
  1945. priv->start_calib = 1;
  1946. }
  1947. /*****************************************************************************
  1948. *
  1949. * mac80211 entry point functions
  1950. *
  1951. *****************************************************************************/
  1952. #define UCODE_READY_TIMEOUT (4 * HZ)
  1953. /*
  1954. * Not a mac80211 entry point function, but it fits in with all the
  1955. * other mac80211 functions grouped here.
  1956. */
  1957. static int iwl_setup_mac(struct iwl_priv *priv)
  1958. {
  1959. int ret;
  1960. struct ieee80211_hw *hw = priv->hw;
  1961. hw->rate_control_algorithm = "iwl-agn-rs";
  1962. /* Tell mac80211 our characteristics */
  1963. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1964. IEEE80211_HW_NOISE_DBM |
  1965. IEEE80211_HW_AMPDU_AGGREGATION |
  1966. IEEE80211_HW_SPECTRUM_MGMT;
  1967. if (!priv->cfg->broken_powersave)
  1968. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1969. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1970. hw->sta_data_size = sizeof(struct iwl_station_priv);
  1971. hw->wiphy->interface_modes =
  1972. BIT(NL80211_IFTYPE_STATION) |
  1973. BIT(NL80211_IFTYPE_ADHOC);
  1974. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  1975. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  1976. /*
  1977. * For now, disable PS by default because it affects
  1978. * RX performance significantly.
  1979. */
  1980. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  1981. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1982. /* we create the 802.11 header and a zero-length SSID element */
  1983. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1984. /* Default value; 4 EDCA QOS priorities */
  1985. hw->queues = 4;
  1986. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1987. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1988. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1989. &priv->bands[IEEE80211_BAND_2GHZ];
  1990. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1991. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1992. &priv->bands[IEEE80211_BAND_5GHZ];
  1993. ret = ieee80211_register_hw(priv->hw);
  1994. if (ret) {
  1995. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1996. return ret;
  1997. }
  1998. priv->mac80211_registered = 1;
  1999. return 0;
  2000. }
  2001. static int iwl_mac_start(struct ieee80211_hw *hw)
  2002. {
  2003. struct iwl_priv *priv = hw->priv;
  2004. int ret;
  2005. IWL_DEBUG_MAC80211(priv, "enter\n");
  2006. /* we should be verifying the device is ready to be opened */
  2007. mutex_lock(&priv->mutex);
  2008. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2009. * ucode filename and max sizes are card-specific. */
  2010. if (!priv->ucode_code.len) {
  2011. ret = iwl_read_ucode(priv);
  2012. if (ret) {
  2013. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2014. mutex_unlock(&priv->mutex);
  2015. return ret;
  2016. }
  2017. }
  2018. ret = __iwl_up(priv);
  2019. mutex_unlock(&priv->mutex);
  2020. if (ret)
  2021. return ret;
  2022. if (iwl_is_rfkill(priv))
  2023. goto out;
  2024. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2025. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2026. * mac80211 will not be run successfully. */
  2027. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2028. test_bit(STATUS_READY, &priv->status),
  2029. UCODE_READY_TIMEOUT);
  2030. if (!ret) {
  2031. if (!test_bit(STATUS_READY, &priv->status)) {
  2032. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2033. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2034. return -ETIMEDOUT;
  2035. }
  2036. }
  2037. iwl_led_start(priv);
  2038. out:
  2039. priv->is_open = 1;
  2040. IWL_DEBUG_MAC80211(priv, "leave\n");
  2041. return 0;
  2042. }
  2043. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2044. {
  2045. struct iwl_priv *priv = hw->priv;
  2046. IWL_DEBUG_MAC80211(priv, "enter\n");
  2047. if (!priv->is_open)
  2048. return;
  2049. priv->is_open = 0;
  2050. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2051. /* stop mac, cancel any scan request and clear
  2052. * RXON_FILTER_ASSOC_MSK BIT
  2053. */
  2054. mutex_lock(&priv->mutex);
  2055. iwl_scan_cancel_timeout(priv, 100);
  2056. mutex_unlock(&priv->mutex);
  2057. }
  2058. iwl_down(priv);
  2059. flush_workqueue(priv->workqueue);
  2060. /* enable interrupts again in order to receive rfkill changes */
  2061. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2062. iwl_enable_interrupts(priv);
  2063. IWL_DEBUG_MAC80211(priv, "leave\n");
  2064. }
  2065. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2066. {
  2067. struct iwl_priv *priv = hw->priv;
  2068. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2069. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2070. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2071. if (iwl_tx_skb(priv, skb))
  2072. dev_kfree_skb_any(skb);
  2073. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2074. return NETDEV_TX_OK;
  2075. }
  2076. void iwl_config_ap(struct iwl_priv *priv)
  2077. {
  2078. int ret = 0;
  2079. unsigned long flags;
  2080. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2081. return;
  2082. /* The following should be done only at AP bring up */
  2083. if (!iwl_is_associated(priv)) {
  2084. /* RXON - unassoc (to set timing command) */
  2085. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2086. iwlcore_commit_rxon(priv);
  2087. /* RXON Timing */
  2088. iwl_setup_rxon_timing(priv);
  2089. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2090. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2091. if (ret)
  2092. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2093. "Attempting to continue.\n");
  2094. /* AP has all antennas */
  2095. priv->chain_noise_data.active_chains =
  2096. priv->hw_params.valid_rx_ant;
  2097. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2098. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2099. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2100. /* FIXME: what should be the assoc_id for AP? */
  2101. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2102. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2103. priv->staging_rxon.flags |=
  2104. RXON_FLG_SHORT_PREAMBLE_MSK;
  2105. else
  2106. priv->staging_rxon.flags &=
  2107. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2108. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2109. if (priv->assoc_capability &
  2110. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2111. priv->staging_rxon.flags |=
  2112. RXON_FLG_SHORT_SLOT_MSK;
  2113. else
  2114. priv->staging_rxon.flags &=
  2115. ~RXON_FLG_SHORT_SLOT_MSK;
  2116. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2117. priv->staging_rxon.flags &=
  2118. ~RXON_FLG_SHORT_SLOT_MSK;
  2119. }
  2120. /* restore RXON assoc */
  2121. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2122. iwlcore_commit_rxon(priv);
  2123. iwl_reset_qos(priv);
  2124. spin_lock_irqsave(&priv->lock, flags);
  2125. iwl_activate_qos(priv, 1);
  2126. spin_unlock_irqrestore(&priv->lock, flags);
  2127. iwl_add_bcast_station(priv);
  2128. }
  2129. iwl_send_beacon_cmd(priv);
  2130. /* FIXME - we need to add code here to detect a totally new
  2131. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2132. * clear sta table, add BCAST sta... */
  2133. }
  2134. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2135. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2136. u32 iv32, u16 *phase1key)
  2137. {
  2138. struct iwl_priv *priv = hw->priv;
  2139. IWL_DEBUG_MAC80211(priv, "enter\n");
  2140. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2141. IWL_DEBUG_MAC80211(priv, "leave\n");
  2142. }
  2143. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2144. struct ieee80211_vif *vif,
  2145. struct ieee80211_sta *sta,
  2146. struct ieee80211_key_conf *key)
  2147. {
  2148. struct iwl_priv *priv = hw->priv;
  2149. const u8 *addr;
  2150. int ret;
  2151. u8 sta_id;
  2152. bool is_default_wep_key = false;
  2153. IWL_DEBUG_MAC80211(priv, "enter\n");
  2154. if (priv->cfg->mod_params->sw_crypto) {
  2155. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2156. return -EOPNOTSUPP;
  2157. }
  2158. addr = sta ? sta->addr : iwl_bcast_addr;
  2159. sta_id = iwl_find_station(priv, addr);
  2160. if (sta_id == IWL_INVALID_STATION) {
  2161. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2162. addr);
  2163. return -EINVAL;
  2164. }
  2165. mutex_lock(&priv->mutex);
  2166. iwl_scan_cancel_timeout(priv, 100);
  2167. mutex_unlock(&priv->mutex);
  2168. /* If we are getting WEP group key and we didn't receive any key mapping
  2169. * so far, we are in legacy wep mode (group key only), otherwise we are
  2170. * in 1X mode.
  2171. * In legacy wep mode, we use another host command to the uCode */
  2172. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2173. priv->iw_mode != NL80211_IFTYPE_AP) {
  2174. if (cmd == SET_KEY)
  2175. is_default_wep_key = !priv->key_mapping_key;
  2176. else
  2177. is_default_wep_key =
  2178. (key->hw_key_idx == HW_KEY_DEFAULT);
  2179. }
  2180. switch (cmd) {
  2181. case SET_KEY:
  2182. if (is_default_wep_key)
  2183. ret = iwl_set_default_wep_key(priv, key);
  2184. else
  2185. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2186. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2187. break;
  2188. case DISABLE_KEY:
  2189. if (is_default_wep_key)
  2190. ret = iwl_remove_default_wep_key(priv, key);
  2191. else
  2192. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2193. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2194. break;
  2195. default:
  2196. ret = -EINVAL;
  2197. }
  2198. IWL_DEBUG_MAC80211(priv, "leave\n");
  2199. return ret;
  2200. }
  2201. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2202. struct ieee80211_vif *vif,
  2203. enum ieee80211_ampdu_mlme_action action,
  2204. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2205. {
  2206. struct iwl_priv *priv = hw->priv;
  2207. int ret;
  2208. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2209. sta->addr, tid);
  2210. if (!(priv->cfg->sku & IWL_SKU_N))
  2211. return -EACCES;
  2212. switch (action) {
  2213. case IEEE80211_AMPDU_RX_START:
  2214. IWL_DEBUG_HT(priv, "start Rx\n");
  2215. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2216. case IEEE80211_AMPDU_RX_STOP:
  2217. IWL_DEBUG_HT(priv, "stop Rx\n");
  2218. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2219. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2220. return 0;
  2221. else
  2222. return ret;
  2223. case IEEE80211_AMPDU_TX_START:
  2224. IWL_DEBUG_HT(priv, "start Tx\n");
  2225. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2226. case IEEE80211_AMPDU_TX_STOP:
  2227. IWL_DEBUG_HT(priv, "stop Tx\n");
  2228. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2229. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2230. return 0;
  2231. else
  2232. return ret;
  2233. default:
  2234. IWL_DEBUG_HT(priv, "unknown\n");
  2235. return -EINVAL;
  2236. break;
  2237. }
  2238. return 0;
  2239. }
  2240. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2241. struct ieee80211_low_level_stats *stats)
  2242. {
  2243. struct iwl_priv *priv = hw->priv;
  2244. priv = hw->priv;
  2245. IWL_DEBUG_MAC80211(priv, "enter\n");
  2246. IWL_DEBUG_MAC80211(priv, "leave\n");
  2247. return 0;
  2248. }
  2249. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2250. struct ieee80211_vif *vif,
  2251. enum sta_notify_cmd cmd,
  2252. struct ieee80211_sta *sta)
  2253. {
  2254. struct iwl_priv *priv = hw->priv;
  2255. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2256. int sta_id;
  2257. /*
  2258. * TODO: We really should use this callback to
  2259. * actually maintain the station table in
  2260. * the device.
  2261. */
  2262. switch (cmd) {
  2263. case STA_NOTIFY_ADD:
  2264. atomic_set(&sta_priv->pending_frames, 0);
  2265. if (vif->type == NL80211_IFTYPE_AP)
  2266. sta_priv->client = true;
  2267. break;
  2268. case STA_NOTIFY_SLEEP:
  2269. WARN_ON(!sta_priv->client);
  2270. sta_priv->asleep = true;
  2271. if (atomic_read(&sta_priv->pending_frames) > 0)
  2272. ieee80211_sta_block_awake(hw, sta, true);
  2273. break;
  2274. case STA_NOTIFY_AWAKE:
  2275. WARN_ON(!sta_priv->client);
  2276. sta_priv->asleep = false;
  2277. sta_id = iwl_find_station(priv, sta->addr);
  2278. if (sta_id != IWL_INVALID_STATION)
  2279. iwl_sta_modify_ps_wake(priv, sta_id);
  2280. break;
  2281. default:
  2282. break;
  2283. }
  2284. }
  2285. /*****************************************************************************
  2286. *
  2287. * sysfs attributes
  2288. *
  2289. *****************************************************************************/
  2290. #ifdef CONFIG_IWLWIFI_DEBUG
  2291. /*
  2292. * The following adds a new attribute to the sysfs representation
  2293. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2294. * used for controlling the debug level.
  2295. *
  2296. * See the level definitions in iwl for details.
  2297. *
  2298. * The debug_level being managed using sysfs below is a per device debug
  2299. * level that is used instead of the global debug level if it (the per
  2300. * device debug level) is set.
  2301. */
  2302. static ssize_t show_debug_level(struct device *d,
  2303. struct device_attribute *attr, char *buf)
  2304. {
  2305. struct iwl_priv *priv = dev_get_drvdata(d);
  2306. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2307. }
  2308. static ssize_t store_debug_level(struct device *d,
  2309. struct device_attribute *attr,
  2310. const char *buf, size_t count)
  2311. {
  2312. struct iwl_priv *priv = dev_get_drvdata(d);
  2313. unsigned long val;
  2314. int ret;
  2315. ret = strict_strtoul(buf, 0, &val);
  2316. if (ret)
  2317. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2318. else {
  2319. priv->debug_level = val;
  2320. if (iwl_alloc_traffic_mem(priv))
  2321. IWL_ERR(priv,
  2322. "Not enough memory to generate traffic log\n");
  2323. }
  2324. return strnlen(buf, count);
  2325. }
  2326. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2327. show_debug_level, store_debug_level);
  2328. #endif /* CONFIG_IWLWIFI_DEBUG */
  2329. static ssize_t show_temperature(struct device *d,
  2330. struct device_attribute *attr, char *buf)
  2331. {
  2332. struct iwl_priv *priv = dev_get_drvdata(d);
  2333. if (!iwl_is_alive(priv))
  2334. return -EAGAIN;
  2335. return sprintf(buf, "%d\n", priv->temperature);
  2336. }
  2337. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2338. static ssize_t show_tx_power(struct device *d,
  2339. struct device_attribute *attr, char *buf)
  2340. {
  2341. struct iwl_priv *priv = dev_get_drvdata(d);
  2342. if (!iwl_is_ready_rf(priv))
  2343. return sprintf(buf, "off\n");
  2344. else
  2345. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2346. }
  2347. static ssize_t store_tx_power(struct device *d,
  2348. struct device_attribute *attr,
  2349. const char *buf, size_t count)
  2350. {
  2351. struct iwl_priv *priv = dev_get_drvdata(d);
  2352. unsigned long val;
  2353. int ret;
  2354. ret = strict_strtoul(buf, 10, &val);
  2355. if (ret)
  2356. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2357. else {
  2358. ret = iwl_set_tx_power(priv, val, false);
  2359. if (ret)
  2360. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2361. ret);
  2362. else
  2363. ret = count;
  2364. }
  2365. return ret;
  2366. }
  2367. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2368. static ssize_t show_flags(struct device *d,
  2369. struct device_attribute *attr, char *buf)
  2370. {
  2371. struct iwl_priv *priv = dev_get_drvdata(d);
  2372. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2373. }
  2374. static ssize_t store_flags(struct device *d,
  2375. struct device_attribute *attr,
  2376. const char *buf, size_t count)
  2377. {
  2378. struct iwl_priv *priv = dev_get_drvdata(d);
  2379. unsigned long val;
  2380. u32 flags;
  2381. int ret = strict_strtoul(buf, 0, &val);
  2382. if (ret)
  2383. return ret;
  2384. flags = (u32)val;
  2385. mutex_lock(&priv->mutex);
  2386. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2387. /* Cancel any currently running scans... */
  2388. if (iwl_scan_cancel_timeout(priv, 100))
  2389. IWL_WARN(priv, "Could not cancel scan.\n");
  2390. else {
  2391. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2392. priv->staging_rxon.flags = cpu_to_le32(flags);
  2393. iwlcore_commit_rxon(priv);
  2394. }
  2395. }
  2396. mutex_unlock(&priv->mutex);
  2397. return count;
  2398. }
  2399. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2400. static ssize_t show_filter_flags(struct device *d,
  2401. struct device_attribute *attr, char *buf)
  2402. {
  2403. struct iwl_priv *priv = dev_get_drvdata(d);
  2404. return sprintf(buf, "0x%04X\n",
  2405. le32_to_cpu(priv->active_rxon.filter_flags));
  2406. }
  2407. static ssize_t store_filter_flags(struct device *d,
  2408. struct device_attribute *attr,
  2409. const char *buf, size_t count)
  2410. {
  2411. struct iwl_priv *priv = dev_get_drvdata(d);
  2412. unsigned long val;
  2413. u32 filter_flags;
  2414. int ret = strict_strtoul(buf, 0, &val);
  2415. if (ret)
  2416. return ret;
  2417. filter_flags = (u32)val;
  2418. mutex_lock(&priv->mutex);
  2419. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2420. /* Cancel any currently running scans... */
  2421. if (iwl_scan_cancel_timeout(priv, 100))
  2422. IWL_WARN(priv, "Could not cancel scan.\n");
  2423. else {
  2424. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2425. "0x%04X\n", filter_flags);
  2426. priv->staging_rxon.filter_flags =
  2427. cpu_to_le32(filter_flags);
  2428. iwlcore_commit_rxon(priv);
  2429. }
  2430. }
  2431. mutex_unlock(&priv->mutex);
  2432. return count;
  2433. }
  2434. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2435. store_filter_flags);
  2436. static ssize_t show_statistics(struct device *d,
  2437. struct device_attribute *attr, char *buf)
  2438. {
  2439. struct iwl_priv *priv = dev_get_drvdata(d);
  2440. u32 size = sizeof(struct iwl_notif_statistics);
  2441. u32 len = 0, ofs = 0;
  2442. u8 *data = (u8 *)&priv->statistics;
  2443. int rc = 0;
  2444. if (!iwl_is_alive(priv))
  2445. return -EAGAIN;
  2446. mutex_lock(&priv->mutex);
  2447. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2448. mutex_unlock(&priv->mutex);
  2449. if (rc) {
  2450. len = sprintf(buf,
  2451. "Error sending statistics request: 0x%08X\n", rc);
  2452. return len;
  2453. }
  2454. while (size && (PAGE_SIZE - len)) {
  2455. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2456. PAGE_SIZE - len, 1);
  2457. len = strlen(buf);
  2458. if (PAGE_SIZE - len)
  2459. buf[len++] = '\n';
  2460. ofs += 16;
  2461. size -= min(size, 16U);
  2462. }
  2463. return len;
  2464. }
  2465. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2466. static ssize_t show_rts_ht_protection(struct device *d,
  2467. struct device_attribute *attr, char *buf)
  2468. {
  2469. struct iwl_priv *priv = dev_get_drvdata(d);
  2470. return sprintf(buf, "%s\n",
  2471. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2472. }
  2473. static ssize_t store_rts_ht_protection(struct device *d,
  2474. struct device_attribute *attr,
  2475. const char *buf, size_t count)
  2476. {
  2477. struct iwl_priv *priv = dev_get_drvdata(d);
  2478. unsigned long val;
  2479. int ret;
  2480. ret = strict_strtoul(buf, 10, &val);
  2481. if (ret)
  2482. IWL_INFO(priv, "Input is not in decimal form.\n");
  2483. else {
  2484. if (!iwl_is_associated(priv))
  2485. priv->cfg->use_rts_for_ht = val ? true : false;
  2486. else
  2487. IWL_ERR(priv, "Sta associated with AP - "
  2488. "Change protection mechanism is not allowed\n");
  2489. ret = count;
  2490. }
  2491. return ret;
  2492. }
  2493. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2494. show_rts_ht_protection, store_rts_ht_protection);
  2495. /*****************************************************************************
  2496. *
  2497. * driver setup and teardown
  2498. *
  2499. *****************************************************************************/
  2500. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2501. {
  2502. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2503. init_waitqueue_head(&priv->wait_command_queue);
  2504. INIT_WORK(&priv->up, iwl_bg_up);
  2505. INIT_WORK(&priv->restart, iwl_bg_restart);
  2506. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2507. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2508. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2509. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2510. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2511. iwl_setup_scan_deferred_work(priv);
  2512. if (priv->cfg->ops->lib->setup_deferred_work)
  2513. priv->cfg->ops->lib->setup_deferred_work(priv);
  2514. init_timer(&priv->statistics_periodic);
  2515. priv->statistics_periodic.data = (unsigned long)priv;
  2516. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2517. if (!priv->cfg->use_isr_legacy)
  2518. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2519. iwl_irq_tasklet, (unsigned long)priv);
  2520. else
  2521. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2522. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2523. }
  2524. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2525. {
  2526. if (priv->cfg->ops->lib->cancel_deferred_work)
  2527. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2528. cancel_delayed_work_sync(&priv->init_alive_start);
  2529. cancel_delayed_work(&priv->scan_check);
  2530. cancel_delayed_work(&priv->alive_start);
  2531. cancel_work_sync(&priv->beacon_update);
  2532. del_timer_sync(&priv->statistics_periodic);
  2533. }
  2534. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2535. struct ieee80211_rate *rates)
  2536. {
  2537. int i;
  2538. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2539. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2540. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2541. rates[i].hw_value_short = i;
  2542. rates[i].flags = 0;
  2543. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2544. /*
  2545. * If CCK != 1M then set short preamble rate flag.
  2546. */
  2547. rates[i].flags |=
  2548. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2549. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2550. }
  2551. }
  2552. }
  2553. static int iwl_init_drv(struct iwl_priv *priv)
  2554. {
  2555. int ret;
  2556. priv->ibss_beacon = NULL;
  2557. spin_lock_init(&priv->lock);
  2558. spin_lock_init(&priv->sta_lock);
  2559. spin_lock_init(&priv->hcmd_lock);
  2560. INIT_LIST_HEAD(&priv->free_frames);
  2561. mutex_init(&priv->mutex);
  2562. /* Clear the driver's (not device's) station table */
  2563. iwl_clear_stations_table(priv);
  2564. priv->ieee_channels = NULL;
  2565. priv->ieee_rates = NULL;
  2566. priv->band = IEEE80211_BAND_2GHZ;
  2567. priv->iw_mode = NL80211_IFTYPE_STATION;
  2568. /* Choose which receivers/antennas to use */
  2569. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2570. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2571. iwl_init_scan_params(priv);
  2572. iwl_reset_qos(priv);
  2573. priv->qos_data.qos_active = 0;
  2574. priv->qos_data.qos_cap.val = 0;
  2575. priv->rates_mask = IWL_RATES_MASK;
  2576. /* Set the tx_power_user_lmt to the lowest power level
  2577. * this value will get overwritten by channel max power avg
  2578. * from eeprom */
  2579. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2580. ret = iwl_init_channel_map(priv);
  2581. if (ret) {
  2582. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2583. goto err;
  2584. }
  2585. ret = iwlcore_init_geos(priv);
  2586. if (ret) {
  2587. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2588. goto err_free_channel_map;
  2589. }
  2590. iwl_init_hw_rates(priv, priv->ieee_rates);
  2591. return 0;
  2592. err_free_channel_map:
  2593. iwl_free_channel_map(priv);
  2594. err:
  2595. return ret;
  2596. }
  2597. static void iwl_uninit_drv(struct iwl_priv *priv)
  2598. {
  2599. iwl_calib_free_results(priv);
  2600. iwlcore_free_geos(priv);
  2601. iwl_free_channel_map(priv);
  2602. kfree(priv->scan);
  2603. }
  2604. static struct attribute *iwl_sysfs_entries[] = {
  2605. &dev_attr_flags.attr,
  2606. &dev_attr_filter_flags.attr,
  2607. &dev_attr_statistics.attr,
  2608. &dev_attr_temperature.attr,
  2609. &dev_attr_tx_power.attr,
  2610. &dev_attr_rts_ht_protection.attr,
  2611. #ifdef CONFIG_IWLWIFI_DEBUG
  2612. &dev_attr_debug_level.attr,
  2613. #endif
  2614. NULL
  2615. };
  2616. static struct attribute_group iwl_attribute_group = {
  2617. .name = NULL, /* put in device directory */
  2618. .attrs = iwl_sysfs_entries,
  2619. };
  2620. static struct ieee80211_ops iwl_hw_ops = {
  2621. .tx = iwl_mac_tx,
  2622. .start = iwl_mac_start,
  2623. .stop = iwl_mac_stop,
  2624. .add_interface = iwl_mac_add_interface,
  2625. .remove_interface = iwl_mac_remove_interface,
  2626. .config = iwl_mac_config,
  2627. .configure_filter = iwl_configure_filter,
  2628. .set_key = iwl_mac_set_key,
  2629. .update_tkip_key = iwl_mac_update_tkip_key,
  2630. .get_stats = iwl_mac_get_stats,
  2631. .get_tx_stats = iwl_mac_get_tx_stats,
  2632. .conf_tx = iwl_mac_conf_tx,
  2633. .reset_tsf = iwl_mac_reset_tsf,
  2634. .bss_info_changed = iwl_bss_info_changed,
  2635. .ampdu_action = iwl_mac_ampdu_action,
  2636. .hw_scan = iwl_mac_hw_scan,
  2637. .sta_notify = iwl_mac_sta_notify,
  2638. };
  2639. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2640. {
  2641. int err = 0;
  2642. struct iwl_priv *priv;
  2643. struct ieee80211_hw *hw;
  2644. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2645. unsigned long flags;
  2646. u16 pci_cmd;
  2647. /************************
  2648. * 1. Allocating HW data
  2649. ************************/
  2650. /* Disabling hardware scan means that mac80211 will perform scans
  2651. * "the hard way", rather than using device's scan. */
  2652. if (cfg->mod_params->disable_hw_scan) {
  2653. if (iwl_debug_level & IWL_DL_INFO)
  2654. dev_printk(KERN_DEBUG, &(pdev->dev),
  2655. "Disabling hw_scan\n");
  2656. iwl_hw_ops.hw_scan = NULL;
  2657. }
  2658. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2659. if (!hw) {
  2660. err = -ENOMEM;
  2661. goto out;
  2662. }
  2663. priv = hw->priv;
  2664. /* At this point both hw and priv are allocated. */
  2665. SET_IEEE80211_DEV(hw, &pdev->dev);
  2666. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2667. priv->cfg = cfg;
  2668. priv->pci_dev = pdev;
  2669. priv->inta_mask = CSR_INI_SET_MASK;
  2670. #ifdef CONFIG_IWLWIFI_DEBUG
  2671. atomic_set(&priv->restrict_refcnt, 0);
  2672. #endif
  2673. if (iwl_alloc_traffic_mem(priv))
  2674. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2675. /**************************
  2676. * 2. Initializing PCI bus
  2677. **************************/
  2678. if (pci_enable_device(pdev)) {
  2679. err = -ENODEV;
  2680. goto out_ieee80211_free_hw;
  2681. }
  2682. pci_set_master(pdev);
  2683. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2684. if (!err)
  2685. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2686. if (err) {
  2687. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2688. if (!err)
  2689. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2690. /* both attempts failed: */
  2691. if (err) {
  2692. IWL_WARN(priv, "No suitable DMA available.\n");
  2693. goto out_pci_disable_device;
  2694. }
  2695. }
  2696. err = pci_request_regions(pdev, DRV_NAME);
  2697. if (err)
  2698. goto out_pci_disable_device;
  2699. pci_set_drvdata(pdev, priv);
  2700. /***********************
  2701. * 3. Read REV register
  2702. ***********************/
  2703. priv->hw_base = pci_iomap(pdev, 0, 0);
  2704. if (!priv->hw_base) {
  2705. err = -ENODEV;
  2706. goto out_pci_release_regions;
  2707. }
  2708. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2709. (unsigned long long) pci_resource_len(pdev, 0));
  2710. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2711. /* this spin lock will be used in apm_ops.init and EEPROM access
  2712. * we should init now
  2713. */
  2714. spin_lock_init(&priv->reg_lock);
  2715. iwl_hw_detect(priv);
  2716. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2717. priv->cfg->name, priv->hw_rev);
  2718. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2719. * PCI Tx retries from interfering with C3 CPU state */
  2720. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2721. iwl_prepare_card_hw(priv);
  2722. if (!priv->hw_ready) {
  2723. IWL_WARN(priv, "Failed, HW not ready\n");
  2724. goto out_iounmap;
  2725. }
  2726. /*****************
  2727. * 4. Read EEPROM
  2728. *****************/
  2729. /* Read the EEPROM */
  2730. err = iwl_eeprom_init(priv);
  2731. if (err) {
  2732. IWL_ERR(priv, "Unable to init EEPROM\n");
  2733. goto out_iounmap;
  2734. }
  2735. err = iwl_eeprom_check_version(priv);
  2736. if (err)
  2737. goto out_free_eeprom;
  2738. /* extract MAC Address */
  2739. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2740. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2741. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2742. /************************
  2743. * 5. Setup HW constants
  2744. ************************/
  2745. if (iwl_set_hw_params(priv)) {
  2746. IWL_ERR(priv, "failed to set hw parameters\n");
  2747. goto out_free_eeprom;
  2748. }
  2749. /*******************
  2750. * 6. Setup priv
  2751. *******************/
  2752. err = iwl_init_drv(priv);
  2753. if (err)
  2754. goto out_free_eeprom;
  2755. /* At this point both hw and priv are initialized. */
  2756. /********************
  2757. * 7. Setup services
  2758. ********************/
  2759. spin_lock_irqsave(&priv->lock, flags);
  2760. iwl_disable_interrupts(priv);
  2761. spin_unlock_irqrestore(&priv->lock, flags);
  2762. pci_enable_msi(priv->pci_dev);
  2763. iwl_alloc_isr_ict(priv);
  2764. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2765. IRQF_SHARED, DRV_NAME, priv);
  2766. if (err) {
  2767. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2768. goto out_disable_msi;
  2769. }
  2770. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2771. if (err) {
  2772. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2773. goto out_free_irq;
  2774. }
  2775. iwl_setup_deferred_work(priv);
  2776. iwl_setup_rx_handlers(priv);
  2777. /**********************************
  2778. * 8. Setup and register mac80211
  2779. **********************************/
  2780. /* enable interrupts if needed: hw bug w/a */
  2781. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2782. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2783. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2784. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2785. }
  2786. iwl_enable_interrupts(priv);
  2787. err = iwl_setup_mac(priv);
  2788. if (err)
  2789. goto out_remove_sysfs;
  2790. err = iwl_dbgfs_register(priv, DRV_NAME);
  2791. if (err)
  2792. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2793. /* If platform's RF_KILL switch is NOT set to KILL */
  2794. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2795. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2796. else
  2797. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2798. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2799. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2800. iwl_power_initialize(priv);
  2801. iwl_tt_initialize(priv);
  2802. return 0;
  2803. out_remove_sysfs:
  2804. destroy_workqueue(priv->workqueue);
  2805. priv->workqueue = NULL;
  2806. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2807. out_free_irq:
  2808. free_irq(priv->pci_dev->irq, priv);
  2809. iwl_free_isr_ict(priv);
  2810. out_disable_msi:
  2811. pci_disable_msi(priv->pci_dev);
  2812. iwl_uninit_drv(priv);
  2813. out_free_eeprom:
  2814. iwl_eeprom_free(priv);
  2815. out_iounmap:
  2816. pci_iounmap(pdev, priv->hw_base);
  2817. out_pci_release_regions:
  2818. pci_set_drvdata(pdev, NULL);
  2819. pci_release_regions(pdev);
  2820. out_pci_disable_device:
  2821. pci_disable_device(pdev);
  2822. out_ieee80211_free_hw:
  2823. iwl_free_traffic_mem(priv);
  2824. ieee80211_free_hw(priv->hw);
  2825. out:
  2826. return err;
  2827. }
  2828. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2829. {
  2830. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2831. unsigned long flags;
  2832. if (!priv)
  2833. return;
  2834. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2835. iwl_dbgfs_unregister(priv);
  2836. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2837. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2838. * to be called and iwl_down since we are removing the device
  2839. * we need to set STATUS_EXIT_PENDING bit.
  2840. */
  2841. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2842. if (priv->mac80211_registered) {
  2843. ieee80211_unregister_hw(priv->hw);
  2844. priv->mac80211_registered = 0;
  2845. } else {
  2846. iwl_down(priv);
  2847. }
  2848. /*
  2849. * Make sure device is reset to low power before unloading driver.
  2850. * This may be redundant with iwl_down(), but there are paths to
  2851. * run iwl_down() without calling apm_ops.stop(), and there are
  2852. * paths to avoid running iwl_down() at all before leaving driver.
  2853. * This (inexpensive) call *makes sure* device is reset.
  2854. */
  2855. priv->cfg->ops->lib->apm_ops.stop(priv);
  2856. iwl_tt_exit(priv);
  2857. /* make sure we flush any pending irq or
  2858. * tasklet for the driver
  2859. */
  2860. spin_lock_irqsave(&priv->lock, flags);
  2861. iwl_disable_interrupts(priv);
  2862. spin_unlock_irqrestore(&priv->lock, flags);
  2863. iwl_synchronize_irq(priv);
  2864. iwl_dealloc_ucode_pci(priv);
  2865. if (priv->rxq.bd)
  2866. iwl_rx_queue_free(priv, &priv->rxq);
  2867. iwl_hw_txq_ctx_free(priv);
  2868. iwl_clear_stations_table(priv);
  2869. iwl_eeprom_free(priv);
  2870. /*netif_stop_queue(dev); */
  2871. flush_workqueue(priv->workqueue);
  2872. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2873. * priv->workqueue... so we can't take down the workqueue
  2874. * until now... */
  2875. destroy_workqueue(priv->workqueue);
  2876. priv->workqueue = NULL;
  2877. iwl_free_traffic_mem(priv);
  2878. free_irq(priv->pci_dev->irq, priv);
  2879. pci_disable_msi(priv->pci_dev);
  2880. pci_iounmap(pdev, priv->hw_base);
  2881. pci_release_regions(pdev);
  2882. pci_disable_device(pdev);
  2883. pci_set_drvdata(pdev, NULL);
  2884. iwl_uninit_drv(priv);
  2885. iwl_free_isr_ict(priv);
  2886. if (priv->ibss_beacon)
  2887. dev_kfree_skb(priv->ibss_beacon);
  2888. ieee80211_free_hw(priv->hw);
  2889. }
  2890. /*****************************************************************************
  2891. *
  2892. * driver and module entry point
  2893. *
  2894. *****************************************************************************/
  2895. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2896. static struct pci_device_id iwl_hw_card_ids[] = {
  2897. #ifdef CONFIG_IWL4965
  2898. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2899. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2900. #endif /* CONFIG_IWL4965 */
  2901. #ifdef CONFIG_IWL5000
  2902. /* 5100 Series WiFi */
  2903. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  2904. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  2905. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  2906. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  2907. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  2908. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2909. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  2910. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  2911. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  2912. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  2913. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  2914. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  2915. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  2916. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2917. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  2918. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  2919. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  2920. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  2921. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  2922. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  2923. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  2924. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2925. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  2926. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  2927. /* 5300 Series WiFi */
  2928. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  2929. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  2930. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  2931. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  2932. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  2933. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  2934. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  2935. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  2936. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  2937. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  2938. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  2939. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  2940. /* 5350 Series WiFi/WiMax */
  2941. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  2942. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  2943. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  2944. /* 5150 Series Wifi/WiMax */
  2945. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  2946. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  2947. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  2948. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  2949. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  2950. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  2951. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  2952. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  2953. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  2954. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  2955. /* 6x00 Series */
  2956. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  2957. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  2958. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  2959. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  2960. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  2961. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  2962. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  2963. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  2964. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  2965. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  2966. /* 6x50 WiFi/WiMax Series */
  2967. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  2968. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  2969. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  2970. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  2971. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  2972. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  2973. /* 1000 Series WiFi */
  2974. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  2975. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  2976. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  2977. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  2978. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  2979. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  2980. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  2981. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  2982. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  2983. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  2984. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  2985. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  2986. #endif /* CONFIG_IWL5000 */
  2987. {0}
  2988. };
  2989. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2990. static struct pci_driver iwl_driver = {
  2991. .name = DRV_NAME,
  2992. .id_table = iwl_hw_card_ids,
  2993. .probe = iwl_pci_probe,
  2994. .remove = __devexit_p(iwl_pci_remove),
  2995. #ifdef CONFIG_PM
  2996. .suspend = iwl_pci_suspend,
  2997. .resume = iwl_pci_resume,
  2998. #endif
  2999. };
  3000. static int __init iwl_init(void)
  3001. {
  3002. int ret;
  3003. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3004. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3005. ret = iwlagn_rate_control_register();
  3006. if (ret) {
  3007. printk(KERN_ERR DRV_NAME
  3008. "Unable to register rate control algorithm: %d\n", ret);
  3009. return ret;
  3010. }
  3011. ret = pci_register_driver(&iwl_driver);
  3012. if (ret) {
  3013. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3014. goto error_register;
  3015. }
  3016. return ret;
  3017. error_register:
  3018. iwlagn_rate_control_unregister();
  3019. return ret;
  3020. }
  3021. static void __exit iwl_exit(void)
  3022. {
  3023. pci_unregister_driver(&iwl_driver);
  3024. iwlagn_rate_control_unregister();
  3025. }
  3026. module_exit(iwl_exit);
  3027. module_init(iwl_init);
  3028. #ifdef CONFIG_IWLWIFI_DEBUG
  3029. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3030. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3031. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3032. MODULE_PARM_DESC(debug, "debug output mask");
  3033. #endif