srq.c 8.4 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/init.h>
  34. #include <linux/mlx4/cmd.h>
  35. #include <linux/mlx4/srq.h>
  36. #include <linux/export.h>
  37. #include <linux/gfp.h>
  38. #include "mlx4.h"
  39. #include "icm.h"
  40. void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
  41. {
  42. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  43. struct mlx4_srq *srq;
  44. spin_lock(&srq_table->lock);
  45. srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
  46. if (srq)
  47. atomic_inc(&srq->refcount);
  48. spin_unlock(&srq_table->lock);
  49. if (!srq) {
  50. mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  51. return;
  52. }
  53. srq->event(srq, event_type);
  54. if (atomic_dec_and_test(&srq->refcount))
  55. complete(&srq->free);
  56. }
  57. static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  58. int srq_num)
  59. {
  60. return mlx4_cmd(dev, mailbox->dma, srq_num, 0,
  61. MLX4_CMD_SW2HW_SRQ, MLX4_CMD_TIME_CLASS_A,
  62. MLX4_CMD_WRAPPED);
  63. }
  64. static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  65. int srq_num)
  66. {
  67. return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
  68. mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
  69. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  70. }
  71. static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
  72. {
  73. return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
  74. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  75. }
  76. static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  77. int srq_num)
  78. {
  79. return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
  80. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  81. }
  82. int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
  83. {
  84. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  85. int err;
  86. *srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
  87. if (*srqn == -1)
  88. return -ENOMEM;
  89. err = mlx4_table_get(dev, &srq_table->table, *srqn);
  90. if (err)
  91. goto err_out;
  92. err = mlx4_table_get(dev, &srq_table->cmpt_table, *srqn);
  93. if (err)
  94. goto err_put;
  95. return 0;
  96. err_put:
  97. mlx4_table_put(dev, &srq_table->table, *srqn);
  98. err_out:
  99. mlx4_bitmap_free(&srq_table->bitmap, *srqn);
  100. return err;
  101. }
  102. static int mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
  103. {
  104. u64 out_param;
  105. int err;
  106. if (mlx4_is_mfunc(dev)) {
  107. err = mlx4_cmd_imm(dev, 0, &out_param, RES_SRQ,
  108. RES_OP_RESERVE_AND_MAP,
  109. MLX4_CMD_ALLOC_RES,
  110. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  111. if (!err)
  112. *srqn = get_param_l(&out_param);
  113. return err;
  114. }
  115. return __mlx4_srq_alloc_icm(dev, srqn);
  116. }
  117. void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
  118. {
  119. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  120. mlx4_table_put(dev, &srq_table->cmpt_table, srqn);
  121. mlx4_table_put(dev, &srq_table->table, srqn);
  122. mlx4_bitmap_free(&srq_table->bitmap, srqn);
  123. }
  124. static void mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
  125. {
  126. u64 in_param = 0;
  127. if (mlx4_is_mfunc(dev)) {
  128. set_param_l(&in_param, srqn);
  129. if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
  130. MLX4_CMD_FREE_RES,
  131. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
  132. mlx4_warn(dev, "Failed freeing cq:%d\n", srqn);
  133. return;
  134. }
  135. __mlx4_srq_free_icm(dev, srqn);
  136. }
  137. int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
  138. struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq)
  139. {
  140. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  141. struct mlx4_cmd_mailbox *mailbox;
  142. struct mlx4_srq_context *srq_context;
  143. u64 mtt_addr;
  144. int err;
  145. err = mlx4_srq_alloc_icm(dev, &srq->srqn);
  146. if (err)
  147. return err;
  148. spin_lock_irq(&srq_table->lock);
  149. err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
  150. spin_unlock_irq(&srq_table->lock);
  151. if (err)
  152. goto err_icm;
  153. mailbox = mlx4_alloc_cmd_mailbox(dev);
  154. if (IS_ERR(mailbox)) {
  155. err = PTR_ERR(mailbox);
  156. goto err_radix;
  157. }
  158. srq_context = mailbox->buf;
  159. memset(srq_context, 0, sizeof *srq_context);
  160. srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
  161. srq->srqn);
  162. srq_context->logstride = srq->wqe_shift - 4;
  163. srq_context->xrcd = cpu_to_be16(xrcd);
  164. srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff);
  165. srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
  166. mtt_addr = mlx4_mtt_addr(dev, mtt);
  167. srq_context->mtt_base_addr_h = mtt_addr >> 32;
  168. srq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
  169. srq_context->pd = cpu_to_be32(pdn);
  170. srq_context->db_rec_addr = cpu_to_be64(db_rec);
  171. err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
  172. mlx4_free_cmd_mailbox(dev, mailbox);
  173. if (err)
  174. goto err_radix;
  175. atomic_set(&srq->refcount, 1);
  176. init_completion(&srq->free);
  177. return 0;
  178. err_radix:
  179. spin_lock_irq(&srq_table->lock);
  180. radix_tree_delete(&srq_table->tree, srq->srqn);
  181. spin_unlock_irq(&srq_table->lock);
  182. err_icm:
  183. mlx4_srq_free_icm(dev, srq->srqn);
  184. return err;
  185. }
  186. EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
  187. void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
  188. {
  189. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  190. int err;
  191. err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
  192. if (err)
  193. mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
  194. spin_lock_irq(&srq_table->lock);
  195. radix_tree_delete(&srq_table->tree, srq->srqn);
  196. spin_unlock_irq(&srq_table->lock);
  197. if (atomic_dec_and_test(&srq->refcount))
  198. complete(&srq->free);
  199. wait_for_completion(&srq->free);
  200. mlx4_srq_free_icm(dev, srq->srqn);
  201. }
  202. EXPORT_SYMBOL_GPL(mlx4_srq_free);
  203. int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
  204. {
  205. return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
  206. }
  207. EXPORT_SYMBOL_GPL(mlx4_srq_arm);
  208. int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
  209. {
  210. struct mlx4_cmd_mailbox *mailbox;
  211. struct mlx4_srq_context *srq_context;
  212. int err;
  213. mailbox = mlx4_alloc_cmd_mailbox(dev);
  214. if (IS_ERR(mailbox))
  215. return PTR_ERR(mailbox);
  216. srq_context = mailbox->buf;
  217. err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
  218. if (err)
  219. goto err_out;
  220. *limit_watermark = be16_to_cpu(srq_context->limit_watermark);
  221. err_out:
  222. mlx4_free_cmd_mailbox(dev, mailbox);
  223. return err;
  224. }
  225. EXPORT_SYMBOL_GPL(mlx4_srq_query);
  226. int mlx4_init_srq_table(struct mlx4_dev *dev)
  227. {
  228. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  229. int err;
  230. spin_lock_init(&srq_table->lock);
  231. INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
  232. if (mlx4_is_slave(dev))
  233. return 0;
  234. err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
  235. dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0);
  236. if (err)
  237. return err;
  238. return 0;
  239. }
  240. void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
  241. {
  242. if (mlx4_is_slave(dev))
  243. return;
  244. mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
  245. }
  246. struct mlx4_srq *mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn)
  247. {
  248. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  249. struct mlx4_srq *srq;
  250. unsigned long flags;
  251. spin_lock_irqsave(&srq_table->lock, flags);
  252. srq = radix_tree_lookup(&srq_table->tree,
  253. srqn & (dev->caps.num_srqs - 1));
  254. spin_unlock_irqrestore(&srq_table->lock, flags);
  255. return srq;
  256. }
  257. EXPORT_SYMBOL_GPL(mlx4_srq_lookup);