base.c 93 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502
  1. /*-
  2. * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
  3. * Copyright (c) 2004-2005 Atheros Communications, Inc.
  4. * Copyright (c) 2006 Devicescape Software, Inc.
  5. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  6. * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
  7. *
  8. * All rights reserved.
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions
  12. * are met:
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer,
  15. * without modification.
  16. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17. * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18. * redistribution must be conditioned upon including a substantially
  19. * similar Disclaimer requirement for further binary redistribution.
  20. * 3. Neither the names of the above-listed copyright holders nor the names
  21. * of any contributors may be used to endorse or promote products derived
  22. * from this software without specific prior written permission.
  23. *
  24. * Alternatively, this software may be distributed under the terms of the
  25. * GNU General Public License ("GPL") version 2 as published by the Free
  26. * Software Foundation.
  27. *
  28. * NO WARRANTY
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32. * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33. * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34. * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37. * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39. * THE POSSIBILITY OF SUCH DAMAGES.
  40. *
  41. */
  42. #include <linux/module.h>
  43. #include <linux/delay.h>
  44. #include <linux/hardirq.h>
  45. #include <linux/if.h>
  46. #include <linux/io.h>
  47. #include <linux/netdevice.h>
  48. #include <linux/cache.h>
  49. #include <linux/pci.h>
  50. #include <linux/ethtool.h>
  51. #include <linux/uaccess.h>
  52. #include <linux/slab.h>
  53. #include <net/ieee80211_radiotap.h>
  54. #include <asm/unaligned.h>
  55. #include "base.h"
  56. #include "reg.h"
  57. #include "debug.h"
  58. #include "ani.h"
  59. static int modparam_nohwcrypt;
  60. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  61. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  62. static int modparam_all_channels;
  63. module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
  64. MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
  65. /******************\
  66. * Internal defines *
  67. \******************/
  68. /* Module info */
  69. MODULE_AUTHOR("Jiri Slaby");
  70. MODULE_AUTHOR("Nick Kossifidis");
  71. MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  72. MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  73. MODULE_LICENSE("Dual BSD/GPL");
  74. MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  75. /* Known PCI ids */
  76. static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
  77. { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
  78. { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
  79. { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
  80. { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
  81. { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
  82. { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
  83. { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
  84. { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
  85. { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
  86. { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
  87. { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
  88. { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
  89. { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
  90. { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
  91. { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
  92. { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
  93. { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
  94. { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
  95. { 0 }
  96. };
  97. MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
  98. /* Known SREVs */
  99. static const struct ath5k_srev_name srev_names[] = {
  100. { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
  101. { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
  102. { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
  103. { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
  104. { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
  105. { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
  106. { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
  107. { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
  108. { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
  109. { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
  110. { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
  111. { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
  112. { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
  113. { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
  114. { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
  115. { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
  116. { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
  117. { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
  118. { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
  119. { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
  120. { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
  121. { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
  122. { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
  123. { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
  124. { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
  125. { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
  126. { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
  127. { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
  128. { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
  129. { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
  130. { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
  131. { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
  132. { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
  133. { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
  134. { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
  135. { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
  136. };
  137. static const struct ieee80211_rate ath5k_rates[] = {
  138. { .bitrate = 10,
  139. .hw_value = ATH5K_RATE_CODE_1M, },
  140. { .bitrate = 20,
  141. .hw_value = ATH5K_RATE_CODE_2M,
  142. .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
  143. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  144. { .bitrate = 55,
  145. .hw_value = ATH5K_RATE_CODE_5_5M,
  146. .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
  147. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  148. { .bitrate = 110,
  149. .hw_value = ATH5K_RATE_CODE_11M,
  150. .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
  151. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  152. { .bitrate = 60,
  153. .hw_value = ATH5K_RATE_CODE_6M,
  154. .flags = 0 },
  155. { .bitrate = 90,
  156. .hw_value = ATH5K_RATE_CODE_9M,
  157. .flags = 0 },
  158. { .bitrate = 120,
  159. .hw_value = ATH5K_RATE_CODE_12M,
  160. .flags = 0 },
  161. { .bitrate = 180,
  162. .hw_value = ATH5K_RATE_CODE_18M,
  163. .flags = 0 },
  164. { .bitrate = 240,
  165. .hw_value = ATH5K_RATE_CODE_24M,
  166. .flags = 0 },
  167. { .bitrate = 360,
  168. .hw_value = ATH5K_RATE_CODE_36M,
  169. .flags = 0 },
  170. { .bitrate = 480,
  171. .hw_value = ATH5K_RATE_CODE_48M,
  172. .flags = 0 },
  173. { .bitrate = 540,
  174. .hw_value = ATH5K_RATE_CODE_54M,
  175. .flags = 0 },
  176. /* XR missing */
  177. };
  178. /*
  179. * Prototypes - PCI stack related functions
  180. */
  181. static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
  182. const struct pci_device_id *id);
  183. static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
  184. #ifdef CONFIG_PM_SLEEP
  185. static int ath5k_pci_suspend(struct device *dev);
  186. static int ath5k_pci_resume(struct device *dev);
  187. static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
  188. #define ATH5K_PM_OPS (&ath5k_pm_ops)
  189. #else
  190. #define ATH5K_PM_OPS NULL
  191. #endif /* CONFIG_PM_SLEEP */
  192. static struct pci_driver ath5k_pci_driver = {
  193. .name = KBUILD_MODNAME,
  194. .id_table = ath5k_pci_id_table,
  195. .probe = ath5k_pci_probe,
  196. .remove = __devexit_p(ath5k_pci_remove),
  197. .driver.pm = ATH5K_PM_OPS,
  198. };
  199. /*
  200. * Prototypes - MAC 802.11 stack related functions
  201. */
  202. static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
  203. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  204. struct ath5k_txq *txq);
  205. static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
  206. static int ath5k_start(struct ieee80211_hw *hw);
  207. static void ath5k_stop(struct ieee80211_hw *hw);
  208. static int ath5k_add_interface(struct ieee80211_hw *hw,
  209. struct ieee80211_vif *vif);
  210. static void ath5k_remove_interface(struct ieee80211_hw *hw,
  211. struct ieee80211_vif *vif);
  212. static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
  213. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  214. struct netdev_hw_addr_list *mc_list);
  215. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  216. unsigned int changed_flags,
  217. unsigned int *new_flags,
  218. u64 multicast);
  219. static int ath5k_set_key(struct ieee80211_hw *hw,
  220. enum set_key_cmd cmd,
  221. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  222. struct ieee80211_key_conf *key);
  223. static int ath5k_get_stats(struct ieee80211_hw *hw,
  224. struct ieee80211_low_level_stats *stats);
  225. static int ath5k_get_survey(struct ieee80211_hw *hw,
  226. int idx, struct survey_info *survey);
  227. static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
  228. static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
  229. static void ath5k_reset_tsf(struct ieee80211_hw *hw);
  230. static int ath5k_beacon_update(struct ieee80211_hw *hw,
  231. struct ieee80211_vif *vif);
  232. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  233. struct ieee80211_vif *vif,
  234. struct ieee80211_bss_conf *bss_conf,
  235. u32 changes);
  236. static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
  237. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
  238. static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
  239. u8 coverage_class);
  240. static const struct ieee80211_ops ath5k_hw_ops = {
  241. .tx = ath5k_tx,
  242. .start = ath5k_start,
  243. .stop = ath5k_stop,
  244. .add_interface = ath5k_add_interface,
  245. .remove_interface = ath5k_remove_interface,
  246. .config = ath5k_config,
  247. .prepare_multicast = ath5k_prepare_multicast,
  248. .configure_filter = ath5k_configure_filter,
  249. .set_key = ath5k_set_key,
  250. .get_stats = ath5k_get_stats,
  251. .get_survey = ath5k_get_survey,
  252. .conf_tx = NULL,
  253. .get_tsf = ath5k_get_tsf,
  254. .set_tsf = ath5k_set_tsf,
  255. .reset_tsf = ath5k_reset_tsf,
  256. .bss_info_changed = ath5k_bss_info_changed,
  257. .sw_scan_start = ath5k_sw_scan_start,
  258. .sw_scan_complete = ath5k_sw_scan_complete,
  259. .set_coverage_class = ath5k_set_coverage_class,
  260. };
  261. /*
  262. * Prototypes - Internal functions
  263. */
  264. /* Attach detach */
  265. static int ath5k_attach(struct pci_dev *pdev,
  266. struct ieee80211_hw *hw);
  267. static void ath5k_detach(struct pci_dev *pdev,
  268. struct ieee80211_hw *hw);
  269. /* Channel/mode setup */
  270. static inline short ath5k_ieee2mhz(short chan);
  271. static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
  272. struct ieee80211_channel *channels,
  273. unsigned int mode,
  274. unsigned int max);
  275. static int ath5k_setup_bands(struct ieee80211_hw *hw);
  276. static int ath5k_chan_set(struct ath5k_softc *sc,
  277. struct ieee80211_channel *chan);
  278. static void ath5k_setcurmode(struct ath5k_softc *sc,
  279. unsigned int mode);
  280. static void ath5k_mode_setup(struct ath5k_softc *sc);
  281. /* Descriptor setup */
  282. static int ath5k_desc_alloc(struct ath5k_softc *sc,
  283. struct pci_dev *pdev);
  284. static void ath5k_desc_free(struct ath5k_softc *sc,
  285. struct pci_dev *pdev);
  286. /* Buffers setup */
  287. static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
  288. struct ath5k_buf *bf);
  289. static int ath5k_txbuf_setup(struct ath5k_softc *sc,
  290. struct ath5k_buf *bf,
  291. struct ath5k_txq *txq, int padsize);
  292. static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
  293. struct ath5k_buf *bf)
  294. {
  295. BUG_ON(!bf);
  296. if (!bf->skb)
  297. return;
  298. pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
  299. PCI_DMA_TODEVICE);
  300. dev_kfree_skb_any(bf->skb);
  301. bf->skb = NULL;
  302. bf->skbaddr = 0;
  303. bf->desc->ds_data = 0;
  304. }
  305. static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
  306. struct ath5k_buf *bf)
  307. {
  308. struct ath5k_hw *ah = sc->ah;
  309. struct ath_common *common = ath5k_hw_common(ah);
  310. BUG_ON(!bf);
  311. if (!bf->skb)
  312. return;
  313. pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
  314. PCI_DMA_FROMDEVICE);
  315. dev_kfree_skb_any(bf->skb);
  316. bf->skb = NULL;
  317. bf->skbaddr = 0;
  318. bf->desc->ds_data = 0;
  319. }
  320. /* Queues setup */
  321. static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
  322. int qtype, int subtype);
  323. static int ath5k_beaconq_setup(struct ath5k_hw *ah);
  324. static int ath5k_beaconq_config(struct ath5k_softc *sc);
  325. static void ath5k_txq_drainq(struct ath5k_softc *sc,
  326. struct ath5k_txq *txq);
  327. static void ath5k_txq_cleanup(struct ath5k_softc *sc);
  328. static void ath5k_txq_release(struct ath5k_softc *sc);
  329. /* Rx handling */
  330. static int ath5k_rx_start(struct ath5k_softc *sc);
  331. static void ath5k_rx_stop(struct ath5k_softc *sc);
  332. static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
  333. struct ath5k_desc *ds,
  334. struct sk_buff *skb,
  335. struct ath5k_rx_status *rs);
  336. static void ath5k_tasklet_rx(unsigned long data);
  337. /* Tx handling */
  338. static void ath5k_tx_processq(struct ath5k_softc *sc,
  339. struct ath5k_txq *txq);
  340. static void ath5k_tasklet_tx(unsigned long data);
  341. /* Beacon handling */
  342. static int ath5k_beacon_setup(struct ath5k_softc *sc,
  343. struct ath5k_buf *bf);
  344. static void ath5k_beacon_send(struct ath5k_softc *sc);
  345. static void ath5k_beacon_config(struct ath5k_softc *sc);
  346. static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
  347. static void ath5k_tasklet_beacon(unsigned long data);
  348. static void ath5k_tasklet_ani(unsigned long data);
  349. static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
  350. {
  351. u64 tsf = ath5k_hw_get_tsf64(ah);
  352. if ((tsf & 0x7fff) < rstamp)
  353. tsf -= 0x8000;
  354. return (tsf & ~0x7fff) | rstamp;
  355. }
  356. /* Interrupt handling */
  357. static int ath5k_init(struct ath5k_softc *sc);
  358. static int ath5k_stop_locked(struct ath5k_softc *sc);
  359. static int ath5k_stop_hw(struct ath5k_softc *sc);
  360. static irqreturn_t ath5k_intr(int irq, void *dev_id);
  361. static void ath5k_tasklet_reset(unsigned long data);
  362. static void ath5k_tasklet_calibrate(unsigned long data);
  363. /*
  364. * Module init/exit functions
  365. */
  366. static int __init
  367. init_ath5k_pci(void)
  368. {
  369. int ret;
  370. ath5k_debug_init();
  371. ret = pci_register_driver(&ath5k_pci_driver);
  372. if (ret) {
  373. printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
  374. return ret;
  375. }
  376. return 0;
  377. }
  378. static void __exit
  379. exit_ath5k_pci(void)
  380. {
  381. pci_unregister_driver(&ath5k_pci_driver);
  382. ath5k_debug_finish();
  383. }
  384. module_init(init_ath5k_pci);
  385. module_exit(exit_ath5k_pci);
  386. /********************\
  387. * PCI Initialization *
  388. \********************/
  389. static const char *
  390. ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
  391. {
  392. const char *name = "xxxxx";
  393. unsigned int i;
  394. for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
  395. if (srev_names[i].sr_type != type)
  396. continue;
  397. if ((val & 0xf0) == srev_names[i].sr_val)
  398. name = srev_names[i].sr_name;
  399. if ((val & 0xff) == srev_names[i].sr_val) {
  400. name = srev_names[i].sr_name;
  401. break;
  402. }
  403. }
  404. return name;
  405. }
  406. static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
  407. {
  408. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  409. return ath5k_hw_reg_read(ah, reg_offset);
  410. }
  411. static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
  412. {
  413. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  414. ath5k_hw_reg_write(ah, val, reg_offset);
  415. }
  416. static const struct ath_ops ath5k_common_ops = {
  417. .read = ath5k_ioread32,
  418. .write = ath5k_iowrite32,
  419. };
  420. static int __devinit
  421. ath5k_pci_probe(struct pci_dev *pdev,
  422. const struct pci_device_id *id)
  423. {
  424. void __iomem *mem;
  425. struct ath5k_softc *sc;
  426. struct ath_common *common;
  427. struct ieee80211_hw *hw;
  428. int ret;
  429. u8 csz;
  430. ret = pci_enable_device(pdev);
  431. if (ret) {
  432. dev_err(&pdev->dev, "can't enable device\n");
  433. goto err;
  434. }
  435. /* XXX 32-bit addressing only */
  436. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  437. if (ret) {
  438. dev_err(&pdev->dev, "32-bit DMA not available\n");
  439. goto err_dis;
  440. }
  441. /*
  442. * Cache line size is used to size and align various
  443. * structures used to communicate with the hardware.
  444. */
  445. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  446. if (csz == 0) {
  447. /*
  448. * Linux 2.4.18 (at least) writes the cache line size
  449. * register as a 16-bit wide register which is wrong.
  450. * We must have this setup properly for rx buffer
  451. * DMA to work so force a reasonable value here if it
  452. * comes up zero.
  453. */
  454. csz = L1_CACHE_BYTES >> 2;
  455. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  456. }
  457. /*
  458. * The default setting of latency timer yields poor results,
  459. * set it to the value used by other systems. It may be worth
  460. * tweaking this setting more.
  461. */
  462. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  463. /* Enable bus mastering */
  464. pci_set_master(pdev);
  465. /*
  466. * Disable the RETRY_TIMEOUT register (0x41) to keep
  467. * PCI Tx retries from interfering with C3 CPU state.
  468. */
  469. pci_write_config_byte(pdev, 0x41, 0);
  470. ret = pci_request_region(pdev, 0, "ath5k");
  471. if (ret) {
  472. dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
  473. goto err_dis;
  474. }
  475. mem = pci_iomap(pdev, 0, 0);
  476. if (!mem) {
  477. dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
  478. ret = -EIO;
  479. goto err_reg;
  480. }
  481. /*
  482. * Allocate hw (mac80211 main struct)
  483. * and hw->priv (driver private data)
  484. */
  485. hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
  486. if (hw == NULL) {
  487. dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
  488. ret = -ENOMEM;
  489. goto err_map;
  490. }
  491. dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
  492. /* Initialize driver private data */
  493. SET_IEEE80211_DEV(hw, &pdev->dev);
  494. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  495. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  496. IEEE80211_HW_SIGNAL_DBM;
  497. hw->wiphy->interface_modes =
  498. BIT(NL80211_IFTYPE_AP) |
  499. BIT(NL80211_IFTYPE_STATION) |
  500. BIT(NL80211_IFTYPE_ADHOC) |
  501. BIT(NL80211_IFTYPE_MESH_POINT);
  502. hw->extra_tx_headroom = 2;
  503. hw->channel_change_time = 5000;
  504. sc = hw->priv;
  505. sc->hw = hw;
  506. sc->pdev = pdev;
  507. ath5k_debug_init_device(sc);
  508. /*
  509. * Mark the device as detached to avoid processing
  510. * interrupts until setup is complete.
  511. */
  512. __set_bit(ATH_STAT_INVALID, sc->status);
  513. sc->iobase = mem; /* So we can unmap it on detach */
  514. sc->opmode = NL80211_IFTYPE_STATION;
  515. sc->bintval = 1000;
  516. mutex_init(&sc->lock);
  517. spin_lock_init(&sc->rxbuflock);
  518. spin_lock_init(&sc->txbuflock);
  519. spin_lock_init(&sc->block);
  520. /* Set private data */
  521. pci_set_drvdata(pdev, sc);
  522. /* Setup interrupt handler */
  523. ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
  524. if (ret) {
  525. ATH5K_ERR(sc, "request_irq failed\n");
  526. goto err_free;
  527. }
  528. /*If we passed the test malloc a ath5k_hw struct*/
  529. sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
  530. if (!sc->ah) {
  531. ret = -ENOMEM;
  532. ATH5K_ERR(sc, "out of memory\n");
  533. goto err_irq;
  534. }
  535. sc->ah->ah_sc = sc;
  536. sc->ah->ah_iobase = sc->iobase;
  537. common = ath5k_hw_common(sc->ah);
  538. common->ops = &ath5k_common_ops;
  539. common->ah = sc->ah;
  540. common->hw = hw;
  541. common->cachelsz = csz << 2; /* convert to bytes */
  542. /* Initialize device */
  543. ret = ath5k_hw_attach(sc);
  544. if (ret) {
  545. goto err_free_ah;
  546. }
  547. /* set up multi-rate retry capabilities */
  548. if (sc->ah->ah_version == AR5K_AR5212) {
  549. hw->max_rates = 4;
  550. hw->max_rate_tries = 11;
  551. }
  552. /* Finish private driver data initialization */
  553. ret = ath5k_attach(pdev, hw);
  554. if (ret)
  555. goto err_ah;
  556. ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
  557. ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
  558. sc->ah->ah_mac_srev,
  559. sc->ah->ah_phy_revision);
  560. if (!sc->ah->ah_single_chip) {
  561. /* Single chip radio (!RF5111) */
  562. if (sc->ah->ah_radio_5ghz_revision &&
  563. !sc->ah->ah_radio_2ghz_revision) {
  564. /* No 5GHz support -> report 2GHz radio */
  565. if (!test_bit(AR5K_MODE_11A,
  566. sc->ah->ah_capabilities.cap_mode)) {
  567. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  568. ath5k_chip_name(AR5K_VERSION_RAD,
  569. sc->ah->ah_radio_5ghz_revision),
  570. sc->ah->ah_radio_5ghz_revision);
  571. /* No 2GHz support (5110 and some
  572. * 5Ghz only cards) -> report 5Ghz radio */
  573. } else if (!test_bit(AR5K_MODE_11B,
  574. sc->ah->ah_capabilities.cap_mode)) {
  575. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  576. ath5k_chip_name(AR5K_VERSION_RAD,
  577. sc->ah->ah_radio_5ghz_revision),
  578. sc->ah->ah_radio_5ghz_revision);
  579. /* Multiband radio */
  580. } else {
  581. ATH5K_INFO(sc, "RF%s multiband radio found"
  582. " (0x%x)\n",
  583. ath5k_chip_name(AR5K_VERSION_RAD,
  584. sc->ah->ah_radio_5ghz_revision),
  585. sc->ah->ah_radio_5ghz_revision);
  586. }
  587. }
  588. /* Multi chip radio (RF5111 - RF2111) ->
  589. * report both 2GHz/5GHz radios */
  590. else if (sc->ah->ah_radio_5ghz_revision &&
  591. sc->ah->ah_radio_2ghz_revision){
  592. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  593. ath5k_chip_name(AR5K_VERSION_RAD,
  594. sc->ah->ah_radio_5ghz_revision),
  595. sc->ah->ah_radio_5ghz_revision);
  596. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  597. ath5k_chip_name(AR5K_VERSION_RAD,
  598. sc->ah->ah_radio_2ghz_revision),
  599. sc->ah->ah_radio_2ghz_revision);
  600. }
  601. }
  602. /* ready to process interrupts */
  603. __clear_bit(ATH_STAT_INVALID, sc->status);
  604. return 0;
  605. err_ah:
  606. ath5k_hw_detach(sc->ah);
  607. err_irq:
  608. free_irq(pdev->irq, sc);
  609. err_free_ah:
  610. kfree(sc->ah);
  611. err_free:
  612. ieee80211_free_hw(hw);
  613. err_map:
  614. pci_iounmap(pdev, mem);
  615. err_reg:
  616. pci_release_region(pdev, 0);
  617. err_dis:
  618. pci_disable_device(pdev);
  619. err:
  620. return ret;
  621. }
  622. static void __devexit
  623. ath5k_pci_remove(struct pci_dev *pdev)
  624. {
  625. struct ath5k_softc *sc = pci_get_drvdata(pdev);
  626. ath5k_debug_finish_device(sc);
  627. ath5k_detach(pdev, sc->hw);
  628. ath5k_hw_detach(sc->ah);
  629. kfree(sc->ah);
  630. free_irq(pdev->irq, sc);
  631. pci_iounmap(pdev, sc->iobase);
  632. pci_release_region(pdev, 0);
  633. pci_disable_device(pdev);
  634. ieee80211_free_hw(sc->hw);
  635. }
  636. #ifdef CONFIG_PM_SLEEP
  637. static int ath5k_pci_suspend(struct device *dev)
  638. {
  639. struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
  640. ath5k_led_off(sc);
  641. return 0;
  642. }
  643. static int ath5k_pci_resume(struct device *dev)
  644. {
  645. struct pci_dev *pdev = to_pci_dev(dev);
  646. struct ath5k_softc *sc = pci_get_drvdata(pdev);
  647. /*
  648. * Suspend/Resume resets the PCI configuration space, so we have to
  649. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  650. * PCI Tx retries from interfering with C3 CPU state
  651. */
  652. pci_write_config_byte(pdev, 0x41, 0);
  653. ath5k_led_enable(sc);
  654. return 0;
  655. }
  656. #endif /* CONFIG_PM_SLEEP */
  657. /***********************\
  658. * Driver Initialization *
  659. \***********************/
  660. static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
  661. {
  662. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  663. struct ath5k_softc *sc = hw->priv;
  664. struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
  665. return ath_reg_notifier_apply(wiphy, request, regulatory);
  666. }
  667. static int
  668. ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  669. {
  670. struct ath5k_softc *sc = hw->priv;
  671. struct ath5k_hw *ah = sc->ah;
  672. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  673. u8 mac[ETH_ALEN] = {};
  674. int ret;
  675. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
  676. /*
  677. * Check if the MAC has multi-rate retry support.
  678. * We do this by trying to setup a fake extended
  679. * descriptor. MAC's that don't have support will
  680. * return false w/o doing anything. MAC's that do
  681. * support it will return true w/o doing anything.
  682. */
  683. ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
  684. if (ret < 0)
  685. goto err;
  686. if (ret > 0)
  687. __set_bit(ATH_STAT_MRRETRY, sc->status);
  688. /*
  689. * Collect the channel list. The 802.11 layer
  690. * is resposible for filtering this list based
  691. * on settings like the phy mode and regulatory
  692. * domain restrictions.
  693. */
  694. ret = ath5k_setup_bands(hw);
  695. if (ret) {
  696. ATH5K_ERR(sc, "can't get channels\n");
  697. goto err;
  698. }
  699. /* NB: setup here so ath5k_rate_update is happy */
  700. if (test_bit(AR5K_MODE_11A, ah->ah_modes))
  701. ath5k_setcurmode(sc, AR5K_MODE_11A);
  702. else
  703. ath5k_setcurmode(sc, AR5K_MODE_11B);
  704. /*
  705. * Allocate tx+rx descriptors and populate the lists.
  706. */
  707. ret = ath5k_desc_alloc(sc, pdev);
  708. if (ret) {
  709. ATH5K_ERR(sc, "can't allocate descriptors\n");
  710. goto err;
  711. }
  712. /*
  713. * Allocate hardware transmit queues: one queue for
  714. * beacon frames and one data queue for each QoS
  715. * priority. Note that hw functions handle reseting
  716. * these queues at the needed time.
  717. */
  718. ret = ath5k_beaconq_setup(ah);
  719. if (ret < 0) {
  720. ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
  721. goto err_desc;
  722. }
  723. sc->bhalq = ret;
  724. sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
  725. if (IS_ERR(sc->cabq)) {
  726. ATH5K_ERR(sc, "can't setup cab queue\n");
  727. ret = PTR_ERR(sc->cabq);
  728. goto err_bhal;
  729. }
  730. sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
  731. if (IS_ERR(sc->txq)) {
  732. ATH5K_ERR(sc, "can't setup xmit queue\n");
  733. ret = PTR_ERR(sc->txq);
  734. goto err_queues;
  735. }
  736. tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
  737. tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
  738. tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
  739. tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
  740. tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
  741. tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
  742. ret = ath5k_eeprom_read_mac(ah, mac);
  743. if (ret) {
  744. ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
  745. sc->pdev->device);
  746. goto err_queues;
  747. }
  748. SET_IEEE80211_PERM_ADDR(hw, mac);
  749. /* All MAC address bits matter for ACKs */
  750. memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
  751. ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
  752. regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
  753. ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
  754. if (ret) {
  755. ATH5K_ERR(sc, "can't initialize regulatory system\n");
  756. goto err_queues;
  757. }
  758. ret = ieee80211_register_hw(hw);
  759. if (ret) {
  760. ATH5K_ERR(sc, "can't register ieee80211 hw\n");
  761. goto err_queues;
  762. }
  763. if (!ath_is_world_regd(regulatory))
  764. regulatory_hint(hw->wiphy, regulatory->alpha2);
  765. ath5k_init_leds(sc);
  766. ath5k_sysfs_register(sc);
  767. return 0;
  768. err_queues:
  769. ath5k_txq_release(sc);
  770. err_bhal:
  771. ath5k_hw_release_tx_queue(ah, sc->bhalq);
  772. err_desc:
  773. ath5k_desc_free(sc, pdev);
  774. err:
  775. return ret;
  776. }
  777. static void
  778. ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  779. {
  780. struct ath5k_softc *sc = hw->priv;
  781. /*
  782. * NB: the order of these is important:
  783. * o call the 802.11 layer before detaching ath5k_hw to
  784. * insure callbacks into the driver to delete global
  785. * key cache entries can be handled
  786. * o reclaim the tx queue data structures after calling
  787. * the 802.11 layer as we'll get called back to reclaim
  788. * node state and potentially want to use them
  789. * o to cleanup the tx queues the hal is called, so detach
  790. * it last
  791. * XXX: ??? detach ath5k_hw ???
  792. * Other than that, it's straightforward...
  793. */
  794. ieee80211_unregister_hw(hw);
  795. ath5k_desc_free(sc, pdev);
  796. ath5k_txq_release(sc);
  797. ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
  798. ath5k_unregister_leds(sc);
  799. ath5k_sysfs_unregister(sc);
  800. /*
  801. * NB: can't reclaim these until after ieee80211_ifdetach
  802. * returns because we'll get called back to reclaim node
  803. * state and potentially want to use them.
  804. */
  805. }
  806. /********************\
  807. * Channel/mode setup *
  808. \********************/
  809. /*
  810. * Convert IEEE channel number to MHz frequency.
  811. */
  812. static inline short
  813. ath5k_ieee2mhz(short chan)
  814. {
  815. if (chan <= 14 || chan >= 27)
  816. return ieee80211chan2mhz(chan);
  817. else
  818. return 2212 + chan * 20;
  819. }
  820. /*
  821. * Returns true for the channel numbers used without all_channels modparam.
  822. */
  823. static bool ath5k_is_standard_channel(short chan)
  824. {
  825. return ((chan <= 14) ||
  826. /* UNII 1,2 */
  827. ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
  828. /* midband */
  829. ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
  830. /* UNII-3 */
  831. ((chan & 3) == 1 && chan >= 149 && chan <= 165));
  832. }
  833. static unsigned int
  834. ath5k_copy_channels(struct ath5k_hw *ah,
  835. struct ieee80211_channel *channels,
  836. unsigned int mode,
  837. unsigned int max)
  838. {
  839. unsigned int i, count, size, chfreq, freq, ch;
  840. if (!test_bit(mode, ah->ah_modes))
  841. return 0;
  842. switch (mode) {
  843. case AR5K_MODE_11A:
  844. case AR5K_MODE_11A_TURBO:
  845. /* 1..220, but 2GHz frequencies are filtered by check_channel */
  846. size = 220 ;
  847. chfreq = CHANNEL_5GHZ;
  848. break;
  849. case AR5K_MODE_11B:
  850. case AR5K_MODE_11G:
  851. case AR5K_MODE_11G_TURBO:
  852. size = 26;
  853. chfreq = CHANNEL_2GHZ;
  854. break;
  855. default:
  856. ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
  857. return 0;
  858. }
  859. for (i = 0, count = 0; i < size && max > 0; i++) {
  860. ch = i + 1 ;
  861. freq = ath5k_ieee2mhz(ch);
  862. /* Check if channel is supported by the chipset */
  863. if (!ath5k_channel_ok(ah, freq, chfreq))
  864. continue;
  865. if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
  866. continue;
  867. /* Write channel info and increment counter */
  868. channels[count].center_freq = freq;
  869. channels[count].band = (chfreq == CHANNEL_2GHZ) ?
  870. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  871. switch (mode) {
  872. case AR5K_MODE_11A:
  873. case AR5K_MODE_11G:
  874. channels[count].hw_value = chfreq | CHANNEL_OFDM;
  875. break;
  876. case AR5K_MODE_11A_TURBO:
  877. case AR5K_MODE_11G_TURBO:
  878. channels[count].hw_value = chfreq |
  879. CHANNEL_OFDM | CHANNEL_TURBO;
  880. break;
  881. case AR5K_MODE_11B:
  882. channels[count].hw_value = CHANNEL_B;
  883. }
  884. count++;
  885. max--;
  886. }
  887. return count;
  888. }
  889. static void
  890. ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
  891. {
  892. u8 i;
  893. for (i = 0; i < AR5K_MAX_RATES; i++)
  894. sc->rate_idx[b->band][i] = -1;
  895. for (i = 0; i < b->n_bitrates; i++) {
  896. sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
  897. if (b->bitrates[i].hw_value_short)
  898. sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
  899. }
  900. }
  901. static int
  902. ath5k_setup_bands(struct ieee80211_hw *hw)
  903. {
  904. struct ath5k_softc *sc = hw->priv;
  905. struct ath5k_hw *ah = sc->ah;
  906. struct ieee80211_supported_band *sband;
  907. int max_c, count_c = 0;
  908. int i;
  909. BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
  910. max_c = ARRAY_SIZE(sc->channels);
  911. /* 2GHz band */
  912. sband = &sc->sbands[IEEE80211_BAND_2GHZ];
  913. sband->band = IEEE80211_BAND_2GHZ;
  914. sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
  915. if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
  916. /* G mode */
  917. memcpy(sband->bitrates, &ath5k_rates[0],
  918. sizeof(struct ieee80211_rate) * 12);
  919. sband->n_bitrates = 12;
  920. sband->channels = sc->channels;
  921. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  922. AR5K_MODE_11G, max_c);
  923. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  924. count_c = sband->n_channels;
  925. max_c -= count_c;
  926. } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
  927. /* B mode */
  928. memcpy(sband->bitrates, &ath5k_rates[0],
  929. sizeof(struct ieee80211_rate) * 4);
  930. sband->n_bitrates = 4;
  931. /* 5211 only supports B rates and uses 4bit rate codes
  932. * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
  933. * fix them up here:
  934. */
  935. if (ah->ah_version == AR5K_AR5211) {
  936. for (i = 0; i < 4; i++) {
  937. sband->bitrates[i].hw_value =
  938. sband->bitrates[i].hw_value & 0xF;
  939. sband->bitrates[i].hw_value_short =
  940. sband->bitrates[i].hw_value_short & 0xF;
  941. }
  942. }
  943. sband->channels = sc->channels;
  944. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  945. AR5K_MODE_11B, max_c);
  946. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  947. count_c = sband->n_channels;
  948. max_c -= count_c;
  949. }
  950. ath5k_setup_rate_idx(sc, sband);
  951. /* 5GHz band, A mode */
  952. if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
  953. sband = &sc->sbands[IEEE80211_BAND_5GHZ];
  954. sband->band = IEEE80211_BAND_5GHZ;
  955. sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
  956. memcpy(sband->bitrates, &ath5k_rates[4],
  957. sizeof(struct ieee80211_rate) * 8);
  958. sband->n_bitrates = 8;
  959. sband->channels = &sc->channels[count_c];
  960. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  961. AR5K_MODE_11A, max_c);
  962. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
  963. }
  964. ath5k_setup_rate_idx(sc, sband);
  965. ath5k_debug_dump_bands(sc);
  966. return 0;
  967. }
  968. /*
  969. * Set/change channels. We always reset the chip.
  970. * To accomplish this we must first cleanup any pending DMA,
  971. * then restart stuff after a la ath5k_init.
  972. *
  973. * Called with sc->lock.
  974. */
  975. static int
  976. ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  977. {
  978. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  979. "channel set, resetting (%u -> %u MHz)\n",
  980. sc->curchan->center_freq, chan->center_freq);
  981. /*
  982. * To switch channels clear any pending DMA operations;
  983. * wait long enough for the RX fifo to drain, reset the
  984. * hardware at the new frequency, and then re-enable
  985. * the relevant bits of the h/w.
  986. */
  987. return ath5k_reset(sc, chan);
  988. }
  989. static void
  990. ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
  991. {
  992. sc->curmode = mode;
  993. if (mode == AR5K_MODE_11A) {
  994. sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
  995. } else {
  996. sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
  997. }
  998. }
  999. static void
  1000. ath5k_mode_setup(struct ath5k_softc *sc)
  1001. {
  1002. struct ath5k_hw *ah = sc->ah;
  1003. u32 rfilt;
  1004. /* configure rx filter */
  1005. rfilt = sc->filter_flags;
  1006. ath5k_hw_set_rx_filter(ah, rfilt);
  1007. if (ath5k_hw_hasbssidmask(ah))
  1008. ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
  1009. /* configure operational mode */
  1010. ath5k_hw_set_opmode(ah, sc->opmode);
  1011. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
  1012. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
  1013. }
  1014. static inline int
  1015. ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
  1016. {
  1017. int rix;
  1018. /* return base rate on errors */
  1019. if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
  1020. "hw_rix out of bounds: %x\n", hw_rix))
  1021. return 0;
  1022. rix = sc->rate_idx[sc->curband->band][hw_rix];
  1023. if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
  1024. rix = 0;
  1025. return rix;
  1026. }
  1027. /***************\
  1028. * Buffers setup *
  1029. \***************/
  1030. static
  1031. struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
  1032. {
  1033. struct ath_common *common = ath5k_hw_common(sc->ah);
  1034. struct sk_buff *skb;
  1035. /*
  1036. * Allocate buffer with headroom_needed space for the
  1037. * fake physical layer header at the start.
  1038. */
  1039. skb = ath_rxbuf_alloc(common,
  1040. common->rx_bufsize,
  1041. GFP_ATOMIC);
  1042. if (!skb) {
  1043. ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
  1044. common->rx_bufsize);
  1045. return NULL;
  1046. }
  1047. *skb_addr = pci_map_single(sc->pdev,
  1048. skb->data, common->rx_bufsize,
  1049. PCI_DMA_FROMDEVICE);
  1050. if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
  1051. ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
  1052. dev_kfree_skb(skb);
  1053. return NULL;
  1054. }
  1055. return skb;
  1056. }
  1057. static int
  1058. ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1059. {
  1060. struct ath5k_hw *ah = sc->ah;
  1061. struct sk_buff *skb = bf->skb;
  1062. struct ath5k_desc *ds;
  1063. int ret;
  1064. if (!skb) {
  1065. skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
  1066. if (!skb)
  1067. return -ENOMEM;
  1068. bf->skb = skb;
  1069. }
  1070. /*
  1071. * Setup descriptors. For receive we always terminate
  1072. * the descriptor list with a self-linked entry so we'll
  1073. * not get overrun under high load (as can happen with a
  1074. * 5212 when ANI processing enables PHY error frames).
  1075. *
  1076. * To ensure the last descriptor is self-linked we create
  1077. * each descriptor as self-linked and add it to the end. As
  1078. * each additional descriptor is added the previous self-linked
  1079. * entry is "fixed" naturally. This should be safe even
  1080. * if DMA is happening. When processing RX interrupts we
  1081. * never remove/process the last, self-linked, entry on the
  1082. * descriptor list. This ensures the hardware always has
  1083. * someplace to write a new frame.
  1084. */
  1085. ds = bf->desc;
  1086. ds->ds_link = bf->daddr; /* link to self */
  1087. ds->ds_data = bf->skbaddr;
  1088. ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
  1089. if (ret) {
  1090. ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
  1091. return ret;
  1092. }
  1093. if (sc->rxlink != NULL)
  1094. *sc->rxlink = bf->daddr;
  1095. sc->rxlink = &ds->ds_link;
  1096. return 0;
  1097. }
  1098. static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  1099. {
  1100. struct ieee80211_hdr *hdr;
  1101. enum ath5k_pkt_type htype;
  1102. __le16 fc;
  1103. hdr = (struct ieee80211_hdr *)skb->data;
  1104. fc = hdr->frame_control;
  1105. if (ieee80211_is_beacon(fc))
  1106. htype = AR5K_PKT_TYPE_BEACON;
  1107. else if (ieee80211_is_probe_resp(fc))
  1108. htype = AR5K_PKT_TYPE_PROBE_RESP;
  1109. else if (ieee80211_is_atim(fc))
  1110. htype = AR5K_PKT_TYPE_ATIM;
  1111. else if (ieee80211_is_pspoll(fc))
  1112. htype = AR5K_PKT_TYPE_PSPOLL;
  1113. else
  1114. htype = AR5K_PKT_TYPE_NORMAL;
  1115. return htype;
  1116. }
  1117. static int
  1118. ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
  1119. struct ath5k_txq *txq, int padsize)
  1120. {
  1121. struct ath5k_hw *ah = sc->ah;
  1122. struct ath5k_desc *ds = bf->desc;
  1123. struct sk_buff *skb = bf->skb;
  1124. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1125. unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
  1126. struct ieee80211_rate *rate;
  1127. unsigned int mrr_rate[3], mrr_tries[3];
  1128. int i, ret;
  1129. u16 hw_rate;
  1130. u16 cts_rate = 0;
  1131. u16 duration = 0;
  1132. u8 rc_flags;
  1133. flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
  1134. /* XXX endianness */
  1135. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1136. PCI_DMA_TODEVICE);
  1137. rate = ieee80211_get_tx_rate(sc->hw, info);
  1138. if (info->flags & IEEE80211_TX_CTL_NO_ACK)
  1139. flags |= AR5K_TXDESC_NOACK;
  1140. rc_flags = info->control.rates[0].flags;
  1141. hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
  1142. rate->hw_value_short : rate->hw_value;
  1143. pktlen = skb->len;
  1144. /* FIXME: If we are in g mode and rate is a CCK rate
  1145. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1146. * from tx power (value is in dB units already) */
  1147. if (info->control.hw_key) {
  1148. keyidx = info->control.hw_key->hw_key_idx;
  1149. pktlen += info->control.hw_key->icv_len;
  1150. }
  1151. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1152. flags |= AR5K_TXDESC_RTSENA;
  1153. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1154. duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
  1155. sc->vif, pktlen, info));
  1156. }
  1157. if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1158. flags |= AR5K_TXDESC_CTSENA;
  1159. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1160. duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
  1161. sc->vif, pktlen, info));
  1162. }
  1163. ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
  1164. ieee80211_get_hdrlen_from_skb(skb), padsize,
  1165. get_hw_packet_type(skb),
  1166. (sc->power_level * 2),
  1167. hw_rate,
  1168. info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
  1169. cts_rate, duration);
  1170. if (ret)
  1171. goto err_unmap;
  1172. memset(mrr_rate, 0, sizeof(mrr_rate));
  1173. memset(mrr_tries, 0, sizeof(mrr_tries));
  1174. for (i = 0; i < 3; i++) {
  1175. rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
  1176. if (!rate)
  1177. break;
  1178. mrr_rate[i] = rate->hw_value;
  1179. mrr_tries[i] = info->control.rates[i + 1].count;
  1180. }
  1181. ah->ah_setup_mrr_tx_desc(ah, ds,
  1182. mrr_rate[0], mrr_tries[0],
  1183. mrr_rate[1], mrr_tries[1],
  1184. mrr_rate[2], mrr_tries[2]);
  1185. ds->ds_link = 0;
  1186. ds->ds_data = bf->skbaddr;
  1187. spin_lock_bh(&txq->lock);
  1188. list_add_tail(&bf->list, &txq->q);
  1189. if (txq->link == NULL) /* is this first packet? */
  1190. ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
  1191. else /* no, so only link it */
  1192. *txq->link = bf->daddr;
  1193. txq->link = &ds->ds_link;
  1194. ath5k_hw_start_tx_dma(ah, txq->qnum);
  1195. mmiowb();
  1196. spin_unlock_bh(&txq->lock);
  1197. return 0;
  1198. err_unmap:
  1199. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1200. return ret;
  1201. }
  1202. /*******************\
  1203. * Descriptors setup *
  1204. \*******************/
  1205. static int
  1206. ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
  1207. {
  1208. struct ath5k_desc *ds;
  1209. struct ath5k_buf *bf;
  1210. dma_addr_t da;
  1211. unsigned int i;
  1212. int ret;
  1213. /* allocate descriptors */
  1214. sc->desc_len = sizeof(struct ath5k_desc) *
  1215. (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
  1216. sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
  1217. if (sc->desc == NULL) {
  1218. ATH5K_ERR(sc, "can't allocate descriptors\n");
  1219. ret = -ENOMEM;
  1220. goto err;
  1221. }
  1222. ds = sc->desc;
  1223. da = sc->desc_daddr;
  1224. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
  1225. ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
  1226. bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
  1227. sizeof(struct ath5k_buf), GFP_KERNEL);
  1228. if (bf == NULL) {
  1229. ATH5K_ERR(sc, "can't allocate bufptr\n");
  1230. ret = -ENOMEM;
  1231. goto err_free;
  1232. }
  1233. sc->bufptr = bf;
  1234. INIT_LIST_HEAD(&sc->rxbuf);
  1235. for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  1236. bf->desc = ds;
  1237. bf->daddr = da;
  1238. list_add_tail(&bf->list, &sc->rxbuf);
  1239. }
  1240. INIT_LIST_HEAD(&sc->txbuf);
  1241. sc->txbuf_len = ATH_TXBUF;
  1242. for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
  1243. da += sizeof(*ds)) {
  1244. bf->desc = ds;
  1245. bf->daddr = da;
  1246. list_add_tail(&bf->list, &sc->txbuf);
  1247. }
  1248. /* beacon buffer */
  1249. bf->desc = ds;
  1250. bf->daddr = da;
  1251. sc->bbuf = bf;
  1252. return 0;
  1253. err_free:
  1254. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1255. err:
  1256. sc->desc = NULL;
  1257. return ret;
  1258. }
  1259. static void
  1260. ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
  1261. {
  1262. struct ath5k_buf *bf;
  1263. ath5k_txbuf_free_skb(sc, sc->bbuf);
  1264. list_for_each_entry(bf, &sc->txbuf, list)
  1265. ath5k_txbuf_free_skb(sc, bf);
  1266. list_for_each_entry(bf, &sc->rxbuf, list)
  1267. ath5k_rxbuf_free_skb(sc, bf);
  1268. /* Free memory associated with all descriptors */
  1269. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1270. sc->desc = NULL;
  1271. sc->desc_daddr = 0;
  1272. kfree(sc->bufptr);
  1273. sc->bufptr = NULL;
  1274. sc->bbuf = NULL;
  1275. }
  1276. /**************\
  1277. * Queues setup *
  1278. \**************/
  1279. static struct ath5k_txq *
  1280. ath5k_txq_setup(struct ath5k_softc *sc,
  1281. int qtype, int subtype)
  1282. {
  1283. struct ath5k_hw *ah = sc->ah;
  1284. struct ath5k_txq *txq;
  1285. struct ath5k_txq_info qi = {
  1286. .tqi_subtype = subtype,
  1287. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1288. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1289. .tqi_cw_max = AR5K_TXQ_USEDEFAULT
  1290. };
  1291. int qnum;
  1292. /*
  1293. * Enable interrupts only for EOL and DESC conditions.
  1294. * We mark tx descriptors to receive a DESC interrupt
  1295. * when a tx queue gets deep; otherwise waiting for the
  1296. * EOL to reap descriptors. Note that this is done to
  1297. * reduce interrupt load and this only defers reaping
  1298. * descriptors, never transmitting frames. Aside from
  1299. * reducing interrupts this also permits more concurrency.
  1300. * The only potential downside is if the tx queue backs
  1301. * up in which case the top half of the kernel may backup
  1302. * due to a lack of tx descriptors.
  1303. */
  1304. qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
  1305. AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
  1306. qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
  1307. if (qnum < 0) {
  1308. /*
  1309. * NB: don't print a message, this happens
  1310. * normally on parts with too few tx queues
  1311. */
  1312. return ERR_PTR(qnum);
  1313. }
  1314. if (qnum >= ARRAY_SIZE(sc->txqs)) {
  1315. ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
  1316. qnum, ARRAY_SIZE(sc->txqs));
  1317. ath5k_hw_release_tx_queue(ah, qnum);
  1318. return ERR_PTR(-EINVAL);
  1319. }
  1320. txq = &sc->txqs[qnum];
  1321. if (!txq->setup) {
  1322. txq->qnum = qnum;
  1323. txq->link = NULL;
  1324. INIT_LIST_HEAD(&txq->q);
  1325. spin_lock_init(&txq->lock);
  1326. txq->setup = true;
  1327. }
  1328. return &sc->txqs[qnum];
  1329. }
  1330. static int
  1331. ath5k_beaconq_setup(struct ath5k_hw *ah)
  1332. {
  1333. struct ath5k_txq_info qi = {
  1334. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1335. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1336. .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
  1337. /* NB: for dynamic turbo, don't enable any other interrupts */
  1338. .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
  1339. };
  1340. return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
  1341. }
  1342. static int
  1343. ath5k_beaconq_config(struct ath5k_softc *sc)
  1344. {
  1345. struct ath5k_hw *ah = sc->ah;
  1346. struct ath5k_txq_info qi;
  1347. int ret;
  1348. ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
  1349. if (ret)
  1350. goto err;
  1351. if (sc->opmode == NL80211_IFTYPE_AP ||
  1352. sc->opmode == NL80211_IFTYPE_MESH_POINT) {
  1353. /*
  1354. * Always burst out beacon and CAB traffic
  1355. * (aifs = cwmin = cwmax = 0)
  1356. */
  1357. qi.tqi_aifs = 0;
  1358. qi.tqi_cw_min = 0;
  1359. qi.tqi_cw_max = 0;
  1360. } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  1361. /*
  1362. * Adhoc mode; backoff between 0 and (2 * cw_min).
  1363. */
  1364. qi.tqi_aifs = 0;
  1365. qi.tqi_cw_min = 0;
  1366. qi.tqi_cw_max = 2 * ah->ah_cw_min;
  1367. }
  1368. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1369. "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
  1370. qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
  1371. ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
  1372. if (ret) {
  1373. ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
  1374. "hardware queue!\n", __func__);
  1375. goto err;
  1376. }
  1377. ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
  1378. if (ret)
  1379. goto err;
  1380. /* reconfigure cabq with ready time to 80% of beacon_interval */
  1381. ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  1382. if (ret)
  1383. goto err;
  1384. qi.tqi_ready_time = (sc->bintval * 80) / 100;
  1385. ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  1386. if (ret)
  1387. goto err;
  1388. ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
  1389. err:
  1390. return ret;
  1391. }
  1392. static void
  1393. ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1394. {
  1395. struct ath5k_buf *bf, *bf0;
  1396. /*
  1397. * NB: this assumes output has been stopped and
  1398. * we do not need to block ath5k_tx_tasklet
  1399. */
  1400. spin_lock_bh(&txq->lock);
  1401. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1402. ath5k_debug_printtxbuf(sc, bf);
  1403. ath5k_txbuf_free_skb(sc, bf);
  1404. spin_lock_bh(&sc->txbuflock);
  1405. list_move_tail(&bf->list, &sc->txbuf);
  1406. sc->txbuf_len++;
  1407. spin_unlock_bh(&sc->txbuflock);
  1408. }
  1409. txq->link = NULL;
  1410. spin_unlock_bh(&txq->lock);
  1411. }
  1412. /*
  1413. * Drain the transmit queues and reclaim resources.
  1414. */
  1415. static void
  1416. ath5k_txq_cleanup(struct ath5k_softc *sc)
  1417. {
  1418. struct ath5k_hw *ah = sc->ah;
  1419. unsigned int i;
  1420. /* XXX return value */
  1421. if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
  1422. /* don't touch the hardware if marked invalid */
  1423. ath5k_hw_stop_tx_dma(ah, sc->bhalq);
  1424. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
  1425. ath5k_hw_get_txdp(ah, sc->bhalq));
  1426. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1427. if (sc->txqs[i].setup) {
  1428. ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
  1429. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
  1430. "link %p\n",
  1431. sc->txqs[i].qnum,
  1432. ath5k_hw_get_txdp(ah,
  1433. sc->txqs[i].qnum),
  1434. sc->txqs[i].link);
  1435. }
  1436. }
  1437. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1438. if (sc->txqs[i].setup)
  1439. ath5k_txq_drainq(sc, &sc->txqs[i]);
  1440. }
  1441. static void
  1442. ath5k_txq_release(struct ath5k_softc *sc)
  1443. {
  1444. struct ath5k_txq *txq = sc->txqs;
  1445. unsigned int i;
  1446. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
  1447. if (txq->setup) {
  1448. ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
  1449. txq->setup = false;
  1450. }
  1451. }
  1452. /*************\
  1453. * RX Handling *
  1454. \*************/
  1455. /*
  1456. * Enable the receive h/w following a reset.
  1457. */
  1458. static int
  1459. ath5k_rx_start(struct ath5k_softc *sc)
  1460. {
  1461. struct ath5k_hw *ah = sc->ah;
  1462. struct ath_common *common = ath5k_hw_common(ah);
  1463. struct ath5k_buf *bf;
  1464. int ret;
  1465. common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
  1466. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
  1467. common->cachelsz, common->rx_bufsize);
  1468. spin_lock_bh(&sc->rxbuflock);
  1469. sc->rxlink = NULL;
  1470. list_for_each_entry(bf, &sc->rxbuf, list) {
  1471. ret = ath5k_rxbuf_setup(sc, bf);
  1472. if (ret != 0) {
  1473. spin_unlock_bh(&sc->rxbuflock);
  1474. goto err;
  1475. }
  1476. }
  1477. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1478. ath5k_hw_set_rxdp(ah, bf->daddr);
  1479. spin_unlock_bh(&sc->rxbuflock);
  1480. ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
  1481. ath5k_mode_setup(sc); /* set filters, etc. */
  1482. ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
  1483. return 0;
  1484. err:
  1485. return ret;
  1486. }
  1487. /*
  1488. * Disable the receive h/w in preparation for a reset.
  1489. */
  1490. static void
  1491. ath5k_rx_stop(struct ath5k_softc *sc)
  1492. {
  1493. struct ath5k_hw *ah = sc->ah;
  1494. ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
  1495. ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
  1496. ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
  1497. ath5k_debug_printrxbuffs(sc, ah);
  1498. sc->rxlink = NULL; /* just in case */
  1499. }
  1500. static unsigned int
  1501. ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
  1502. struct sk_buff *skb, struct ath5k_rx_status *rs)
  1503. {
  1504. struct ath5k_hw *ah = sc->ah;
  1505. struct ath_common *common = ath5k_hw_common(ah);
  1506. struct ieee80211_hdr *hdr = (void *)skb->data;
  1507. unsigned int keyix, hlen;
  1508. if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1509. rs->rs_keyix != AR5K_RXKEYIX_INVALID)
  1510. return RX_FLAG_DECRYPTED;
  1511. /* Apparently when a default key is used to decrypt the packet
  1512. the hw does not set the index used to decrypt. In such cases
  1513. get the index from the packet. */
  1514. hlen = ieee80211_hdrlen(hdr->frame_control);
  1515. if (ieee80211_has_protected(hdr->frame_control) &&
  1516. !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1517. skb->len >= hlen + 4) {
  1518. keyix = skb->data[hlen + 3] >> 6;
  1519. if (test_bit(keyix, common->keymap))
  1520. return RX_FLAG_DECRYPTED;
  1521. }
  1522. return 0;
  1523. }
  1524. static void
  1525. ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
  1526. struct ieee80211_rx_status *rxs)
  1527. {
  1528. struct ath_common *common = ath5k_hw_common(sc->ah);
  1529. u64 tsf, bc_tstamp;
  1530. u32 hw_tu;
  1531. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1532. if (ieee80211_is_beacon(mgmt->frame_control) &&
  1533. le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
  1534. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
  1535. /*
  1536. * Received an IBSS beacon with the same BSSID. Hardware *must*
  1537. * have updated the local TSF. We have to work around various
  1538. * hardware bugs, though...
  1539. */
  1540. tsf = ath5k_hw_get_tsf64(sc->ah);
  1541. bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
  1542. hw_tu = TSF_TO_TU(tsf);
  1543. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1544. "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
  1545. (unsigned long long)bc_tstamp,
  1546. (unsigned long long)rxs->mactime,
  1547. (unsigned long long)(rxs->mactime - bc_tstamp),
  1548. (unsigned long long)tsf);
  1549. /*
  1550. * Sometimes the HW will give us a wrong tstamp in the rx
  1551. * status, causing the timestamp extension to go wrong.
  1552. * (This seems to happen especially with beacon frames bigger
  1553. * than 78 byte (incl. FCS))
  1554. * But we know that the receive timestamp must be later than the
  1555. * timestamp of the beacon since HW must have synced to that.
  1556. *
  1557. * NOTE: here we assume mactime to be after the frame was
  1558. * received, not like mac80211 which defines it at the start.
  1559. */
  1560. if (bc_tstamp > rxs->mactime) {
  1561. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1562. "fixing mactime from %llx to %llx\n",
  1563. (unsigned long long)rxs->mactime,
  1564. (unsigned long long)tsf);
  1565. rxs->mactime = tsf;
  1566. }
  1567. /*
  1568. * Local TSF might have moved higher than our beacon timers,
  1569. * in that case we have to update them to continue sending
  1570. * beacons. This also takes care of synchronizing beacon sending
  1571. * times with other stations.
  1572. */
  1573. if (hw_tu >= sc->nexttbtt)
  1574. ath5k_beacon_update_timers(sc, bc_tstamp);
  1575. }
  1576. }
  1577. static void
  1578. ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
  1579. {
  1580. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1581. struct ath5k_hw *ah = sc->ah;
  1582. struct ath_common *common = ath5k_hw_common(ah);
  1583. /* only beacons from our BSSID */
  1584. if (!ieee80211_is_beacon(mgmt->frame_control) ||
  1585. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
  1586. return;
  1587. ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
  1588. rssi);
  1589. /* in IBSS mode we should keep RSSI statistics per neighbour */
  1590. /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
  1591. }
  1592. /*
  1593. * Compute padding position. skb must contains an IEEE 802.11 frame
  1594. */
  1595. static int ath5k_common_padpos(struct sk_buff *skb)
  1596. {
  1597. struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
  1598. __le16 frame_control = hdr->frame_control;
  1599. int padpos = 24;
  1600. if (ieee80211_has_a4(frame_control)) {
  1601. padpos += ETH_ALEN;
  1602. }
  1603. if (ieee80211_is_data_qos(frame_control)) {
  1604. padpos += IEEE80211_QOS_CTL_LEN;
  1605. }
  1606. return padpos;
  1607. }
  1608. /*
  1609. * This function expects a 802.11 frame and returns the number of
  1610. * bytes added, or -1 if we don't have enought header room.
  1611. */
  1612. static int ath5k_add_padding(struct sk_buff *skb)
  1613. {
  1614. int padpos = ath5k_common_padpos(skb);
  1615. int padsize = padpos & 3;
  1616. if (padsize && skb->len>padpos) {
  1617. if (skb_headroom(skb) < padsize)
  1618. return -1;
  1619. skb_push(skb, padsize);
  1620. memmove(skb->data, skb->data+padsize, padpos);
  1621. return padsize;
  1622. }
  1623. return 0;
  1624. }
  1625. /*
  1626. * This function expects a 802.11 frame and returns the number of
  1627. * bytes removed
  1628. */
  1629. static int ath5k_remove_padding(struct sk_buff *skb)
  1630. {
  1631. int padpos = ath5k_common_padpos(skb);
  1632. int padsize = padpos & 3;
  1633. if (padsize && skb->len>=padpos+padsize) {
  1634. memmove(skb->data + padsize, skb->data, padpos);
  1635. skb_pull(skb, padsize);
  1636. return padsize;
  1637. }
  1638. return 0;
  1639. }
  1640. static void
  1641. ath5k_tasklet_rx(unsigned long data)
  1642. {
  1643. struct ieee80211_rx_status *rxs;
  1644. struct ath5k_rx_status rs = {};
  1645. struct sk_buff *skb, *next_skb;
  1646. dma_addr_t next_skb_addr;
  1647. struct ath5k_softc *sc = (void *)data;
  1648. struct ath5k_hw *ah = sc->ah;
  1649. struct ath_common *common = ath5k_hw_common(ah);
  1650. struct ath5k_buf *bf;
  1651. struct ath5k_desc *ds;
  1652. int ret;
  1653. int rx_flag;
  1654. spin_lock(&sc->rxbuflock);
  1655. if (list_empty(&sc->rxbuf)) {
  1656. ATH5K_WARN(sc, "empty rx buf pool\n");
  1657. goto unlock;
  1658. }
  1659. do {
  1660. rx_flag = 0;
  1661. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1662. BUG_ON(bf->skb == NULL);
  1663. skb = bf->skb;
  1664. ds = bf->desc;
  1665. /* bail if HW is still using self-linked descriptor */
  1666. if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
  1667. break;
  1668. ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
  1669. if (unlikely(ret == -EINPROGRESS))
  1670. break;
  1671. else if (unlikely(ret)) {
  1672. ATH5K_ERR(sc, "error in processing rx descriptor\n");
  1673. sc->stats.rxerr_proc++;
  1674. spin_unlock(&sc->rxbuflock);
  1675. return;
  1676. }
  1677. sc->stats.rx_all_count++;
  1678. if (unlikely(rs.rs_status)) {
  1679. if (rs.rs_status & AR5K_RXERR_CRC)
  1680. sc->stats.rxerr_crc++;
  1681. if (rs.rs_status & AR5K_RXERR_FIFO)
  1682. sc->stats.rxerr_fifo++;
  1683. if (rs.rs_status & AR5K_RXERR_PHY) {
  1684. sc->stats.rxerr_phy++;
  1685. if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
  1686. sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
  1687. goto next;
  1688. }
  1689. if (rs.rs_status & AR5K_RXERR_DECRYPT) {
  1690. /*
  1691. * Decrypt error. If the error occurred
  1692. * because there was no hardware key, then
  1693. * let the frame through so the upper layers
  1694. * can process it. This is necessary for 5210
  1695. * parts which have no way to setup a ``clear''
  1696. * key cache entry.
  1697. *
  1698. * XXX do key cache faulting
  1699. */
  1700. sc->stats.rxerr_decrypt++;
  1701. if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
  1702. !(rs.rs_status & AR5K_RXERR_CRC))
  1703. goto accept;
  1704. }
  1705. if (rs.rs_status & AR5K_RXERR_MIC) {
  1706. rx_flag |= RX_FLAG_MMIC_ERROR;
  1707. sc->stats.rxerr_mic++;
  1708. goto accept;
  1709. }
  1710. /* let crypto-error packets fall through in MNTR */
  1711. if ((rs.rs_status &
  1712. ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
  1713. sc->opmode != NL80211_IFTYPE_MONITOR)
  1714. goto next;
  1715. }
  1716. if (unlikely(rs.rs_more)) {
  1717. sc->stats.rxerr_jumbo++;
  1718. goto next;
  1719. }
  1720. accept:
  1721. next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
  1722. /*
  1723. * If we can't replace bf->skb with a new skb under memory
  1724. * pressure, just skip this packet
  1725. */
  1726. if (!next_skb)
  1727. goto next;
  1728. pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
  1729. PCI_DMA_FROMDEVICE);
  1730. skb_put(skb, rs.rs_datalen);
  1731. /* The MAC header is padded to have 32-bit boundary if the
  1732. * packet payload is non-zero. The general calculation for
  1733. * padsize would take into account odd header lengths:
  1734. * padsize = (4 - hdrlen % 4) % 4; However, since only
  1735. * even-length headers are used, padding can only be 0 or 2
  1736. * bytes and we can optimize this a bit. In addition, we must
  1737. * not try to remove padding from short control frames that do
  1738. * not have payload. */
  1739. ath5k_remove_padding(skb);
  1740. rxs = IEEE80211_SKB_RXCB(skb);
  1741. /*
  1742. * always extend the mac timestamp, since this information is
  1743. * also needed for proper IBSS merging.
  1744. *
  1745. * XXX: it might be too late to do it here, since rs_tstamp is
  1746. * 15bit only. that means TSF extension has to be done within
  1747. * 32768usec (about 32ms). it might be necessary to move this to
  1748. * the interrupt handler, like it is done in madwifi.
  1749. *
  1750. * Unfortunately we don't know when the hardware takes the rx
  1751. * timestamp (beginning of phy frame, data frame, end of rx?).
  1752. * The only thing we know is that it is hardware specific...
  1753. * On AR5213 it seems the rx timestamp is at the end of the
  1754. * frame, but i'm not sure.
  1755. *
  1756. * NOTE: mac80211 defines mactime at the beginning of the first
  1757. * data symbol. Since we don't have any time references it's
  1758. * impossible to comply to that. This affects IBSS merge only
  1759. * right now, so it's not too bad...
  1760. */
  1761. rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
  1762. rxs->flag = rx_flag | RX_FLAG_TSFT;
  1763. rxs->freq = sc->curchan->center_freq;
  1764. rxs->band = sc->curband->band;
  1765. rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
  1766. rxs->antenna = rs.rs_antenna;
  1767. if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
  1768. sc->stats.antenna_rx[rs.rs_antenna]++;
  1769. else
  1770. sc->stats.antenna_rx[0]++; /* invalid */
  1771. rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
  1772. rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
  1773. if (rxs->rate_idx >= 0 && rs.rs_rate ==
  1774. sc->curband->bitrates[rxs->rate_idx].hw_value_short)
  1775. rxs->flag |= RX_FLAG_SHORTPRE;
  1776. ath5k_debug_dump_skb(sc, skb, "RX ", 0);
  1777. ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
  1778. /* check beacons in IBSS mode */
  1779. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  1780. ath5k_check_ibss_tsf(sc, skb, rxs);
  1781. ieee80211_rx(sc->hw, skb);
  1782. bf->skb = next_skb;
  1783. bf->skbaddr = next_skb_addr;
  1784. next:
  1785. list_move_tail(&bf->list, &sc->rxbuf);
  1786. } while (ath5k_rxbuf_setup(sc, bf) == 0);
  1787. unlock:
  1788. spin_unlock(&sc->rxbuflock);
  1789. }
  1790. /*************\
  1791. * TX Handling *
  1792. \*************/
  1793. static void
  1794. ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1795. {
  1796. struct ath5k_tx_status ts = {};
  1797. struct ath5k_buf *bf, *bf0;
  1798. struct ath5k_desc *ds;
  1799. struct sk_buff *skb;
  1800. struct ieee80211_tx_info *info;
  1801. int i, ret;
  1802. spin_lock(&txq->lock);
  1803. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1804. ds = bf->desc;
  1805. /*
  1806. * It's possible that the hardware can say the buffer is
  1807. * completed when it hasn't yet loaded the ds_link from
  1808. * host memory and moved on. If there are more TX
  1809. * descriptors in the queue, wait for TXDP to change
  1810. * before processing this one.
  1811. */
  1812. if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
  1813. !list_is_last(&bf->list, &txq->q))
  1814. break;
  1815. ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
  1816. if (unlikely(ret == -EINPROGRESS))
  1817. break;
  1818. else if (unlikely(ret)) {
  1819. ATH5K_ERR(sc, "error %d while processing queue %u\n",
  1820. ret, txq->qnum);
  1821. break;
  1822. }
  1823. sc->stats.tx_all_count++;
  1824. skb = bf->skb;
  1825. info = IEEE80211_SKB_CB(skb);
  1826. bf->skb = NULL;
  1827. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
  1828. PCI_DMA_TODEVICE);
  1829. ieee80211_tx_info_clear_status(info);
  1830. for (i = 0; i < 4; i++) {
  1831. struct ieee80211_tx_rate *r =
  1832. &info->status.rates[i];
  1833. if (ts.ts_rate[i]) {
  1834. r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
  1835. r->count = ts.ts_retry[i];
  1836. } else {
  1837. r->idx = -1;
  1838. r->count = 0;
  1839. }
  1840. }
  1841. /* count the successful attempt as well */
  1842. info->status.rates[ts.ts_final_idx].count++;
  1843. if (unlikely(ts.ts_status)) {
  1844. sc->stats.ack_fail++;
  1845. if (ts.ts_status & AR5K_TXERR_FILT) {
  1846. info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1847. sc->stats.txerr_filt++;
  1848. }
  1849. if (ts.ts_status & AR5K_TXERR_XRETRY)
  1850. sc->stats.txerr_retry++;
  1851. if (ts.ts_status & AR5K_TXERR_FIFO)
  1852. sc->stats.txerr_fifo++;
  1853. } else {
  1854. info->flags |= IEEE80211_TX_STAT_ACK;
  1855. info->status.ack_signal = ts.ts_rssi;
  1856. }
  1857. /*
  1858. * Remove MAC header padding before giving the frame
  1859. * back to mac80211.
  1860. */
  1861. ath5k_remove_padding(skb);
  1862. if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
  1863. sc->stats.antenna_tx[ts.ts_antenna]++;
  1864. else
  1865. sc->stats.antenna_tx[0]++; /* invalid */
  1866. ieee80211_tx_status(sc->hw, skb);
  1867. spin_lock(&sc->txbuflock);
  1868. list_move_tail(&bf->list, &sc->txbuf);
  1869. sc->txbuf_len++;
  1870. spin_unlock(&sc->txbuflock);
  1871. }
  1872. if (likely(list_empty(&txq->q)))
  1873. txq->link = NULL;
  1874. spin_unlock(&txq->lock);
  1875. if (sc->txbuf_len > ATH_TXBUF / 5)
  1876. ieee80211_wake_queues(sc->hw);
  1877. }
  1878. static void
  1879. ath5k_tasklet_tx(unsigned long data)
  1880. {
  1881. int i;
  1882. struct ath5k_softc *sc = (void *)data;
  1883. for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
  1884. if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
  1885. ath5k_tx_processq(sc, &sc->txqs[i]);
  1886. }
  1887. /*****************\
  1888. * Beacon handling *
  1889. \*****************/
  1890. /*
  1891. * Setup the beacon frame for transmit.
  1892. */
  1893. static int
  1894. ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1895. {
  1896. struct sk_buff *skb = bf->skb;
  1897. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1898. struct ath5k_hw *ah = sc->ah;
  1899. struct ath5k_desc *ds;
  1900. int ret = 0;
  1901. u8 antenna;
  1902. u32 flags;
  1903. const int padsize = 0;
  1904. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1905. PCI_DMA_TODEVICE);
  1906. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
  1907. "skbaddr %llx\n", skb, skb->data, skb->len,
  1908. (unsigned long long)bf->skbaddr);
  1909. if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
  1910. ATH5K_ERR(sc, "beacon DMA mapping failed\n");
  1911. return -EIO;
  1912. }
  1913. ds = bf->desc;
  1914. antenna = ah->ah_tx_ant;
  1915. flags = AR5K_TXDESC_NOACK;
  1916. if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
  1917. ds->ds_link = bf->daddr; /* self-linked */
  1918. flags |= AR5K_TXDESC_VEOL;
  1919. } else
  1920. ds->ds_link = 0;
  1921. /*
  1922. * If we use multiple antennas on AP and use
  1923. * the Sectored AP scenario, switch antenna every
  1924. * 4 beacons to make sure everybody hears our AP.
  1925. * When a client tries to associate, hw will keep
  1926. * track of the tx antenna to be used for this client
  1927. * automaticaly, based on ACKed packets.
  1928. *
  1929. * Note: AP still listens and transmits RTS on the
  1930. * default antenna which is supposed to be an omni.
  1931. *
  1932. * Note2: On sectored scenarios it's possible to have
  1933. * multiple antennas (1omni -the default- and 14 sectors)
  1934. * so if we choose to actually support this mode we need
  1935. * to allow user to set how many antennas we have and tweak
  1936. * the code below to send beacons on all of them.
  1937. */
  1938. if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
  1939. antenna = sc->bsent & 4 ? 2 : 1;
  1940. /* FIXME: If we are in g mode and rate is a CCK rate
  1941. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1942. * from tx power (value is in dB units already) */
  1943. ds->ds_data = bf->skbaddr;
  1944. ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
  1945. ieee80211_get_hdrlen_from_skb(skb), padsize,
  1946. AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
  1947. ieee80211_get_tx_rate(sc->hw, info)->hw_value,
  1948. 1, AR5K_TXKEYIX_INVALID,
  1949. antenna, flags, 0, 0);
  1950. if (ret)
  1951. goto err_unmap;
  1952. return 0;
  1953. err_unmap:
  1954. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1955. return ret;
  1956. }
  1957. /*
  1958. * Transmit a beacon frame at SWBA. Dynamic updates to the
  1959. * frame contents are done as needed and the slot time is
  1960. * also adjusted based on current state.
  1961. *
  1962. * This is called from software irq context (beacontq or restq
  1963. * tasklets) or user context from ath5k_beacon_config.
  1964. */
  1965. static void
  1966. ath5k_beacon_send(struct ath5k_softc *sc)
  1967. {
  1968. struct ath5k_buf *bf = sc->bbuf;
  1969. struct ath5k_hw *ah = sc->ah;
  1970. struct sk_buff *skb;
  1971. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
  1972. if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
  1973. sc->opmode == NL80211_IFTYPE_MONITOR)) {
  1974. ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
  1975. return;
  1976. }
  1977. /*
  1978. * Check if the previous beacon has gone out. If
  1979. * not don't don't try to post another, skip this
  1980. * period and wait for the next. Missed beacons
  1981. * indicate a problem and should not occur. If we
  1982. * miss too many consecutive beacons reset the device.
  1983. */
  1984. if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
  1985. sc->bmisscount++;
  1986. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1987. "missed %u consecutive beacons\n", sc->bmisscount);
  1988. if (sc->bmisscount > 10) { /* NB: 10 is a guess */
  1989. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1990. "stuck beacon time (%u missed)\n",
  1991. sc->bmisscount);
  1992. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  1993. "stuck beacon, resetting\n");
  1994. tasklet_schedule(&sc->restq);
  1995. }
  1996. return;
  1997. }
  1998. if (unlikely(sc->bmisscount != 0)) {
  1999. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2000. "resume beacon xmit after %u misses\n",
  2001. sc->bmisscount);
  2002. sc->bmisscount = 0;
  2003. }
  2004. /*
  2005. * Stop any current dma and put the new frame on the queue.
  2006. * This should never fail since we check above that no frames
  2007. * are still pending on the queue.
  2008. */
  2009. if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
  2010. ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
  2011. /* NB: hw still stops DMA, so proceed */
  2012. }
  2013. /* refresh the beacon for AP mode */
  2014. if (sc->opmode == NL80211_IFTYPE_AP)
  2015. ath5k_beacon_update(sc->hw, sc->vif);
  2016. ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
  2017. ath5k_hw_start_tx_dma(ah, sc->bhalq);
  2018. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
  2019. sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
  2020. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  2021. while (skb) {
  2022. ath5k_tx_queue(sc->hw, skb, sc->cabq);
  2023. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  2024. }
  2025. sc->bsent++;
  2026. }
  2027. /**
  2028. * ath5k_beacon_update_timers - update beacon timers
  2029. *
  2030. * @sc: struct ath5k_softc pointer we are operating on
  2031. * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
  2032. * beacon timer update based on the current HW TSF.
  2033. *
  2034. * Calculate the next target beacon transmit time (TBTT) based on the timestamp
  2035. * of a received beacon or the current local hardware TSF and write it to the
  2036. * beacon timer registers.
  2037. *
  2038. * This is called in a variety of situations, e.g. when a beacon is received,
  2039. * when a TSF update has been detected, but also when an new IBSS is created or
  2040. * when we otherwise know we have to update the timers, but we keep it in this
  2041. * function to have it all together in one place.
  2042. */
  2043. static void
  2044. ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
  2045. {
  2046. struct ath5k_hw *ah = sc->ah;
  2047. u32 nexttbtt, intval, hw_tu, bc_tu;
  2048. u64 hw_tsf;
  2049. intval = sc->bintval & AR5K_BEACON_PERIOD;
  2050. if (WARN_ON(!intval))
  2051. return;
  2052. /* beacon TSF converted to TU */
  2053. bc_tu = TSF_TO_TU(bc_tsf);
  2054. /* current TSF converted to TU */
  2055. hw_tsf = ath5k_hw_get_tsf64(ah);
  2056. hw_tu = TSF_TO_TU(hw_tsf);
  2057. #define FUDGE 3
  2058. /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
  2059. if (bc_tsf == -1) {
  2060. /*
  2061. * no beacons received, called internally.
  2062. * just need to refresh timers based on HW TSF.
  2063. */
  2064. nexttbtt = roundup(hw_tu + FUDGE, intval);
  2065. } else if (bc_tsf == 0) {
  2066. /*
  2067. * no beacon received, probably called by ath5k_reset_tsf().
  2068. * reset TSF to start with 0.
  2069. */
  2070. nexttbtt = intval;
  2071. intval |= AR5K_BEACON_RESET_TSF;
  2072. } else if (bc_tsf > hw_tsf) {
  2073. /*
  2074. * beacon received, SW merge happend but HW TSF not yet updated.
  2075. * not possible to reconfigure timers yet, but next time we
  2076. * receive a beacon with the same BSSID, the hardware will
  2077. * automatically update the TSF and then we need to reconfigure
  2078. * the timers.
  2079. */
  2080. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2081. "need to wait for HW TSF sync\n");
  2082. return;
  2083. } else {
  2084. /*
  2085. * most important case for beacon synchronization between STA.
  2086. *
  2087. * beacon received and HW TSF has been already updated by HW.
  2088. * update next TBTT based on the TSF of the beacon, but make
  2089. * sure it is ahead of our local TSF timer.
  2090. */
  2091. nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
  2092. }
  2093. #undef FUDGE
  2094. sc->nexttbtt = nexttbtt;
  2095. intval |= AR5K_BEACON_ENA;
  2096. ath5k_hw_init_beacon(ah, nexttbtt, intval);
  2097. /*
  2098. * debugging output last in order to preserve the time critical aspect
  2099. * of this function
  2100. */
  2101. if (bc_tsf == -1)
  2102. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2103. "reconfigured timers based on HW TSF\n");
  2104. else if (bc_tsf == 0)
  2105. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2106. "reset HW TSF and timers\n");
  2107. else
  2108. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2109. "updated timers based on beacon TSF\n");
  2110. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2111. "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
  2112. (unsigned long long) bc_tsf,
  2113. (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
  2114. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
  2115. intval & AR5K_BEACON_PERIOD,
  2116. intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
  2117. intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
  2118. }
  2119. /**
  2120. * ath5k_beacon_config - Configure the beacon queues and interrupts
  2121. *
  2122. * @sc: struct ath5k_softc pointer we are operating on
  2123. *
  2124. * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  2125. * interrupts to detect TSF updates only.
  2126. */
  2127. static void
  2128. ath5k_beacon_config(struct ath5k_softc *sc)
  2129. {
  2130. struct ath5k_hw *ah = sc->ah;
  2131. unsigned long flags;
  2132. spin_lock_irqsave(&sc->block, flags);
  2133. sc->bmisscount = 0;
  2134. sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
  2135. if (sc->enable_beacon) {
  2136. /*
  2137. * In IBSS mode we use a self-linked tx descriptor and let the
  2138. * hardware send the beacons automatically. We have to load it
  2139. * only once here.
  2140. * We use the SWBA interrupt only to keep track of the beacon
  2141. * timers in order to detect automatic TSF updates.
  2142. */
  2143. ath5k_beaconq_config(sc);
  2144. sc->imask |= AR5K_INT_SWBA;
  2145. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  2146. if (ath5k_hw_hasveol(ah))
  2147. ath5k_beacon_send(sc);
  2148. } else
  2149. ath5k_beacon_update_timers(sc, -1);
  2150. } else {
  2151. ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
  2152. }
  2153. ath5k_hw_set_imr(ah, sc->imask);
  2154. mmiowb();
  2155. spin_unlock_irqrestore(&sc->block, flags);
  2156. }
  2157. static void ath5k_tasklet_beacon(unsigned long data)
  2158. {
  2159. struct ath5k_softc *sc = (struct ath5k_softc *) data;
  2160. /*
  2161. * Software beacon alert--time to send a beacon.
  2162. *
  2163. * In IBSS mode we use this interrupt just to
  2164. * keep track of the next TBTT (target beacon
  2165. * transmission time) in order to detect wether
  2166. * automatic TSF updates happened.
  2167. */
  2168. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  2169. /* XXX: only if VEOL suppported */
  2170. u64 tsf = ath5k_hw_get_tsf64(sc->ah);
  2171. sc->nexttbtt += sc->bintval;
  2172. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2173. "SWBA nexttbtt: %x hw_tu: %x "
  2174. "TSF: %llx\n",
  2175. sc->nexttbtt,
  2176. TSF_TO_TU(tsf),
  2177. (unsigned long long) tsf);
  2178. } else {
  2179. spin_lock(&sc->block);
  2180. ath5k_beacon_send(sc);
  2181. spin_unlock(&sc->block);
  2182. }
  2183. }
  2184. /********************\
  2185. * Interrupt handling *
  2186. \********************/
  2187. static int
  2188. ath5k_init(struct ath5k_softc *sc)
  2189. {
  2190. struct ath5k_hw *ah = sc->ah;
  2191. int ret, i;
  2192. mutex_lock(&sc->lock);
  2193. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
  2194. /*
  2195. * Stop anything previously setup. This is safe
  2196. * no matter this is the first time through or not.
  2197. */
  2198. ath5k_stop_locked(sc);
  2199. /*
  2200. * The basic interface to setting the hardware in a good
  2201. * state is ``reset''. On return the hardware is known to
  2202. * be powered up and with interrupts disabled. This must
  2203. * be followed by initialization of the appropriate bits
  2204. * and then setup of the interrupt mask.
  2205. */
  2206. sc->curchan = sc->hw->conf.channel;
  2207. sc->curband = &sc->sbands[sc->curchan->band];
  2208. sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
  2209. AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
  2210. AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
  2211. ret = ath5k_reset(sc, NULL);
  2212. if (ret)
  2213. goto done;
  2214. ath5k_rfkill_hw_start(ah);
  2215. /*
  2216. * Reset the key cache since some parts do not reset the
  2217. * contents on initial power up or resume from suspend.
  2218. */
  2219. for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
  2220. ath5k_hw_reset_key(ah, i);
  2221. ath5k_hw_set_ack_bitrate_high(ah, true);
  2222. ret = 0;
  2223. done:
  2224. mmiowb();
  2225. mutex_unlock(&sc->lock);
  2226. return ret;
  2227. }
  2228. static int
  2229. ath5k_stop_locked(struct ath5k_softc *sc)
  2230. {
  2231. struct ath5k_hw *ah = sc->ah;
  2232. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
  2233. test_bit(ATH_STAT_INVALID, sc->status));
  2234. /*
  2235. * Shutdown the hardware and driver:
  2236. * stop output from above
  2237. * disable interrupts
  2238. * turn off timers
  2239. * turn off the radio
  2240. * clear transmit machinery
  2241. * clear receive machinery
  2242. * drain and release tx queues
  2243. * reclaim beacon resources
  2244. * power down hardware
  2245. *
  2246. * Note that some of this work is not possible if the
  2247. * hardware is gone (invalid).
  2248. */
  2249. ieee80211_stop_queues(sc->hw);
  2250. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2251. ath5k_led_off(sc);
  2252. ath5k_hw_set_imr(ah, 0);
  2253. synchronize_irq(sc->pdev->irq);
  2254. }
  2255. ath5k_txq_cleanup(sc);
  2256. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2257. ath5k_rx_stop(sc);
  2258. ath5k_hw_phy_disable(ah);
  2259. } else
  2260. sc->rxlink = NULL;
  2261. return 0;
  2262. }
  2263. /*
  2264. * Stop the device, grabbing the top-level lock to protect
  2265. * against concurrent entry through ath5k_init (which can happen
  2266. * if another thread does a system call and the thread doing the
  2267. * stop is preempted).
  2268. */
  2269. static int
  2270. ath5k_stop_hw(struct ath5k_softc *sc)
  2271. {
  2272. int ret;
  2273. mutex_lock(&sc->lock);
  2274. ret = ath5k_stop_locked(sc);
  2275. if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
  2276. /*
  2277. * Don't set the card in full sleep mode!
  2278. *
  2279. * a) When the device is in this state it must be carefully
  2280. * woken up or references to registers in the PCI clock
  2281. * domain may freeze the bus (and system). This varies
  2282. * by chip and is mostly an issue with newer parts
  2283. * (madwifi sources mentioned srev >= 0x78) that go to
  2284. * sleep more quickly.
  2285. *
  2286. * b) On older chips full sleep results a weird behaviour
  2287. * during wakeup. I tested various cards with srev < 0x78
  2288. * and they don't wake up after module reload, a second
  2289. * module reload is needed to bring the card up again.
  2290. *
  2291. * Until we figure out what's going on don't enable
  2292. * full chip reset on any chip (this is what Legacy HAL
  2293. * and Sam's HAL do anyway). Instead Perform a full reset
  2294. * on the device (same as initial state after attach) and
  2295. * leave it idle (keep MAC/BB on warm reset) */
  2296. ret = ath5k_hw_on_hold(sc->ah);
  2297. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2298. "putting device to sleep\n");
  2299. }
  2300. ath5k_txbuf_free_skb(sc, sc->bbuf);
  2301. mmiowb();
  2302. mutex_unlock(&sc->lock);
  2303. tasklet_kill(&sc->rxtq);
  2304. tasklet_kill(&sc->txtq);
  2305. tasklet_kill(&sc->restq);
  2306. tasklet_kill(&sc->calib);
  2307. tasklet_kill(&sc->beacontq);
  2308. tasklet_kill(&sc->ani_tasklet);
  2309. ath5k_rfkill_hw_stop(sc->ah);
  2310. return ret;
  2311. }
  2312. static void
  2313. ath5k_intr_calibration_poll(struct ath5k_hw *ah)
  2314. {
  2315. if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
  2316. !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
  2317. /* run ANI only when full calibration is not active */
  2318. ah->ah_cal_next_ani = jiffies +
  2319. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
  2320. tasklet_schedule(&ah->ah_sc->ani_tasklet);
  2321. } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
  2322. ah->ah_cal_next_full = jiffies +
  2323. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
  2324. tasklet_schedule(&ah->ah_sc->calib);
  2325. }
  2326. /* we could use SWI to generate enough interrupts to meet our
  2327. * calibration interval requirements, if necessary:
  2328. * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
  2329. }
  2330. static irqreturn_t
  2331. ath5k_intr(int irq, void *dev_id)
  2332. {
  2333. struct ath5k_softc *sc = dev_id;
  2334. struct ath5k_hw *ah = sc->ah;
  2335. enum ath5k_int status;
  2336. unsigned int counter = 1000;
  2337. if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
  2338. !ath5k_hw_is_intr_pending(ah)))
  2339. return IRQ_NONE;
  2340. do {
  2341. ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
  2342. ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
  2343. status, sc->imask);
  2344. if (unlikely(status & AR5K_INT_FATAL)) {
  2345. /*
  2346. * Fatal errors are unrecoverable.
  2347. * Typically these are caused by DMA errors.
  2348. */
  2349. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2350. "fatal int, resetting\n");
  2351. tasklet_schedule(&sc->restq);
  2352. } else if (unlikely(status & AR5K_INT_RXORN)) {
  2353. /*
  2354. * Receive buffers are full. Either the bus is busy or
  2355. * the CPU is not fast enough to process all received
  2356. * frames.
  2357. * Older chipsets need a reset to come out of this
  2358. * condition, but we treat it as RX for newer chips.
  2359. * We don't know exactly which versions need a reset -
  2360. * this guess is copied from the HAL.
  2361. */
  2362. sc->stats.rxorn_intr++;
  2363. if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
  2364. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2365. "rx overrun, resetting\n");
  2366. tasklet_schedule(&sc->restq);
  2367. }
  2368. else
  2369. tasklet_schedule(&sc->rxtq);
  2370. } else {
  2371. if (status & AR5K_INT_SWBA) {
  2372. tasklet_hi_schedule(&sc->beacontq);
  2373. }
  2374. if (status & AR5K_INT_RXEOL) {
  2375. /*
  2376. * NB: the hardware should re-read the link when
  2377. * RXE bit is written, but it doesn't work at
  2378. * least on older hardware revs.
  2379. */
  2380. sc->rxlink = NULL;
  2381. }
  2382. if (status & AR5K_INT_TXURN) {
  2383. /* bump tx trigger level */
  2384. ath5k_hw_update_tx_triglevel(ah, true);
  2385. }
  2386. if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
  2387. tasklet_schedule(&sc->rxtq);
  2388. if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
  2389. | AR5K_INT_TXERR | AR5K_INT_TXEOL))
  2390. tasklet_schedule(&sc->txtq);
  2391. if (status & AR5K_INT_BMISS) {
  2392. /* TODO */
  2393. }
  2394. if (status & AR5K_INT_MIB) {
  2395. sc->stats.mib_intr++;
  2396. ath5k_hw_update_mib_counters(ah);
  2397. ath5k_ani_mib_intr(ah);
  2398. }
  2399. if (status & AR5K_INT_GPIO)
  2400. tasklet_schedule(&sc->rf_kill.toggleq);
  2401. }
  2402. } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
  2403. if (unlikely(!counter))
  2404. ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
  2405. ath5k_intr_calibration_poll(ah);
  2406. return IRQ_HANDLED;
  2407. }
  2408. static void
  2409. ath5k_tasklet_reset(unsigned long data)
  2410. {
  2411. struct ath5k_softc *sc = (void *)data;
  2412. ath5k_reset(sc, sc->curchan);
  2413. }
  2414. /*
  2415. * Periodically recalibrate the PHY to account
  2416. * for temperature/environment changes.
  2417. */
  2418. static void
  2419. ath5k_tasklet_calibrate(unsigned long data)
  2420. {
  2421. struct ath5k_softc *sc = (void *)data;
  2422. struct ath5k_hw *ah = sc->ah;
  2423. /* Only full calibration for now */
  2424. ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
  2425. ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
  2426. ieee80211_frequency_to_channel(sc->curchan->center_freq),
  2427. sc->curchan->hw_value);
  2428. if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
  2429. /*
  2430. * Rfgain is out of bounds, reset the chip
  2431. * to load new gain values.
  2432. */
  2433. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
  2434. ath5k_reset(sc, sc->curchan);
  2435. }
  2436. if (ath5k_hw_phy_calibrate(ah, sc->curchan))
  2437. ATH5K_ERR(sc, "calibration of channel %u failed\n",
  2438. ieee80211_frequency_to_channel(
  2439. sc->curchan->center_freq));
  2440. /* Noise floor calibration interrupts rx/tx path while I/Q calibration
  2441. * doesn't. We stop the queues so that calibration doesn't interfere
  2442. * with TX and don't run it as often */
  2443. if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
  2444. ah->ah_cal_next_nf = jiffies +
  2445. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
  2446. ieee80211_stop_queues(sc->hw);
  2447. ath5k_hw_update_noise_floor(ah);
  2448. ieee80211_wake_queues(sc->hw);
  2449. }
  2450. ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
  2451. }
  2452. static void
  2453. ath5k_tasklet_ani(unsigned long data)
  2454. {
  2455. struct ath5k_softc *sc = (void *)data;
  2456. struct ath5k_hw *ah = sc->ah;
  2457. ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
  2458. ath5k_ani_calibration(ah);
  2459. ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
  2460. }
  2461. /********************\
  2462. * Mac80211 functions *
  2463. \********************/
  2464. static int
  2465. ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2466. {
  2467. struct ath5k_softc *sc = hw->priv;
  2468. return ath5k_tx_queue(hw, skb, sc->txq);
  2469. }
  2470. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  2471. struct ath5k_txq *txq)
  2472. {
  2473. struct ath5k_softc *sc = hw->priv;
  2474. struct ath5k_buf *bf;
  2475. unsigned long flags;
  2476. int padsize;
  2477. ath5k_debug_dump_skb(sc, skb, "TX ", 1);
  2478. if (sc->opmode == NL80211_IFTYPE_MONITOR)
  2479. ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
  2480. /*
  2481. * the hardware expects the header padded to 4 byte boundaries
  2482. * if this is not the case we add the padding after the header
  2483. */
  2484. padsize = ath5k_add_padding(skb);
  2485. if (padsize < 0) {
  2486. ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
  2487. " headroom to pad");
  2488. goto drop_packet;
  2489. }
  2490. spin_lock_irqsave(&sc->txbuflock, flags);
  2491. if (list_empty(&sc->txbuf)) {
  2492. ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
  2493. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2494. ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
  2495. goto drop_packet;
  2496. }
  2497. bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
  2498. list_del(&bf->list);
  2499. sc->txbuf_len--;
  2500. if (list_empty(&sc->txbuf))
  2501. ieee80211_stop_queues(hw);
  2502. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2503. bf->skb = skb;
  2504. if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
  2505. bf->skb = NULL;
  2506. spin_lock_irqsave(&sc->txbuflock, flags);
  2507. list_add_tail(&bf->list, &sc->txbuf);
  2508. sc->txbuf_len++;
  2509. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2510. goto drop_packet;
  2511. }
  2512. return NETDEV_TX_OK;
  2513. drop_packet:
  2514. dev_kfree_skb_any(skb);
  2515. return NETDEV_TX_OK;
  2516. }
  2517. /*
  2518. * Reset the hardware. If chan is not NULL, then also pause rx/tx
  2519. * and change to the given channel.
  2520. */
  2521. static int
  2522. ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  2523. {
  2524. struct ath5k_hw *ah = sc->ah;
  2525. int ret;
  2526. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
  2527. if (chan) {
  2528. ath5k_hw_set_imr(ah, 0);
  2529. ath5k_txq_cleanup(sc);
  2530. ath5k_rx_stop(sc);
  2531. sc->curchan = chan;
  2532. sc->curband = &sc->sbands[chan->band];
  2533. }
  2534. ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
  2535. if (ret) {
  2536. ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
  2537. goto err;
  2538. }
  2539. ret = ath5k_rx_start(sc);
  2540. if (ret) {
  2541. ATH5K_ERR(sc, "can't start recv logic\n");
  2542. goto err;
  2543. }
  2544. ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
  2545. ah->ah_cal_next_full = jiffies;
  2546. ah->ah_cal_next_ani = jiffies;
  2547. ah->ah_cal_next_nf = jiffies;
  2548. /*
  2549. * Change channels and update the h/w rate map if we're switching;
  2550. * e.g. 11a to 11b/g.
  2551. *
  2552. * We may be doing a reset in response to an ioctl that changes the
  2553. * channel so update any state that might change as a result.
  2554. *
  2555. * XXX needed?
  2556. */
  2557. /* ath5k_chan_change(sc, c); */
  2558. ath5k_beacon_config(sc);
  2559. /* intrs are enabled by ath5k_beacon_config */
  2560. ieee80211_wake_queues(sc->hw);
  2561. return 0;
  2562. err:
  2563. return ret;
  2564. }
  2565. static int ath5k_start(struct ieee80211_hw *hw)
  2566. {
  2567. return ath5k_init(hw->priv);
  2568. }
  2569. static void ath5k_stop(struct ieee80211_hw *hw)
  2570. {
  2571. ath5k_stop_hw(hw->priv);
  2572. }
  2573. static int ath5k_add_interface(struct ieee80211_hw *hw,
  2574. struct ieee80211_vif *vif)
  2575. {
  2576. struct ath5k_softc *sc = hw->priv;
  2577. int ret;
  2578. mutex_lock(&sc->lock);
  2579. if (sc->vif) {
  2580. ret = 0;
  2581. goto end;
  2582. }
  2583. sc->vif = vif;
  2584. switch (vif->type) {
  2585. case NL80211_IFTYPE_AP:
  2586. case NL80211_IFTYPE_STATION:
  2587. case NL80211_IFTYPE_ADHOC:
  2588. case NL80211_IFTYPE_MESH_POINT:
  2589. case NL80211_IFTYPE_MONITOR:
  2590. sc->opmode = vif->type;
  2591. break;
  2592. default:
  2593. ret = -EOPNOTSUPP;
  2594. goto end;
  2595. }
  2596. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
  2597. ath5k_hw_set_lladdr(sc->ah, vif->addr);
  2598. ath5k_mode_setup(sc);
  2599. ret = 0;
  2600. end:
  2601. mutex_unlock(&sc->lock);
  2602. return ret;
  2603. }
  2604. static void
  2605. ath5k_remove_interface(struct ieee80211_hw *hw,
  2606. struct ieee80211_vif *vif)
  2607. {
  2608. struct ath5k_softc *sc = hw->priv;
  2609. u8 mac[ETH_ALEN] = {};
  2610. mutex_lock(&sc->lock);
  2611. if (sc->vif != vif)
  2612. goto end;
  2613. ath5k_hw_set_lladdr(sc->ah, mac);
  2614. sc->vif = NULL;
  2615. end:
  2616. mutex_unlock(&sc->lock);
  2617. }
  2618. /*
  2619. * TODO: Phy disable/diversity etc
  2620. */
  2621. static int
  2622. ath5k_config(struct ieee80211_hw *hw, u32 changed)
  2623. {
  2624. struct ath5k_softc *sc = hw->priv;
  2625. struct ath5k_hw *ah = sc->ah;
  2626. struct ieee80211_conf *conf = &hw->conf;
  2627. int ret = 0;
  2628. mutex_lock(&sc->lock);
  2629. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  2630. ret = ath5k_chan_set(sc, conf->channel);
  2631. if (ret < 0)
  2632. goto unlock;
  2633. }
  2634. if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
  2635. (sc->power_level != conf->power_level)) {
  2636. sc->power_level = conf->power_level;
  2637. /* Half dB steps */
  2638. ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
  2639. }
  2640. /* TODO:
  2641. * 1) Move this on config_interface and handle each case
  2642. * separately eg. when we have only one STA vif, use
  2643. * AR5K_ANTMODE_SINGLE_AP
  2644. *
  2645. * 2) Allow the user to change antenna mode eg. when only
  2646. * one antenna is present
  2647. *
  2648. * 3) Allow the user to set default/tx antenna when possible
  2649. *
  2650. * 4) Default mode should handle 90% of the cases, together
  2651. * with fixed a/b and single AP modes we should be able to
  2652. * handle 99%. Sectored modes are extreme cases and i still
  2653. * haven't found a usage for them. If we decide to support them,
  2654. * then we must allow the user to set how many tx antennas we
  2655. * have available
  2656. */
  2657. ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
  2658. unlock:
  2659. mutex_unlock(&sc->lock);
  2660. return ret;
  2661. }
  2662. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  2663. struct netdev_hw_addr_list *mc_list)
  2664. {
  2665. u32 mfilt[2], val;
  2666. u8 pos;
  2667. struct netdev_hw_addr *ha;
  2668. mfilt[0] = 0;
  2669. mfilt[1] = 1;
  2670. netdev_hw_addr_list_for_each(ha, mc_list) {
  2671. /* calculate XOR of eight 6-bit values */
  2672. val = get_unaligned_le32(ha->addr + 0);
  2673. pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2674. val = get_unaligned_le32(ha->addr + 3);
  2675. pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2676. pos &= 0x3f;
  2677. mfilt[pos / 32] |= (1 << (pos % 32));
  2678. /* XXX: we might be able to just do this instead,
  2679. * but not sure, needs testing, if we do use this we'd
  2680. * neet to inform below to not reset the mcast */
  2681. /* ath5k_hw_set_mcast_filterindex(ah,
  2682. * ha->addr[5]); */
  2683. }
  2684. return ((u64)(mfilt[1]) << 32) | mfilt[0];
  2685. }
  2686. #define SUPPORTED_FIF_FLAGS \
  2687. FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
  2688. FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
  2689. FIF_BCN_PRBRESP_PROMISC
  2690. /*
  2691. * o always accept unicast, broadcast, and multicast traffic
  2692. * o multicast traffic for all BSSIDs will be enabled if mac80211
  2693. * says it should be
  2694. * o maintain current state of phy ofdm or phy cck error reception.
  2695. * If the hardware detects any of these type of errors then
  2696. * ath5k_hw_get_rx_filter() will pass to us the respective
  2697. * hardware filters to be able to receive these type of frames.
  2698. * o probe request frames are accepted only when operating in
  2699. * hostap, adhoc, or monitor modes
  2700. * o enable promiscuous mode according to the interface state
  2701. * o accept beacons:
  2702. * - when operating in adhoc mode so the 802.11 layer creates
  2703. * node table entries for peers,
  2704. * - when operating in station mode for collecting rssi data when
  2705. * the station is otherwise quiet, or
  2706. * - when scanning
  2707. */
  2708. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  2709. unsigned int changed_flags,
  2710. unsigned int *new_flags,
  2711. u64 multicast)
  2712. {
  2713. struct ath5k_softc *sc = hw->priv;
  2714. struct ath5k_hw *ah = sc->ah;
  2715. u32 mfilt[2], rfilt;
  2716. mutex_lock(&sc->lock);
  2717. mfilt[0] = multicast;
  2718. mfilt[1] = multicast >> 32;
  2719. /* Only deal with supported flags */
  2720. changed_flags &= SUPPORTED_FIF_FLAGS;
  2721. *new_flags &= SUPPORTED_FIF_FLAGS;
  2722. /* If HW detects any phy or radar errors, leave those filters on.
  2723. * Also, always enable Unicast, Broadcasts and Multicast
  2724. * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
  2725. rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
  2726. (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
  2727. AR5K_RX_FILTER_MCAST);
  2728. if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  2729. if (*new_flags & FIF_PROMISC_IN_BSS) {
  2730. __set_bit(ATH_STAT_PROMISC, sc->status);
  2731. } else {
  2732. __clear_bit(ATH_STAT_PROMISC, sc->status);
  2733. }
  2734. }
  2735. if (test_bit(ATH_STAT_PROMISC, sc->status))
  2736. rfilt |= AR5K_RX_FILTER_PROM;
  2737. /* Note, AR5K_RX_FILTER_MCAST is already enabled */
  2738. if (*new_flags & FIF_ALLMULTI) {
  2739. mfilt[0] = ~0;
  2740. mfilt[1] = ~0;
  2741. }
  2742. /* This is the best we can do */
  2743. if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
  2744. rfilt |= AR5K_RX_FILTER_PHYERR;
  2745. /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
  2746. * and probes for any BSSID, this needs testing */
  2747. if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
  2748. rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
  2749. /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
  2750. * set we should only pass on control frames for this
  2751. * station. This needs testing. I believe right now this
  2752. * enables *all* control frames, which is OK.. but
  2753. * but we should see if we can improve on granularity */
  2754. if (*new_flags & FIF_CONTROL)
  2755. rfilt |= AR5K_RX_FILTER_CONTROL;
  2756. /* Additional settings per mode -- this is per ath5k */
  2757. /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
  2758. switch (sc->opmode) {
  2759. case NL80211_IFTYPE_MESH_POINT:
  2760. case NL80211_IFTYPE_MONITOR:
  2761. rfilt |= AR5K_RX_FILTER_CONTROL |
  2762. AR5K_RX_FILTER_BEACON |
  2763. AR5K_RX_FILTER_PROBEREQ |
  2764. AR5K_RX_FILTER_PROM;
  2765. break;
  2766. case NL80211_IFTYPE_AP:
  2767. case NL80211_IFTYPE_ADHOC:
  2768. rfilt |= AR5K_RX_FILTER_PROBEREQ |
  2769. AR5K_RX_FILTER_BEACON;
  2770. break;
  2771. case NL80211_IFTYPE_STATION:
  2772. if (sc->assoc)
  2773. rfilt |= AR5K_RX_FILTER_BEACON;
  2774. default:
  2775. break;
  2776. }
  2777. /* Set filters */
  2778. ath5k_hw_set_rx_filter(ah, rfilt);
  2779. /* Set multicast bits */
  2780. ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
  2781. /* Set the cached hw filter flags, this will alter actually
  2782. * be set in HW */
  2783. sc->filter_flags = rfilt;
  2784. mutex_unlock(&sc->lock);
  2785. }
  2786. static int
  2787. ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2788. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  2789. struct ieee80211_key_conf *key)
  2790. {
  2791. struct ath5k_softc *sc = hw->priv;
  2792. struct ath5k_hw *ah = sc->ah;
  2793. struct ath_common *common = ath5k_hw_common(ah);
  2794. int ret = 0;
  2795. if (modparam_nohwcrypt)
  2796. return -EOPNOTSUPP;
  2797. if (sc->opmode == NL80211_IFTYPE_AP)
  2798. return -EOPNOTSUPP;
  2799. switch (key->alg) {
  2800. case ALG_WEP:
  2801. case ALG_TKIP:
  2802. break;
  2803. case ALG_CCMP:
  2804. if (sc->ah->ah_aes_support)
  2805. break;
  2806. return -EOPNOTSUPP;
  2807. default:
  2808. WARN_ON(1);
  2809. return -EINVAL;
  2810. }
  2811. mutex_lock(&sc->lock);
  2812. switch (cmd) {
  2813. case SET_KEY:
  2814. ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
  2815. sta ? sta->addr : NULL);
  2816. if (ret) {
  2817. ATH5K_ERR(sc, "can't set the key\n");
  2818. goto unlock;
  2819. }
  2820. __set_bit(key->keyidx, common->keymap);
  2821. key->hw_key_idx = key->keyidx;
  2822. key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
  2823. IEEE80211_KEY_FLAG_GENERATE_MMIC);
  2824. break;
  2825. case DISABLE_KEY:
  2826. ath5k_hw_reset_key(sc->ah, key->keyidx);
  2827. __clear_bit(key->keyidx, common->keymap);
  2828. break;
  2829. default:
  2830. ret = -EINVAL;
  2831. goto unlock;
  2832. }
  2833. unlock:
  2834. mmiowb();
  2835. mutex_unlock(&sc->lock);
  2836. return ret;
  2837. }
  2838. static int
  2839. ath5k_get_stats(struct ieee80211_hw *hw,
  2840. struct ieee80211_low_level_stats *stats)
  2841. {
  2842. struct ath5k_softc *sc = hw->priv;
  2843. /* Force update */
  2844. ath5k_hw_update_mib_counters(sc->ah);
  2845. stats->dot11ACKFailureCount = sc->stats.ack_fail;
  2846. stats->dot11RTSFailureCount = sc->stats.rts_fail;
  2847. stats->dot11RTSSuccessCount = sc->stats.rts_ok;
  2848. stats->dot11FCSErrorCount = sc->stats.fcs_error;
  2849. return 0;
  2850. }
  2851. static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
  2852. struct survey_info *survey)
  2853. {
  2854. struct ath5k_softc *sc = hw->priv;
  2855. struct ieee80211_conf *conf = &hw->conf;
  2856. if (idx != 0)
  2857. return -ENOENT;
  2858. survey->channel = conf->channel;
  2859. survey->filled = SURVEY_INFO_NOISE_DBM;
  2860. survey->noise = sc->ah->ah_noise_floor;
  2861. return 0;
  2862. }
  2863. static u64
  2864. ath5k_get_tsf(struct ieee80211_hw *hw)
  2865. {
  2866. struct ath5k_softc *sc = hw->priv;
  2867. return ath5k_hw_get_tsf64(sc->ah);
  2868. }
  2869. static void
  2870. ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  2871. {
  2872. struct ath5k_softc *sc = hw->priv;
  2873. ath5k_hw_set_tsf64(sc->ah, tsf);
  2874. }
  2875. static void
  2876. ath5k_reset_tsf(struct ieee80211_hw *hw)
  2877. {
  2878. struct ath5k_softc *sc = hw->priv;
  2879. /*
  2880. * in IBSS mode we need to update the beacon timers too.
  2881. * this will also reset the TSF if we call it with 0
  2882. */
  2883. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  2884. ath5k_beacon_update_timers(sc, 0);
  2885. else
  2886. ath5k_hw_reset_tsf(sc->ah);
  2887. }
  2888. /*
  2889. * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
  2890. * this is called only once at config_bss time, for AP we do it every
  2891. * SWBA interrupt so that the TIM will reflect buffered frames.
  2892. *
  2893. * Called with the beacon lock.
  2894. */
  2895. static int
  2896. ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  2897. {
  2898. int ret;
  2899. struct ath5k_softc *sc = hw->priv;
  2900. struct sk_buff *skb;
  2901. if (WARN_ON(!vif)) {
  2902. ret = -EINVAL;
  2903. goto out;
  2904. }
  2905. skb = ieee80211_beacon_get(hw, vif);
  2906. if (!skb) {
  2907. ret = -ENOMEM;
  2908. goto out;
  2909. }
  2910. ath5k_debug_dump_skb(sc, skb, "BC ", 1);
  2911. ath5k_txbuf_free_skb(sc, sc->bbuf);
  2912. sc->bbuf->skb = skb;
  2913. ret = ath5k_beacon_setup(sc, sc->bbuf);
  2914. if (ret)
  2915. sc->bbuf->skb = NULL;
  2916. out:
  2917. return ret;
  2918. }
  2919. static void
  2920. set_beacon_filter(struct ieee80211_hw *hw, bool enable)
  2921. {
  2922. struct ath5k_softc *sc = hw->priv;
  2923. struct ath5k_hw *ah = sc->ah;
  2924. u32 rfilt;
  2925. rfilt = ath5k_hw_get_rx_filter(ah);
  2926. if (enable)
  2927. rfilt |= AR5K_RX_FILTER_BEACON;
  2928. else
  2929. rfilt &= ~AR5K_RX_FILTER_BEACON;
  2930. ath5k_hw_set_rx_filter(ah, rfilt);
  2931. sc->filter_flags = rfilt;
  2932. }
  2933. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  2934. struct ieee80211_vif *vif,
  2935. struct ieee80211_bss_conf *bss_conf,
  2936. u32 changes)
  2937. {
  2938. struct ath5k_softc *sc = hw->priv;
  2939. struct ath5k_hw *ah = sc->ah;
  2940. struct ath_common *common = ath5k_hw_common(ah);
  2941. unsigned long flags;
  2942. mutex_lock(&sc->lock);
  2943. if (WARN_ON(sc->vif != vif))
  2944. goto unlock;
  2945. if (changes & BSS_CHANGED_BSSID) {
  2946. /* Cache for later use during resets */
  2947. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  2948. common->curaid = 0;
  2949. ath5k_hw_set_associd(ah);
  2950. mmiowb();
  2951. }
  2952. if (changes & BSS_CHANGED_BEACON_INT)
  2953. sc->bintval = bss_conf->beacon_int;
  2954. if (changes & BSS_CHANGED_ASSOC) {
  2955. sc->assoc = bss_conf->assoc;
  2956. if (sc->opmode == NL80211_IFTYPE_STATION)
  2957. set_beacon_filter(hw, sc->assoc);
  2958. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  2959. AR5K_LED_ASSOC : AR5K_LED_INIT);
  2960. if (bss_conf->assoc) {
  2961. ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
  2962. "Bss Info ASSOC %d, bssid: %pM\n",
  2963. bss_conf->aid, common->curbssid);
  2964. common->curaid = bss_conf->aid;
  2965. ath5k_hw_set_associd(ah);
  2966. /* Once ANI is available you would start it here */
  2967. }
  2968. }
  2969. if (changes & BSS_CHANGED_BEACON) {
  2970. spin_lock_irqsave(&sc->block, flags);
  2971. ath5k_beacon_update(hw, vif);
  2972. spin_unlock_irqrestore(&sc->block, flags);
  2973. }
  2974. if (changes & BSS_CHANGED_BEACON_ENABLED)
  2975. sc->enable_beacon = bss_conf->enable_beacon;
  2976. if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
  2977. BSS_CHANGED_BEACON_INT))
  2978. ath5k_beacon_config(sc);
  2979. unlock:
  2980. mutex_unlock(&sc->lock);
  2981. }
  2982. static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
  2983. {
  2984. struct ath5k_softc *sc = hw->priv;
  2985. if (!sc->assoc)
  2986. ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
  2987. }
  2988. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
  2989. {
  2990. struct ath5k_softc *sc = hw->priv;
  2991. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  2992. AR5K_LED_ASSOC : AR5K_LED_INIT);
  2993. }
  2994. /**
  2995. * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
  2996. *
  2997. * @hw: struct ieee80211_hw pointer
  2998. * @coverage_class: IEEE 802.11 coverage class number
  2999. *
  3000. * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
  3001. * coverage class. The values are persistent, they are restored after device
  3002. * reset.
  3003. */
  3004. static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  3005. {
  3006. struct ath5k_softc *sc = hw->priv;
  3007. mutex_lock(&sc->lock);
  3008. ath5k_hw_set_coverage_class(sc->ah, coverage_class);
  3009. mutex_unlock(&sc->lock);
  3010. }