vmxnet3_drv.c 85 KB

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  1. /*
  2. * Linux driver for VMware's vmxnet3 ethernet NIC.
  3. *
  4. * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; version 2 of the License and no later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more
  14. * details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * The full GNU General Public License is included in this distribution in
  21. * the file called "COPYING".
  22. *
  23. * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
  24. *
  25. */
  26. #include <net/ip6_checksum.h>
  27. #include "vmxnet3_int.h"
  28. char vmxnet3_driver_name[] = "vmxnet3";
  29. #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
  30. /*
  31. * PCI Device ID Table
  32. * Last entry must be all 0s
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
  35. {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
  36. {0}
  37. };
  38. MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
  39. static atomic_t devices_found;
  40. #define VMXNET3_MAX_DEVICES 10
  41. static int enable_mq = 1;
  42. static int irq_share_mode;
  43. static void
  44. vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
  45. /*
  46. * Enable/Disable the given intr
  47. */
  48. static void
  49. vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  50. {
  51. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
  52. }
  53. static void
  54. vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  55. {
  56. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
  57. }
  58. /*
  59. * Enable/Disable all intrs used by the device
  60. */
  61. static void
  62. vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
  63. {
  64. int i;
  65. for (i = 0; i < adapter->intr.num_intrs; i++)
  66. vmxnet3_enable_intr(adapter, i);
  67. adapter->shared->devRead.intrConf.intrCtrl &=
  68. cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
  69. }
  70. static void
  71. vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
  72. {
  73. int i;
  74. adapter->shared->devRead.intrConf.intrCtrl |=
  75. cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  76. for (i = 0; i < adapter->intr.num_intrs; i++)
  77. vmxnet3_disable_intr(adapter, i);
  78. }
  79. static void
  80. vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
  81. {
  82. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
  83. }
  84. static bool
  85. vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  86. {
  87. return tq->stopped;
  88. }
  89. static void
  90. vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  91. {
  92. tq->stopped = false;
  93. netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
  94. }
  95. static void
  96. vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  97. {
  98. tq->stopped = false;
  99. netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  100. }
  101. static void
  102. vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  103. {
  104. tq->stopped = true;
  105. tq->num_stop++;
  106. netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  107. }
  108. /*
  109. * Check the link state. This may start or stop the tx queue.
  110. */
  111. static void
  112. vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
  113. {
  114. u32 ret;
  115. int i;
  116. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
  117. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  118. adapter->link_speed = ret >> 16;
  119. if (ret & 1) { /* Link is up. */
  120. printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
  121. adapter->netdev->name, adapter->link_speed);
  122. if (!netif_carrier_ok(adapter->netdev))
  123. netif_carrier_on(adapter->netdev);
  124. if (affectTxQueue) {
  125. for (i = 0; i < adapter->num_tx_queues; i++)
  126. vmxnet3_tq_start(&adapter->tx_queue[i],
  127. adapter);
  128. }
  129. } else {
  130. printk(KERN_INFO "%s: NIC Link is Down\n",
  131. adapter->netdev->name);
  132. if (netif_carrier_ok(adapter->netdev))
  133. netif_carrier_off(adapter->netdev);
  134. if (affectTxQueue) {
  135. for (i = 0; i < adapter->num_tx_queues; i++)
  136. vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
  137. }
  138. }
  139. }
  140. static void
  141. vmxnet3_process_events(struct vmxnet3_adapter *adapter)
  142. {
  143. int i;
  144. u32 events = le32_to_cpu(adapter->shared->ecr);
  145. if (!events)
  146. return;
  147. vmxnet3_ack_events(adapter, events);
  148. /* Check if link state has changed */
  149. if (events & VMXNET3_ECR_LINK)
  150. vmxnet3_check_link(adapter, true);
  151. /* Check if there is an error on xmit/recv queues */
  152. if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
  153. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  154. VMXNET3_CMD_GET_QUEUE_STATUS);
  155. for (i = 0; i < adapter->num_tx_queues; i++)
  156. if (adapter->tqd_start[i].status.stopped)
  157. dev_err(&adapter->netdev->dev,
  158. "%s: tq[%d] error 0x%x\n",
  159. adapter->netdev->name, i, le32_to_cpu(
  160. adapter->tqd_start[i].status.error));
  161. for (i = 0; i < adapter->num_rx_queues; i++)
  162. if (adapter->rqd_start[i].status.stopped)
  163. dev_err(&adapter->netdev->dev,
  164. "%s: rq[%d] error 0x%x\n",
  165. adapter->netdev->name, i,
  166. adapter->rqd_start[i].status.error);
  167. schedule_work(&adapter->work);
  168. }
  169. }
  170. #ifdef __BIG_ENDIAN_BITFIELD
  171. /*
  172. * The device expects the bitfields in shared structures to be written in
  173. * little endian. When CPU is big endian, the following routines are used to
  174. * correctly read and write into ABI.
  175. * The general technique used here is : double word bitfields are defined in
  176. * opposite order for big endian architecture. Then before reading them in
  177. * driver the complete double word is translated using le32_to_cpu. Similarly
  178. * After the driver writes into bitfields, cpu_to_le32 is used to translate the
  179. * double words into required format.
  180. * In order to avoid touching bits in shared structure more than once, temporary
  181. * descriptors are used. These are passed as srcDesc to following functions.
  182. */
  183. static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
  184. struct Vmxnet3_RxDesc *dstDesc)
  185. {
  186. u32 *src = (u32 *)srcDesc + 2;
  187. u32 *dst = (u32 *)dstDesc + 2;
  188. dstDesc->addr = le64_to_cpu(srcDesc->addr);
  189. *dst = le32_to_cpu(*src);
  190. dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
  191. }
  192. static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
  193. struct Vmxnet3_TxDesc *dstDesc)
  194. {
  195. int i;
  196. u32 *src = (u32 *)(srcDesc + 1);
  197. u32 *dst = (u32 *)(dstDesc + 1);
  198. /* Working backwards so that the gen bit is set at the end. */
  199. for (i = 2; i > 0; i--) {
  200. src--;
  201. dst--;
  202. *dst = cpu_to_le32(*src);
  203. }
  204. }
  205. static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
  206. struct Vmxnet3_RxCompDesc *dstDesc)
  207. {
  208. int i = 0;
  209. u32 *src = (u32 *)srcDesc;
  210. u32 *dst = (u32 *)dstDesc;
  211. for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
  212. *dst = le32_to_cpu(*src);
  213. src++;
  214. dst++;
  215. }
  216. }
  217. /* Used to read bitfield values from double words. */
  218. static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
  219. {
  220. u32 temp = le32_to_cpu(*bitfield);
  221. u32 mask = ((1 << size) - 1) << pos;
  222. temp &= mask;
  223. temp >>= pos;
  224. return temp;
  225. }
  226. #endif /* __BIG_ENDIAN_BITFIELD */
  227. #ifdef __BIG_ENDIAN_BITFIELD
  228. # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
  229. txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
  230. VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
  231. # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
  232. txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
  233. VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
  234. # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
  235. VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
  236. VMXNET3_TCD_GEN_SIZE)
  237. # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
  238. VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
  239. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
  240. (dstrcd) = (tmp); \
  241. vmxnet3_RxCompToCPU((rcd), (tmp)); \
  242. } while (0)
  243. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
  244. (dstrxd) = (tmp); \
  245. vmxnet3_RxDescToCPU((rxd), (tmp)); \
  246. } while (0)
  247. #else
  248. # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
  249. # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
  250. # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
  251. # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
  252. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
  253. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
  254. #endif /* __BIG_ENDIAN_BITFIELD */
  255. static void
  256. vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
  257. struct pci_dev *pdev)
  258. {
  259. if (tbi->map_type == VMXNET3_MAP_SINGLE)
  260. pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
  261. PCI_DMA_TODEVICE);
  262. else if (tbi->map_type == VMXNET3_MAP_PAGE)
  263. pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
  264. PCI_DMA_TODEVICE);
  265. else
  266. BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
  267. tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
  268. }
  269. static int
  270. vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
  271. struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
  272. {
  273. struct sk_buff *skb;
  274. int entries = 0;
  275. /* no out of order completion */
  276. BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
  277. BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
  278. skb = tq->buf_info[eop_idx].skb;
  279. BUG_ON(skb == NULL);
  280. tq->buf_info[eop_idx].skb = NULL;
  281. VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
  282. while (tq->tx_ring.next2comp != eop_idx) {
  283. vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
  284. pdev);
  285. /* update next2comp w/o tx_lock. Since we are marking more,
  286. * instead of less, tx ring entries avail, the worst case is
  287. * that the tx routine incorrectly re-queues a pkt due to
  288. * insufficient tx ring entries.
  289. */
  290. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  291. entries++;
  292. }
  293. dev_kfree_skb_any(skb);
  294. return entries;
  295. }
  296. static int
  297. vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
  298. struct vmxnet3_adapter *adapter)
  299. {
  300. int completed = 0;
  301. union Vmxnet3_GenericDesc *gdesc;
  302. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  303. while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
  304. completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
  305. &gdesc->tcd), tq, adapter->pdev,
  306. adapter);
  307. vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
  308. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  309. }
  310. if (completed) {
  311. spin_lock(&tq->tx_lock);
  312. if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
  313. vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
  314. VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
  315. netif_carrier_ok(adapter->netdev))) {
  316. vmxnet3_tq_wake(tq, adapter);
  317. }
  318. spin_unlock(&tq->tx_lock);
  319. }
  320. return completed;
  321. }
  322. static void
  323. vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
  324. struct vmxnet3_adapter *adapter)
  325. {
  326. int i;
  327. while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
  328. struct vmxnet3_tx_buf_info *tbi;
  329. union Vmxnet3_GenericDesc *gdesc;
  330. tbi = tq->buf_info + tq->tx_ring.next2comp;
  331. gdesc = tq->tx_ring.base + tq->tx_ring.next2comp;
  332. vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
  333. if (tbi->skb) {
  334. dev_kfree_skb_any(tbi->skb);
  335. tbi->skb = NULL;
  336. }
  337. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  338. }
  339. /* sanity check, verify all buffers are indeed unmapped and freed */
  340. for (i = 0; i < tq->tx_ring.size; i++) {
  341. BUG_ON(tq->buf_info[i].skb != NULL ||
  342. tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
  343. }
  344. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  345. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  346. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  347. tq->comp_ring.next2proc = 0;
  348. }
  349. static void
  350. vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
  351. struct vmxnet3_adapter *adapter)
  352. {
  353. if (tq->tx_ring.base) {
  354. pci_free_consistent(adapter->pdev, tq->tx_ring.size *
  355. sizeof(struct Vmxnet3_TxDesc),
  356. tq->tx_ring.base, tq->tx_ring.basePA);
  357. tq->tx_ring.base = NULL;
  358. }
  359. if (tq->data_ring.base) {
  360. pci_free_consistent(adapter->pdev, tq->data_ring.size *
  361. sizeof(struct Vmxnet3_TxDataDesc),
  362. tq->data_ring.base, tq->data_ring.basePA);
  363. tq->data_ring.base = NULL;
  364. }
  365. if (tq->comp_ring.base) {
  366. pci_free_consistent(adapter->pdev, tq->comp_ring.size *
  367. sizeof(struct Vmxnet3_TxCompDesc),
  368. tq->comp_ring.base, tq->comp_ring.basePA);
  369. tq->comp_ring.base = NULL;
  370. }
  371. kfree(tq->buf_info);
  372. tq->buf_info = NULL;
  373. }
  374. /* Destroy all tx queues */
  375. void
  376. vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
  377. {
  378. int i;
  379. for (i = 0; i < adapter->num_tx_queues; i++)
  380. vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
  381. }
  382. static void
  383. vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
  384. struct vmxnet3_adapter *adapter)
  385. {
  386. int i;
  387. /* reset the tx ring contents to 0 and reset the tx ring states */
  388. memset(tq->tx_ring.base, 0, tq->tx_ring.size *
  389. sizeof(struct Vmxnet3_TxDesc));
  390. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  391. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  392. memset(tq->data_ring.base, 0, tq->data_ring.size *
  393. sizeof(struct Vmxnet3_TxDataDesc));
  394. /* reset the tx comp ring contents to 0 and reset comp ring states */
  395. memset(tq->comp_ring.base, 0, tq->comp_ring.size *
  396. sizeof(struct Vmxnet3_TxCompDesc));
  397. tq->comp_ring.next2proc = 0;
  398. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  399. /* reset the bookkeeping data */
  400. memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
  401. for (i = 0; i < tq->tx_ring.size; i++)
  402. tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
  403. /* stats are not reset */
  404. }
  405. static int
  406. vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
  407. struct vmxnet3_adapter *adapter)
  408. {
  409. BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
  410. tq->comp_ring.base || tq->buf_info);
  411. tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
  412. * sizeof(struct Vmxnet3_TxDesc),
  413. &tq->tx_ring.basePA);
  414. if (!tq->tx_ring.base) {
  415. printk(KERN_ERR "%s: failed to allocate tx ring\n",
  416. adapter->netdev->name);
  417. goto err;
  418. }
  419. tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
  420. tq->data_ring.size *
  421. sizeof(struct Vmxnet3_TxDataDesc),
  422. &tq->data_ring.basePA);
  423. if (!tq->data_ring.base) {
  424. printk(KERN_ERR "%s: failed to allocate data ring\n",
  425. adapter->netdev->name);
  426. goto err;
  427. }
  428. tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
  429. tq->comp_ring.size *
  430. sizeof(struct Vmxnet3_TxCompDesc),
  431. &tq->comp_ring.basePA);
  432. if (!tq->comp_ring.base) {
  433. printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
  434. adapter->netdev->name);
  435. goto err;
  436. }
  437. tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
  438. GFP_KERNEL);
  439. if (!tq->buf_info) {
  440. printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
  441. adapter->netdev->name);
  442. goto err;
  443. }
  444. return 0;
  445. err:
  446. vmxnet3_tq_destroy(tq, adapter);
  447. return -ENOMEM;
  448. }
  449. static void
  450. vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
  451. {
  452. int i;
  453. for (i = 0; i < adapter->num_tx_queues; i++)
  454. vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
  455. }
  456. /*
  457. * starting from ring->next2fill, allocate rx buffers for the given ring
  458. * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
  459. * are allocated or allocation fails
  460. */
  461. static int
  462. vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
  463. int num_to_alloc, struct vmxnet3_adapter *adapter)
  464. {
  465. int num_allocated = 0;
  466. struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
  467. struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
  468. u32 val;
  469. while (num_allocated < num_to_alloc) {
  470. struct vmxnet3_rx_buf_info *rbi;
  471. union Vmxnet3_GenericDesc *gd;
  472. rbi = rbi_base + ring->next2fill;
  473. gd = ring->base + ring->next2fill;
  474. if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
  475. if (rbi->skb == NULL) {
  476. rbi->skb = dev_alloc_skb(rbi->len +
  477. NET_IP_ALIGN);
  478. if (unlikely(rbi->skb == NULL)) {
  479. rq->stats.rx_buf_alloc_failure++;
  480. break;
  481. }
  482. rbi->skb->dev = adapter->netdev;
  483. skb_reserve(rbi->skb, NET_IP_ALIGN);
  484. rbi->dma_addr = pci_map_single(adapter->pdev,
  485. rbi->skb->data, rbi->len,
  486. PCI_DMA_FROMDEVICE);
  487. } else {
  488. /* rx buffer skipped by the device */
  489. }
  490. val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
  491. } else {
  492. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
  493. rbi->len != PAGE_SIZE);
  494. if (rbi->page == NULL) {
  495. rbi->page = alloc_page(GFP_ATOMIC);
  496. if (unlikely(rbi->page == NULL)) {
  497. rq->stats.rx_buf_alloc_failure++;
  498. break;
  499. }
  500. rbi->dma_addr = pci_map_page(adapter->pdev,
  501. rbi->page, 0, PAGE_SIZE,
  502. PCI_DMA_FROMDEVICE);
  503. } else {
  504. /* rx buffers skipped by the device */
  505. }
  506. val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
  507. }
  508. BUG_ON(rbi->dma_addr == 0);
  509. gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
  510. gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT)
  511. | val | rbi->len);
  512. num_allocated++;
  513. vmxnet3_cmd_ring_adv_next2fill(ring);
  514. }
  515. rq->uncommitted[ring_idx] += num_allocated;
  516. dev_dbg(&adapter->netdev->dev,
  517. "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
  518. "%u, uncommited %u\n", num_allocated, ring->next2fill,
  519. ring->next2comp, rq->uncommitted[ring_idx]);
  520. /* so that the device can distinguish a full ring and an empty ring */
  521. BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
  522. return num_allocated;
  523. }
  524. static void
  525. vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
  526. struct vmxnet3_rx_buf_info *rbi)
  527. {
  528. struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
  529. skb_shinfo(skb)->nr_frags;
  530. BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
  531. frag->page = rbi->page;
  532. frag->page_offset = 0;
  533. frag->size = rcd->len;
  534. skb->data_len += frag->size;
  535. skb_shinfo(skb)->nr_frags++;
  536. }
  537. static void
  538. vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
  539. struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
  540. struct vmxnet3_adapter *adapter)
  541. {
  542. u32 dw2, len;
  543. unsigned long buf_offset;
  544. int i;
  545. union Vmxnet3_GenericDesc *gdesc;
  546. struct vmxnet3_tx_buf_info *tbi = NULL;
  547. BUG_ON(ctx->copy_size > skb_headlen(skb));
  548. /* use the previous gen bit for the SOP desc */
  549. dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
  550. ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
  551. gdesc = ctx->sop_txd; /* both loops below can be skipped */
  552. /* no need to map the buffer if headers are copied */
  553. if (ctx->copy_size) {
  554. ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
  555. tq->tx_ring.next2fill *
  556. sizeof(struct Vmxnet3_TxDataDesc));
  557. ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
  558. ctx->sop_txd->dword[3] = 0;
  559. tbi = tq->buf_info + tq->tx_ring.next2fill;
  560. tbi->map_type = VMXNET3_MAP_NONE;
  561. dev_dbg(&adapter->netdev->dev,
  562. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  563. tq->tx_ring.next2fill,
  564. le64_to_cpu(ctx->sop_txd->txd.addr),
  565. ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
  566. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  567. /* use the right gen for non-SOP desc */
  568. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  569. }
  570. /* linear part can use multiple tx desc if it's big */
  571. len = skb_headlen(skb) - ctx->copy_size;
  572. buf_offset = ctx->copy_size;
  573. while (len) {
  574. u32 buf_size;
  575. if (len < VMXNET3_MAX_TX_BUF_SIZE) {
  576. buf_size = len;
  577. dw2 |= len;
  578. } else {
  579. buf_size = VMXNET3_MAX_TX_BUF_SIZE;
  580. /* spec says that for TxDesc.len, 0 == 2^14 */
  581. }
  582. tbi = tq->buf_info + tq->tx_ring.next2fill;
  583. tbi->map_type = VMXNET3_MAP_SINGLE;
  584. tbi->dma_addr = pci_map_single(adapter->pdev,
  585. skb->data + buf_offset, buf_size,
  586. PCI_DMA_TODEVICE);
  587. tbi->len = buf_size;
  588. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  589. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  590. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  591. gdesc->dword[2] = cpu_to_le32(dw2);
  592. gdesc->dword[3] = 0;
  593. dev_dbg(&adapter->netdev->dev,
  594. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  595. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  596. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  597. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  598. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  599. len -= buf_size;
  600. buf_offset += buf_size;
  601. }
  602. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  603. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  604. tbi = tq->buf_info + tq->tx_ring.next2fill;
  605. tbi->map_type = VMXNET3_MAP_PAGE;
  606. tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
  607. frag->page_offset, frag->size,
  608. PCI_DMA_TODEVICE);
  609. tbi->len = frag->size;
  610. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  611. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  612. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  613. gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
  614. gdesc->dword[3] = 0;
  615. dev_dbg(&adapter->netdev->dev,
  616. "txd[%u]: 0x%llu %u %u\n",
  617. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  618. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  619. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  620. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  621. }
  622. ctx->eop_txd = gdesc;
  623. /* set the last buf_info for the pkt */
  624. tbi->skb = skb;
  625. tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
  626. }
  627. /* Init all tx queues */
  628. static void
  629. vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
  630. {
  631. int i;
  632. for (i = 0; i < adapter->num_tx_queues; i++)
  633. vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
  634. }
  635. /*
  636. * parse and copy relevant protocol headers:
  637. * For a tso pkt, relevant headers are L2/3/4 including options
  638. * For a pkt requesting csum offloading, they are L2/3 and may include L4
  639. * if it's a TCP/UDP pkt
  640. *
  641. * Returns:
  642. * -1: error happens during parsing
  643. * 0: protocol headers parsed, but too big to be copied
  644. * 1: protocol headers parsed and copied
  645. *
  646. * Other effects:
  647. * 1. related *ctx fields are updated.
  648. * 2. ctx->copy_size is # of bytes copied
  649. * 3. the portion copied is guaranteed to be in the linear part
  650. *
  651. */
  652. static int
  653. vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  654. struct vmxnet3_tx_ctx *ctx,
  655. struct vmxnet3_adapter *adapter)
  656. {
  657. struct Vmxnet3_TxDataDesc *tdd;
  658. if (ctx->mss) { /* TSO */
  659. ctx->eth_ip_hdr_size = skb_transport_offset(skb);
  660. ctx->l4_hdr_size = ((struct tcphdr *)
  661. skb_transport_header(skb))->doff * 4;
  662. ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
  663. } else {
  664. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  665. ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
  666. if (ctx->ipv4) {
  667. struct iphdr *iph = (struct iphdr *)
  668. skb_network_header(skb);
  669. if (iph->protocol == IPPROTO_TCP)
  670. ctx->l4_hdr_size = ((struct tcphdr *)
  671. skb_transport_header(skb))->doff * 4;
  672. else if (iph->protocol == IPPROTO_UDP)
  673. /*
  674. * Use tcp header size so that bytes to
  675. * be copied are more than required by
  676. * the device.
  677. */
  678. ctx->l4_hdr_size =
  679. sizeof(struct tcphdr);
  680. else
  681. ctx->l4_hdr_size = 0;
  682. } else {
  683. /* for simplicity, don't copy L4 headers */
  684. ctx->l4_hdr_size = 0;
  685. }
  686. ctx->copy_size = ctx->eth_ip_hdr_size +
  687. ctx->l4_hdr_size;
  688. } else {
  689. ctx->eth_ip_hdr_size = 0;
  690. ctx->l4_hdr_size = 0;
  691. /* copy as much as allowed */
  692. ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
  693. , skb_headlen(skb));
  694. }
  695. /* make sure headers are accessible directly */
  696. if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
  697. goto err;
  698. }
  699. if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
  700. tq->stats.oversized_hdr++;
  701. ctx->copy_size = 0;
  702. return 0;
  703. }
  704. tdd = tq->data_ring.base + tq->tx_ring.next2fill;
  705. memcpy(tdd->data, skb->data, ctx->copy_size);
  706. dev_dbg(&adapter->netdev->dev,
  707. "copy %u bytes to dataRing[%u]\n",
  708. ctx->copy_size, tq->tx_ring.next2fill);
  709. return 1;
  710. err:
  711. return -1;
  712. }
  713. static void
  714. vmxnet3_prepare_tso(struct sk_buff *skb,
  715. struct vmxnet3_tx_ctx *ctx)
  716. {
  717. struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
  718. if (ctx->ipv4) {
  719. struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
  720. iph->check = 0;
  721. tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
  722. IPPROTO_TCP, 0);
  723. } else {
  724. struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
  725. tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
  726. IPPROTO_TCP, 0);
  727. }
  728. }
  729. /*
  730. * Transmits a pkt thru a given tq
  731. * Returns:
  732. * NETDEV_TX_OK: descriptors are setup successfully
  733. * NETDEV_TX_OK: error occured, the pkt is dropped
  734. * NETDEV_TX_BUSY: tx ring is full, queue is stopped
  735. *
  736. * Side-effects:
  737. * 1. tx ring may be changed
  738. * 2. tq stats may be updated accordingly
  739. * 3. shared->txNumDeferred may be updated
  740. */
  741. static int
  742. vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  743. struct vmxnet3_adapter *adapter, struct net_device *netdev)
  744. {
  745. int ret;
  746. u32 count;
  747. unsigned long flags;
  748. struct vmxnet3_tx_ctx ctx;
  749. union Vmxnet3_GenericDesc *gdesc;
  750. #ifdef __BIG_ENDIAN_BITFIELD
  751. /* Use temporary descriptor to avoid touching bits multiple times */
  752. union Vmxnet3_GenericDesc tempTxDesc;
  753. #endif
  754. /* conservatively estimate # of descriptors to use */
  755. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
  756. skb_shinfo(skb)->nr_frags + 1;
  757. ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP));
  758. ctx.mss = skb_shinfo(skb)->gso_size;
  759. if (ctx.mss) {
  760. if (skb_header_cloned(skb)) {
  761. if (unlikely(pskb_expand_head(skb, 0, 0,
  762. GFP_ATOMIC) != 0)) {
  763. tq->stats.drop_tso++;
  764. goto drop_pkt;
  765. }
  766. tq->stats.copy_skb_header++;
  767. }
  768. vmxnet3_prepare_tso(skb, &ctx);
  769. } else {
  770. if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
  771. /* non-tso pkts must not use more than
  772. * VMXNET3_MAX_TXD_PER_PKT entries
  773. */
  774. if (skb_linearize(skb) != 0) {
  775. tq->stats.drop_too_many_frags++;
  776. goto drop_pkt;
  777. }
  778. tq->stats.linearized++;
  779. /* recalculate the # of descriptors to use */
  780. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
  781. }
  782. }
  783. spin_lock_irqsave(&tq->tx_lock, flags);
  784. if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
  785. tq->stats.tx_ring_full++;
  786. dev_dbg(&adapter->netdev->dev,
  787. "tx queue stopped on %s, next2comp %u"
  788. " next2fill %u\n", adapter->netdev->name,
  789. tq->tx_ring.next2comp, tq->tx_ring.next2fill);
  790. vmxnet3_tq_stop(tq, adapter);
  791. spin_unlock_irqrestore(&tq->tx_lock, flags);
  792. return NETDEV_TX_BUSY;
  793. }
  794. ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
  795. if (ret >= 0) {
  796. BUG_ON(ret <= 0 && ctx.copy_size != 0);
  797. /* hdrs parsed, check against other limits */
  798. if (ctx.mss) {
  799. if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
  800. VMXNET3_MAX_TX_BUF_SIZE)) {
  801. goto hdr_too_big;
  802. }
  803. } else {
  804. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  805. if (unlikely(ctx.eth_ip_hdr_size +
  806. skb->csum_offset >
  807. VMXNET3_MAX_CSUM_OFFSET)) {
  808. goto hdr_too_big;
  809. }
  810. }
  811. }
  812. } else {
  813. tq->stats.drop_hdr_inspect_err++;
  814. goto unlock_drop_pkt;
  815. }
  816. /* fill tx descs related to addr & len */
  817. vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
  818. /* setup the EOP desc */
  819. ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
  820. /* setup the SOP desc */
  821. #ifdef __BIG_ENDIAN_BITFIELD
  822. gdesc = &tempTxDesc;
  823. gdesc->dword[2] = ctx.sop_txd->dword[2];
  824. gdesc->dword[3] = ctx.sop_txd->dword[3];
  825. #else
  826. gdesc = ctx.sop_txd;
  827. #endif
  828. if (ctx.mss) {
  829. gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
  830. gdesc->txd.om = VMXNET3_OM_TSO;
  831. gdesc->txd.msscof = ctx.mss;
  832. le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
  833. gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
  834. } else {
  835. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  836. gdesc->txd.hlen = ctx.eth_ip_hdr_size;
  837. gdesc->txd.om = VMXNET3_OM_CSUM;
  838. gdesc->txd.msscof = ctx.eth_ip_hdr_size +
  839. skb->csum_offset;
  840. } else {
  841. gdesc->txd.om = 0;
  842. gdesc->txd.msscof = 0;
  843. }
  844. le32_add_cpu(&tq->shared->txNumDeferred, 1);
  845. }
  846. if (vlan_tx_tag_present(skb)) {
  847. gdesc->txd.ti = 1;
  848. gdesc->txd.tci = vlan_tx_tag_get(skb);
  849. }
  850. /* finally flips the GEN bit of the SOP desc. */
  851. gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
  852. VMXNET3_TXD_GEN);
  853. #ifdef __BIG_ENDIAN_BITFIELD
  854. /* Finished updating in bitfields of Tx Desc, so write them in original
  855. * place.
  856. */
  857. vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
  858. (struct Vmxnet3_TxDesc *)ctx.sop_txd);
  859. gdesc = ctx.sop_txd;
  860. #endif
  861. dev_dbg(&adapter->netdev->dev,
  862. "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
  863. (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
  864. tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
  865. le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
  866. spin_unlock_irqrestore(&tq->tx_lock, flags);
  867. if (le32_to_cpu(tq->shared->txNumDeferred) >=
  868. le32_to_cpu(tq->shared->txThreshold)) {
  869. tq->shared->txNumDeferred = 0;
  870. VMXNET3_WRITE_BAR0_REG(adapter,
  871. VMXNET3_REG_TXPROD + tq->qid * 8,
  872. tq->tx_ring.next2fill);
  873. }
  874. return NETDEV_TX_OK;
  875. hdr_too_big:
  876. tq->stats.drop_oversized_hdr++;
  877. unlock_drop_pkt:
  878. spin_unlock_irqrestore(&tq->tx_lock, flags);
  879. drop_pkt:
  880. tq->stats.drop_total++;
  881. dev_kfree_skb(skb);
  882. return NETDEV_TX_OK;
  883. }
  884. static netdev_tx_t
  885. vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  886. {
  887. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  888. BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
  889. return vmxnet3_tq_xmit(skb,
  890. &adapter->tx_queue[skb->queue_mapping],
  891. adapter, netdev);
  892. }
  893. static void
  894. vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
  895. struct sk_buff *skb,
  896. union Vmxnet3_GenericDesc *gdesc)
  897. {
  898. if (!gdesc->rcd.cnc && adapter->rxcsum) {
  899. /* typical case: TCP/UDP over IP and both csums are correct */
  900. if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
  901. VMXNET3_RCD_CSUM_OK) {
  902. skb->ip_summed = CHECKSUM_UNNECESSARY;
  903. BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
  904. BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
  905. BUG_ON(gdesc->rcd.frg);
  906. } else {
  907. if (gdesc->rcd.csum) {
  908. skb->csum = htons(gdesc->rcd.csum);
  909. skb->ip_summed = CHECKSUM_PARTIAL;
  910. } else {
  911. skb_checksum_none_assert(skb);
  912. }
  913. }
  914. } else {
  915. skb_checksum_none_assert(skb);
  916. }
  917. }
  918. static void
  919. vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
  920. struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
  921. {
  922. rq->stats.drop_err++;
  923. if (!rcd->fcs)
  924. rq->stats.drop_fcs++;
  925. rq->stats.drop_total++;
  926. /*
  927. * We do not unmap and chain the rx buffer to the skb.
  928. * We basically pretend this buffer is not used and will be recycled
  929. * by vmxnet3_rq_alloc_rx_buf()
  930. */
  931. /*
  932. * ctx->skb may be NULL if this is the first and the only one
  933. * desc for the pkt
  934. */
  935. if (ctx->skb)
  936. dev_kfree_skb_irq(ctx->skb);
  937. ctx->skb = NULL;
  938. }
  939. static int
  940. vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
  941. struct vmxnet3_adapter *adapter, int quota)
  942. {
  943. static const u32 rxprod_reg[2] = {
  944. VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
  945. };
  946. u32 num_rxd = 0;
  947. struct Vmxnet3_RxCompDesc *rcd;
  948. struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
  949. #ifdef __BIG_ENDIAN_BITFIELD
  950. struct Vmxnet3_RxDesc rxCmdDesc;
  951. struct Vmxnet3_RxCompDesc rxComp;
  952. #endif
  953. vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
  954. &rxComp);
  955. while (rcd->gen == rq->comp_ring.gen) {
  956. struct vmxnet3_rx_buf_info *rbi;
  957. struct sk_buff *skb;
  958. int num_to_alloc;
  959. struct Vmxnet3_RxDesc *rxd;
  960. u32 idx, ring_idx;
  961. if (num_rxd >= quota) {
  962. /* we may stop even before we see the EOP desc of
  963. * the current pkt
  964. */
  965. break;
  966. }
  967. num_rxd++;
  968. BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
  969. idx = rcd->rxdIdx;
  970. ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
  971. vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
  972. &rxCmdDesc);
  973. rbi = rq->buf_info[ring_idx] + idx;
  974. BUG_ON(rxd->addr != rbi->dma_addr ||
  975. rxd->len != rbi->len);
  976. if (unlikely(rcd->eop && rcd->err)) {
  977. vmxnet3_rx_error(rq, rcd, ctx, adapter);
  978. goto rcd_done;
  979. }
  980. if (rcd->sop) { /* first buf of the pkt */
  981. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
  982. rcd->rqID != rq->qid);
  983. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
  984. BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
  985. if (unlikely(rcd->len == 0)) {
  986. /* Pretend the rx buffer is skipped. */
  987. BUG_ON(!(rcd->sop && rcd->eop));
  988. dev_dbg(&adapter->netdev->dev,
  989. "rxRing[%u][%u] 0 length\n",
  990. ring_idx, idx);
  991. goto rcd_done;
  992. }
  993. ctx->skb = rbi->skb;
  994. rbi->skb = NULL;
  995. pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
  996. PCI_DMA_FROMDEVICE);
  997. skb_put(ctx->skb, rcd->len);
  998. } else {
  999. BUG_ON(ctx->skb == NULL);
  1000. /* non SOP buffer must be type 1 in most cases */
  1001. if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) {
  1002. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
  1003. if (rcd->len) {
  1004. pci_unmap_page(adapter->pdev,
  1005. rbi->dma_addr, rbi->len,
  1006. PCI_DMA_FROMDEVICE);
  1007. vmxnet3_append_frag(ctx->skb, rcd, rbi);
  1008. rbi->page = NULL;
  1009. }
  1010. } else {
  1011. /*
  1012. * The only time a non-SOP buffer is type 0 is
  1013. * when it's EOP and error flag is raised, which
  1014. * has already been handled.
  1015. */
  1016. BUG_ON(true);
  1017. }
  1018. }
  1019. skb = ctx->skb;
  1020. if (rcd->eop) {
  1021. skb->len += skb->data_len;
  1022. skb->truesize += skb->data_len;
  1023. vmxnet3_rx_csum(adapter, skb,
  1024. (union Vmxnet3_GenericDesc *)rcd);
  1025. skb->protocol = eth_type_trans(skb, adapter->netdev);
  1026. if (unlikely(adapter->vlan_grp && rcd->ts)) {
  1027. vlan_hwaccel_receive_skb(skb,
  1028. adapter->vlan_grp, rcd->tci);
  1029. } else {
  1030. netif_receive_skb(skb);
  1031. }
  1032. ctx->skb = NULL;
  1033. }
  1034. rcd_done:
  1035. /* device may skip some rx descs */
  1036. rq->rx_ring[ring_idx].next2comp = idx;
  1037. VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp,
  1038. rq->rx_ring[ring_idx].size);
  1039. /* refill rx buffers frequently to avoid starving the h/w */
  1040. num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring +
  1041. ring_idx);
  1042. if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq,
  1043. ring_idx, adapter))) {
  1044. vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc,
  1045. adapter);
  1046. /* if needed, update the register */
  1047. if (unlikely(rq->shared->updateRxProd)) {
  1048. VMXNET3_WRITE_BAR0_REG(adapter,
  1049. rxprod_reg[ring_idx] + rq->qid * 8,
  1050. rq->rx_ring[ring_idx].next2fill);
  1051. rq->uncommitted[ring_idx] = 0;
  1052. }
  1053. }
  1054. vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
  1055. vmxnet3_getRxComp(rcd,
  1056. &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
  1057. }
  1058. return num_rxd;
  1059. }
  1060. static void
  1061. vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
  1062. struct vmxnet3_adapter *adapter)
  1063. {
  1064. u32 i, ring_idx;
  1065. struct Vmxnet3_RxDesc *rxd;
  1066. for (ring_idx = 0; ring_idx < 2; ring_idx++) {
  1067. for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
  1068. #ifdef __BIG_ENDIAN_BITFIELD
  1069. struct Vmxnet3_RxDesc rxDesc;
  1070. #endif
  1071. vmxnet3_getRxDesc(rxd,
  1072. &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
  1073. if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
  1074. rq->buf_info[ring_idx][i].skb) {
  1075. pci_unmap_single(adapter->pdev, rxd->addr,
  1076. rxd->len, PCI_DMA_FROMDEVICE);
  1077. dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
  1078. rq->buf_info[ring_idx][i].skb = NULL;
  1079. } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
  1080. rq->buf_info[ring_idx][i].page) {
  1081. pci_unmap_page(adapter->pdev, rxd->addr,
  1082. rxd->len, PCI_DMA_FROMDEVICE);
  1083. put_page(rq->buf_info[ring_idx][i].page);
  1084. rq->buf_info[ring_idx][i].page = NULL;
  1085. }
  1086. }
  1087. rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
  1088. rq->rx_ring[ring_idx].next2fill =
  1089. rq->rx_ring[ring_idx].next2comp = 0;
  1090. rq->uncommitted[ring_idx] = 0;
  1091. }
  1092. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1093. rq->comp_ring.next2proc = 0;
  1094. }
  1095. static void
  1096. vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
  1097. {
  1098. int i;
  1099. for (i = 0; i < adapter->num_rx_queues; i++)
  1100. vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
  1101. }
  1102. void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
  1103. struct vmxnet3_adapter *adapter)
  1104. {
  1105. int i;
  1106. int j;
  1107. /* all rx buffers must have already been freed */
  1108. for (i = 0; i < 2; i++) {
  1109. if (rq->buf_info[i]) {
  1110. for (j = 0; j < rq->rx_ring[i].size; j++)
  1111. BUG_ON(rq->buf_info[i][j].page != NULL);
  1112. }
  1113. }
  1114. kfree(rq->buf_info[0]);
  1115. for (i = 0; i < 2; i++) {
  1116. if (rq->rx_ring[i].base) {
  1117. pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
  1118. * sizeof(struct Vmxnet3_RxDesc),
  1119. rq->rx_ring[i].base,
  1120. rq->rx_ring[i].basePA);
  1121. rq->rx_ring[i].base = NULL;
  1122. }
  1123. rq->buf_info[i] = NULL;
  1124. }
  1125. if (rq->comp_ring.base) {
  1126. pci_free_consistent(adapter->pdev, rq->comp_ring.size *
  1127. sizeof(struct Vmxnet3_RxCompDesc),
  1128. rq->comp_ring.base, rq->comp_ring.basePA);
  1129. rq->comp_ring.base = NULL;
  1130. }
  1131. }
  1132. static int
  1133. vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
  1134. struct vmxnet3_adapter *adapter)
  1135. {
  1136. int i;
  1137. /* initialize buf_info */
  1138. for (i = 0; i < rq->rx_ring[0].size; i++) {
  1139. /* 1st buf for a pkt is skbuff */
  1140. if (i % adapter->rx_buf_per_pkt == 0) {
  1141. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
  1142. rq->buf_info[0][i].len = adapter->skb_buf_size;
  1143. } else { /* subsequent bufs for a pkt is frag */
  1144. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1145. rq->buf_info[0][i].len = PAGE_SIZE;
  1146. }
  1147. }
  1148. for (i = 0; i < rq->rx_ring[1].size; i++) {
  1149. rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1150. rq->buf_info[1][i].len = PAGE_SIZE;
  1151. }
  1152. /* reset internal state and allocate buffers for both rings */
  1153. for (i = 0; i < 2; i++) {
  1154. rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
  1155. rq->uncommitted[i] = 0;
  1156. memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
  1157. sizeof(struct Vmxnet3_RxDesc));
  1158. rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
  1159. }
  1160. if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
  1161. adapter) == 0) {
  1162. /* at least has 1 rx buffer for the 1st ring */
  1163. return -ENOMEM;
  1164. }
  1165. vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
  1166. /* reset the comp ring */
  1167. rq->comp_ring.next2proc = 0;
  1168. memset(rq->comp_ring.base, 0, rq->comp_ring.size *
  1169. sizeof(struct Vmxnet3_RxCompDesc));
  1170. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1171. /* reset rxctx */
  1172. rq->rx_ctx.skb = NULL;
  1173. /* stats are not reset */
  1174. return 0;
  1175. }
  1176. static int
  1177. vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
  1178. {
  1179. int i, err = 0;
  1180. for (i = 0; i < adapter->num_rx_queues; i++) {
  1181. err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
  1182. if (unlikely(err)) {
  1183. dev_err(&adapter->netdev->dev, "%s: failed to "
  1184. "initialize rx queue%i\n",
  1185. adapter->netdev->name, i);
  1186. break;
  1187. }
  1188. }
  1189. return err;
  1190. }
  1191. static int
  1192. vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
  1193. {
  1194. int i;
  1195. size_t sz;
  1196. struct vmxnet3_rx_buf_info *bi;
  1197. for (i = 0; i < 2; i++) {
  1198. sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
  1199. rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
  1200. &rq->rx_ring[i].basePA);
  1201. if (!rq->rx_ring[i].base) {
  1202. printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
  1203. adapter->netdev->name, i);
  1204. goto err;
  1205. }
  1206. }
  1207. sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
  1208. rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
  1209. &rq->comp_ring.basePA);
  1210. if (!rq->comp_ring.base) {
  1211. printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
  1212. adapter->netdev->name);
  1213. goto err;
  1214. }
  1215. sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
  1216. rq->rx_ring[1].size);
  1217. bi = kzalloc(sz, GFP_KERNEL);
  1218. if (!bi) {
  1219. printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
  1220. adapter->netdev->name);
  1221. goto err;
  1222. }
  1223. rq->buf_info[0] = bi;
  1224. rq->buf_info[1] = bi + rq->rx_ring[0].size;
  1225. return 0;
  1226. err:
  1227. vmxnet3_rq_destroy(rq, adapter);
  1228. return -ENOMEM;
  1229. }
  1230. static int
  1231. vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
  1232. {
  1233. int i, err = 0;
  1234. for (i = 0; i < adapter->num_rx_queues; i++) {
  1235. err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
  1236. if (unlikely(err)) {
  1237. dev_err(&adapter->netdev->dev,
  1238. "%s: failed to create rx queue%i\n",
  1239. adapter->netdev->name, i);
  1240. goto err_out;
  1241. }
  1242. }
  1243. return err;
  1244. err_out:
  1245. vmxnet3_rq_destroy_all(adapter);
  1246. return err;
  1247. }
  1248. /* Multiple queue aware polling function for tx and rx */
  1249. static int
  1250. vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
  1251. {
  1252. int rcd_done = 0, i;
  1253. if (unlikely(adapter->shared->ecr))
  1254. vmxnet3_process_events(adapter);
  1255. for (i = 0; i < adapter->num_tx_queues; i++)
  1256. vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
  1257. for (i = 0; i < adapter->num_rx_queues; i++)
  1258. rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
  1259. adapter, budget);
  1260. return rcd_done;
  1261. }
  1262. static int
  1263. vmxnet3_poll(struct napi_struct *napi, int budget)
  1264. {
  1265. struct vmxnet3_rx_queue *rx_queue = container_of(napi,
  1266. struct vmxnet3_rx_queue, napi);
  1267. int rxd_done;
  1268. rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
  1269. if (rxd_done < budget) {
  1270. napi_complete(napi);
  1271. vmxnet3_enable_all_intrs(rx_queue->adapter);
  1272. }
  1273. return rxd_done;
  1274. }
  1275. /*
  1276. * NAPI polling function for MSI-X mode with multiple Rx queues
  1277. * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
  1278. */
  1279. static int
  1280. vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
  1281. {
  1282. struct vmxnet3_rx_queue *rq = container_of(napi,
  1283. struct vmxnet3_rx_queue, napi);
  1284. struct vmxnet3_adapter *adapter = rq->adapter;
  1285. int rxd_done;
  1286. /* When sharing interrupt with corresponding tx queue, process
  1287. * tx completions in that queue as well
  1288. */
  1289. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
  1290. struct vmxnet3_tx_queue *tq =
  1291. &adapter->tx_queue[rq - adapter->rx_queue];
  1292. vmxnet3_tq_tx_complete(tq, adapter);
  1293. }
  1294. rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
  1295. if (rxd_done < budget) {
  1296. napi_complete(napi);
  1297. vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
  1298. }
  1299. return rxd_done;
  1300. }
  1301. #ifdef CONFIG_PCI_MSI
  1302. /*
  1303. * Handle completion interrupts on tx queues
  1304. * Returns whether or not the intr is handled
  1305. */
  1306. static irqreturn_t
  1307. vmxnet3_msix_tx(int irq, void *data)
  1308. {
  1309. struct vmxnet3_tx_queue *tq = data;
  1310. struct vmxnet3_adapter *adapter = tq->adapter;
  1311. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1312. vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
  1313. /* Handle the case where only one irq is allocate for all tx queues */
  1314. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1315. int i;
  1316. for (i = 0; i < adapter->num_tx_queues; i++) {
  1317. struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
  1318. vmxnet3_tq_tx_complete(txq, adapter);
  1319. }
  1320. } else {
  1321. vmxnet3_tq_tx_complete(tq, adapter);
  1322. }
  1323. vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
  1324. return IRQ_HANDLED;
  1325. }
  1326. /*
  1327. * Handle completion interrupts on rx queues. Returns whether or not the
  1328. * intr is handled
  1329. */
  1330. static irqreturn_t
  1331. vmxnet3_msix_rx(int irq, void *data)
  1332. {
  1333. struct vmxnet3_rx_queue *rq = data;
  1334. struct vmxnet3_adapter *adapter = rq->adapter;
  1335. /* disable intr if needed */
  1336. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1337. vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
  1338. napi_schedule(&rq->napi);
  1339. return IRQ_HANDLED;
  1340. }
  1341. /*
  1342. *----------------------------------------------------------------------------
  1343. *
  1344. * vmxnet3_msix_event --
  1345. *
  1346. * vmxnet3 msix event intr handler
  1347. *
  1348. * Result:
  1349. * whether or not the intr is handled
  1350. *
  1351. *----------------------------------------------------------------------------
  1352. */
  1353. static irqreturn_t
  1354. vmxnet3_msix_event(int irq, void *data)
  1355. {
  1356. struct net_device *dev = data;
  1357. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1358. /* disable intr if needed */
  1359. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1360. vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
  1361. if (adapter->shared->ecr)
  1362. vmxnet3_process_events(adapter);
  1363. vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
  1364. return IRQ_HANDLED;
  1365. }
  1366. #endif /* CONFIG_PCI_MSI */
  1367. /* Interrupt handler for vmxnet3 */
  1368. static irqreturn_t
  1369. vmxnet3_intr(int irq, void *dev_id)
  1370. {
  1371. struct net_device *dev = dev_id;
  1372. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1373. if (adapter->intr.type == VMXNET3_IT_INTX) {
  1374. u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
  1375. if (unlikely(icr == 0))
  1376. /* not ours */
  1377. return IRQ_NONE;
  1378. }
  1379. /* disable intr if needed */
  1380. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1381. vmxnet3_disable_all_intrs(adapter);
  1382. napi_schedule(&adapter->rx_queue[0].napi);
  1383. return IRQ_HANDLED;
  1384. }
  1385. #ifdef CONFIG_NET_POLL_CONTROLLER
  1386. /* netpoll callback. */
  1387. static void
  1388. vmxnet3_netpoll(struct net_device *netdev)
  1389. {
  1390. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1391. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1392. vmxnet3_disable_all_intrs(adapter);
  1393. vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
  1394. vmxnet3_enable_all_intrs(adapter);
  1395. }
  1396. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1397. static int
  1398. vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
  1399. {
  1400. struct vmxnet3_intr *intr = &adapter->intr;
  1401. int err = 0, i;
  1402. int vector = 0;
  1403. #ifdef CONFIG_PCI_MSI
  1404. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  1405. for (i = 0; i < adapter->num_tx_queues; i++) {
  1406. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1407. sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
  1408. adapter->netdev->name, vector);
  1409. err = request_irq(
  1410. intr->msix_entries[vector].vector,
  1411. vmxnet3_msix_tx, 0,
  1412. adapter->tx_queue[i].name,
  1413. &adapter->tx_queue[i]);
  1414. } else {
  1415. sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
  1416. adapter->netdev->name, vector);
  1417. }
  1418. if (err) {
  1419. dev_err(&adapter->netdev->dev,
  1420. "Failed to request irq for MSIX, %s, "
  1421. "error %d\n",
  1422. adapter->tx_queue[i].name, err);
  1423. return err;
  1424. }
  1425. /* Handle the case where only 1 MSIx was allocated for
  1426. * all tx queues */
  1427. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1428. for (; i < adapter->num_tx_queues; i++)
  1429. adapter->tx_queue[i].comp_ring.intr_idx
  1430. = vector;
  1431. vector++;
  1432. break;
  1433. } else {
  1434. adapter->tx_queue[i].comp_ring.intr_idx
  1435. = vector++;
  1436. }
  1437. }
  1438. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
  1439. vector = 0;
  1440. for (i = 0; i < adapter->num_rx_queues; i++) {
  1441. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
  1442. sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
  1443. adapter->netdev->name, vector);
  1444. else
  1445. sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
  1446. adapter->netdev->name, vector);
  1447. err = request_irq(intr->msix_entries[vector].vector,
  1448. vmxnet3_msix_rx, 0,
  1449. adapter->rx_queue[i].name,
  1450. &(adapter->rx_queue[i]));
  1451. if (err) {
  1452. printk(KERN_ERR "Failed to request irq for MSIX"
  1453. ", %s, error %d\n",
  1454. adapter->rx_queue[i].name, err);
  1455. return err;
  1456. }
  1457. adapter->rx_queue[i].comp_ring.intr_idx = vector++;
  1458. }
  1459. sprintf(intr->event_msi_vector_name, "%s-event-%d",
  1460. adapter->netdev->name, vector);
  1461. err = request_irq(intr->msix_entries[vector].vector,
  1462. vmxnet3_msix_event, 0,
  1463. intr->event_msi_vector_name, adapter->netdev);
  1464. intr->event_intr_idx = vector;
  1465. } else if (intr->type == VMXNET3_IT_MSI) {
  1466. adapter->num_rx_queues = 1;
  1467. err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
  1468. adapter->netdev->name, adapter->netdev);
  1469. } else {
  1470. #endif
  1471. adapter->num_rx_queues = 1;
  1472. err = request_irq(adapter->pdev->irq, vmxnet3_intr,
  1473. IRQF_SHARED, adapter->netdev->name,
  1474. adapter->netdev);
  1475. #ifdef CONFIG_PCI_MSI
  1476. }
  1477. #endif
  1478. intr->num_intrs = vector + 1;
  1479. if (err) {
  1480. printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
  1481. ":%d\n", adapter->netdev->name, intr->type, err);
  1482. } else {
  1483. /* Number of rx queues will not change after this */
  1484. for (i = 0; i < adapter->num_rx_queues; i++) {
  1485. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1486. rq->qid = i;
  1487. rq->qid2 = i + adapter->num_rx_queues;
  1488. }
  1489. /* init our intr settings */
  1490. for (i = 0; i < intr->num_intrs; i++)
  1491. intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
  1492. if (adapter->intr.type != VMXNET3_IT_MSIX) {
  1493. adapter->intr.event_intr_idx = 0;
  1494. for (i = 0; i < adapter->num_tx_queues; i++)
  1495. adapter->tx_queue[i].comp_ring.intr_idx = 0;
  1496. adapter->rx_queue[0].comp_ring.intr_idx = 0;
  1497. }
  1498. printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
  1499. "allocated\n", adapter->netdev->name, intr->type,
  1500. intr->mask_mode, intr->num_intrs);
  1501. }
  1502. return err;
  1503. }
  1504. static void
  1505. vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
  1506. {
  1507. struct vmxnet3_intr *intr = &adapter->intr;
  1508. BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
  1509. switch (intr->type) {
  1510. #ifdef CONFIG_PCI_MSI
  1511. case VMXNET3_IT_MSIX:
  1512. {
  1513. int i, vector = 0;
  1514. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1515. for (i = 0; i < adapter->num_tx_queues; i++) {
  1516. free_irq(intr->msix_entries[vector++].vector,
  1517. &(adapter->tx_queue[i]));
  1518. if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
  1519. break;
  1520. }
  1521. }
  1522. for (i = 0; i < adapter->num_rx_queues; i++) {
  1523. free_irq(intr->msix_entries[vector++].vector,
  1524. &(adapter->rx_queue[i]));
  1525. }
  1526. free_irq(intr->msix_entries[vector].vector,
  1527. adapter->netdev);
  1528. BUG_ON(vector >= intr->num_intrs);
  1529. break;
  1530. }
  1531. #endif
  1532. case VMXNET3_IT_MSI:
  1533. free_irq(adapter->pdev->irq, adapter->netdev);
  1534. break;
  1535. case VMXNET3_IT_INTX:
  1536. free_irq(adapter->pdev->irq, adapter->netdev);
  1537. break;
  1538. default:
  1539. BUG_ON(true);
  1540. }
  1541. }
  1542. static void
  1543. vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  1544. {
  1545. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1546. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1547. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1548. if (grp) {
  1549. /* add vlan rx stripping. */
  1550. if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
  1551. int i;
  1552. adapter->vlan_grp = grp;
  1553. /*
  1554. * Clear entire vfTable; then enable untagged pkts.
  1555. * Note: setting one entry in vfTable to non-zero turns
  1556. * on VLAN rx filtering.
  1557. */
  1558. for (i = 0; i < VMXNET3_VFT_SIZE; i++)
  1559. vfTable[i] = 0;
  1560. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1561. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1562. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1563. } else {
  1564. printk(KERN_ERR "%s: vlan_rx_register when device has "
  1565. "no NETIF_F_HW_VLAN_RX\n", netdev->name);
  1566. }
  1567. } else {
  1568. /* remove vlan rx stripping. */
  1569. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1570. adapter->vlan_grp = NULL;
  1571. if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) {
  1572. int i;
  1573. for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
  1574. /* clear entire vfTable; this also disables
  1575. * VLAN rx filtering
  1576. */
  1577. vfTable[i] = 0;
  1578. }
  1579. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1580. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1581. }
  1582. }
  1583. }
  1584. static void
  1585. vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
  1586. {
  1587. if (adapter->vlan_grp) {
  1588. u16 vid;
  1589. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1590. bool activeVlan = false;
  1591. for (vid = 0; vid < VLAN_N_VID; vid++) {
  1592. if (vlan_group_get_device(adapter->vlan_grp, vid)) {
  1593. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1594. activeVlan = true;
  1595. }
  1596. }
  1597. if (activeVlan) {
  1598. /* continue to allow untagged pkts */
  1599. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1600. }
  1601. }
  1602. }
  1603. static void
  1604. vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  1605. {
  1606. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1607. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1608. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1609. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1610. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1611. }
  1612. static void
  1613. vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  1614. {
  1615. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1616. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1617. VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
  1618. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1619. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1620. }
  1621. static u8 *
  1622. vmxnet3_copy_mc(struct net_device *netdev)
  1623. {
  1624. u8 *buf = NULL;
  1625. u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
  1626. /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
  1627. if (sz <= 0xffff) {
  1628. /* We may be called with BH disabled */
  1629. buf = kmalloc(sz, GFP_ATOMIC);
  1630. if (buf) {
  1631. struct netdev_hw_addr *ha;
  1632. int i = 0;
  1633. netdev_for_each_mc_addr(ha, netdev)
  1634. memcpy(buf + i++ * ETH_ALEN, ha->addr,
  1635. ETH_ALEN);
  1636. }
  1637. }
  1638. return buf;
  1639. }
  1640. static void
  1641. vmxnet3_set_mc(struct net_device *netdev)
  1642. {
  1643. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1644. struct Vmxnet3_RxFilterConf *rxConf =
  1645. &adapter->shared->devRead.rxFilterConf;
  1646. u8 *new_table = NULL;
  1647. u32 new_mode = VMXNET3_RXM_UCAST;
  1648. if (netdev->flags & IFF_PROMISC)
  1649. new_mode |= VMXNET3_RXM_PROMISC;
  1650. if (netdev->flags & IFF_BROADCAST)
  1651. new_mode |= VMXNET3_RXM_BCAST;
  1652. if (netdev->flags & IFF_ALLMULTI)
  1653. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1654. else
  1655. if (!netdev_mc_empty(netdev)) {
  1656. new_table = vmxnet3_copy_mc(netdev);
  1657. if (new_table) {
  1658. new_mode |= VMXNET3_RXM_MCAST;
  1659. rxConf->mfTableLen = cpu_to_le16(
  1660. netdev_mc_count(netdev) * ETH_ALEN);
  1661. rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
  1662. new_table));
  1663. } else {
  1664. printk(KERN_INFO "%s: failed to copy mcast list"
  1665. ", setting ALL_MULTI\n", netdev->name);
  1666. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1667. }
  1668. }
  1669. if (!(new_mode & VMXNET3_RXM_MCAST)) {
  1670. rxConf->mfTableLen = 0;
  1671. rxConf->mfTablePA = 0;
  1672. }
  1673. if (new_mode != rxConf->rxMode) {
  1674. rxConf->rxMode = cpu_to_le32(new_mode);
  1675. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1676. VMXNET3_CMD_UPDATE_RX_MODE);
  1677. }
  1678. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1679. VMXNET3_CMD_UPDATE_MAC_FILTERS);
  1680. kfree(new_table);
  1681. }
  1682. void
  1683. vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
  1684. {
  1685. int i;
  1686. for (i = 0; i < adapter->num_rx_queues; i++)
  1687. vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
  1688. }
  1689. /*
  1690. * Set up driver_shared based on settings in adapter.
  1691. */
  1692. static void
  1693. vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
  1694. {
  1695. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1696. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1697. struct Vmxnet3_TxQueueConf *tqc;
  1698. struct Vmxnet3_RxQueueConf *rqc;
  1699. int i;
  1700. memset(shared, 0, sizeof(*shared));
  1701. /* driver settings */
  1702. shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
  1703. devRead->misc.driverInfo.version = cpu_to_le32(
  1704. VMXNET3_DRIVER_VERSION_NUM);
  1705. devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
  1706. VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
  1707. devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
  1708. *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
  1709. *((u32 *)&devRead->misc.driverInfo.gos));
  1710. devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
  1711. devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
  1712. devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
  1713. devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
  1714. /* set up feature flags */
  1715. if (adapter->rxcsum)
  1716. devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
  1717. if (adapter->lro) {
  1718. devRead->misc.uptFeatures |= UPT1_F_LRO;
  1719. devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
  1720. }
  1721. if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
  1722. devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
  1723. devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
  1724. devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
  1725. devRead->misc.queueDescLen = cpu_to_le32(
  1726. adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
  1727. adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
  1728. /* tx queue settings */
  1729. devRead->misc.numTxQueues = adapter->num_tx_queues;
  1730. for (i = 0; i < adapter->num_tx_queues; i++) {
  1731. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  1732. BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
  1733. tqc = &adapter->tqd_start[i].conf;
  1734. tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
  1735. tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
  1736. tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
  1737. tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
  1738. tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
  1739. tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
  1740. tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
  1741. tqc->ddLen = cpu_to_le32(
  1742. sizeof(struct vmxnet3_tx_buf_info) *
  1743. tqc->txRingSize);
  1744. tqc->intrIdx = tq->comp_ring.intr_idx;
  1745. }
  1746. /* rx queue settings */
  1747. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1748. for (i = 0; i < adapter->num_rx_queues; i++) {
  1749. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1750. rqc = &adapter->rqd_start[i].conf;
  1751. rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
  1752. rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
  1753. rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
  1754. rqc->ddPA = cpu_to_le64(virt_to_phys(
  1755. rq->buf_info));
  1756. rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
  1757. rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
  1758. rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
  1759. rqc->ddLen = cpu_to_le32(
  1760. sizeof(struct vmxnet3_rx_buf_info) *
  1761. (rqc->rxRingSize[0] +
  1762. rqc->rxRingSize[1]));
  1763. rqc->intrIdx = rq->comp_ring.intr_idx;
  1764. }
  1765. #ifdef VMXNET3_RSS
  1766. memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
  1767. if (adapter->rss) {
  1768. struct UPT1_RSSConf *rssConf = adapter->rss_conf;
  1769. devRead->misc.uptFeatures |= UPT1_F_RSS;
  1770. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1771. rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
  1772. UPT1_RSS_HASH_TYPE_IPV4 |
  1773. UPT1_RSS_HASH_TYPE_TCP_IPV6 |
  1774. UPT1_RSS_HASH_TYPE_IPV6;
  1775. rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
  1776. rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
  1777. rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
  1778. get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
  1779. for (i = 0; i < rssConf->indTableSize; i++)
  1780. rssConf->indTable[i] = i % adapter->num_rx_queues;
  1781. devRead->rssConfDesc.confVer = 1;
  1782. devRead->rssConfDesc.confLen = sizeof(*rssConf);
  1783. devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
  1784. }
  1785. #endif /* VMXNET3_RSS */
  1786. /* intr settings */
  1787. devRead->intrConf.autoMask = adapter->intr.mask_mode ==
  1788. VMXNET3_IMM_AUTO;
  1789. devRead->intrConf.numIntrs = adapter->intr.num_intrs;
  1790. for (i = 0; i < adapter->intr.num_intrs; i++)
  1791. devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
  1792. devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
  1793. devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  1794. /* rx filter settings */
  1795. devRead->rxFilterConf.rxMode = 0;
  1796. vmxnet3_restore_vlan(adapter);
  1797. vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
  1798. /* the rest are already zeroed */
  1799. }
  1800. int
  1801. vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
  1802. {
  1803. int err, i;
  1804. u32 ret;
  1805. dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
  1806. " ring sizes %u %u %u\n", adapter->netdev->name,
  1807. adapter->skb_buf_size, adapter->rx_buf_per_pkt,
  1808. adapter->tx_queue[0].tx_ring.size,
  1809. adapter->rx_queue[0].rx_ring[0].size,
  1810. adapter->rx_queue[0].rx_ring[1].size);
  1811. vmxnet3_tq_init_all(adapter);
  1812. err = vmxnet3_rq_init_all(adapter);
  1813. if (err) {
  1814. printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
  1815. adapter->netdev->name, err);
  1816. goto rq_err;
  1817. }
  1818. err = vmxnet3_request_irqs(adapter);
  1819. if (err) {
  1820. printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
  1821. adapter->netdev->name, err);
  1822. goto irq_err;
  1823. }
  1824. vmxnet3_setup_driver_shared(adapter);
  1825. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
  1826. adapter->shared_pa));
  1827. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
  1828. adapter->shared_pa));
  1829. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1830. VMXNET3_CMD_ACTIVATE_DEV);
  1831. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  1832. if (ret != 0) {
  1833. printk(KERN_ERR "Failed to activate dev %s: error %u\n",
  1834. adapter->netdev->name, ret);
  1835. err = -EINVAL;
  1836. goto activate_err;
  1837. }
  1838. for (i = 0; i < adapter->num_rx_queues; i++) {
  1839. VMXNET3_WRITE_BAR0_REG(adapter,
  1840. VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
  1841. adapter->rx_queue[i].rx_ring[0].next2fill);
  1842. VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
  1843. (i * VMXNET3_REG_ALIGN)),
  1844. adapter->rx_queue[i].rx_ring[1].next2fill);
  1845. }
  1846. /* Apply the rx filter settins last. */
  1847. vmxnet3_set_mc(adapter->netdev);
  1848. /*
  1849. * Check link state when first activating device. It will start the
  1850. * tx queue if the link is up.
  1851. */
  1852. vmxnet3_check_link(adapter, true);
  1853. for (i = 0; i < adapter->num_rx_queues; i++)
  1854. napi_enable(&adapter->rx_queue[i].napi);
  1855. vmxnet3_enable_all_intrs(adapter);
  1856. clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  1857. return 0;
  1858. activate_err:
  1859. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
  1860. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
  1861. vmxnet3_free_irqs(adapter);
  1862. irq_err:
  1863. rq_err:
  1864. /* free up buffers we allocated */
  1865. vmxnet3_rq_cleanup_all(adapter);
  1866. return err;
  1867. }
  1868. void
  1869. vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
  1870. {
  1871. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
  1872. }
  1873. int
  1874. vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
  1875. {
  1876. int i;
  1877. if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
  1878. return 0;
  1879. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1880. VMXNET3_CMD_QUIESCE_DEV);
  1881. vmxnet3_disable_all_intrs(adapter);
  1882. for (i = 0; i < adapter->num_rx_queues; i++)
  1883. napi_disable(&adapter->rx_queue[i].napi);
  1884. netif_tx_disable(adapter->netdev);
  1885. adapter->link_speed = 0;
  1886. netif_carrier_off(adapter->netdev);
  1887. vmxnet3_tq_cleanup_all(adapter);
  1888. vmxnet3_rq_cleanup_all(adapter);
  1889. vmxnet3_free_irqs(adapter);
  1890. return 0;
  1891. }
  1892. static void
  1893. vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  1894. {
  1895. u32 tmp;
  1896. tmp = *(u32 *)mac;
  1897. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
  1898. tmp = (mac[5] << 8) | mac[4];
  1899. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
  1900. }
  1901. static int
  1902. vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
  1903. {
  1904. struct sockaddr *addr = p;
  1905. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1906. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1907. vmxnet3_write_mac_addr(adapter, addr->sa_data);
  1908. return 0;
  1909. }
  1910. /* ==================== initialization and cleanup routines ============ */
  1911. static int
  1912. vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
  1913. {
  1914. int err;
  1915. unsigned long mmio_start, mmio_len;
  1916. struct pci_dev *pdev = adapter->pdev;
  1917. err = pci_enable_device(pdev);
  1918. if (err) {
  1919. printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
  1920. pci_name(pdev), err);
  1921. return err;
  1922. }
  1923. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  1924. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
  1925. printk(KERN_ERR "pci_set_consistent_dma_mask failed "
  1926. "for adapter %s\n", pci_name(pdev));
  1927. err = -EIO;
  1928. goto err_set_mask;
  1929. }
  1930. *dma64 = true;
  1931. } else {
  1932. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
  1933. printk(KERN_ERR "pci_set_dma_mask failed for adapter "
  1934. "%s\n", pci_name(pdev));
  1935. err = -EIO;
  1936. goto err_set_mask;
  1937. }
  1938. *dma64 = false;
  1939. }
  1940. err = pci_request_selected_regions(pdev, (1 << 2) - 1,
  1941. vmxnet3_driver_name);
  1942. if (err) {
  1943. printk(KERN_ERR "Failed to request region for adapter %s: "
  1944. "error %d\n", pci_name(pdev), err);
  1945. goto err_set_mask;
  1946. }
  1947. pci_set_master(pdev);
  1948. mmio_start = pci_resource_start(pdev, 0);
  1949. mmio_len = pci_resource_len(pdev, 0);
  1950. adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
  1951. if (!adapter->hw_addr0) {
  1952. printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
  1953. pci_name(pdev));
  1954. err = -EIO;
  1955. goto err_ioremap;
  1956. }
  1957. mmio_start = pci_resource_start(pdev, 1);
  1958. mmio_len = pci_resource_len(pdev, 1);
  1959. adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
  1960. if (!adapter->hw_addr1) {
  1961. printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
  1962. pci_name(pdev));
  1963. err = -EIO;
  1964. goto err_bar1;
  1965. }
  1966. return 0;
  1967. err_bar1:
  1968. iounmap(adapter->hw_addr0);
  1969. err_ioremap:
  1970. pci_release_selected_regions(pdev, (1 << 2) - 1);
  1971. err_set_mask:
  1972. pci_disable_device(pdev);
  1973. return err;
  1974. }
  1975. static void
  1976. vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
  1977. {
  1978. BUG_ON(!adapter->pdev);
  1979. iounmap(adapter->hw_addr0);
  1980. iounmap(adapter->hw_addr1);
  1981. pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
  1982. pci_disable_device(adapter->pdev);
  1983. }
  1984. static void
  1985. vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
  1986. {
  1987. size_t sz, i, ring0_size, ring1_size, comp_size;
  1988. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
  1989. if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
  1990. VMXNET3_MAX_ETH_HDR_SIZE) {
  1991. adapter->skb_buf_size = adapter->netdev->mtu +
  1992. VMXNET3_MAX_ETH_HDR_SIZE;
  1993. if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
  1994. adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
  1995. adapter->rx_buf_per_pkt = 1;
  1996. } else {
  1997. adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
  1998. sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
  1999. VMXNET3_MAX_ETH_HDR_SIZE;
  2000. adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
  2001. }
  2002. /*
  2003. * for simplicity, force the ring0 size to be a multiple of
  2004. * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
  2005. */
  2006. sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
  2007. ring0_size = adapter->rx_queue[0].rx_ring[0].size;
  2008. ring0_size = (ring0_size + sz - 1) / sz * sz;
  2009. ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
  2010. sz * sz);
  2011. ring1_size = adapter->rx_queue[0].rx_ring[1].size;
  2012. comp_size = ring0_size + ring1_size;
  2013. for (i = 0; i < adapter->num_rx_queues; i++) {
  2014. rq = &adapter->rx_queue[i];
  2015. rq->rx_ring[0].size = ring0_size;
  2016. rq->rx_ring[1].size = ring1_size;
  2017. rq->comp_ring.size = comp_size;
  2018. }
  2019. }
  2020. int
  2021. vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
  2022. u32 rx_ring_size, u32 rx_ring2_size)
  2023. {
  2024. int err = 0, i;
  2025. for (i = 0; i < adapter->num_tx_queues; i++) {
  2026. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  2027. tq->tx_ring.size = tx_ring_size;
  2028. tq->data_ring.size = tx_ring_size;
  2029. tq->comp_ring.size = tx_ring_size;
  2030. tq->shared = &adapter->tqd_start[i].ctrl;
  2031. tq->stopped = true;
  2032. tq->adapter = adapter;
  2033. tq->qid = i;
  2034. err = vmxnet3_tq_create(tq, adapter);
  2035. /*
  2036. * Too late to change num_tx_queues. We cannot do away with
  2037. * lesser number of queues than what we asked for
  2038. */
  2039. if (err)
  2040. goto queue_err;
  2041. }
  2042. adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
  2043. adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
  2044. vmxnet3_adjust_rx_ring_size(adapter);
  2045. for (i = 0; i < adapter->num_rx_queues; i++) {
  2046. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  2047. /* qid and qid2 for rx queues will be assigned later when num
  2048. * of rx queues is finalized after allocating intrs */
  2049. rq->shared = &adapter->rqd_start[i].ctrl;
  2050. rq->adapter = adapter;
  2051. err = vmxnet3_rq_create(rq, adapter);
  2052. if (err) {
  2053. if (i == 0) {
  2054. printk(KERN_ERR "Could not allocate any rx"
  2055. "queues. Aborting.\n");
  2056. goto queue_err;
  2057. } else {
  2058. printk(KERN_INFO "Number of rx queues changed "
  2059. "to : %d.\n", i);
  2060. adapter->num_rx_queues = i;
  2061. err = 0;
  2062. break;
  2063. }
  2064. }
  2065. }
  2066. return err;
  2067. queue_err:
  2068. vmxnet3_tq_destroy_all(adapter);
  2069. return err;
  2070. }
  2071. static int
  2072. vmxnet3_open(struct net_device *netdev)
  2073. {
  2074. struct vmxnet3_adapter *adapter;
  2075. int err, i;
  2076. adapter = netdev_priv(netdev);
  2077. for (i = 0; i < adapter->num_tx_queues; i++)
  2078. spin_lock_init(&adapter->tx_queue[i].tx_lock);
  2079. err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
  2080. VMXNET3_DEF_RX_RING_SIZE,
  2081. VMXNET3_DEF_RX_RING_SIZE);
  2082. if (err)
  2083. goto queue_err;
  2084. err = vmxnet3_activate_dev(adapter);
  2085. if (err)
  2086. goto activate_err;
  2087. return 0;
  2088. activate_err:
  2089. vmxnet3_rq_destroy_all(adapter);
  2090. vmxnet3_tq_destroy_all(adapter);
  2091. queue_err:
  2092. return err;
  2093. }
  2094. static int
  2095. vmxnet3_close(struct net_device *netdev)
  2096. {
  2097. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2098. /*
  2099. * Reset_work may be in the middle of resetting the device, wait for its
  2100. * completion.
  2101. */
  2102. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2103. msleep(1);
  2104. vmxnet3_quiesce_dev(adapter);
  2105. vmxnet3_rq_destroy_all(adapter);
  2106. vmxnet3_tq_destroy_all(adapter);
  2107. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2108. return 0;
  2109. }
  2110. void
  2111. vmxnet3_force_close(struct vmxnet3_adapter *adapter)
  2112. {
  2113. int i;
  2114. /*
  2115. * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
  2116. * vmxnet3_close() will deadlock.
  2117. */
  2118. BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
  2119. /* we need to enable NAPI, otherwise dev_close will deadlock */
  2120. for (i = 0; i < adapter->num_rx_queues; i++)
  2121. napi_enable(&adapter->rx_queue[i].napi);
  2122. dev_close(adapter->netdev);
  2123. }
  2124. static int
  2125. vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
  2126. {
  2127. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2128. int err = 0;
  2129. if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
  2130. return -EINVAL;
  2131. if (new_mtu > 1500 && !adapter->jumbo_frame)
  2132. return -EINVAL;
  2133. netdev->mtu = new_mtu;
  2134. /*
  2135. * Reset_work may be in the middle of resetting the device, wait for its
  2136. * completion.
  2137. */
  2138. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2139. msleep(1);
  2140. if (netif_running(netdev)) {
  2141. vmxnet3_quiesce_dev(adapter);
  2142. vmxnet3_reset_dev(adapter);
  2143. /* we need to re-create the rx queue based on the new mtu */
  2144. vmxnet3_rq_destroy_all(adapter);
  2145. vmxnet3_adjust_rx_ring_size(adapter);
  2146. err = vmxnet3_rq_create_all(adapter);
  2147. if (err) {
  2148. printk(KERN_ERR "%s: failed to re-create rx queues,"
  2149. " error %d. Closing it.\n", netdev->name, err);
  2150. goto out;
  2151. }
  2152. err = vmxnet3_activate_dev(adapter);
  2153. if (err) {
  2154. printk(KERN_ERR "%s: failed to re-activate, error %d. "
  2155. "Closing it\n", netdev->name, err);
  2156. goto out;
  2157. }
  2158. }
  2159. out:
  2160. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2161. if (err)
  2162. vmxnet3_force_close(adapter);
  2163. return err;
  2164. }
  2165. static void
  2166. vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
  2167. {
  2168. struct net_device *netdev = adapter->netdev;
  2169. netdev->features = NETIF_F_SG |
  2170. NETIF_F_HW_CSUM |
  2171. NETIF_F_HW_VLAN_TX |
  2172. NETIF_F_HW_VLAN_RX |
  2173. NETIF_F_HW_VLAN_FILTER |
  2174. NETIF_F_TSO |
  2175. NETIF_F_TSO6 |
  2176. NETIF_F_LRO;
  2177. printk(KERN_INFO "features: sg csum vlan jf tso tsoIPv6 lro");
  2178. adapter->rxcsum = true;
  2179. adapter->jumbo_frame = true;
  2180. adapter->lro = true;
  2181. if (dma64) {
  2182. netdev->features |= NETIF_F_HIGHDMA;
  2183. printk(" highDMA");
  2184. }
  2185. netdev->vlan_features = netdev->features;
  2186. printk("\n");
  2187. }
  2188. static void
  2189. vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  2190. {
  2191. u32 tmp;
  2192. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
  2193. *(u32 *)mac = tmp;
  2194. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
  2195. mac[4] = tmp & 0xff;
  2196. mac[5] = (tmp >> 8) & 0xff;
  2197. }
  2198. #ifdef CONFIG_PCI_MSI
  2199. /*
  2200. * Enable MSIx vectors.
  2201. * Returns :
  2202. * 0 on successful enabling of required vectors,
  2203. * VMXNET3_LINUX_MIN_MSIX_VECT when only minumum number of vectors required
  2204. * could be enabled.
  2205. * number of vectors which can be enabled otherwise (this number is smaller
  2206. * than VMXNET3_LINUX_MIN_MSIX_VECT)
  2207. */
  2208. static int
  2209. vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
  2210. int vectors)
  2211. {
  2212. int err = 0, vector_threshold;
  2213. vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
  2214. while (vectors >= vector_threshold) {
  2215. err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
  2216. vectors);
  2217. if (!err) {
  2218. adapter->intr.num_intrs = vectors;
  2219. return 0;
  2220. } else if (err < 0) {
  2221. printk(KERN_ERR "Failed to enable MSI-X for %s, error"
  2222. " %d\n", adapter->netdev->name, err);
  2223. vectors = 0;
  2224. } else if (err < vector_threshold) {
  2225. break;
  2226. } else {
  2227. /* If fails to enable required number of MSI-x vectors
  2228. * try enabling 3 of them. One each for rx, tx and event
  2229. */
  2230. vectors = vector_threshold;
  2231. printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
  2232. " %d instead\n", vectors, adapter->netdev->name,
  2233. vector_threshold);
  2234. }
  2235. }
  2236. printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
  2237. " are lower than min threshold required.\n");
  2238. return err;
  2239. }
  2240. #endif /* CONFIG_PCI_MSI */
  2241. static void
  2242. vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
  2243. {
  2244. u32 cfg;
  2245. /* intr settings */
  2246. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2247. VMXNET3_CMD_GET_CONF_INTR);
  2248. cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  2249. adapter->intr.type = cfg & 0x3;
  2250. adapter->intr.mask_mode = (cfg >> 2) & 0x3;
  2251. if (adapter->intr.type == VMXNET3_IT_AUTO) {
  2252. adapter->intr.type = VMXNET3_IT_MSIX;
  2253. }
  2254. #ifdef CONFIG_PCI_MSI
  2255. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2256. int vector, err = 0;
  2257. adapter->intr.num_intrs = (adapter->share_intr ==
  2258. VMXNET3_INTR_TXSHARE) ? 1 :
  2259. adapter->num_tx_queues;
  2260. adapter->intr.num_intrs += (adapter->share_intr ==
  2261. VMXNET3_INTR_BUDDYSHARE) ? 0 :
  2262. adapter->num_rx_queues;
  2263. adapter->intr.num_intrs += 1; /* for link event */
  2264. adapter->intr.num_intrs = (adapter->intr.num_intrs >
  2265. VMXNET3_LINUX_MIN_MSIX_VECT
  2266. ? adapter->intr.num_intrs :
  2267. VMXNET3_LINUX_MIN_MSIX_VECT);
  2268. for (vector = 0; vector < adapter->intr.num_intrs; vector++)
  2269. adapter->intr.msix_entries[vector].entry = vector;
  2270. err = vmxnet3_acquire_msix_vectors(adapter,
  2271. adapter->intr.num_intrs);
  2272. /* If we cannot allocate one MSIx vector per queue
  2273. * then limit the number of rx queues to 1
  2274. */
  2275. if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
  2276. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
  2277. || adapter->num_rx_queues != 2) {
  2278. adapter->share_intr = VMXNET3_INTR_TXSHARE;
  2279. printk(KERN_ERR "Number of rx queues : 1\n");
  2280. adapter->num_rx_queues = 1;
  2281. adapter->intr.num_intrs =
  2282. VMXNET3_LINUX_MIN_MSIX_VECT;
  2283. }
  2284. return;
  2285. }
  2286. if (!err)
  2287. return;
  2288. /* If we cannot allocate MSIx vectors use only one rx queue */
  2289. printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
  2290. "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
  2291. adapter->intr.type = VMXNET3_IT_MSI;
  2292. }
  2293. if (adapter->intr.type == VMXNET3_IT_MSI) {
  2294. int err;
  2295. err = pci_enable_msi(adapter->pdev);
  2296. if (!err) {
  2297. adapter->num_rx_queues = 1;
  2298. adapter->intr.num_intrs = 1;
  2299. return;
  2300. }
  2301. }
  2302. #endif /* CONFIG_PCI_MSI */
  2303. adapter->num_rx_queues = 1;
  2304. printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
  2305. adapter->intr.type = VMXNET3_IT_INTX;
  2306. /* INT-X related setting */
  2307. adapter->intr.num_intrs = 1;
  2308. }
  2309. static void
  2310. vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
  2311. {
  2312. if (adapter->intr.type == VMXNET3_IT_MSIX)
  2313. pci_disable_msix(adapter->pdev);
  2314. else if (adapter->intr.type == VMXNET3_IT_MSI)
  2315. pci_disable_msi(adapter->pdev);
  2316. else
  2317. BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
  2318. }
  2319. static void
  2320. vmxnet3_tx_timeout(struct net_device *netdev)
  2321. {
  2322. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2323. adapter->tx_timeout_count++;
  2324. printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
  2325. schedule_work(&adapter->work);
  2326. netif_wake_queue(adapter->netdev);
  2327. }
  2328. static void
  2329. vmxnet3_reset_work(struct work_struct *data)
  2330. {
  2331. struct vmxnet3_adapter *adapter;
  2332. adapter = container_of(data, struct vmxnet3_adapter, work);
  2333. /* if another thread is resetting the device, no need to proceed */
  2334. if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2335. return;
  2336. /* if the device is closed, we must leave it alone */
  2337. rtnl_lock();
  2338. if (netif_running(adapter->netdev)) {
  2339. printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
  2340. vmxnet3_quiesce_dev(adapter);
  2341. vmxnet3_reset_dev(adapter);
  2342. vmxnet3_activate_dev(adapter);
  2343. } else {
  2344. printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
  2345. }
  2346. rtnl_unlock();
  2347. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2348. }
  2349. static int __devinit
  2350. vmxnet3_probe_device(struct pci_dev *pdev,
  2351. const struct pci_device_id *id)
  2352. {
  2353. static const struct net_device_ops vmxnet3_netdev_ops = {
  2354. .ndo_open = vmxnet3_open,
  2355. .ndo_stop = vmxnet3_close,
  2356. .ndo_start_xmit = vmxnet3_xmit_frame,
  2357. .ndo_set_mac_address = vmxnet3_set_mac_addr,
  2358. .ndo_change_mtu = vmxnet3_change_mtu,
  2359. .ndo_get_stats = vmxnet3_get_stats,
  2360. .ndo_tx_timeout = vmxnet3_tx_timeout,
  2361. .ndo_set_multicast_list = vmxnet3_set_mc,
  2362. .ndo_vlan_rx_register = vmxnet3_vlan_rx_register,
  2363. .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
  2364. .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
  2365. #ifdef CONFIG_NET_POLL_CONTROLLER
  2366. .ndo_poll_controller = vmxnet3_netpoll,
  2367. #endif
  2368. };
  2369. int err;
  2370. bool dma64 = false; /* stupid gcc */
  2371. u32 ver;
  2372. struct net_device *netdev;
  2373. struct vmxnet3_adapter *adapter;
  2374. u8 mac[ETH_ALEN];
  2375. int size;
  2376. int num_tx_queues;
  2377. int num_rx_queues;
  2378. #ifdef VMXNET3_RSS
  2379. if (enable_mq)
  2380. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2381. (int)num_online_cpus());
  2382. else
  2383. #endif
  2384. num_rx_queues = 1;
  2385. if (enable_mq)
  2386. num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
  2387. (int)num_online_cpus());
  2388. else
  2389. num_tx_queues = 1;
  2390. netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
  2391. max(num_tx_queues, num_rx_queues));
  2392. printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
  2393. num_tx_queues, num_rx_queues);
  2394. if (!netdev) {
  2395. printk(KERN_ERR "Failed to alloc ethernet device for adapter "
  2396. "%s\n", pci_name(pdev));
  2397. return -ENOMEM;
  2398. }
  2399. pci_set_drvdata(pdev, netdev);
  2400. adapter = netdev_priv(netdev);
  2401. adapter->netdev = netdev;
  2402. adapter->pdev = pdev;
  2403. adapter->shared = pci_alloc_consistent(adapter->pdev,
  2404. sizeof(struct Vmxnet3_DriverShared),
  2405. &adapter->shared_pa);
  2406. if (!adapter->shared) {
  2407. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2408. pci_name(pdev));
  2409. err = -ENOMEM;
  2410. goto err_alloc_shared;
  2411. }
  2412. adapter->num_rx_queues = num_rx_queues;
  2413. adapter->num_tx_queues = num_tx_queues;
  2414. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2415. size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
  2416. adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
  2417. &adapter->queue_desc_pa);
  2418. if (!adapter->tqd_start) {
  2419. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2420. pci_name(pdev));
  2421. err = -ENOMEM;
  2422. goto err_alloc_queue_desc;
  2423. }
  2424. adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
  2425. adapter->num_tx_queues);
  2426. adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
  2427. if (adapter->pm_conf == NULL) {
  2428. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2429. pci_name(pdev));
  2430. err = -ENOMEM;
  2431. goto err_alloc_pm;
  2432. }
  2433. #ifdef VMXNET3_RSS
  2434. adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
  2435. if (adapter->rss_conf == NULL) {
  2436. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2437. pci_name(pdev));
  2438. err = -ENOMEM;
  2439. goto err_alloc_rss;
  2440. }
  2441. #endif /* VMXNET3_RSS */
  2442. err = vmxnet3_alloc_pci_resources(adapter, &dma64);
  2443. if (err < 0)
  2444. goto err_alloc_pci;
  2445. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
  2446. if (ver & 1) {
  2447. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
  2448. } else {
  2449. printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
  2450. " %s\n", ver, pci_name(pdev));
  2451. err = -EBUSY;
  2452. goto err_ver;
  2453. }
  2454. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
  2455. if (ver & 1) {
  2456. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
  2457. } else {
  2458. printk(KERN_ERR "Incompatible upt version (0x%x) for "
  2459. "adapter %s\n", ver, pci_name(pdev));
  2460. err = -EBUSY;
  2461. goto err_ver;
  2462. }
  2463. vmxnet3_declare_features(adapter, dma64);
  2464. adapter->dev_number = atomic_read(&devices_found);
  2465. adapter->share_intr = irq_share_mode;
  2466. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
  2467. adapter->num_tx_queues != adapter->num_rx_queues)
  2468. adapter->share_intr = VMXNET3_INTR_DONTSHARE;
  2469. vmxnet3_alloc_intr_resources(adapter);
  2470. #ifdef VMXNET3_RSS
  2471. if (adapter->num_rx_queues > 1 &&
  2472. adapter->intr.type == VMXNET3_IT_MSIX) {
  2473. adapter->rss = true;
  2474. printk(KERN_INFO "RSS is enabled.\n");
  2475. } else {
  2476. adapter->rss = false;
  2477. }
  2478. #endif
  2479. vmxnet3_read_mac_addr(adapter, mac);
  2480. memcpy(netdev->dev_addr, mac, netdev->addr_len);
  2481. netdev->netdev_ops = &vmxnet3_netdev_ops;
  2482. vmxnet3_set_ethtool_ops(netdev);
  2483. netdev->watchdog_timeo = 5 * HZ;
  2484. INIT_WORK(&adapter->work, vmxnet3_reset_work);
  2485. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2486. int i;
  2487. for (i = 0; i < adapter->num_rx_queues; i++) {
  2488. netif_napi_add(adapter->netdev,
  2489. &adapter->rx_queue[i].napi,
  2490. vmxnet3_poll_rx_only, 64);
  2491. }
  2492. } else {
  2493. netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
  2494. vmxnet3_poll, 64);
  2495. }
  2496. netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
  2497. netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
  2498. SET_NETDEV_DEV(netdev, &pdev->dev);
  2499. err = register_netdev(netdev);
  2500. if (err) {
  2501. printk(KERN_ERR "Failed to register adapter %s\n",
  2502. pci_name(pdev));
  2503. goto err_register;
  2504. }
  2505. set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  2506. vmxnet3_check_link(adapter, false);
  2507. atomic_inc(&devices_found);
  2508. return 0;
  2509. err_register:
  2510. vmxnet3_free_intr_resources(adapter);
  2511. err_ver:
  2512. vmxnet3_free_pci_resources(adapter);
  2513. err_alloc_pci:
  2514. #ifdef VMXNET3_RSS
  2515. kfree(adapter->rss_conf);
  2516. err_alloc_rss:
  2517. #endif
  2518. kfree(adapter->pm_conf);
  2519. err_alloc_pm:
  2520. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2521. adapter->queue_desc_pa);
  2522. err_alloc_queue_desc:
  2523. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2524. adapter->shared, adapter->shared_pa);
  2525. err_alloc_shared:
  2526. pci_set_drvdata(pdev, NULL);
  2527. free_netdev(netdev);
  2528. return err;
  2529. }
  2530. static void __devexit
  2531. vmxnet3_remove_device(struct pci_dev *pdev)
  2532. {
  2533. struct net_device *netdev = pci_get_drvdata(pdev);
  2534. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2535. int size = 0;
  2536. int num_rx_queues;
  2537. #ifdef VMXNET3_RSS
  2538. if (enable_mq)
  2539. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2540. (int)num_online_cpus());
  2541. else
  2542. #endif
  2543. num_rx_queues = 1;
  2544. cancel_work_sync(&adapter->work);
  2545. unregister_netdev(netdev);
  2546. vmxnet3_free_intr_resources(adapter);
  2547. vmxnet3_free_pci_resources(adapter);
  2548. #ifdef VMXNET3_RSS
  2549. kfree(adapter->rss_conf);
  2550. #endif
  2551. kfree(adapter->pm_conf);
  2552. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2553. size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
  2554. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2555. adapter->queue_desc_pa);
  2556. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2557. adapter->shared, adapter->shared_pa);
  2558. free_netdev(netdev);
  2559. }
  2560. #ifdef CONFIG_PM
  2561. static int
  2562. vmxnet3_suspend(struct device *device)
  2563. {
  2564. struct pci_dev *pdev = to_pci_dev(device);
  2565. struct net_device *netdev = pci_get_drvdata(pdev);
  2566. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2567. struct Vmxnet3_PMConf *pmConf;
  2568. struct ethhdr *ehdr;
  2569. struct arphdr *ahdr;
  2570. u8 *arpreq;
  2571. struct in_device *in_dev;
  2572. struct in_ifaddr *ifa;
  2573. int i = 0;
  2574. if (!netif_running(netdev))
  2575. return 0;
  2576. vmxnet3_disable_all_intrs(adapter);
  2577. vmxnet3_free_irqs(adapter);
  2578. vmxnet3_free_intr_resources(adapter);
  2579. netif_device_detach(netdev);
  2580. netif_tx_stop_all_queues(netdev);
  2581. /* Create wake-up filters. */
  2582. pmConf = adapter->pm_conf;
  2583. memset(pmConf, 0, sizeof(*pmConf));
  2584. if (adapter->wol & WAKE_UCAST) {
  2585. pmConf->filters[i].patternSize = ETH_ALEN;
  2586. pmConf->filters[i].maskSize = 1;
  2587. memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
  2588. pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
  2589. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2590. i++;
  2591. }
  2592. if (adapter->wol & WAKE_ARP) {
  2593. in_dev = in_dev_get(netdev);
  2594. if (!in_dev)
  2595. goto skip_arp;
  2596. ifa = (struct in_ifaddr *)in_dev->ifa_list;
  2597. if (!ifa)
  2598. goto skip_arp;
  2599. pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
  2600. sizeof(struct arphdr) + /* ARP header */
  2601. 2 * ETH_ALEN + /* 2 Ethernet addresses*/
  2602. 2 * sizeof(u32); /*2 IPv4 addresses */
  2603. pmConf->filters[i].maskSize =
  2604. (pmConf->filters[i].patternSize - 1) / 8 + 1;
  2605. /* ETH_P_ARP in Ethernet header. */
  2606. ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
  2607. ehdr->h_proto = htons(ETH_P_ARP);
  2608. /* ARPOP_REQUEST in ARP header. */
  2609. ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
  2610. ahdr->ar_op = htons(ARPOP_REQUEST);
  2611. arpreq = (u8 *)(ahdr + 1);
  2612. /* The Unicast IPv4 address in 'tip' field. */
  2613. arpreq += 2 * ETH_ALEN + sizeof(u32);
  2614. *(u32 *)arpreq = ifa->ifa_address;
  2615. /* The mask for the relevant bits. */
  2616. pmConf->filters[i].mask[0] = 0x00;
  2617. pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
  2618. pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
  2619. pmConf->filters[i].mask[3] = 0x00;
  2620. pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
  2621. pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
  2622. in_dev_put(in_dev);
  2623. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2624. i++;
  2625. }
  2626. skip_arp:
  2627. if (adapter->wol & WAKE_MAGIC)
  2628. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
  2629. pmConf->numFilters = i;
  2630. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2631. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2632. *pmConf));
  2633. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2634. pmConf));
  2635. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2636. VMXNET3_CMD_UPDATE_PMCFG);
  2637. pci_save_state(pdev);
  2638. pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
  2639. adapter->wol);
  2640. pci_disable_device(pdev);
  2641. pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
  2642. return 0;
  2643. }
  2644. static int
  2645. vmxnet3_resume(struct device *device)
  2646. {
  2647. int err;
  2648. struct pci_dev *pdev = to_pci_dev(device);
  2649. struct net_device *netdev = pci_get_drvdata(pdev);
  2650. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2651. struct Vmxnet3_PMConf *pmConf;
  2652. if (!netif_running(netdev))
  2653. return 0;
  2654. /* Destroy wake-up filters. */
  2655. pmConf = adapter->pm_conf;
  2656. memset(pmConf, 0, sizeof(*pmConf));
  2657. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2658. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2659. *pmConf));
  2660. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2661. pmConf));
  2662. netif_device_attach(netdev);
  2663. pci_set_power_state(pdev, PCI_D0);
  2664. pci_restore_state(pdev);
  2665. err = pci_enable_device_mem(pdev);
  2666. if (err != 0)
  2667. return err;
  2668. pci_enable_wake(pdev, PCI_D0, 0);
  2669. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2670. VMXNET3_CMD_UPDATE_PMCFG);
  2671. vmxnet3_alloc_intr_resources(adapter);
  2672. vmxnet3_request_irqs(adapter);
  2673. vmxnet3_enable_all_intrs(adapter);
  2674. return 0;
  2675. }
  2676. static const struct dev_pm_ops vmxnet3_pm_ops = {
  2677. .suspend = vmxnet3_suspend,
  2678. .resume = vmxnet3_resume,
  2679. };
  2680. #endif
  2681. static struct pci_driver vmxnet3_driver = {
  2682. .name = vmxnet3_driver_name,
  2683. .id_table = vmxnet3_pciid_table,
  2684. .probe = vmxnet3_probe_device,
  2685. .remove = __devexit_p(vmxnet3_remove_device),
  2686. #ifdef CONFIG_PM
  2687. .driver.pm = &vmxnet3_pm_ops,
  2688. #endif
  2689. };
  2690. static int __init
  2691. vmxnet3_init_module(void)
  2692. {
  2693. printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
  2694. VMXNET3_DRIVER_VERSION_REPORT);
  2695. return pci_register_driver(&vmxnet3_driver);
  2696. }
  2697. module_init(vmxnet3_init_module);
  2698. static void
  2699. vmxnet3_exit_module(void)
  2700. {
  2701. pci_unregister_driver(&vmxnet3_driver);
  2702. }
  2703. module_exit(vmxnet3_exit_module);
  2704. MODULE_AUTHOR("VMware, Inc.");
  2705. MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
  2706. MODULE_LICENSE("GPL v2");
  2707. MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);