radeon_object.c 15 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <drm/drmP.h>
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. struct radeon_object {
  37. struct ttm_buffer_object tobj;
  38. struct list_head list;
  39. struct radeon_device *rdev;
  40. struct drm_gem_object *gobj;
  41. struct ttm_bo_kmap_obj kmap;
  42. unsigned pin_count;
  43. uint64_t gpu_addr;
  44. void *kptr;
  45. bool is_iomem;
  46. uint32_t tiling_flags;
  47. uint32_t pitch;
  48. int surface_reg;
  49. };
  50. int radeon_ttm_init(struct radeon_device *rdev);
  51. void radeon_ttm_fini(struct radeon_device *rdev);
  52. /*
  53. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  54. * function are calling it.
  55. */
  56. static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
  57. {
  58. return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
  59. }
  60. static void radeon_object_unreserve(struct radeon_object *robj)
  61. {
  62. ttm_bo_unreserve(&robj->tobj);
  63. }
  64. static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
  65. {
  66. struct radeon_object *robj;
  67. robj = container_of(tobj, struct radeon_object, tobj);
  68. list_del_init(&robj->list);
  69. radeon_object_clear_surface_reg(robj);
  70. kfree(robj);
  71. }
  72. static inline void radeon_object_gpu_addr(struct radeon_object *robj)
  73. {
  74. /* Default gpu address */
  75. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  76. if (robj->tobj.mem.mm_node == NULL) {
  77. return;
  78. }
  79. robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
  80. switch (robj->tobj.mem.mem_type) {
  81. case TTM_PL_VRAM:
  82. robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
  83. break;
  84. case TTM_PL_TT:
  85. robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
  86. break;
  87. default:
  88. DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
  89. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  90. return;
  91. }
  92. }
  93. static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
  94. {
  95. uint32_t flags = 0;
  96. if (domain & RADEON_GEM_DOMAIN_VRAM) {
  97. flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
  98. }
  99. if (domain & RADEON_GEM_DOMAIN_GTT) {
  100. flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  101. }
  102. if (domain & RADEON_GEM_DOMAIN_CPU) {
  103. flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
  104. }
  105. if (!flags) {
  106. flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
  107. }
  108. return flags;
  109. }
  110. int radeon_object_create(struct radeon_device *rdev,
  111. struct drm_gem_object *gobj,
  112. unsigned long size,
  113. bool kernel,
  114. uint32_t domain,
  115. bool interruptible,
  116. struct radeon_object **robj_ptr)
  117. {
  118. struct radeon_object *robj;
  119. enum ttm_bo_type type;
  120. uint32_t flags;
  121. int r;
  122. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  123. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  124. }
  125. if (kernel) {
  126. type = ttm_bo_type_kernel;
  127. } else {
  128. type = ttm_bo_type_device;
  129. }
  130. *robj_ptr = NULL;
  131. robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
  132. if (robj == NULL) {
  133. return -ENOMEM;
  134. }
  135. robj->rdev = rdev;
  136. robj->gobj = gobj;
  137. robj->surface_reg = -1;
  138. INIT_LIST_HEAD(&robj->list);
  139. flags = radeon_object_flags_from_domain(domain);
  140. r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
  141. 0, 0, false, NULL, size,
  142. &radeon_ttm_object_object_destroy);
  143. if (unlikely(r != 0)) {
  144. /* ttm call radeon_ttm_object_object_destroy if error happen */
  145. DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
  146. size, flags, 0);
  147. return r;
  148. }
  149. *robj_ptr = robj;
  150. if (gobj) {
  151. list_add_tail(&robj->list, &rdev->gem.objects);
  152. }
  153. return 0;
  154. }
  155. int radeon_object_kmap(struct radeon_object *robj, void **ptr)
  156. {
  157. int r;
  158. spin_lock(&robj->tobj.lock);
  159. if (robj->kptr) {
  160. if (ptr) {
  161. *ptr = robj->kptr;
  162. }
  163. spin_unlock(&robj->tobj.lock);
  164. return 0;
  165. }
  166. spin_unlock(&robj->tobj.lock);
  167. r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
  168. if (r) {
  169. return r;
  170. }
  171. spin_lock(&robj->tobj.lock);
  172. robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
  173. spin_unlock(&robj->tobj.lock);
  174. if (ptr) {
  175. *ptr = robj->kptr;
  176. }
  177. return 0;
  178. }
  179. void radeon_object_kunmap(struct radeon_object *robj)
  180. {
  181. spin_lock(&robj->tobj.lock);
  182. if (robj->kptr == NULL) {
  183. spin_unlock(&robj->tobj.lock);
  184. return;
  185. }
  186. robj->kptr = NULL;
  187. spin_unlock(&robj->tobj.lock);
  188. ttm_bo_kunmap(&robj->kmap);
  189. }
  190. void radeon_object_unref(struct radeon_object **robj)
  191. {
  192. struct ttm_buffer_object *tobj;
  193. if ((*robj) == NULL) {
  194. return;
  195. }
  196. tobj = &((*robj)->tobj);
  197. ttm_bo_unref(&tobj);
  198. if (tobj == NULL) {
  199. *robj = NULL;
  200. }
  201. }
  202. int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
  203. {
  204. *offset = robj->tobj.addr_space_offset;
  205. return 0;
  206. }
  207. int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
  208. uint64_t *gpu_addr)
  209. {
  210. uint32_t flags;
  211. uint32_t tmp;
  212. int r;
  213. flags = radeon_object_flags_from_domain(domain);
  214. spin_lock(&robj->tobj.lock);
  215. if (robj->pin_count) {
  216. robj->pin_count++;
  217. if (gpu_addr != NULL) {
  218. *gpu_addr = robj->gpu_addr;
  219. }
  220. spin_unlock(&robj->tobj.lock);
  221. return 0;
  222. }
  223. spin_unlock(&robj->tobj.lock);
  224. r = radeon_object_reserve(robj, false);
  225. if (unlikely(r != 0)) {
  226. DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
  227. return r;
  228. }
  229. tmp = robj->tobj.mem.placement;
  230. ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
  231. robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
  232. r = ttm_buffer_object_validate(&robj->tobj,
  233. robj->tobj.proposed_placement,
  234. false, false);
  235. radeon_object_gpu_addr(robj);
  236. if (gpu_addr != NULL) {
  237. *gpu_addr = robj->gpu_addr;
  238. }
  239. robj->pin_count = 1;
  240. if (unlikely(r != 0)) {
  241. DRM_ERROR("radeon: failed to pin object.\n");
  242. }
  243. radeon_object_unreserve(robj);
  244. return r;
  245. }
  246. void radeon_object_unpin(struct radeon_object *robj)
  247. {
  248. uint32_t flags;
  249. int r;
  250. spin_lock(&robj->tobj.lock);
  251. if (!robj->pin_count) {
  252. spin_unlock(&robj->tobj.lock);
  253. printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
  254. return;
  255. }
  256. robj->pin_count--;
  257. if (robj->pin_count) {
  258. spin_unlock(&robj->tobj.lock);
  259. return;
  260. }
  261. spin_unlock(&robj->tobj.lock);
  262. r = radeon_object_reserve(robj, false);
  263. if (unlikely(r != 0)) {
  264. DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
  265. return;
  266. }
  267. flags = robj->tobj.mem.placement;
  268. robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
  269. r = ttm_buffer_object_validate(&robj->tobj,
  270. robj->tobj.proposed_placement,
  271. false, false);
  272. if (unlikely(r != 0)) {
  273. DRM_ERROR("radeon: failed to unpin buffer.\n");
  274. }
  275. radeon_object_unreserve(robj);
  276. }
  277. int radeon_object_wait(struct radeon_object *robj)
  278. {
  279. int r = 0;
  280. /* FIXME: should use block reservation instead */
  281. r = radeon_object_reserve(robj, true);
  282. if (unlikely(r != 0)) {
  283. DRM_ERROR("radeon: failed to reserve object for waiting.\n");
  284. return r;
  285. }
  286. spin_lock(&robj->tobj.lock);
  287. if (robj->tobj.sync_obj) {
  288. r = ttm_bo_wait(&robj->tobj, true, true, false);
  289. }
  290. spin_unlock(&robj->tobj.lock);
  291. radeon_object_unreserve(robj);
  292. return r;
  293. }
  294. int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement)
  295. {
  296. int r = 0;
  297. r = radeon_object_reserve(robj, true);
  298. if (unlikely(r != 0)) {
  299. DRM_ERROR("radeon: failed to reserve object for waiting.\n");
  300. return r;
  301. }
  302. spin_lock(&robj->tobj.lock);
  303. *cur_placement = robj->tobj.mem.mem_type;
  304. if (robj->tobj.sync_obj) {
  305. r = ttm_bo_wait(&robj->tobj, true, true, true);
  306. }
  307. spin_unlock(&robj->tobj.lock);
  308. radeon_object_unreserve(robj);
  309. return r;
  310. }
  311. int radeon_object_evict_vram(struct radeon_device *rdev)
  312. {
  313. if (rdev->flags & RADEON_IS_IGP) {
  314. /* Useless to evict on IGP chips */
  315. return 0;
  316. }
  317. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  318. }
  319. void radeon_object_force_delete(struct radeon_device *rdev)
  320. {
  321. struct radeon_object *robj, *n;
  322. struct drm_gem_object *gobj;
  323. if (list_empty(&rdev->gem.objects)) {
  324. return;
  325. }
  326. DRM_ERROR("Userspace still has active objects !\n");
  327. list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
  328. mutex_lock(&rdev->ddev->struct_mutex);
  329. gobj = robj->gobj;
  330. DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
  331. gobj, robj, (unsigned long)gobj->size,
  332. *((unsigned long *)&gobj->refcount));
  333. list_del_init(&robj->list);
  334. radeon_object_unref(&robj);
  335. gobj->driver_private = NULL;
  336. drm_gem_object_unreference(gobj);
  337. mutex_unlock(&rdev->ddev->struct_mutex);
  338. }
  339. }
  340. int radeon_object_init(struct radeon_device *rdev)
  341. {
  342. return radeon_ttm_init(rdev);
  343. }
  344. void radeon_object_fini(struct radeon_device *rdev)
  345. {
  346. radeon_ttm_fini(rdev);
  347. }
  348. void radeon_object_list_add_object(struct radeon_object_list *lobj,
  349. struct list_head *head)
  350. {
  351. if (lobj->wdomain) {
  352. list_add(&lobj->list, head);
  353. } else {
  354. list_add_tail(&lobj->list, head);
  355. }
  356. }
  357. int radeon_object_list_reserve(struct list_head *head)
  358. {
  359. struct radeon_object_list *lobj;
  360. struct list_head *i;
  361. int r;
  362. list_for_each(i, head) {
  363. lobj = list_entry(i, struct radeon_object_list, list);
  364. if (!lobj->robj->pin_count) {
  365. r = radeon_object_reserve(lobj->robj, true);
  366. if (unlikely(r != 0)) {
  367. DRM_ERROR("radeon: failed to reserve object.\n");
  368. return r;
  369. }
  370. } else {
  371. }
  372. }
  373. return 0;
  374. }
  375. void radeon_object_list_unreserve(struct list_head *head)
  376. {
  377. struct radeon_object_list *lobj;
  378. struct list_head *i;
  379. list_for_each(i, head) {
  380. lobj = list_entry(i, struct radeon_object_list, list);
  381. if (!lobj->robj->pin_count) {
  382. radeon_object_unreserve(lobj->robj);
  383. } else {
  384. }
  385. }
  386. }
  387. int radeon_object_list_validate(struct list_head *head, void *fence)
  388. {
  389. struct radeon_object_list *lobj;
  390. struct radeon_object *robj;
  391. struct radeon_fence *old_fence = NULL;
  392. struct list_head *i;
  393. int r;
  394. r = radeon_object_list_reserve(head);
  395. if (unlikely(r != 0)) {
  396. radeon_object_list_unreserve(head);
  397. return r;
  398. }
  399. list_for_each(i, head) {
  400. lobj = list_entry(i, struct radeon_object_list, list);
  401. robj = lobj->robj;
  402. if (!robj->pin_count) {
  403. if (lobj->wdomain) {
  404. robj->tobj.proposed_placement =
  405. radeon_object_flags_from_domain(lobj->wdomain);
  406. } else {
  407. robj->tobj.proposed_placement =
  408. radeon_object_flags_from_domain(lobj->rdomain);
  409. }
  410. r = ttm_buffer_object_validate(&robj->tobj,
  411. robj->tobj.proposed_placement,
  412. true, false);
  413. if (unlikely(r)) {
  414. DRM_ERROR("radeon: failed to validate.\n");
  415. return r;
  416. }
  417. radeon_object_gpu_addr(robj);
  418. }
  419. lobj->gpu_offset = robj->gpu_addr;
  420. lobj->tiling_flags = robj->tiling_flags;
  421. if (fence) {
  422. old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
  423. robj->tobj.sync_obj = radeon_fence_ref(fence);
  424. robj->tobj.sync_obj_arg = NULL;
  425. }
  426. if (old_fence) {
  427. radeon_fence_unref(&old_fence);
  428. }
  429. }
  430. return 0;
  431. }
  432. void radeon_object_list_unvalidate(struct list_head *head)
  433. {
  434. struct radeon_object_list *lobj;
  435. struct radeon_fence *old_fence = NULL;
  436. struct list_head *i;
  437. list_for_each(i, head) {
  438. lobj = list_entry(i, struct radeon_object_list, list);
  439. old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
  440. lobj->robj->tobj.sync_obj = NULL;
  441. if (old_fence) {
  442. radeon_fence_unref(&old_fence);
  443. }
  444. }
  445. radeon_object_list_unreserve(head);
  446. }
  447. void radeon_object_list_clean(struct list_head *head)
  448. {
  449. radeon_object_list_unreserve(head);
  450. }
  451. int radeon_object_fbdev_mmap(struct radeon_object *robj,
  452. struct vm_area_struct *vma)
  453. {
  454. return ttm_fbdev_mmap(vma, &robj->tobj);
  455. }
  456. unsigned long radeon_object_size(struct radeon_object *robj)
  457. {
  458. return robj->tobj.num_pages << PAGE_SHIFT;
  459. }
  460. int radeon_object_get_surface_reg(struct radeon_object *robj)
  461. {
  462. struct radeon_device *rdev = robj->rdev;
  463. struct radeon_surface_reg *reg;
  464. struct radeon_object *old_object;
  465. int steal;
  466. int i;
  467. if (!robj->tiling_flags)
  468. return 0;
  469. if (robj->surface_reg >= 0) {
  470. reg = &rdev->surface_regs[robj->surface_reg];
  471. i = robj->surface_reg;
  472. goto out;
  473. }
  474. steal = -1;
  475. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  476. reg = &rdev->surface_regs[i];
  477. if (!reg->robj)
  478. break;
  479. old_object = reg->robj;
  480. if (old_object->pin_count == 0)
  481. steal = i;
  482. }
  483. /* if we are all out */
  484. if (i == RADEON_GEM_MAX_SURFACES) {
  485. if (steal == -1)
  486. return -ENOMEM;
  487. /* find someone with a surface reg and nuke their BO */
  488. reg = &rdev->surface_regs[steal];
  489. old_object = reg->robj;
  490. /* blow away the mapping */
  491. DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
  492. ttm_bo_unmap_virtual(&old_object->tobj);
  493. old_object->surface_reg = -1;
  494. i = steal;
  495. }
  496. robj->surface_reg = i;
  497. reg->robj = robj;
  498. out:
  499. radeon_set_surface_reg(rdev, i, robj->tiling_flags, robj->pitch,
  500. robj->tobj.mem.mm_node->start << PAGE_SHIFT,
  501. robj->tobj.num_pages << PAGE_SHIFT);
  502. return 0;
  503. }
  504. void radeon_object_clear_surface_reg(struct radeon_object *robj)
  505. {
  506. struct radeon_device *rdev = robj->rdev;
  507. struct radeon_surface_reg *reg;
  508. if (robj->surface_reg == -1)
  509. return;
  510. reg = &rdev->surface_regs[robj->surface_reg];
  511. radeon_clear_surface_reg(rdev, robj->surface_reg);
  512. reg->robj = NULL;
  513. robj->surface_reg = -1;
  514. }
  515. void radeon_object_set_tiling_flags(struct radeon_object *robj,
  516. uint32_t tiling_flags, uint32_t pitch)
  517. {
  518. robj->tiling_flags = tiling_flags;
  519. robj->pitch = pitch;
  520. }
  521. void radeon_object_get_tiling_flags(struct radeon_object *robj,
  522. uint32_t *tiling_flags,
  523. uint32_t *pitch)
  524. {
  525. if (tiling_flags)
  526. *tiling_flags = robj->tiling_flags;
  527. if (pitch)
  528. *pitch = robj->pitch;
  529. }
  530. int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
  531. bool force_drop)
  532. {
  533. if (!(robj->tiling_flags & RADEON_TILING_SURFACE))
  534. return 0;
  535. if (force_drop) {
  536. radeon_object_clear_surface_reg(robj);
  537. return 0;
  538. }
  539. if (robj->tobj.mem.mem_type != TTM_PL_VRAM) {
  540. if (!has_moved)
  541. return 0;
  542. if (robj->surface_reg >= 0)
  543. radeon_object_clear_surface_reg(robj);
  544. return 0;
  545. }
  546. if ((robj->surface_reg >= 0) && !has_moved)
  547. return 0;
  548. return radeon_object_get_surface_reg(robj);
  549. }
  550. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  551. struct ttm_mem_reg *mem)
  552. {
  553. struct radeon_object *robj = container_of(bo, struct radeon_object, tobj);
  554. radeon_object_check_tiling(robj, 0, 1);
  555. }
  556. void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
  557. {
  558. struct radeon_object *robj = container_of(bo, struct radeon_object, tobj);
  559. radeon_object_check_tiling(robj, 0, 0);
  560. }