coda.c 57 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/genalloc.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/module.h>
  21. #include <linux/of_device.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #include <linux/videodev2.h>
  25. #include <linux/of.h>
  26. #include <linux/platform_data/coda.h>
  27. #include <media/v4l2-ctrls.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-ioctl.h>
  30. #include <media/v4l2-mem2mem.h>
  31. #include <media/videobuf2-core.h>
  32. #include <media/videobuf2-dma-contig.h>
  33. #include "coda.h"
  34. #define CODA_NAME "coda"
  35. #define CODA_MAX_INSTANCES 4
  36. #define CODA_FMO_BUF_SIZE 32
  37. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  39. #define CODA_PARA_BUF_SIZE (10 * 1024)
  40. #define CODA_ISRAM_SIZE (2048 * 2)
  41. #define CODADX6_IRAM_SIZE 0xb000
  42. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  43. #define CODA_MAX_FRAMEBUFFERS 2
  44. #define MAX_W 720
  45. #define MAX_H 576
  46. #define CODA_MAX_FRAME_SIZE 0x90000
  47. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  48. #define CODA_DEFAULT_GAMMA 4096
  49. #define MIN_W 176
  50. #define MIN_H 144
  51. #define MAX_W 720
  52. #define MAX_H 576
  53. #define S_ALIGN 1 /* multiple of 2 */
  54. #define W_ALIGN 1 /* multiple of 2 */
  55. #define H_ALIGN 1 /* multiple of 2 */
  56. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  57. static int coda_debug;
  58. module_param(coda_debug, int, 0644);
  59. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  60. enum {
  61. V4L2_M2M_SRC = 0,
  62. V4L2_M2M_DST = 1,
  63. };
  64. enum coda_fmt_type {
  65. CODA_FMT_ENC,
  66. CODA_FMT_RAW,
  67. };
  68. enum coda_inst_type {
  69. CODA_INST_ENCODER,
  70. CODA_INST_DECODER,
  71. };
  72. enum coda_product {
  73. CODA_DX6 = 0xf001,
  74. CODA_7541 = 0xf012,
  75. };
  76. struct coda_fmt {
  77. char *name;
  78. u32 fourcc;
  79. enum coda_fmt_type type;
  80. };
  81. struct coda_devtype {
  82. char *firmware;
  83. enum coda_product product;
  84. struct coda_fmt *formats;
  85. unsigned int num_formats;
  86. size_t workbuf_size;
  87. };
  88. /* Per-queue, driver-specific private data */
  89. struct coda_q_data {
  90. unsigned int width;
  91. unsigned int height;
  92. unsigned int sizeimage;
  93. struct coda_fmt *fmt;
  94. };
  95. struct coda_aux_buf {
  96. void *vaddr;
  97. dma_addr_t paddr;
  98. u32 size;
  99. };
  100. struct coda_dev {
  101. struct v4l2_device v4l2_dev;
  102. struct video_device vfd;
  103. struct platform_device *plat_dev;
  104. const struct coda_devtype *devtype;
  105. void __iomem *regs_base;
  106. struct clk *clk_per;
  107. struct clk *clk_ahb;
  108. struct coda_aux_buf codebuf;
  109. struct coda_aux_buf workbuf;
  110. struct gen_pool *iram_pool;
  111. long unsigned int iram_vaddr;
  112. long unsigned int iram_paddr;
  113. unsigned long iram_size;
  114. spinlock_t irqlock;
  115. struct mutex dev_mutex;
  116. struct v4l2_m2m_dev *m2m_dev;
  117. struct vb2_alloc_ctx *alloc_ctx;
  118. struct list_head instances;
  119. unsigned long instance_mask;
  120. struct delayed_work timeout;
  121. struct completion done;
  122. };
  123. struct coda_params {
  124. u8 rot_mode;
  125. u8 h264_intra_qp;
  126. u8 h264_inter_qp;
  127. u8 mpeg4_intra_qp;
  128. u8 mpeg4_inter_qp;
  129. u8 gop_size;
  130. int codec_mode;
  131. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  132. u32 framerate;
  133. u16 bitrate;
  134. u32 slice_max_bits;
  135. u32 slice_max_mb;
  136. };
  137. struct coda_ctx {
  138. struct coda_dev *dev;
  139. struct list_head list;
  140. int aborting;
  141. int rawstreamon;
  142. int compstreamon;
  143. u32 isequence;
  144. struct coda_q_data q_data[2];
  145. enum coda_inst_type inst_type;
  146. enum v4l2_colorspace colorspace;
  147. struct coda_params params;
  148. struct v4l2_m2m_ctx *m2m_ctx;
  149. struct v4l2_ctrl_handler ctrls;
  150. struct v4l2_fh fh;
  151. int gopcounter;
  152. char vpu_header[3][64];
  153. int vpu_header_size[3];
  154. struct coda_aux_buf parabuf;
  155. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  156. int num_internal_frames;
  157. int idx;
  158. };
  159. static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
  160. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80 };
  161. static const u8 coda_filler_size[8] = { 0, 7, 14, 13, 12, 11, 10, 9 };
  162. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  163. {
  164. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  165. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  166. writel(data, dev->regs_base + reg);
  167. }
  168. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  169. {
  170. u32 data;
  171. data = readl(dev->regs_base + reg);
  172. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  173. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  174. return data;
  175. }
  176. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  177. {
  178. return coda_read(dev, CODA_REG_BIT_BUSY);
  179. }
  180. static inline int coda_is_initialized(struct coda_dev *dev)
  181. {
  182. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  183. }
  184. static int coda_wait_timeout(struct coda_dev *dev)
  185. {
  186. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  187. while (coda_isbusy(dev)) {
  188. if (time_after(jiffies, timeout))
  189. return -ETIMEDOUT;
  190. }
  191. return 0;
  192. }
  193. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  194. {
  195. struct coda_dev *dev = ctx->dev;
  196. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  197. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  198. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  199. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  200. }
  201. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  202. {
  203. struct coda_dev *dev = ctx->dev;
  204. coda_command_async(ctx, cmd);
  205. return coda_wait_timeout(dev);
  206. }
  207. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  208. enum v4l2_buf_type type)
  209. {
  210. switch (type) {
  211. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  212. return &(ctx->q_data[V4L2_M2M_SRC]);
  213. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  214. return &(ctx->q_data[V4L2_M2M_DST]);
  215. default:
  216. BUG();
  217. }
  218. return NULL;
  219. }
  220. /*
  221. * Add one array of supported formats for each version of Coda:
  222. * i.MX27 -> codadx6
  223. * i.MX51 -> coda7
  224. * i.MX6 -> coda960
  225. */
  226. static struct coda_fmt codadx6_formats[] = {
  227. {
  228. .name = "YUV 4:2:0 Planar",
  229. .fourcc = V4L2_PIX_FMT_YUV420,
  230. .type = CODA_FMT_RAW,
  231. },
  232. {
  233. .name = "H264 Encoded Stream",
  234. .fourcc = V4L2_PIX_FMT_H264,
  235. .type = CODA_FMT_ENC,
  236. },
  237. {
  238. .name = "MPEG4 Encoded Stream",
  239. .fourcc = V4L2_PIX_FMT_MPEG4,
  240. .type = CODA_FMT_ENC,
  241. },
  242. };
  243. static struct coda_fmt coda7_formats[] = {
  244. {
  245. .name = "YUV 4:2:0 Planar",
  246. .fourcc = V4L2_PIX_FMT_YUV420,
  247. .type = CODA_FMT_RAW,
  248. },
  249. {
  250. .name = "H264 Encoded Stream",
  251. .fourcc = V4L2_PIX_FMT_H264,
  252. .type = CODA_FMT_ENC,
  253. },
  254. {
  255. .name = "MPEG4 Encoded Stream",
  256. .fourcc = V4L2_PIX_FMT_MPEG4,
  257. .type = CODA_FMT_ENC,
  258. },
  259. };
  260. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  261. {
  262. struct coda_fmt *formats = dev->devtype->formats;
  263. int num_formats = dev->devtype->num_formats;
  264. unsigned int k;
  265. for (k = 0; k < num_formats; k++) {
  266. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  267. break;
  268. }
  269. if (k == num_formats)
  270. return NULL;
  271. return &formats[k];
  272. }
  273. /*
  274. * V4L2 ioctl() operations.
  275. */
  276. static int vidioc_querycap(struct file *file, void *priv,
  277. struct v4l2_capability *cap)
  278. {
  279. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  280. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  281. strlcpy(cap->bus_info, "platform:" CODA_NAME, sizeof(cap->bus_info));
  282. /*
  283. * This is only a mem-to-mem video device. The capture and output
  284. * device capability flags are left only for backward compatibility
  285. * and are scheduled for removal.
  286. */
  287. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  288. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  289. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  290. return 0;
  291. }
  292. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  293. enum coda_fmt_type type)
  294. {
  295. struct coda_ctx *ctx = fh_to_ctx(priv);
  296. struct coda_dev *dev = ctx->dev;
  297. struct coda_fmt *formats = dev->devtype->formats;
  298. struct coda_fmt *fmt;
  299. int num_formats = dev->devtype->num_formats;
  300. int i, num = 0;
  301. for (i = 0; i < num_formats; i++) {
  302. if (formats[i].type == type) {
  303. if (num == f->index)
  304. break;
  305. ++num;
  306. }
  307. }
  308. if (i < num_formats) {
  309. fmt = &formats[i];
  310. strlcpy(f->description, fmt->name, sizeof(f->description));
  311. f->pixelformat = fmt->fourcc;
  312. return 0;
  313. }
  314. /* Format not found */
  315. return -EINVAL;
  316. }
  317. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  318. struct v4l2_fmtdesc *f)
  319. {
  320. return enum_fmt(priv, f, CODA_FMT_ENC);
  321. }
  322. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  323. struct v4l2_fmtdesc *f)
  324. {
  325. return enum_fmt(priv, f, CODA_FMT_RAW);
  326. }
  327. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  328. {
  329. struct vb2_queue *vq;
  330. struct coda_q_data *q_data;
  331. struct coda_ctx *ctx = fh_to_ctx(priv);
  332. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  333. if (!vq)
  334. return -EINVAL;
  335. q_data = get_q_data(ctx, f->type);
  336. f->fmt.pix.field = V4L2_FIELD_NONE;
  337. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  338. f->fmt.pix.width = q_data->width;
  339. f->fmt.pix.height = q_data->height;
  340. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  341. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  342. else /* encoded formats h.264/mpeg4 */
  343. f->fmt.pix.bytesperline = 0;
  344. f->fmt.pix.sizeimage = q_data->sizeimage;
  345. f->fmt.pix.colorspace = ctx->colorspace;
  346. return 0;
  347. }
  348. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  349. {
  350. enum v4l2_field field;
  351. field = f->fmt.pix.field;
  352. if (field == V4L2_FIELD_ANY)
  353. field = V4L2_FIELD_NONE;
  354. else if (V4L2_FIELD_NONE != field)
  355. return -EINVAL;
  356. /* V4L2 specification suggests the driver corrects the format struct
  357. * if any of the dimensions is unsupported */
  358. f->fmt.pix.field = field;
  359. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  360. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  361. W_ALIGN, &f->fmt.pix.height,
  362. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  363. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  364. f->fmt.pix.sizeimage = f->fmt.pix.width *
  365. f->fmt.pix.height * 3 / 2;
  366. } else { /*encoded formats h.264/mpeg4 */
  367. f->fmt.pix.bytesperline = 0;
  368. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  369. }
  370. return 0;
  371. }
  372. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  373. struct v4l2_format *f)
  374. {
  375. int ret;
  376. struct coda_fmt *fmt;
  377. struct coda_ctx *ctx = fh_to_ctx(priv);
  378. fmt = find_format(ctx->dev, f);
  379. /*
  380. * Since decoding support is not implemented yet do not allow
  381. * CODA_FMT_RAW formats in the capture interface.
  382. */
  383. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  384. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  385. f->fmt.pix.colorspace = ctx->colorspace;
  386. ret = vidioc_try_fmt(ctx->dev, f);
  387. if (ret < 0)
  388. return ret;
  389. return 0;
  390. }
  391. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  392. struct v4l2_format *f)
  393. {
  394. struct coda_ctx *ctx = fh_to_ctx(priv);
  395. struct coda_fmt *fmt;
  396. int ret;
  397. fmt = find_format(ctx->dev, f);
  398. /*
  399. * Since decoding support is not implemented yet do not allow
  400. * CODA_FMT formats in the capture interface.
  401. */
  402. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  403. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  404. if (!f->fmt.pix.colorspace)
  405. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  406. ret = vidioc_try_fmt(ctx->dev, f);
  407. if (ret < 0)
  408. return ret;
  409. return 0;
  410. }
  411. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  412. {
  413. struct coda_q_data *q_data;
  414. struct vb2_queue *vq;
  415. int ret;
  416. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  417. if (!vq)
  418. return -EINVAL;
  419. q_data = get_q_data(ctx, f->type);
  420. if (!q_data)
  421. return -EINVAL;
  422. if (vb2_is_busy(vq)) {
  423. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  424. return -EBUSY;
  425. }
  426. ret = vidioc_try_fmt(ctx->dev, f);
  427. if (ret)
  428. return ret;
  429. q_data->fmt = find_format(ctx->dev, f);
  430. q_data->width = f->fmt.pix.width;
  431. q_data->height = f->fmt.pix.height;
  432. q_data->sizeimage = f->fmt.pix.sizeimage;
  433. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  434. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  435. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  436. return 0;
  437. }
  438. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  439. struct v4l2_format *f)
  440. {
  441. int ret;
  442. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  443. if (ret)
  444. return ret;
  445. return vidioc_s_fmt(fh_to_ctx(priv), f);
  446. }
  447. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  448. struct v4l2_format *f)
  449. {
  450. struct coda_ctx *ctx = fh_to_ctx(priv);
  451. int ret;
  452. ret = vidioc_try_fmt_vid_out(file, priv, f);
  453. if (ret)
  454. return ret;
  455. ret = vidioc_s_fmt(ctx, f);
  456. if (ret)
  457. ctx->colorspace = f->fmt.pix.colorspace;
  458. return ret;
  459. }
  460. static int vidioc_reqbufs(struct file *file, void *priv,
  461. struct v4l2_requestbuffers *reqbufs)
  462. {
  463. struct coda_ctx *ctx = fh_to_ctx(priv);
  464. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  465. }
  466. static int vidioc_querybuf(struct file *file, void *priv,
  467. struct v4l2_buffer *buf)
  468. {
  469. struct coda_ctx *ctx = fh_to_ctx(priv);
  470. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  471. }
  472. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  473. {
  474. struct coda_ctx *ctx = fh_to_ctx(priv);
  475. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  476. }
  477. static int vidioc_expbuf(struct file *file, void *priv,
  478. struct v4l2_exportbuffer *eb)
  479. {
  480. struct coda_ctx *ctx = fh_to_ctx(priv);
  481. return v4l2_m2m_expbuf(file, ctx->m2m_ctx, eb);
  482. }
  483. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  484. {
  485. struct coda_ctx *ctx = fh_to_ctx(priv);
  486. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  487. }
  488. static int vidioc_streamon(struct file *file, void *priv,
  489. enum v4l2_buf_type type)
  490. {
  491. struct coda_ctx *ctx = fh_to_ctx(priv);
  492. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  493. }
  494. static int vidioc_streamoff(struct file *file, void *priv,
  495. enum v4l2_buf_type type)
  496. {
  497. struct coda_ctx *ctx = fh_to_ctx(priv);
  498. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  499. }
  500. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  501. .vidioc_querycap = vidioc_querycap,
  502. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  503. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  504. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  505. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  506. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  507. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  508. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  509. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  510. .vidioc_reqbufs = vidioc_reqbufs,
  511. .vidioc_querybuf = vidioc_querybuf,
  512. .vidioc_qbuf = vidioc_qbuf,
  513. .vidioc_expbuf = vidioc_expbuf,
  514. .vidioc_dqbuf = vidioc_dqbuf,
  515. .vidioc_streamon = vidioc_streamon,
  516. .vidioc_streamoff = vidioc_streamoff,
  517. };
  518. /*
  519. * Mem-to-mem operations.
  520. */
  521. static void coda_device_run(void *m2m_priv)
  522. {
  523. struct coda_ctx *ctx = m2m_priv;
  524. struct coda_q_data *q_data_src, *q_data_dst;
  525. struct vb2_buffer *src_buf, *dst_buf;
  526. struct coda_dev *dev = ctx->dev;
  527. int force_ipicture;
  528. int quant_param = 0;
  529. u32 picture_y, picture_cb, picture_cr;
  530. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  531. u32 dst_fourcc;
  532. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  533. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  534. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  535. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  536. dst_fourcc = q_data_dst->fmt->fourcc;
  537. src_buf->v4l2_buf.sequence = ctx->isequence;
  538. dst_buf->v4l2_buf.sequence = ctx->isequence;
  539. ctx->isequence++;
  540. /*
  541. * Workaround coda firmware BUG that only marks the first
  542. * frame as IDR. This is a problem for some decoders that can't
  543. * recover when a frame is lost.
  544. */
  545. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  546. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  547. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  548. } else {
  549. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  550. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  551. }
  552. /*
  553. * Copy headers at the beginning of the first frame for H.264 only.
  554. * In MPEG4 they are already copied by the coda.
  555. */
  556. if (src_buf->v4l2_buf.sequence == 0) {
  557. pic_stream_buffer_addr =
  558. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  559. ctx->vpu_header_size[0] +
  560. ctx->vpu_header_size[1] +
  561. ctx->vpu_header_size[2];
  562. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  563. ctx->vpu_header_size[0] -
  564. ctx->vpu_header_size[1] -
  565. ctx->vpu_header_size[2];
  566. memcpy(vb2_plane_vaddr(dst_buf, 0),
  567. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  568. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  569. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  570. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  571. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  572. ctx->vpu_header_size[2]);
  573. } else {
  574. pic_stream_buffer_addr =
  575. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  576. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  577. }
  578. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  579. force_ipicture = 1;
  580. switch (dst_fourcc) {
  581. case V4L2_PIX_FMT_H264:
  582. quant_param = ctx->params.h264_intra_qp;
  583. break;
  584. case V4L2_PIX_FMT_MPEG4:
  585. quant_param = ctx->params.mpeg4_intra_qp;
  586. break;
  587. default:
  588. v4l2_warn(&ctx->dev->v4l2_dev,
  589. "cannot set intra qp, fmt not supported\n");
  590. break;
  591. }
  592. } else {
  593. force_ipicture = 0;
  594. switch (dst_fourcc) {
  595. case V4L2_PIX_FMT_H264:
  596. quant_param = ctx->params.h264_inter_qp;
  597. break;
  598. case V4L2_PIX_FMT_MPEG4:
  599. quant_param = ctx->params.mpeg4_inter_qp;
  600. break;
  601. default:
  602. v4l2_warn(&ctx->dev->v4l2_dev,
  603. "cannot set inter qp, fmt not supported\n");
  604. break;
  605. }
  606. }
  607. /* submit */
  608. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  609. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  610. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  611. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  612. picture_cr = picture_cb + q_data_src->width / 2 *
  613. q_data_src->height / 2;
  614. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  615. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  616. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  617. coda_write(dev, force_ipicture << 1 & 0x2,
  618. CODA_CMD_ENC_PIC_OPTION);
  619. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  620. coda_write(dev, pic_stream_buffer_size / 1024,
  621. CODA_CMD_ENC_PIC_BB_SIZE);
  622. if (dev->devtype->product == CODA_7541) {
  623. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  624. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  625. CODA7_REG_BIT_AXI_SRAM_USE);
  626. }
  627. /* 1 second timeout in case CODA locks up */
  628. schedule_delayed_work(&dev->timeout, HZ);
  629. INIT_COMPLETION(dev->done);
  630. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  631. }
  632. static int coda_job_ready(void *m2m_priv)
  633. {
  634. struct coda_ctx *ctx = m2m_priv;
  635. /*
  636. * For both 'P' and 'key' frame cases 1 picture
  637. * and 1 frame are needed.
  638. */
  639. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  640. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  641. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  642. "not ready: not enough video buffers.\n");
  643. return 0;
  644. }
  645. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  646. "job ready\n");
  647. return 1;
  648. }
  649. static void coda_job_abort(void *priv)
  650. {
  651. struct coda_ctx *ctx = priv;
  652. struct coda_dev *dev = ctx->dev;
  653. ctx->aborting = 1;
  654. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  655. "Aborting task\n");
  656. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  657. }
  658. static void coda_lock(void *m2m_priv)
  659. {
  660. struct coda_ctx *ctx = m2m_priv;
  661. struct coda_dev *pcdev = ctx->dev;
  662. mutex_lock(&pcdev->dev_mutex);
  663. }
  664. static void coda_unlock(void *m2m_priv)
  665. {
  666. struct coda_ctx *ctx = m2m_priv;
  667. struct coda_dev *pcdev = ctx->dev;
  668. mutex_unlock(&pcdev->dev_mutex);
  669. }
  670. static struct v4l2_m2m_ops coda_m2m_ops = {
  671. .device_run = coda_device_run,
  672. .job_ready = coda_job_ready,
  673. .job_abort = coda_job_abort,
  674. .lock = coda_lock,
  675. .unlock = coda_unlock,
  676. };
  677. static void set_default_params(struct coda_ctx *ctx)
  678. {
  679. struct coda_dev *dev = ctx->dev;
  680. ctx->params.codec_mode = CODA_MODE_INVALID;
  681. ctx->colorspace = V4L2_COLORSPACE_REC709;
  682. ctx->params.framerate = 30;
  683. ctx->aborting = 0;
  684. /* Default formats for output and input queues */
  685. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  686. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  687. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  688. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  689. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  690. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  691. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  692. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  693. }
  694. /*
  695. * Queue operations
  696. */
  697. static int coda_queue_setup(struct vb2_queue *vq,
  698. const struct v4l2_format *fmt,
  699. unsigned int *nbuffers, unsigned int *nplanes,
  700. unsigned int sizes[], void *alloc_ctxs[])
  701. {
  702. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  703. struct coda_q_data *q_data;
  704. unsigned int size;
  705. q_data = get_q_data(ctx, vq->type);
  706. size = q_data->sizeimage;
  707. *nplanes = 1;
  708. sizes[0] = size;
  709. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  710. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  711. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  712. return 0;
  713. }
  714. static int coda_buf_prepare(struct vb2_buffer *vb)
  715. {
  716. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  717. struct coda_q_data *q_data;
  718. q_data = get_q_data(ctx, vb->vb2_queue->type);
  719. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  720. v4l2_warn(&ctx->dev->v4l2_dev,
  721. "%s data will not fit into plane (%lu < %lu)\n",
  722. __func__, vb2_plane_size(vb, 0),
  723. (long)q_data->sizeimage);
  724. return -EINVAL;
  725. }
  726. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  727. return 0;
  728. }
  729. static void coda_buf_queue(struct vb2_buffer *vb)
  730. {
  731. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  732. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  733. }
  734. static void coda_wait_prepare(struct vb2_queue *q)
  735. {
  736. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  737. coda_unlock(ctx);
  738. }
  739. static void coda_wait_finish(struct vb2_queue *q)
  740. {
  741. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  742. coda_lock(ctx);
  743. }
  744. static void coda_free_framebuffers(struct coda_ctx *ctx)
  745. {
  746. int i;
  747. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  748. if (ctx->internal_frames[i].vaddr) {
  749. dma_free_coherent(&ctx->dev->plat_dev->dev,
  750. ctx->internal_frames[i].size,
  751. ctx->internal_frames[i].vaddr,
  752. ctx->internal_frames[i].paddr);
  753. ctx->internal_frames[i].vaddr = NULL;
  754. }
  755. }
  756. }
  757. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  758. {
  759. struct coda_dev *dev = ctx->dev;
  760. int height = q_data->height;
  761. int width = q_data->width;
  762. u32 *p;
  763. int i;
  764. /* Allocate frame buffers */
  765. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  766. for (i = 0; i < ctx->num_internal_frames; i++) {
  767. ctx->internal_frames[i].size = q_data->sizeimage;
  768. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  769. ctx->internal_frames[i].size += width / 2 * height / 2;
  770. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  771. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  772. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  773. if (!ctx->internal_frames[i].vaddr) {
  774. coda_free_framebuffers(ctx);
  775. return -ENOMEM;
  776. }
  777. }
  778. /* Register frame buffers in the parameter buffer */
  779. p = ctx->parabuf.vaddr;
  780. if (dev->devtype->product == CODA_DX6) {
  781. for (i = 0; i < ctx->num_internal_frames; i++) {
  782. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  783. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  784. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  785. }
  786. } else {
  787. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  788. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  789. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  790. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  791. if (fourcc == V4L2_PIX_FMT_H264)
  792. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  793. if (i + 1 < ctx->num_internal_frames) {
  794. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  795. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  796. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  797. if (fourcc == V4L2_PIX_FMT_H264)
  798. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  799. }
  800. }
  801. }
  802. return 0;
  803. }
  804. static int coda_h264_padding(int size, char *p)
  805. {
  806. int nal_size;
  807. int diff;
  808. diff = size - (size & ~0x7);
  809. if (diff == 0)
  810. return 0;
  811. nal_size = coda_filler_size[diff];
  812. memcpy(p, coda_filler_nal, nal_size);
  813. /* Add rbsp stop bit and trailing at the end */
  814. *(p + nal_size - 1) = 0x80;
  815. return nal_size;
  816. }
  817. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  818. {
  819. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  820. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  821. u32 bitstream_buf, bitstream_size;
  822. struct coda_dev *dev = ctx->dev;
  823. struct coda_q_data *q_data_src, *q_data_dst;
  824. struct vb2_buffer *buf;
  825. u32 dst_fourcc;
  826. u32 value;
  827. int ret;
  828. if (count < 1)
  829. return -EINVAL;
  830. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  831. ctx->rawstreamon = 1;
  832. else
  833. ctx->compstreamon = 1;
  834. /* Don't start the coda unless both queues are on */
  835. if (!(ctx->rawstreamon & ctx->compstreamon))
  836. return 0;
  837. if (coda_isbusy(dev))
  838. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
  839. return -EBUSY;
  840. ctx->gopcounter = ctx->params.gop_size - 1;
  841. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  842. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  843. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  844. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  845. bitstream_size = q_data_dst->sizeimage;
  846. dst_fourcc = q_data_dst->fmt->fourcc;
  847. /* Find out whether coda must encode or decode */
  848. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  849. q_data_dst->fmt->type == CODA_FMT_ENC) {
  850. ctx->inst_type = CODA_INST_ENCODER;
  851. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  852. q_data_dst->fmt->type == CODA_FMT_RAW) {
  853. ctx->inst_type = CODA_INST_DECODER;
  854. v4l2_err(v4l2_dev, "decoding not supported.\n");
  855. return -EINVAL;
  856. } else {
  857. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  858. return -EINVAL;
  859. }
  860. if (!coda_is_initialized(dev)) {
  861. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  862. return -EFAULT;
  863. }
  864. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  865. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  866. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  867. switch (dev->devtype->product) {
  868. case CODA_DX6:
  869. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  870. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  871. break;
  872. default:
  873. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  874. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  875. }
  876. if (dev->devtype->product == CODA_DX6) {
  877. /* Configure the coda */
  878. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  879. }
  880. /* Could set rotation here if needed */
  881. switch (dev->devtype->product) {
  882. case CODA_DX6:
  883. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  884. break;
  885. default:
  886. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  887. }
  888. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  889. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  890. coda_write(dev, ctx->params.framerate,
  891. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  892. switch (dst_fourcc) {
  893. case V4L2_PIX_FMT_MPEG4:
  894. if (dev->devtype->product == CODA_DX6)
  895. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  896. else
  897. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  898. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  899. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  900. break;
  901. case V4L2_PIX_FMT_H264:
  902. if (dev->devtype->product == CODA_DX6)
  903. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  904. else
  905. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  906. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  907. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  908. break;
  909. default:
  910. v4l2_err(v4l2_dev,
  911. "dst format (0x%08x) invalid.\n", dst_fourcc);
  912. return -EINVAL;
  913. }
  914. switch (ctx->params.slice_mode) {
  915. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  916. value = 0;
  917. break;
  918. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  919. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  920. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  921. value |= 1 & CODA_SLICING_MODE_MASK;
  922. break;
  923. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  924. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  925. value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  926. value |= 1 & CODA_SLICING_MODE_MASK;
  927. break;
  928. }
  929. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  930. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  931. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  932. if (ctx->params.bitrate) {
  933. /* Rate control enabled */
  934. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  935. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  936. } else {
  937. value = 0;
  938. }
  939. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  940. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  941. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  942. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  943. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  944. /* set default gamma */
  945. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  946. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  947. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  948. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  949. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  950. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  951. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  952. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  953. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  954. if (dev->devtype->product == CODA_DX6) {
  955. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  956. } else {
  957. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  958. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  959. }
  960. }
  961. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  962. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  963. return -ETIMEDOUT;
  964. }
  965. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  966. return -EFAULT;
  967. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  968. if (ret < 0)
  969. return ret;
  970. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  971. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  972. if (dev->devtype->product != CODA_DX6) {
  973. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  974. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  975. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  976. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  977. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  978. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  979. }
  980. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  981. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  982. return -ETIMEDOUT;
  983. }
  984. /* Save stream headers */
  985. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  986. switch (dst_fourcc) {
  987. case V4L2_PIX_FMT_H264:
  988. /*
  989. * Get SPS in the first frame and copy it to an
  990. * intermediate buffer.
  991. */
  992. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  993. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  994. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  995. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  996. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  997. return -ETIMEDOUT;
  998. }
  999. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1000. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1001. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1002. ctx->vpu_header_size[0]);
  1003. /*
  1004. * Get PPS in the first frame and copy it to an
  1005. * intermediate buffer.
  1006. */
  1007. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1008. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1009. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  1010. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1011. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1012. return -ETIMEDOUT;
  1013. }
  1014. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1015. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1016. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1017. ctx->vpu_header_size[1]);
  1018. /*
  1019. * Length of H.264 headers is variable and thus it might not be
  1020. * aligned for the coda to append the encoded frame. In that is
  1021. * the case a filler NAL must be added to header 2.
  1022. */
  1023. ctx->vpu_header_size[2] = coda_h264_padding(
  1024. (ctx->vpu_header_size[0] +
  1025. ctx->vpu_header_size[1]),
  1026. ctx->vpu_header[2]);
  1027. break;
  1028. case V4L2_PIX_FMT_MPEG4:
  1029. /*
  1030. * Get VOS in the first frame and copy it to an
  1031. * intermediate buffer
  1032. */
  1033. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1034. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1035. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  1036. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1037. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1038. return -ETIMEDOUT;
  1039. }
  1040. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1041. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1042. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1043. ctx->vpu_header_size[0]);
  1044. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1045. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1046. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1047. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1048. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1049. return -ETIMEDOUT;
  1050. }
  1051. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1052. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1053. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1054. ctx->vpu_header_size[1]);
  1055. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1056. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1057. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1058. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1059. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1060. return -ETIMEDOUT;
  1061. }
  1062. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1063. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1064. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1065. ctx->vpu_header_size[2]);
  1066. break;
  1067. default:
  1068. /* No more formats need to save headers at the moment */
  1069. break;
  1070. }
  1071. return 0;
  1072. }
  1073. static int coda_stop_streaming(struct vb2_queue *q)
  1074. {
  1075. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1076. struct coda_dev *dev = ctx->dev;
  1077. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1078. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1079. "%s: output\n", __func__);
  1080. ctx->rawstreamon = 0;
  1081. } else {
  1082. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1083. "%s: capture\n", __func__);
  1084. ctx->compstreamon = 0;
  1085. }
  1086. /* Don't stop the coda unless both queues are off */
  1087. if (ctx->rawstreamon || ctx->compstreamon)
  1088. return 0;
  1089. if (coda_isbusy(dev)) {
  1090. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
  1091. v4l2_warn(&dev->v4l2_dev,
  1092. "%s: timeout, sending SEQ_END anyway\n", __func__);
  1093. }
  1094. }
  1095. cancel_delayed_work(&dev->timeout);
  1096. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1097. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1098. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1099. v4l2_err(&dev->v4l2_dev,
  1100. "CODA_COMMAND_SEQ_END failed\n");
  1101. return -ETIMEDOUT;
  1102. }
  1103. coda_free_framebuffers(ctx);
  1104. return 0;
  1105. }
  1106. static struct vb2_ops coda_qops = {
  1107. .queue_setup = coda_queue_setup,
  1108. .buf_prepare = coda_buf_prepare,
  1109. .buf_queue = coda_buf_queue,
  1110. .wait_prepare = coda_wait_prepare,
  1111. .wait_finish = coda_wait_finish,
  1112. .start_streaming = coda_start_streaming,
  1113. .stop_streaming = coda_stop_streaming,
  1114. };
  1115. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1116. {
  1117. struct coda_ctx *ctx =
  1118. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1119. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1120. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1121. switch (ctrl->id) {
  1122. case V4L2_CID_HFLIP:
  1123. if (ctrl->val)
  1124. ctx->params.rot_mode |= CODA_MIR_HOR;
  1125. else
  1126. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1127. break;
  1128. case V4L2_CID_VFLIP:
  1129. if (ctrl->val)
  1130. ctx->params.rot_mode |= CODA_MIR_VER;
  1131. else
  1132. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1133. break;
  1134. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1135. ctx->params.bitrate = ctrl->val / 1000;
  1136. break;
  1137. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1138. ctx->params.gop_size = ctrl->val;
  1139. break;
  1140. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1141. ctx->params.h264_intra_qp = ctrl->val;
  1142. break;
  1143. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1144. ctx->params.h264_inter_qp = ctrl->val;
  1145. break;
  1146. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1147. ctx->params.mpeg4_intra_qp = ctrl->val;
  1148. break;
  1149. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1150. ctx->params.mpeg4_inter_qp = ctrl->val;
  1151. break;
  1152. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1153. ctx->params.slice_mode = ctrl->val;
  1154. break;
  1155. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1156. ctx->params.slice_max_mb = ctrl->val;
  1157. break;
  1158. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
  1159. ctx->params.slice_max_bits = ctrl->val * 8;
  1160. break;
  1161. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1162. break;
  1163. default:
  1164. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1165. "Invalid control, id=%d, val=%d\n",
  1166. ctrl->id, ctrl->val);
  1167. return -EINVAL;
  1168. }
  1169. return 0;
  1170. }
  1171. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1172. .s_ctrl = coda_s_ctrl,
  1173. };
  1174. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1175. {
  1176. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1177. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1178. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1179. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1180. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1181. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1182. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1183. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1184. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1185. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1186. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1187. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1188. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1189. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1190. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1191. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1192. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1193. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1194. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1195. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
  1196. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
  1197. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1198. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1199. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1200. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
  1201. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1202. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1203. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1204. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1205. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1206. if (ctx->ctrls.error) {
  1207. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1208. ctx->ctrls.error);
  1209. return -EINVAL;
  1210. }
  1211. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1212. }
  1213. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1214. struct vb2_queue *dst_vq)
  1215. {
  1216. struct coda_ctx *ctx = priv;
  1217. int ret;
  1218. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1219. src_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
  1220. src_vq->drv_priv = ctx;
  1221. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1222. src_vq->ops = &coda_qops;
  1223. src_vq->mem_ops = &vb2_dma_contig_memops;
  1224. src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1225. ret = vb2_queue_init(src_vq);
  1226. if (ret)
  1227. return ret;
  1228. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1229. dst_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
  1230. dst_vq->drv_priv = ctx;
  1231. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1232. dst_vq->ops = &coda_qops;
  1233. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1234. dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1235. return vb2_queue_init(dst_vq);
  1236. }
  1237. static int coda_next_free_instance(struct coda_dev *dev)
  1238. {
  1239. return ffz(dev->instance_mask);
  1240. }
  1241. static int coda_open(struct file *file)
  1242. {
  1243. struct coda_dev *dev = video_drvdata(file);
  1244. struct coda_ctx *ctx = NULL;
  1245. int ret = 0;
  1246. int idx;
  1247. idx = coda_next_free_instance(dev);
  1248. if (idx >= CODA_MAX_INSTANCES)
  1249. return -EBUSY;
  1250. set_bit(idx, &dev->instance_mask);
  1251. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1252. if (!ctx)
  1253. return -ENOMEM;
  1254. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1255. file->private_data = &ctx->fh;
  1256. v4l2_fh_add(&ctx->fh);
  1257. ctx->dev = dev;
  1258. ctx->idx = idx;
  1259. set_default_params(ctx);
  1260. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1261. &coda_queue_init);
  1262. if (IS_ERR(ctx->m2m_ctx)) {
  1263. ret = PTR_ERR(ctx->m2m_ctx);
  1264. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1265. __func__, ret);
  1266. goto err;
  1267. }
  1268. ret = coda_ctrls_setup(ctx);
  1269. if (ret) {
  1270. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1271. goto err;
  1272. }
  1273. ctx->fh.ctrl_handler = &ctx->ctrls;
  1274. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1275. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1276. if (!ctx->parabuf.vaddr) {
  1277. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1278. ret = -ENOMEM;
  1279. goto err;
  1280. }
  1281. coda_lock(ctx);
  1282. list_add(&ctx->list, &dev->instances);
  1283. coda_unlock(ctx);
  1284. clk_prepare_enable(dev->clk_per);
  1285. clk_prepare_enable(dev->clk_ahb);
  1286. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1287. ctx->idx, ctx);
  1288. return 0;
  1289. err:
  1290. v4l2_fh_del(&ctx->fh);
  1291. v4l2_fh_exit(&ctx->fh);
  1292. kfree(ctx);
  1293. return ret;
  1294. }
  1295. static int coda_release(struct file *file)
  1296. {
  1297. struct coda_dev *dev = video_drvdata(file);
  1298. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1299. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1300. ctx);
  1301. coda_lock(ctx);
  1302. list_del(&ctx->list);
  1303. coda_unlock(ctx);
  1304. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1305. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1306. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1307. v4l2_ctrl_handler_free(&ctx->ctrls);
  1308. clk_disable_unprepare(dev->clk_per);
  1309. clk_disable_unprepare(dev->clk_ahb);
  1310. v4l2_fh_del(&ctx->fh);
  1311. v4l2_fh_exit(&ctx->fh);
  1312. clear_bit(ctx->idx, &dev->instance_mask);
  1313. kfree(ctx);
  1314. return 0;
  1315. }
  1316. static unsigned int coda_poll(struct file *file,
  1317. struct poll_table_struct *wait)
  1318. {
  1319. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1320. int ret;
  1321. coda_lock(ctx);
  1322. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1323. coda_unlock(ctx);
  1324. return ret;
  1325. }
  1326. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1327. {
  1328. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1329. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1330. }
  1331. static const struct v4l2_file_operations coda_fops = {
  1332. .owner = THIS_MODULE,
  1333. .open = coda_open,
  1334. .release = coda_release,
  1335. .poll = coda_poll,
  1336. .unlocked_ioctl = video_ioctl2,
  1337. .mmap = coda_mmap,
  1338. };
  1339. static irqreturn_t coda_irq_handler(int irq, void *data)
  1340. {
  1341. struct vb2_buffer *src_buf, *dst_buf;
  1342. struct coda_dev *dev = data;
  1343. u32 wr_ptr, start_ptr;
  1344. struct coda_ctx *ctx;
  1345. cancel_delayed_work(&dev->timeout);
  1346. /* read status register to attend the IRQ */
  1347. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1348. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1349. CODA_REG_BIT_INT_CLEAR);
  1350. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1351. if (ctx == NULL) {
  1352. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1353. return IRQ_HANDLED;
  1354. }
  1355. if (ctx->aborting) {
  1356. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1357. "task has been aborted\n");
  1358. return IRQ_HANDLED;
  1359. }
  1360. if (coda_isbusy(ctx->dev)) {
  1361. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1362. "coda is still busy!!!!\n");
  1363. return IRQ_NONE;
  1364. }
  1365. complete(&dev->done);
  1366. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1367. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1368. /* Get results from the coda */
  1369. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1370. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1371. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1372. /* Calculate bytesused field */
  1373. if (dst_buf->v4l2_buf.sequence == 0) {
  1374. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1375. ctx->vpu_header_size[0] +
  1376. ctx->vpu_header_size[1] +
  1377. ctx->vpu_header_size[2];
  1378. } else {
  1379. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1380. }
  1381. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1382. wr_ptr - start_ptr);
  1383. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1384. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1385. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1386. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1387. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1388. } else {
  1389. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1390. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1391. }
  1392. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1393. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1394. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1395. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1396. ctx->gopcounter--;
  1397. if (ctx->gopcounter < 0)
  1398. ctx->gopcounter = ctx->params.gop_size - 1;
  1399. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1400. "job finished: encoding frame (%d) (%s)\n",
  1401. dst_buf->v4l2_buf.sequence,
  1402. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1403. "KEYFRAME" : "PFRAME");
  1404. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1405. return IRQ_HANDLED;
  1406. }
  1407. static void coda_timeout(struct work_struct *work)
  1408. {
  1409. struct coda_ctx *ctx;
  1410. struct coda_dev *dev = container_of(to_delayed_work(work),
  1411. struct coda_dev, timeout);
  1412. if (completion_done(&dev->done))
  1413. return;
  1414. complete(&dev->done);
  1415. dev_err(&dev->plat_dev->dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1416. mutex_lock(&dev->dev_mutex);
  1417. list_for_each_entry(ctx, &dev->instances, list) {
  1418. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1419. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1420. }
  1421. mutex_unlock(&dev->dev_mutex);
  1422. }
  1423. static u32 coda_supported_firmwares[] = {
  1424. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1425. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1426. };
  1427. static bool coda_firmware_supported(u32 vernum)
  1428. {
  1429. int i;
  1430. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1431. if (vernum == coda_supported_firmwares[i])
  1432. return true;
  1433. return false;
  1434. }
  1435. static char *coda_product_name(int product)
  1436. {
  1437. static char buf[9];
  1438. switch (product) {
  1439. case CODA_DX6:
  1440. return "CodaDx6";
  1441. case CODA_7541:
  1442. return "CODA7541";
  1443. default:
  1444. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1445. return buf;
  1446. }
  1447. }
  1448. static int coda_hw_init(struct coda_dev *dev)
  1449. {
  1450. u16 product, major, minor, release;
  1451. u32 data;
  1452. u16 *p;
  1453. int i;
  1454. clk_prepare_enable(dev->clk_per);
  1455. clk_prepare_enable(dev->clk_ahb);
  1456. /*
  1457. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1458. * The 16-bit chars in the code buffer are in memory access
  1459. * order, re-sort them to CODA order for register download.
  1460. * Data in this SRAM survives a reboot.
  1461. */
  1462. p = (u16 *)dev->codebuf.vaddr;
  1463. if (dev->devtype->product == CODA_DX6) {
  1464. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1465. data = CODA_DOWN_ADDRESS_SET(i) |
  1466. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1467. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1468. }
  1469. } else {
  1470. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1471. data = CODA_DOWN_ADDRESS_SET(i) |
  1472. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1473. 3 - (i % 4)]);
  1474. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1475. }
  1476. }
  1477. /* Tell the BIT where to find everything it needs */
  1478. coda_write(dev, dev->workbuf.paddr,
  1479. CODA_REG_BIT_WORK_BUF_ADDR);
  1480. coda_write(dev, dev->codebuf.paddr,
  1481. CODA_REG_BIT_CODE_BUF_ADDR);
  1482. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1483. /* Set default values */
  1484. switch (dev->devtype->product) {
  1485. case CODA_DX6:
  1486. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1487. break;
  1488. default:
  1489. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1490. }
  1491. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1492. if (dev->devtype->product != CODA_DX6)
  1493. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1494. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1495. CODA_REG_BIT_INT_ENABLE);
  1496. /* Reset VPU and start processor */
  1497. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1498. data |= CODA_REG_RESET_ENABLE;
  1499. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1500. udelay(10);
  1501. data &= ~CODA_REG_RESET_ENABLE;
  1502. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1503. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1504. /* Load firmware */
  1505. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1506. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1507. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1508. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1509. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1510. if (coda_wait_timeout(dev)) {
  1511. clk_disable_unprepare(dev->clk_per);
  1512. clk_disable_unprepare(dev->clk_ahb);
  1513. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1514. return -EIO;
  1515. }
  1516. /* Check we are compatible with the loaded firmware */
  1517. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1518. product = CODA_FIRMWARE_PRODUCT(data);
  1519. major = CODA_FIRMWARE_MAJOR(data);
  1520. minor = CODA_FIRMWARE_MINOR(data);
  1521. release = CODA_FIRMWARE_RELEASE(data);
  1522. clk_disable_unprepare(dev->clk_per);
  1523. clk_disable_unprepare(dev->clk_ahb);
  1524. if (product != dev->devtype->product) {
  1525. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1526. " Version: %u.%u.%u\n",
  1527. coda_product_name(dev->devtype->product),
  1528. coda_product_name(product), major, minor, release);
  1529. return -EINVAL;
  1530. }
  1531. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1532. coda_product_name(product));
  1533. if (coda_firmware_supported(data)) {
  1534. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1535. major, minor, release);
  1536. } else {
  1537. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1538. "%u.%u.%u\n", major, minor, release);
  1539. }
  1540. return 0;
  1541. }
  1542. static void coda_fw_callback(const struct firmware *fw, void *context)
  1543. {
  1544. struct coda_dev *dev = context;
  1545. struct platform_device *pdev = dev->plat_dev;
  1546. int ret;
  1547. if (!fw) {
  1548. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1549. return;
  1550. }
  1551. /* allocate auxiliary per-device code buffer for the BIT processor */
  1552. dev->codebuf.size = fw->size;
  1553. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1554. &dev->codebuf.paddr,
  1555. GFP_KERNEL);
  1556. if (!dev->codebuf.vaddr) {
  1557. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1558. return;
  1559. }
  1560. /* Copy the whole firmware image to the code buffer */
  1561. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1562. release_firmware(fw);
  1563. ret = coda_hw_init(dev);
  1564. if (ret) {
  1565. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1566. return;
  1567. }
  1568. dev->vfd.fops = &coda_fops,
  1569. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1570. dev->vfd.release = video_device_release_empty,
  1571. dev->vfd.lock = &dev->dev_mutex;
  1572. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1573. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1574. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1575. video_set_drvdata(&dev->vfd, dev);
  1576. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1577. if (IS_ERR(dev->alloc_ctx)) {
  1578. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1579. return;
  1580. }
  1581. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1582. if (IS_ERR(dev->m2m_dev)) {
  1583. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1584. goto rel_ctx;
  1585. }
  1586. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1587. if (ret) {
  1588. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1589. goto rel_m2m;
  1590. }
  1591. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1592. dev->vfd.num);
  1593. return;
  1594. rel_m2m:
  1595. v4l2_m2m_release(dev->m2m_dev);
  1596. rel_ctx:
  1597. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1598. }
  1599. static int coda_firmware_request(struct coda_dev *dev)
  1600. {
  1601. char *fw = dev->devtype->firmware;
  1602. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1603. coda_product_name(dev->devtype->product));
  1604. return request_firmware_nowait(THIS_MODULE, true,
  1605. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1606. }
  1607. enum coda_platform {
  1608. CODA_IMX27,
  1609. CODA_IMX53,
  1610. };
  1611. static const struct coda_devtype coda_devdata[] = {
  1612. [CODA_IMX27] = {
  1613. .firmware = "v4l-codadx6-imx27.bin",
  1614. .product = CODA_DX6,
  1615. .formats = codadx6_formats,
  1616. .num_formats = ARRAY_SIZE(codadx6_formats),
  1617. },
  1618. [CODA_IMX53] = {
  1619. .firmware = "v4l-coda7541-imx53.bin",
  1620. .product = CODA_7541,
  1621. .formats = coda7_formats,
  1622. .num_formats = ARRAY_SIZE(coda7_formats),
  1623. },
  1624. };
  1625. static struct platform_device_id coda_platform_ids[] = {
  1626. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1627. { .name = "coda-imx53", .driver_data = CODA_IMX53 },
  1628. { /* sentinel */ }
  1629. };
  1630. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1631. #ifdef CONFIG_OF
  1632. static const struct of_device_id coda_dt_ids[] = {
  1633. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1634. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1635. { /* sentinel */ }
  1636. };
  1637. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1638. #endif
  1639. static int coda_probe(struct platform_device *pdev)
  1640. {
  1641. const struct of_device_id *of_id =
  1642. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1643. const struct platform_device_id *pdev_id;
  1644. struct coda_platform_data *pdata = pdev->dev.platform_data;
  1645. struct device_node *np = pdev->dev.of_node;
  1646. struct gen_pool *pool;
  1647. struct coda_dev *dev;
  1648. struct resource *res;
  1649. int ret, irq;
  1650. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1651. if (!dev) {
  1652. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1653. CODA_NAME);
  1654. return -ENOMEM;
  1655. }
  1656. spin_lock_init(&dev->irqlock);
  1657. INIT_LIST_HEAD(&dev->instances);
  1658. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1659. init_completion(&dev->done);
  1660. complete(&dev->done);
  1661. dev->plat_dev = pdev;
  1662. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1663. if (IS_ERR(dev->clk_per)) {
  1664. dev_err(&pdev->dev, "Could not get per clock\n");
  1665. return PTR_ERR(dev->clk_per);
  1666. }
  1667. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1668. if (IS_ERR(dev->clk_ahb)) {
  1669. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1670. return PTR_ERR(dev->clk_ahb);
  1671. }
  1672. /* Get memory for physical registers */
  1673. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1674. if (res == NULL) {
  1675. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1676. return -ENOENT;
  1677. }
  1678. dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
  1679. if (IS_ERR(dev->regs_base))
  1680. return PTR_ERR(dev->regs_base);
  1681. /* IRQ */
  1682. irq = platform_get_irq(pdev, 0);
  1683. if (irq < 0) {
  1684. dev_err(&pdev->dev, "failed to get irq resource\n");
  1685. return -ENOENT;
  1686. }
  1687. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1688. 0, CODA_NAME, dev) < 0) {
  1689. dev_err(&pdev->dev, "failed to request irq\n");
  1690. return -ENOENT;
  1691. }
  1692. /* Get IRAM pool from device tree or platform data */
  1693. pool = of_get_named_gen_pool(np, "iram", 0);
  1694. if (!pool && pdata)
  1695. pool = dev_get_gen_pool(pdata->iram_dev);
  1696. if (!pool) {
  1697. dev_err(&pdev->dev, "iram pool not available\n");
  1698. return -ENOMEM;
  1699. }
  1700. dev->iram_pool = pool;
  1701. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1702. if (ret)
  1703. return ret;
  1704. mutex_init(&dev->dev_mutex);
  1705. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1706. if (of_id) {
  1707. dev->devtype = of_id->data;
  1708. } else if (pdev_id) {
  1709. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1710. } else {
  1711. v4l2_device_unregister(&dev->v4l2_dev);
  1712. return -EINVAL;
  1713. }
  1714. /* allocate auxiliary per-device buffers for the BIT processor */
  1715. switch (dev->devtype->product) {
  1716. case CODA_DX6:
  1717. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1718. break;
  1719. default:
  1720. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1721. }
  1722. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1723. &dev->workbuf.paddr,
  1724. GFP_KERNEL);
  1725. if (!dev->workbuf.vaddr) {
  1726. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1727. v4l2_device_unregister(&dev->v4l2_dev);
  1728. return -ENOMEM;
  1729. }
  1730. if (dev->devtype->product == CODA_DX6)
  1731. dev->iram_size = CODADX6_IRAM_SIZE;
  1732. else
  1733. dev->iram_size = CODA7_IRAM_SIZE;
  1734. dev->iram_vaddr = gen_pool_alloc(dev->iram_pool, dev->iram_size);
  1735. if (!dev->iram_vaddr) {
  1736. dev_err(&pdev->dev, "unable to alloc iram\n");
  1737. return -ENOMEM;
  1738. }
  1739. dev->iram_paddr = gen_pool_virt_to_phys(dev->iram_pool,
  1740. dev->iram_vaddr);
  1741. platform_set_drvdata(pdev, dev);
  1742. return coda_firmware_request(dev);
  1743. }
  1744. static int coda_remove(struct platform_device *pdev)
  1745. {
  1746. struct coda_dev *dev = platform_get_drvdata(pdev);
  1747. video_unregister_device(&dev->vfd);
  1748. if (dev->m2m_dev)
  1749. v4l2_m2m_release(dev->m2m_dev);
  1750. if (dev->alloc_ctx)
  1751. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1752. v4l2_device_unregister(&dev->v4l2_dev);
  1753. if (dev->iram_vaddr)
  1754. gen_pool_free(dev->iram_pool, dev->iram_vaddr, dev->iram_size);
  1755. if (dev->codebuf.vaddr)
  1756. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1757. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1758. if (dev->workbuf.vaddr)
  1759. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1760. dev->workbuf.paddr);
  1761. return 0;
  1762. }
  1763. static struct platform_driver coda_driver = {
  1764. .probe = coda_probe,
  1765. .remove = coda_remove,
  1766. .driver = {
  1767. .name = CODA_NAME,
  1768. .owner = THIS_MODULE,
  1769. .of_match_table = of_match_ptr(coda_dt_ids),
  1770. },
  1771. .id_table = coda_platform_ids,
  1772. };
  1773. module_platform_driver(coda_driver);
  1774. MODULE_LICENSE("GPL");
  1775. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1776. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");