qla_isr.c 82 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. /**
  20. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  21. * @irq:
  22. * @dev_id: SCSI driver HA context
  23. *
  24. * Called by system whenever the host adapter generates an interrupt.
  25. *
  26. * Returns handled flag.
  27. */
  28. irqreturn_t
  29. qla2100_intr_handler(int irq, void *dev_id)
  30. {
  31. scsi_qla_host_t *vha;
  32. struct qla_hw_data *ha;
  33. struct device_reg_2xxx __iomem *reg;
  34. int status;
  35. unsigned long iter;
  36. uint16_t hccr;
  37. uint16_t mb[4];
  38. struct rsp_que *rsp;
  39. unsigned long flags;
  40. rsp = (struct rsp_que *) dev_id;
  41. if (!rsp) {
  42. ql_log(ql_log_info, NULL, 0x505d,
  43. "%s: NULL response queue pointer.\n", __func__);
  44. return (IRQ_NONE);
  45. }
  46. ha = rsp->hw;
  47. reg = &ha->iobase->isp;
  48. status = 0;
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. vha = pci_get_drvdata(ha->pdev);
  51. for (iter = 50; iter--; ) {
  52. hccr = RD_REG_WORD(&reg->hccr);
  53. if (hccr & HCCR_RISC_PAUSE) {
  54. if (pci_channel_offline(ha->pdev))
  55. break;
  56. /*
  57. * Issue a "HARD" reset in order for the RISC interrupt
  58. * bit to be cleared. Schedule a big hammer to get
  59. * out of the RISC PAUSED state.
  60. */
  61. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  62. RD_REG_WORD(&reg->hccr);
  63. ha->isp_ops->fw_dump(vha, 1);
  64. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  65. break;
  66. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  67. break;
  68. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  69. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  70. RD_REG_WORD(&reg->hccr);
  71. /* Get mailbox data. */
  72. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  73. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  74. qla2x00_mbx_completion(vha, mb[0]);
  75. status |= MBX_INTERRUPT;
  76. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  77. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  78. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  79. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  80. qla2x00_async_event(vha, rsp, mb);
  81. } else {
  82. /*EMPTY*/
  83. ql_dbg(ql_dbg_async, vha, 0x5025,
  84. "Unrecognized interrupt type (%d).\n",
  85. mb[0]);
  86. }
  87. /* Release mailbox registers. */
  88. WRT_REG_WORD(&reg->semaphore, 0);
  89. RD_REG_WORD(&reg->semaphore);
  90. } else {
  91. qla2x00_process_response_queue(rsp);
  92. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  93. RD_REG_WORD(&reg->hccr);
  94. }
  95. }
  96. qla2x00_handle_mbx_completion(ha, status);
  97. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  98. return (IRQ_HANDLED);
  99. }
  100. /**
  101. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  102. * @irq:
  103. * @dev_id: SCSI driver HA context
  104. *
  105. * Called by system whenever the host adapter generates an interrupt.
  106. *
  107. * Returns handled flag.
  108. */
  109. irqreturn_t
  110. qla2300_intr_handler(int irq, void *dev_id)
  111. {
  112. scsi_qla_host_t *vha;
  113. struct device_reg_2xxx __iomem *reg;
  114. int status;
  115. unsigned long iter;
  116. uint32_t stat;
  117. uint16_t hccr;
  118. uint16_t mb[4];
  119. struct rsp_que *rsp;
  120. struct qla_hw_data *ha;
  121. unsigned long flags;
  122. rsp = (struct rsp_que *) dev_id;
  123. if (!rsp) {
  124. ql_log(ql_log_info, NULL, 0x5058,
  125. "%s: NULL response queue pointer.\n", __func__);
  126. return (IRQ_NONE);
  127. }
  128. ha = rsp->hw;
  129. reg = &ha->iobase->isp;
  130. status = 0;
  131. spin_lock_irqsave(&ha->hardware_lock, flags);
  132. vha = pci_get_drvdata(ha->pdev);
  133. for (iter = 50; iter--; ) {
  134. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  135. if (stat & HSR_RISC_PAUSED) {
  136. if (unlikely(pci_channel_offline(ha->pdev)))
  137. break;
  138. hccr = RD_REG_WORD(&reg->hccr);
  139. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  140. ql_log(ql_log_warn, vha, 0x5026,
  141. "Parity error -- HCCR=%x, Dumping "
  142. "firmware.\n", hccr);
  143. else
  144. ql_log(ql_log_warn, vha, 0x5027,
  145. "RISC paused -- HCCR=%x, Dumping "
  146. "firmware.\n", hccr);
  147. /*
  148. * Issue a "HARD" reset in order for the RISC
  149. * interrupt bit to be cleared. Schedule a big
  150. * hammer to get out of the RISC PAUSED state.
  151. */
  152. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  153. RD_REG_WORD(&reg->hccr);
  154. ha->isp_ops->fw_dump(vha, 1);
  155. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  156. break;
  157. } else if ((stat & HSR_RISC_INT) == 0)
  158. break;
  159. switch (stat & 0xff) {
  160. case 0x1:
  161. case 0x2:
  162. case 0x10:
  163. case 0x11:
  164. qla2x00_mbx_completion(vha, MSW(stat));
  165. status |= MBX_INTERRUPT;
  166. /* Release mailbox registers. */
  167. WRT_REG_WORD(&reg->semaphore, 0);
  168. break;
  169. case 0x12:
  170. mb[0] = MSW(stat);
  171. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  172. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  173. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  174. qla2x00_async_event(vha, rsp, mb);
  175. break;
  176. case 0x13:
  177. qla2x00_process_response_queue(rsp);
  178. break;
  179. case 0x15:
  180. mb[0] = MBA_CMPLT_1_16BIT;
  181. mb[1] = MSW(stat);
  182. qla2x00_async_event(vha, rsp, mb);
  183. break;
  184. case 0x16:
  185. mb[0] = MBA_SCSI_COMPLETION;
  186. mb[1] = MSW(stat);
  187. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  188. qla2x00_async_event(vha, rsp, mb);
  189. break;
  190. default:
  191. ql_dbg(ql_dbg_async, vha, 0x5028,
  192. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  193. break;
  194. }
  195. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  196. RD_REG_WORD_RELAXED(&reg->hccr);
  197. }
  198. qla2x00_handle_mbx_completion(ha, status);
  199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  200. return (IRQ_HANDLED);
  201. }
  202. /**
  203. * qla2x00_mbx_completion() - Process mailbox command completions.
  204. * @ha: SCSI driver HA context
  205. * @mb0: Mailbox0 register
  206. */
  207. static void
  208. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  209. {
  210. uint16_t cnt;
  211. uint32_t mboxes;
  212. uint16_t __iomem *wptr;
  213. struct qla_hw_data *ha = vha->hw;
  214. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  215. /* Read all mbox registers? */
  216. mboxes = (1 << ha->mbx_count) - 1;
  217. if (!ha->mcp)
  218. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  219. else
  220. mboxes = ha->mcp->in_mb;
  221. /* Load return mailbox registers. */
  222. ha->flags.mbox_int = 1;
  223. ha->mailbox_out[0] = mb0;
  224. mboxes >>= 1;
  225. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  226. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  227. if (IS_QLA2200(ha) && cnt == 8)
  228. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  229. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  230. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  231. else if (mboxes & BIT_0)
  232. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  233. wptr++;
  234. mboxes >>= 1;
  235. }
  236. }
  237. static void
  238. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  239. {
  240. static char *event[] =
  241. { "Complete", "Request Notification", "Time Extension" };
  242. int rval;
  243. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  244. uint16_t __iomem *wptr;
  245. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  246. /* Seed data -- mailbox1 -> mailbox7. */
  247. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  248. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  249. mb[cnt] = RD_REG_WORD(wptr);
  250. ql_dbg(ql_dbg_async, vha, 0x5021,
  251. "Inter-Driver Communication %s -- "
  252. "%04x %04x %04x %04x %04x %04x %04x.\n",
  253. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  254. mb[4], mb[5], mb[6]);
  255. switch (aen) {
  256. /* Handle IDC Error completion case. */
  257. case MBA_IDC_COMPLETE:
  258. if (mb[1] >> 15) {
  259. vha->hw->flags.idc_compl_status = 1;
  260. if (vha->hw->notify_dcbx_comp)
  261. complete(&vha->hw->dcbx_comp);
  262. }
  263. break;
  264. case MBA_IDC_NOTIFY:
  265. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  266. timeout = (descr >> 8) & 0xf;
  267. ql_dbg(ql_dbg_async, vha, 0x5022,
  268. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  269. vha->host_no, event[aen & 0xff], timeout);
  270. if (!timeout)
  271. return;
  272. rval = qla2x00_post_idc_ack_work(vha, mb);
  273. if (rval != QLA_SUCCESS)
  274. ql_log(ql_log_warn, vha, 0x5023,
  275. "IDC failed to post ACK.\n");
  276. break;
  277. case MBA_IDC_TIME_EXT:
  278. vha->hw->idc_extend_tmo = descr;
  279. ql_dbg(ql_dbg_async, vha, 0x5087,
  280. "%lu Inter-Driver Communication %s -- "
  281. "Extend timeout by=%d.\n",
  282. vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
  283. break;
  284. }
  285. }
  286. #define LS_UNKNOWN 2
  287. const char *
  288. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  289. {
  290. static const char * const link_speeds[] = {
  291. "1", "2", "?", "4", "8", "16", "10"
  292. };
  293. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  294. return link_speeds[0];
  295. else if (speed == 0x13)
  296. return link_speeds[6];
  297. else if (speed < 6)
  298. return link_speeds[speed];
  299. else
  300. return link_speeds[LS_UNKNOWN];
  301. }
  302. static void
  303. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  304. {
  305. struct qla_hw_data *ha = vha->hw;
  306. /*
  307. * 8200 AEN Interpretation:
  308. * mb[0] = AEN code
  309. * mb[1] = AEN Reason code
  310. * mb[2] = LSW of Peg-Halt Status-1 Register
  311. * mb[6] = MSW of Peg-Halt Status-1 Register
  312. * mb[3] = LSW of Peg-Halt Status-2 register
  313. * mb[7] = MSW of Peg-Halt Status-2 register
  314. * mb[4] = IDC Device-State Register value
  315. * mb[5] = IDC Driver-Presence Register value
  316. */
  317. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  318. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  319. mb[0], mb[1], mb[2], mb[6]);
  320. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  321. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  322. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  323. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  324. IDC_HEARTBEAT_FAILURE)) {
  325. ha->flags.nic_core_hung = 1;
  326. ql_log(ql_log_warn, vha, 0x5060,
  327. "83XX: F/W Error Reported: Check if reset required.\n");
  328. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  329. uint32_t protocol_engine_id, fw_err_code, err_level;
  330. /*
  331. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  332. * - PEG-Halt Status-1 Register:
  333. * (LSW = mb[2], MSW = mb[6])
  334. * Bits 0-7 = protocol-engine ID
  335. * Bits 8-28 = f/w error code
  336. * Bits 29-31 = Error-level
  337. * Error-level 0x1 = Non-Fatal error
  338. * Error-level 0x2 = Recoverable Fatal error
  339. * Error-level 0x4 = UnRecoverable Fatal error
  340. * - PEG-Halt Status-2 Register:
  341. * (LSW = mb[3], MSW = mb[7])
  342. */
  343. protocol_engine_id = (mb[2] & 0xff);
  344. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  345. ((mb[6] & 0x1fff) << 8));
  346. err_level = ((mb[6] & 0xe000) >> 13);
  347. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  348. "Register: protocol_engine_id=0x%x "
  349. "fw_err_code=0x%x err_level=0x%x.\n",
  350. protocol_engine_id, fw_err_code, err_level);
  351. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  352. "Register: 0x%x%x.\n", mb[7], mb[3]);
  353. if (err_level == ERR_LEVEL_NON_FATAL) {
  354. ql_log(ql_log_warn, vha, 0x5063,
  355. "Not a fatal error, f/w has recovered "
  356. "iteself.\n");
  357. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  358. ql_log(ql_log_fatal, vha, 0x5064,
  359. "Recoverable Fatal error: Chip reset "
  360. "required.\n");
  361. qla83xx_schedule_work(vha,
  362. QLA83XX_NIC_CORE_RESET);
  363. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  364. ql_log(ql_log_fatal, vha, 0x5065,
  365. "Unrecoverable Fatal error: Set FAILED "
  366. "state, reboot required.\n");
  367. qla83xx_schedule_work(vha,
  368. QLA83XX_NIC_CORE_UNRECOVERABLE);
  369. }
  370. }
  371. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  372. uint16_t peg_fw_state, nw_interface_link_up;
  373. uint16_t nw_interface_signal_detect, sfp_status;
  374. uint16_t htbt_counter, htbt_monitor_enable;
  375. uint16_t sfp_additonal_info, sfp_multirate;
  376. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  377. /*
  378. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  379. * - PEG-to-FC Status Register:
  380. * (LSW = mb[2], MSW = mb[6])
  381. * Bits 0-7 = Peg-Firmware state
  382. * Bit 8 = N/W Interface Link-up
  383. * Bit 9 = N/W Interface signal detected
  384. * Bits 10-11 = SFP Status
  385. * SFP Status 0x0 = SFP+ transceiver not expected
  386. * SFP Status 0x1 = SFP+ transceiver not present
  387. * SFP Status 0x2 = SFP+ transceiver invalid
  388. * SFP Status 0x3 = SFP+ transceiver present and
  389. * valid
  390. * Bits 12-14 = Heartbeat Counter
  391. * Bit 15 = Heartbeat Monitor Enable
  392. * Bits 16-17 = SFP Additional Info
  393. * SFP info 0x0 = Unregocnized transceiver for
  394. * Ethernet
  395. * SFP info 0x1 = SFP+ brand validation failed
  396. * SFP info 0x2 = SFP+ speed validation failed
  397. * SFP info 0x3 = SFP+ access error
  398. * Bit 18 = SFP Multirate
  399. * Bit 19 = SFP Tx Fault
  400. * Bits 20-22 = Link Speed
  401. * Bits 23-27 = Reserved
  402. * Bits 28-30 = DCBX Status
  403. * DCBX Status 0x0 = DCBX Disabled
  404. * DCBX Status 0x1 = DCBX Enabled
  405. * DCBX Status 0x2 = DCBX Exchange error
  406. * Bit 31 = Reserved
  407. */
  408. peg_fw_state = (mb[2] & 0x00ff);
  409. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  410. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  411. sfp_status = ((mb[2] & 0x0c00) >> 10);
  412. htbt_counter = ((mb[2] & 0x7000) >> 12);
  413. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  414. sfp_additonal_info = (mb[6] & 0x0003);
  415. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  416. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  417. link_speed = ((mb[6] & 0x0070) >> 4);
  418. dcbx_status = ((mb[6] & 0x7000) >> 12);
  419. ql_log(ql_log_warn, vha, 0x5066,
  420. "Peg-to-Fc Status Register:\n"
  421. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  422. "nw_interface_signal_detect=0x%x"
  423. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  424. nw_interface_link_up, nw_interface_signal_detect,
  425. sfp_status);
  426. ql_log(ql_log_warn, vha, 0x5067,
  427. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  428. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  429. htbt_counter, htbt_monitor_enable,
  430. sfp_additonal_info, sfp_multirate);
  431. ql_log(ql_log_warn, vha, 0x5068,
  432. "sfp_tx_fault=0x%x, link_state=0x%x, "
  433. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  434. dcbx_status);
  435. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  436. }
  437. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  438. ql_log(ql_log_warn, vha, 0x5069,
  439. "Heartbeat Failure encountered, chip reset "
  440. "required.\n");
  441. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  442. }
  443. }
  444. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  445. ql_log(ql_log_info, vha, 0x506a,
  446. "IDC Device-State changed = 0x%x.\n", mb[4]);
  447. if (ha->flags.nic_core_reset_owner)
  448. return;
  449. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  450. }
  451. }
  452. int
  453. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  454. {
  455. struct qla_hw_data *ha = vha->hw;
  456. scsi_qla_host_t *vp;
  457. uint32_t vp_did;
  458. unsigned long flags;
  459. int ret = 0;
  460. if (!ha->num_vhosts)
  461. return ret;
  462. spin_lock_irqsave(&ha->vport_slock, flags);
  463. list_for_each_entry(vp, &ha->vp_list, list) {
  464. vp_did = vp->d_id.b24;
  465. if (vp_did == rscn_entry) {
  466. ret = 1;
  467. break;
  468. }
  469. }
  470. spin_unlock_irqrestore(&ha->vport_slock, flags);
  471. return ret;
  472. }
  473. /**
  474. * qla2x00_async_event() - Process aynchronous events.
  475. * @ha: SCSI driver HA context
  476. * @mb: Mailbox registers (0 - 3)
  477. */
  478. void
  479. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  480. {
  481. uint16_t handle_cnt;
  482. uint16_t cnt, mbx;
  483. uint32_t handles[5];
  484. struct qla_hw_data *ha = vha->hw;
  485. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  486. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  487. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  488. uint32_t rscn_entry, host_pid;
  489. unsigned long flags;
  490. /* Setup to process RIO completion. */
  491. handle_cnt = 0;
  492. if (IS_CNA_CAPABLE(ha))
  493. goto skip_rio;
  494. switch (mb[0]) {
  495. case MBA_SCSI_COMPLETION:
  496. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  497. handle_cnt = 1;
  498. break;
  499. case MBA_CMPLT_1_16BIT:
  500. handles[0] = mb[1];
  501. handle_cnt = 1;
  502. mb[0] = MBA_SCSI_COMPLETION;
  503. break;
  504. case MBA_CMPLT_2_16BIT:
  505. handles[0] = mb[1];
  506. handles[1] = mb[2];
  507. handle_cnt = 2;
  508. mb[0] = MBA_SCSI_COMPLETION;
  509. break;
  510. case MBA_CMPLT_3_16BIT:
  511. handles[0] = mb[1];
  512. handles[1] = mb[2];
  513. handles[2] = mb[3];
  514. handle_cnt = 3;
  515. mb[0] = MBA_SCSI_COMPLETION;
  516. break;
  517. case MBA_CMPLT_4_16BIT:
  518. handles[0] = mb[1];
  519. handles[1] = mb[2];
  520. handles[2] = mb[3];
  521. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  522. handle_cnt = 4;
  523. mb[0] = MBA_SCSI_COMPLETION;
  524. break;
  525. case MBA_CMPLT_5_16BIT:
  526. handles[0] = mb[1];
  527. handles[1] = mb[2];
  528. handles[2] = mb[3];
  529. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  530. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  531. handle_cnt = 5;
  532. mb[0] = MBA_SCSI_COMPLETION;
  533. break;
  534. case MBA_CMPLT_2_32BIT:
  535. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  536. handles[1] = le32_to_cpu(
  537. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  538. RD_MAILBOX_REG(ha, reg, 6));
  539. handle_cnt = 2;
  540. mb[0] = MBA_SCSI_COMPLETION;
  541. break;
  542. default:
  543. break;
  544. }
  545. skip_rio:
  546. switch (mb[0]) {
  547. case MBA_SCSI_COMPLETION: /* Fast Post */
  548. if (!vha->flags.online)
  549. break;
  550. for (cnt = 0; cnt < handle_cnt; cnt++)
  551. qla2x00_process_completed_request(vha, rsp->req,
  552. handles[cnt]);
  553. break;
  554. case MBA_RESET: /* Reset */
  555. ql_dbg(ql_dbg_async, vha, 0x5002,
  556. "Asynchronous RESET.\n");
  557. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  558. break;
  559. case MBA_SYSTEM_ERR: /* System Error */
  560. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  561. RD_REG_WORD(&reg24->mailbox7) : 0;
  562. ql_log(ql_log_warn, vha, 0x5003,
  563. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  564. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  565. ha->isp_ops->fw_dump(vha, 1);
  566. if (IS_FWI2_CAPABLE(ha)) {
  567. if (mb[1] == 0 && mb[2] == 0) {
  568. ql_log(ql_log_fatal, vha, 0x5004,
  569. "Unrecoverable Hardware Error: adapter "
  570. "marked OFFLINE!\n");
  571. vha->flags.online = 0;
  572. vha->device_flags |= DFLG_DEV_FAILED;
  573. } else {
  574. /* Check to see if MPI timeout occurred */
  575. if ((mbx & MBX_3) && (ha->flags.port0))
  576. set_bit(MPI_RESET_NEEDED,
  577. &vha->dpc_flags);
  578. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  579. }
  580. } else if (mb[1] == 0) {
  581. ql_log(ql_log_fatal, vha, 0x5005,
  582. "Unrecoverable Hardware Error: adapter marked "
  583. "OFFLINE!\n");
  584. vha->flags.online = 0;
  585. vha->device_flags |= DFLG_DEV_FAILED;
  586. } else
  587. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  588. break;
  589. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  590. ql_log(ql_log_warn, vha, 0x5006,
  591. "ISP Request Transfer Error (%x).\n", mb[1]);
  592. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  593. break;
  594. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  595. ql_log(ql_log_warn, vha, 0x5007,
  596. "ISP Response Transfer Error.\n");
  597. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  598. break;
  599. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  600. ql_dbg(ql_dbg_async, vha, 0x5008,
  601. "Asynchronous WAKEUP_THRES.\n");
  602. break;
  603. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  604. ql_dbg(ql_dbg_async, vha, 0x5009,
  605. "LIP occurred (%x).\n", mb[1]);
  606. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  607. atomic_set(&vha->loop_state, LOOP_DOWN);
  608. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  609. qla2x00_mark_all_devices_lost(vha, 1);
  610. }
  611. if (vha->vp_idx) {
  612. atomic_set(&vha->vp_state, VP_FAILED);
  613. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  614. }
  615. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  616. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  617. vha->flags.management_server_logged_in = 0;
  618. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  619. break;
  620. case MBA_LOOP_UP: /* Loop Up Event */
  621. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  622. ha->link_data_rate = PORT_SPEED_1GB;
  623. else
  624. ha->link_data_rate = mb[1];
  625. ql_dbg(ql_dbg_async, vha, 0x500a,
  626. "LOOP UP detected (%s Gbps).\n",
  627. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  628. vha->flags.management_server_logged_in = 0;
  629. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  630. break;
  631. case MBA_LOOP_DOWN: /* Loop Down Event */
  632. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  633. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  634. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  635. : mbx;
  636. ql_dbg(ql_dbg_async, vha, 0x500b,
  637. "LOOP DOWN detected (%x %x %x %x).\n",
  638. mb[1], mb[2], mb[3], mbx);
  639. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  640. atomic_set(&vha->loop_state, LOOP_DOWN);
  641. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  642. vha->device_flags |= DFLG_NO_CABLE;
  643. qla2x00_mark_all_devices_lost(vha, 1);
  644. }
  645. if (vha->vp_idx) {
  646. atomic_set(&vha->vp_state, VP_FAILED);
  647. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  648. }
  649. vha->flags.management_server_logged_in = 0;
  650. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  651. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  652. break;
  653. case MBA_LIP_RESET: /* LIP reset occurred */
  654. ql_dbg(ql_dbg_async, vha, 0x500c,
  655. "LIP reset occurred (%x).\n", mb[1]);
  656. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  657. atomic_set(&vha->loop_state, LOOP_DOWN);
  658. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  659. qla2x00_mark_all_devices_lost(vha, 1);
  660. }
  661. if (vha->vp_idx) {
  662. atomic_set(&vha->vp_state, VP_FAILED);
  663. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  664. }
  665. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  666. ha->operating_mode = LOOP;
  667. vha->flags.management_server_logged_in = 0;
  668. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  669. break;
  670. /* case MBA_DCBX_COMPLETE: */
  671. case MBA_POINT_TO_POINT: /* Point-to-Point */
  672. if (IS_QLA2100(ha))
  673. break;
  674. if (IS_CNA_CAPABLE(ha)) {
  675. ql_dbg(ql_dbg_async, vha, 0x500d,
  676. "DCBX Completed -- %04x %04x %04x.\n",
  677. mb[1], mb[2], mb[3]);
  678. if (ha->notify_dcbx_comp)
  679. complete(&ha->dcbx_comp);
  680. } else
  681. ql_dbg(ql_dbg_async, vha, 0x500e,
  682. "Asynchronous P2P MODE received.\n");
  683. /*
  684. * Until there's a transition from loop down to loop up, treat
  685. * this as loop down only.
  686. */
  687. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  688. atomic_set(&vha->loop_state, LOOP_DOWN);
  689. if (!atomic_read(&vha->loop_down_timer))
  690. atomic_set(&vha->loop_down_timer,
  691. LOOP_DOWN_TIME);
  692. qla2x00_mark_all_devices_lost(vha, 1);
  693. }
  694. if (vha->vp_idx) {
  695. atomic_set(&vha->vp_state, VP_FAILED);
  696. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  697. }
  698. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  699. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  700. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  701. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  702. ha->flags.gpsc_supported = 1;
  703. vha->flags.management_server_logged_in = 0;
  704. break;
  705. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  706. if (IS_QLA2100(ha))
  707. break;
  708. ql_dbg(ql_dbg_async, vha, 0x500f,
  709. "Configuration change detected: value=%x.\n", mb[1]);
  710. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  711. atomic_set(&vha->loop_state, LOOP_DOWN);
  712. if (!atomic_read(&vha->loop_down_timer))
  713. atomic_set(&vha->loop_down_timer,
  714. LOOP_DOWN_TIME);
  715. qla2x00_mark_all_devices_lost(vha, 1);
  716. }
  717. if (vha->vp_idx) {
  718. atomic_set(&vha->vp_state, VP_FAILED);
  719. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  720. }
  721. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  722. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  723. break;
  724. case MBA_PORT_UPDATE: /* Port database update */
  725. /*
  726. * Handle only global and vn-port update events
  727. *
  728. * Relevant inputs:
  729. * mb[1] = N_Port handle of changed port
  730. * OR 0xffff for global event
  731. * mb[2] = New login state
  732. * 7 = Port logged out
  733. * mb[3] = LSB is vp_idx, 0xff = all vps
  734. *
  735. * Skip processing if:
  736. * Event is global, vp_idx is NOT all vps,
  737. * vp_idx does not match
  738. * Event is not global, vp_idx does not match
  739. */
  740. if (IS_QLA2XXX_MIDTYPE(ha) &&
  741. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  742. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  743. break;
  744. /* Global event -- port logout or port unavailable. */
  745. if (mb[1] == 0xffff && mb[2] == 0x7) {
  746. ql_dbg(ql_dbg_async, vha, 0x5010,
  747. "Port unavailable %04x %04x %04x.\n",
  748. mb[1], mb[2], mb[3]);
  749. ql_log(ql_log_warn, vha, 0x505e,
  750. "Link is offline.\n");
  751. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  752. atomic_set(&vha->loop_state, LOOP_DOWN);
  753. atomic_set(&vha->loop_down_timer,
  754. LOOP_DOWN_TIME);
  755. vha->device_flags |= DFLG_NO_CABLE;
  756. qla2x00_mark_all_devices_lost(vha, 1);
  757. }
  758. if (vha->vp_idx) {
  759. atomic_set(&vha->vp_state, VP_FAILED);
  760. fc_vport_set_state(vha->fc_vport,
  761. FC_VPORT_FAILED);
  762. qla2x00_mark_all_devices_lost(vha, 1);
  763. }
  764. vha->flags.management_server_logged_in = 0;
  765. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  766. break;
  767. }
  768. /*
  769. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  770. * event etc. earlier indicating loop is down) then process
  771. * it. Otherwise ignore it and Wait for RSCN to come in.
  772. */
  773. atomic_set(&vha->loop_down_timer, 0);
  774. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  775. ql_dbg(ql_dbg_async, vha, 0x5011,
  776. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  777. mb[1], mb[2], mb[3]);
  778. qlt_async_event(mb[0], vha, mb);
  779. break;
  780. }
  781. ql_dbg(ql_dbg_async, vha, 0x5012,
  782. "Port database changed %04x %04x %04x.\n",
  783. mb[1], mb[2], mb[3]);
  784. ql_log(ql_log_warn, vha, 0x505f,
  785. "Link is operational (%s Gbps).\n",
  786. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  787. /*
  788. * Mark all devices as missing so we will login again.
  789. */
  790. atomic_set(&vha->loop_state, LOOP_UP);
  791. qla2x00_mark_all_devices_lost(vha, 1);
  792. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  793. set_bit(SCR_PENDING, &vha->dpc_flags);
  794. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  795. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  796. qlt_async_event(mb[0], vha, mb);
  797. break;
  798. case MBA_RSCN_UPDATE: /* State Change Registration */
  799. /* Check if the Vport has issued a SCR */
  800. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  801. break;
  802. /* Only handle SCNs for our Vport index. */
  803. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  804. break;
  805. ql_dbg(ql_dbg_async, vha, 0x5013,
  806. "RSCN database changed -- %04x %04x %04x.\n",
  807. mb[1], mb[2], mb[3]);
  808. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  809. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  810. | vha->d_id.b.al_pa;
  811. if (rscn_entry == host_pid) {
  812. ql_dbg(ql_dbg_async, vha, 0x5014,
  813. "Ignoring RSCN update to local host "
  814. "port ID (%06x).\n", host_pid);
  815. break;
  816. }
  817. /* Ignore reserved bits from RSCN-payload. */
  818. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  819. /* Skip RSCNs for virtual ports on the same physical port */
  820. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  821. break;
  822. atomic_set(&vha->loop_down_timer, 0);
  823. vha->flags.management_server_logged_in = 0;
  824. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  825. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  826. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  827. break;
  828. /* case MBA_RIO_RESPONSE: */
  829. case MBA_ZIO_RESPONSE:
  830. ql_dbg(ql_dbg_async, vha, 0x5015,
  831. "[R|Z]IO update completion.\n");
  832. if (IS_FWI2_CAPABLE(ha))
  833. qla24xx_process_response_queue(vha, rsp);
  834. else
  835. qla2x00_process_response_queue(rsp);
  836. break;
  837. case MBA_DISCARD_RND_FRAME:
  838. ql_dbg(ql_dbg_async, vha, 0x5016,
  839. "Discard RND Frame -- %04x %04x %04x.\n",
  840. mb[1], mb[2], mb[3]);
  841. break;
  842. case MBA_TRACE_NOTIFICATION:
  843. ql_dbg(ql_dbg_async, vha, 0x5017,
  844. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  845. break;
  846. case MBA_ISP84XX_ALERT:
  847. ql_dbg(ql_dbg_async, vha, 0x5018,
  848. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  849. mb[1], mb[2], mb[3]);
  850. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  851. switch (mb[1]) {
  852. case A84_PANIC_RECOVERY:
  853. ql_log(ql_log_info, vha, 0x5019,
  854. "Alert 84XX: panic recovery %04x %04x.\n",
  855. mb[2], mb[3]);
  856. break;
  857. case A84_OP_LOGIN_COMPLETE:
  858. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  859. ql_log(ql_log_info, vha, 0x501a,
  860. "Alert 84XX: firmware version %x.\n",
  861. ha->cs84xx->op_fw_version);
  862. break;
  863. case A84_DIAG_LOGIN_COMPLETE:
  864. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  865. ql_log(ql_log_info, vha, 0x501b,
  866. "Alert 84XX: diagnostic firmware version %x.\n",
  867. ha->cs84xx->diag_fw_version);
  868. break;
  869. case A84_GOLD_LOGIN_COMPLETE:
  870. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  871. ha->cs84xx->fw_update = 1;
  872. ql_log(ql_log_info, vha, 0x501c,
  873. "Alert 84XX: gold firmware version %x.\n",
  874. ha->cs84xx->gold_fw_version);
  875. break;
  876. default:
  877. ql_log(ql_log_warn, vha, 0x501d,
  878. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  879. mb[1], mb[2], mb[3]);
  880. }
  881. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  882. break;
  883. case MBA_DCBX_START:
  884. ql_dbg(ql_dbg_async, vha, 0x501e,
  885. "DCBX Started -- %04x %04x %04x.\n",
  886. mb[1], mb[2], mb[3]);
  887. break;
  888. case MBA_DCBX_PARAM_UPDATE:
  889. ql_dbg(ql_dbg_async, vha, 0x501f,
  890. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  891. mb[1], mb[2], mb[3]);
  892. break;
  893. case MBA_FCF_CONF_ERR:
  894. ql_dbg(ql_dbg_async, vha, 0x5020,
  895. "FCF Configuration Error -- %04x %04x %04x.\n",
  896. mb[1], mb[2], mb[3]);
  897. break;
  898. case MBA_IDC_NOTIFY:
  899. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  900. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  901. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  902. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  903. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  904. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  905. /*
  906. * Extend loop down timer since port is active.
  907. */
  908. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  909. atomic_set(&vha->loop_down_timer,
  910. LOOP_DOWN_TIME);
  911. qla2xxx_wake_dpc(vha);
  912. }
  913. }
  914. case MBA_IDC_COMPLETE:
  915. if (ha->notify_lb_portup_comp)
  916. complete(&ha->lb_portup_comp);
  917. /* Fallthru */
  918. case MBA_IDC_TIME_EXT:
  919. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  920. IS_QLA8044(ha))
  921. qla81xx_idc_event(vha, mb[0], mb[1]);
  922. break;
  923. case MBA_IDC_AEN:
  924. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  925. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  926. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  927. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  928. qla83xx_handle_8200_aen(vha, mb);
  929. break;
  930. default:
  931. ql_dbg(ql_dbg_async, vha, 0x5057,
  932. "Unknown AEN:%04x %04x %04x %04x\n",
  933. mb[0], mb[1], mb[2], mb[3]);
  934. }
  935. qlt_async_event(mb[0], vha, mb);
  936. if (!vha->vp_idx && ha->num_vhosts)
  937. qla2x00_alert_all_vps(rsp, mb);
  938. }
  939. /**
  940. * qla2x00_process_completed_request() - Process a Fast Post response.
  941. * @ha: SCSI driver HA context
  942. * @index: SRB index
  943. */
  944. void
  945. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  946. struct req_que *req, uint32_t index)
  947. {
  948. srb_t *sp;
  949. struct qla_hw_data *ha = vha->hw;
  950. /* Validate handle. */
  951. if (index >= req->num_outstanding_cmds) {
  952. ql_log(ql_log_warn, vha, 0x3014,
  953. "Invalid SCSI command index (%x).\n", index);
  954. if (IS_P3P_TYPE(ha))
  955. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  956. else
  957. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  958. return;
  959. }
  960. sp = req->outstanding_cmds[index];
  961. if (sp) {
  962. /* Free outstanding command slot. */
  963. req->outstanding_cmds[index] = NULL;
  964. /* Save ISP completion status */
  965. sp->done(ha, sp, DID_OK << 16);
  966. } else {
  967. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  968. if (IS_P3P_TYPE(ha))
  969. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  970. else
  971. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  972. }
  973. }
  974. srb_t *
  975. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  976. struct req_que *req, void *iocb)
  977. {
  978. struct qla_hw_data *ha = vha->hw;
  979. sts_entry_t *pkt = iocb;
  980. srb_t *sp = NULL;
  981. uint16_t index;
  982. index = LSW(pkt->handle);
  983. if (index >= req->num_outstanding_cmds) {
  984. ql_log(ql_log_warn, vha, 0x5031,
  985. "Invalid command index (%x).\n", index);
  986. if (IS_P3P_TYPE(ha))
  987. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  988. else
  989. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  990. goto done;
  991. }
  992. sp = req->outstanding_cmds[index];
  993. if (!sp) {
  994. ql_log(ql_log_warn, vha, 0x5032,
  995. "Invalid completion handle (%x) -- timed-out.\n", index);
  996. return sp;
  997. }
  998. if (sp->handle != index) {
  999. ql_log(ql_log_warn, vha, 0x5033,
  1000. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  1001. return NULL;
  1002. }
  1003. req->outstanding_cmds[index] = NULL;
  1004. done:
  1005. return sp;
  1006. }
  1007. static void
  1008. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1009. struct mbx_entry *mbx)
  1010. {
  1011. const char func[] = "MBX-IOCB";
  1012. const char *type;
  1013. fc_port_t *fcport;
  1014. srb_t *sp;
  1015. struct srb_iocb *lio;
  1016. uint16_t *data;
  1017. uint16_t status;
  1018. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1019. if (!sp)
  1020. return;
  1021. lio = &sp->u.iocb_cmd;
  1022. type = sp->name;
  1023. fcport = sp->fcport;
  1024. data = lio->u.logio.data;
  1025. data[0] = MBS_COMMAND_ERROR;
  1026. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1027. QLA_LOGIO_LOGIN_RETRIED : 0;
  1028. if (mbx->entry_status) {
  1029. ql_dbg(ql_dbg_async, vha, 0x5043,
  1030. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1031. "entry-status=%x status=%x state-flag=%x "
  1032. "status-flags=%x.\n", type, sp->handle,
  1033. fcport->d_id.b.domain, fcport->d_id.b.area,
  1034. fcport->d_id.b.al_pa, mbx->entry_status,
  1035. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1036. le16_to_cpu(mbx->status_flags));
  1037. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1038. (uint8_t *)mbx, sizeof(*mbx));
  1039. goto logio_done;
  1040. }
  1041. status = le16_to_cpu(mbx->status);
  1042. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1043. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1044. status = 0;
  1045. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1046. ql_dbg(ql_dbg_async, vha, 0x5045,
  1047. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1048. type, sp->handle, fcport->d_id.b.domain,
  1049. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1050. le16_to_cpu(mbx->mb1));
  1051. data[0] = MBS_COMMAND_COMPLETE;
  1052. if (sp->type == SRB_LOGIN_CMD) {
  1053. fcport->port_type = FCT_TARGET;
  1054. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1055. fcport->port_type = FCT_INITIATOR;
  1056. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1057. fcport->flags |= FCF_FCP2_DEVICE;
  1058. }
  1059. goto logio_done;
  1060. }
  1061. data[0] = le16_to_cpu(mbx->mb0);
  1062. switch (data[0]) {
  1063. case MBS_PORT_ID_USED:
  1064. data[1] = le16_to_cpu(mbx->mb1);
  1065. break;
  1066. case MBS_LOOP_ID_USED:
  1067. break;
  1068. default:
  1069. data[0] = MBS_COMMAND_ERROR;
  1070. break;
  1071. }
  1072. ql_log(ql_log_warn, vha, 0x5046,
  1073. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1074. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1075. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1076. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1077. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1078. le16_to_cpu(mbx->mb7));
  1079. logio_done:
  1080. sp->done(vha, sp, 0);
  1081. }
  1082. static void
  1083. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1084. sts_entry_t *pkt, int iocb_type)
  1085. {
  1086. const char func[] = "CT_IOCB";
  1087. const char *type;
  1088. srb_t *sp;
  1089. struct fc_bsg_job *bsg_job;
  1090. uint16_t comp_status;
  1091. int res;
  1092. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1093. if (!sp)
  1094. return;
  1095. bsg_job = sp->u.bsg_job;
  1096. type = "ct pass-through";
  1097. comp_status = le16_to_cpu(pkt->comp_status);
  1098. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1099. * fc payload to the caller
  1100. */
  1101. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1102. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1103. if (comp_status != CS_COMPLETE) {
  1104. if (comp_status == CS_DATA_UNDERRUN) {
  1105. res = DID_OK << 16;
  1106. bsg_job->reply->reply_payload_rcv_len =
  1107. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1108. ql_log(ql_log_warn, vha, 0x5048,
  1109. "CT pass-through-%s error "
  1110. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1111. type, comp_status,
  1112. bsg_job->reply->reply_payload_rcv_len);
  1113. } else {
  1114. ql_log(ql_log_warn, vha, 0x5049,
  1115. "CT pass-through-%s error "
  1116. "comp_status-status=0x%x.\n", type, comp_status);
  1117. res = DID_ERROR << 16;
  1118. bsg_job->reply->reply_payload_rcv_len = 0;
  1119. }
  1120. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1121. (uint8_t *)pkt, sizeof(*pkt));
  1122. } else {
  1123. res = DID_OK << 16;
  1124. bsg_job->reply->reply_payload_rcv_len =
  1125. bsg_job->reply_payload.payload_len;
  1126. bsg_job->reply_len = 0;
  1127. }
  1128. sp->done(vha, sp, res);
  1129. }
  1130. static void
  1131. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1132. struct sts_entry_24xx *pkt, int iocb_type)
  1133. {
  1134. const char func[] = "ELS_CT_IOCB";
  1135. const char *type;
  1136. srb_t *sp;
  1137. struct fc_bsg_job *bsg_job;
  1138. uint16_t comp_status;
  1139. uint32_t fw_status[3];
  1140. uint8_t* fw_sts_ptr;
  1141. int res;
  1142. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1143. if (!sp)
  1144. return;
  1145. bsg_job = sp->u.bsg_job;
  1146. type = NULL;
  1147. switch (sp->type) {
  1148. case SRB_ELS_CMD_RPT:
  1149. case SRB_ELS_CMD_HST:
  1150. type = "els";
  1151. break;
  1152. case SRB_CT_CMD:
  1153. type = "ct pass-through";
  1154. break;
  1155. default:
  1156. ql_dbg(ql_dbg_user, vha, 0x503e,
  1157. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1158. return;
  1159. }
  1160. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1161. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1162. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1163. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1164. * fc payload to the caller
  1165. */
  1166. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1167. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1168. if (comp_status != CS_COMPLETE) {
  1169. if (comp_status == CS_DATA_UNDERRUN) {
  1170. res = DID_OK << 16;
  1171. bsg_job->reply->reply_payload_rcv_len =
  1172. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1173. ql_dbg(ql_dbg_user, vha, 0x503f,
  1174. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1175. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1176. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1177. le16_to_cpu(((struct els_sts_entry_24xx *)
  1178. pkt)->total_byte_count));
  1179. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1180. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1181. }
  1182. else {
  1183. ql_dbg(ql_dbg_user, vha, 0x5040,
  1184. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1185. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1186. type, sp->handle, comp_status,
  1187. le16_to_cpu(((struct els_sts_entry_24xx *)
  1188. pkt)->error_subcode_1),
  1189. le16_to_cpu(((struct els_sts_entry_24xx *)
  1190. pkt)->error_subcode_2));
  1191. res = DID_ERROR << 16;
  1192. bsg_job->reply->reply_payload_rcv_len = 0;
  1193. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1194. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1195. }
  1196. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1197. (uint8_t *)pkt, sizeof(*pkt));
  1198. }
  1199. else {
  1200. res = DID_OK << 16;
  1201. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1202. bsg_job->reply_len = 0;
  1203. }
  1204. sp->done(vha, sp, res);
  1205. }
  1206. static void
  1207. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1208. struct logio_entry_24xx *logio)
  1209. {
  1210. const char func[] = "LOGIO-IOCB";
  1211. const char *type;
  1212. fc_port_t *fcport;
  1213. srb_t *sp;
  1214. struct srb_iocb *lio;
  1215. uint16_t *data;
  1216. uint32_t iop[2];
  1217. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1218. if (!sp)
  1219. return;
  1220. lio = &sp->u.iocb_cmd;
  1221. type = sp->name;
  1222. fcport = sp->fcport;
  1223. data = lio->u.logio.data;
  1224. data[0] = MBS_COMMAND_ERROR;
  1225. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1226. QLA_LOGIO_LOGIN_RETRIED : 0;
  1227. if (logio->entry_status) {
  1228. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1229. "Async-%s error entry - hdl=%x"
  1230. "portid=%02x%02x%02x entry-status=%x.\n",
  1231. type, sp->handle, fcport->d_id.b.domain,
  1232. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1233. logio->entry_status);
  1234. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1235. (uint8_t *)logio, sizeof(*logio));
  1236. goto logio_done;
  1237. }
  1238. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1239. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1240. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1241. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1242. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1243. le32_to_cpu(logio->io_parameter[0]));
  1244. data[0] = MBS_COMMAND_COMPLETE;
  1245. if (sp->type != SRB_LOGIN_CMD)
  1246. goto logio_done;
  1247. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1248. if (iop[0] & BIT_4) {
  1249. fcport->port_type = FCT_TARGET;
  1250. if (iop[0] & BIT_8)
  1251. fcport->flags |= FCF_FCP2_DEVICE;
  1252. } else if (iop[0] & BIT_5)
  1253. fcport->port_type = FCT_INITIATOR;
  1254. if (iop[0] & BIT_7)
  1255. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1256. if (logio->io_parameter[7] || logio->io_parameter[8])
  1257. fcport->supported_classes |= FC_COS_CLASS2;
  1258. if (logio->io_parameter[9] || logio->io_parameter[10])
  1259. fcport->supported_classes |= FC_COS_CLASS3;
  1260. goto logio_done;
  1261. }
  1262. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1263. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1264. switch (iop[0]) {
  1265. case LSC_SCODE_PORTID_USED:
  1266. data[0] = MBS_PORT_ID_USED;
  1267. data[1] = LSW(iop[1]);
  1268. break;
  1269. case LSC_SCODE_NPORT_USED:
  1270. data[0] = MBS_LOOP_ID_USED;
  1271. break;
  1272. default:
  1273. data[0] = MBS_COMMAND_ERROR;
  1274. break;
  1275. }
  1276. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1277. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1278. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1279. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1280. le16_to_cpu(logio->comp_status),
  1281. le32_to_cpu(logio->io_parameter[0]),
  1282. le32_to_cpu(logio->io_parameter[1]));
  1283. logio_done:
  1284. sp->done(vha, sp, 0);
  1285. }
  1286. static void
  1287. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1288. struct tsk_mgmt_entry *tsk)
  1289. {
  1290. const char func[] = "TMF-IOCB";
  1291. const char *type;
  1292. fc_port_t *fcport;
  1293. srb_t *sp;
  1294. struct srb_iocb *iocb;
  1295. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1296. int error = 1;
  1297. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1298. if (!sp)
  1299. return;
  1300. iocb = &sp->u.iocb_cmd;
  1301. type = sp->name;
  1302. fcport = sp->fcport;
  1303. if (sts->entry_status) {
  1304. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1305. "Async-%s error - hdl=%x entry-status(%x).\n",
  1306. type, sp->handle, sts->entry_status);
  1307. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1308. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1309. "Async-%s error - hdl=%x completion status(%x).\n",
  1310. type, sp->handle, sts->comp_status);
  1311. } else if (!(le16_to_cpu(sts->scsi_status) &
  1312. SS_RESPONSE_INFO_LEN_VALID)) {
  1313. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1314. "Async-%s error - hdl=%x no response info(%x).\n",
  1315. type, sp->handle, sts->scsi_status);
  1316. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1317. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1318. "Async-%s error - hdl=%x not enough response(%d).\n",
  1319. type, sp->handle, sts->rsp_data_len);
  1320. } else if (sts->data[3]) {
  1321. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1322. "Async-%s error - hdl=%x response(%x).\n",
  1323. type, sp->handle, sts->data[3]);
  1324. } else {
  1325. error = 0;
  1326. }
  1327. if (error) {
  1328. iocb->u.tmf.data = error;
  1329. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1330. (uint8_t *)sts, sizeof(*sts));
  1331. }
  1332. sp->done(vha, sp, 0);
  1333. }
  1334. /**
  1335. * qla2x00_process_response_queue() - Process response queue entries.
  1336. * @ha: SCSI driver HA context
  1337. */
  1338. void
  1339. qla2x00_process_response_queue(struct rsp_que *rsp)
  1340. {
  1341. struct scsi_qla_host *vha;
  1342. struct qla_hw_data *ha = rsp->hw;
  1343. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1344. sts_entry_t *pkt;
  1345. uint16_t handle_cnt;
  1346. uint16_t cnt;
  1347. vha = pci_get_drvdata(ha->pdev);
  1348. if (!vha->flags.online)
  1349. return;
  1350. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1351. pkt = (sts_entry_t *)rsp->ring_ptr;
  1352. rsp->ring_index++;
  1353. if (rsp->ring_index == rsp->length) {
  1354. rsp->ring_index = 0;
  1355. rsp->ring_ptr = rsp->ring;
  1356. } else {
  1357. rsp->ring_ptr++;
  1358. }
  1359. if (pkt->entry_status != 0) {
  1360. qla2x00_error_entry(vha, rsp, pkt);
  1361. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1362. wmb();
  1363. continue;
  1364. }
  1365. switch (pkt->entry_type) {
  1366. case STATUS_TYPE:
  1367. qla2x00_status_entry(vha, rsp, pkt);
  1368. break;
  1369. case STATUS_TYPE_21:
  1370. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1371. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1372. qla2x00_process_completed_request(vha, rsp->req,
  1373. ((sts21_entry_t *)pkt)->handle[cnt]);
  1374. }
  1375. break;
  1376. case STATUS_TYPE_22:
  1377. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1378. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1379. qla2x00_process_completed_request(vha, rsp->req,
  1380. ((sts22_entry_t *)pkt)->handle[cnt]);
  1381. }
  1382. break;
  1383. case STATUS_CONT_TYPE:
  1384. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1385. break;
  1386. case MBX_IOCB_TYPE:
  1387. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1388. (struct mbx_entry *)pkt);
  1389. break;
  1390. case CT_IOCB_TYPE:
  1391. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1392. break;
  1393. default:
  1394. /* Type Not Supported. */
  1395. ql_log(ql_log_warn, vha, 0x504a,
  1396. "Received unknown response pkt type %x "
  1397. "entry status=%x.\n",
  1398. pkt->entry_type, pkt->entry_status);
  1399. break;
  1400. }
  1401. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1402. wmb();
  1403. }
  1404. /* Adjust ring index */
  1405. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1406. }
  1407. static inline void
  1408. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1409. uint32_t sense_len, struct rsp_que *rsp, int res)
  1410. {
  1411. struct scsi_qla_host *vha = sp->fcport->vha;
  1412. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1413. uint32_t track_sense_len;
  1414. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1415. sense_len = SCSI_SENSE_BUFFERSIZE;
  1416. SET_CMD_SENSE_LEN(sp, sense_len);
  1417. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1418. track_sense_len = sense_len;
  1419. if (sense_len > par_sense_len)
  1420. sense_len = par_sense_len;
  1421. memcpy(cp->sense_buffer, sense_data, sense_len);
  1422. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1423. track_sense_len -= sense_len;
  1424. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1425. if (track_sense_len != 0) {
  1426. rsp->status_srb = sp;
  1427. cp->result = res;
  1428. }
  1429. if (sense_len) {
  1430. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1431. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1432. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1433. cp);
  1434. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1435. cp->sense_buffer, sense_len);
  1436. }
  1437. }
  1438. struct scsi_dif_tuple {
  1439. __be16 guard; /* Checksum */
  1440. __be16 app_tag; /* APPL identifier */
  1441. __be32 ref_tag; /* Target LBA or indirect LBA */
  1442. };
  1443. /*
  1444. * Checks the guard or meta-data for the type of error
  1445. * detected by the HBA. In case of errors, we set the
  1446. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1447. * to indicate to the kernel that the HBA detected error.
  1448. */
  1449. static inline int
  1450. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1451. {
  1452. struct scsi_qla_host *vha = sp->fcport->vha;
  1453. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1454. uint8_t *ap = &sts24->data[12];
  1455. uint8_t *ep = &sts24->data[20];
  1456. uint32_t e_ref_tag, a_ref_tag;
  1457. uint16_t e_app_tag, a_app_tag;
  1458. uint16_t e_guard, a_guard;
  1459. /*
  1460. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1461. * would make guard field appear at offset 2
  1462. */
  1463. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1464. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1465. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1466. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1467. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1468. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1469. ql_dbg(ql_dbg_io, vha, 0x3023,
  1470. "iocb(s) %p Returned STATUS.\n", sts24);
  1471. ql_dbg(ql_dbg_io, vha, 0x3024,
  1472. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1473. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1474. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1475. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1476. a_app_tag, e_app_tag, a_guard, e_guard);
  1477. /*
  1478. * Ignore sector if:
  1479. * For type 3: ref & app tag is all 'f's
  1480. * For type 0,1,2: app tag is all 'f's
  1481. */
  1482. if ((a_app_tag == 0xffff) &&
  1483. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1484. (a_ref_tag == 0xffffffff))) {
  1485. uint32_t blocks_done, resid;
  1486. sector_t lba_s = scsi_get_lba(cmd);
  1487. /* 2TB boundary case covered automatically with this */
  1488. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1489. resid = scsi_bufflen(cmd) - (blocks_done *
  1490. cmd->device->sector_size);
  1491. scsi_set_resid(cmd, resid);
  1492. cmd->result = DID_OK << 16;
  1493. /* Update protection tag */
  1494. if (scsi_prot_sg_count(cmd)) {
  1495. uint32_t i, j = 0, k = 0, num_ent;
  1496. struct scatterlist *sg;
  1497. struct sd_dif_tuple *spt;
  1498. /* Patch the corresponding protection tags */
  1499. scsi_for_each_prot_sg(cmd, sg,
  1500. scsi_prot_sg_count(cmd), i) {
  1501. num_ent = sg_dma_len(sg) / 8;
  1502. if (k + num_ent < blocks_done) {
  1503. k += num_ent;
  1504. continue;
  1505. }
  1506. j = blocks_done - k - 1;
  1507. k = blocks_done;
  1508. break;
  1509. }
  1510. if (k != blocks_done) {
  1511. ql_log(ql_log_warn, vha, 0x302f,
  1512. "unexpected tag values tag:lba=%x:%llx)\n",
  1513. e_ref_tag, (unsigned long long)lba_s);
  1514. return 1;
  1515. }
  1516. spt = page_address(sg_page(sg)) + sg->offset;
  1517. spt += j;
  1518. spt->app_tag = 0xffff;
  1519. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1520. spt->ref_tag = 0xffffffff;
  1521. }
  1522. return 0;
  1523. }
  1524. /* check guard */
  1525. if (e_guard != a_guard) {
  1526. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1527. 0x10, 0x1);
  1528. set_driver_byte(cmd, DRIVER_SENSE);
  1529. set_host_byte(cmd, DID_ABORT);
  1530. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1531. return 1;
  1532. }
  1533. /* check ref tag */
  1534. if (e_ref_tag != a_ref_tag) {
  1535. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1536. 0x10, 0x3);
  1537. set_driver_byte(cmd, DRIVER_SENSE);
  1538. set_host_byte(cmd, DID_ABORT);
  1539. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1540. return 1;
  1541. }
  1542. /* check appl tag */
  1543. if (e_app_tag != a_app_tag) {
  1544. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1545. 0x10, 0x2);
  1546. set_driver_byte(cmd, DRIVER_SENSE);
  1547. set_host_byte(cmd, DID_ABORT);
  1548. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1549. return 1;
  1550. }
  1551. return 1;
  1552. }
  1553. static void
  1554. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1555. struct req_que *req, uint32_t index)
  1556. {
  1557. struct qla_hw_data *ha = vha->hw;
  1558. srb_t *sp;
  1559. uint16_t comp_status;
  1560. uint16_t scsi_status;
  1561. uint16_t thread_id;
  1562. uint32_t rval = EXT_STATUS_OK;
  1563. struct fc_bsg_job *bsg_job = NULL;
  1564. sts_entry_t *sts;
  1565. struct sts_entry_24xx *sts24;
  1566. sts = (sts_entry_t *) pkt;
  1567. sts24 = (struct sts_entry_24xx *) pkt;
  1568. /* Validate handle. */
  1569. if (index >= req->num_outstanding_cmds) {
  1570. ql_log(ql_log_warn, vha, 0x70af,
  1571. "Invalid SCSI completion handle 0x%x.\n", index);
  1572. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1573. return;
  1574. }
  1575. sp = req->outstanding_cmds[index];
  1576. if (sp) {
  1577. /* Free outstanding command slot. */
  1578. req->outstanding_cmds[index] = NULL;
  1579. bsg_job = sp->u.bsg_job;
  1580. } else {
  1581. ql_log(ql_log_warn, vha, 0x70b0,
  1582. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1583. req->id, index);
  1584. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1585. return;
  1586. }
  1587. if (IS_FWI2_CAPABLE(ha)) {
  1588. comp_status = le16_to_cpu(sts24->comp_status);
  1589. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1590. } else {
  1591. comp_status = le16_to_cpu(sts->comp_status);
  1592. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1593. }
  1594. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1595. switch (comp_status) {
  1596. case CS_COMPLETE:
  1597. if (scsi_status == 0) {
  1598. bsg_job->reply->reply_payload_rcv_len =
  1599. bsg_job->reply_payload.payload_len;
  1600. vha->qla_stats.input_bytes +=
  1601. bsg_job->reply->reply_payload_rcv_len;
  1602. vha->qla_stats.input_requests++;
  1603. rval = EXT_STATUS_OK;
  1604. }
  1605. goto done;
  1606. case CS_DATA_OVERRUN:
  1607. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1608. "Command completed with date overrun thread_id=%d\n",
  1609. thread_id);
  1610. rval = EXT_STATUS_DATA_OVERRUN;
  1611. break;
  1612. case CS_DATA_UNDERRUN:
  1613. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1614. "Command completed with date underrun thread_id=%d\n",
  1615. thread_id);
  1616. rval = EXT_STATUS_DATA_UNDERRUN;
  1617. break;
  1618. case CS_BIDIR_RD_OVERRUN:
  1619. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1620. "Command completed with read data overrun thread_id=%d\n",
  1621. thread_id);
  1622. rval = EXT_STATUS_DATA_OVERRUN;
  1623. break;
  1624. case CS_BIDIR_RD_WR_OVERRUN:
  1625. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1626. "Command completed with read and write data overrun "
  1627. "thread_id=%d\n", thread_id);
  1628. rval = EXT_STATUS_DATA_OVERRUN;
  1629. break;
  1630. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1631. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1632. "Command completed with read data over and write data "
  1633. "underrun thread_id=%d\n", thread_id);
  1634. rval = EXT_STATUS_DATA_OVERRUN;
  1635. break;
  1636. case CS_BIDIR_RD_UNDERRUN:
  1637. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1638. "Command completed with read data data underrun "
  1639. "thread_id=%d\n", thread_id);
  1640. rval = EXT_STATUS_DATA_UNDERRUN;
  1641. break;
  1642. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1643. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1644. "Command completed with read data under and write data "
  1645. "overrun thread_id=%d\n", thread_id);
  1646. rval = EXT_STATUS_DATA_UNDERRUN;
  1647. break;
  1648. case CS_BIDIR_RD_WR_UNDERRUN:
  1649. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1650. "Command completed with read and write data underrun "
  1651. "thread_id=%d\n", thread_id);
  1652. rval = EXT_STATUS_DATA_UNDERRUN;
  1653. break;
  1654. case CS_BIDIR_DMA:
  1655. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1656. "Command completed with data DMA error thread_id=%d\n",
  1657. thread_id);
  1658. rval = EXT_STATUS_DMA_ERR;
  1659. break;
  1660. case CS_TIMEOUT:
  1661. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1662. "Command completed with timeout thread_id=%d\n",
  1663. thread_id);
  1664. rval = EXT_STATUS_TIMEOUT;
  1665. break;
  1666. default:
  1667. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1668. "Command completed with completion status=0x%x "
  1669. "thread_id=%d\n", comp_status, thread_id);
  1670. rval = EXT_STATUS_ERR;
  1671. break;
  1672. }
  1673. bsg_job->reply->reply_payload_rcv_len = 0;
  1674. done:
  1675. /* Return the vendor specific reply to API */
  1676. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1677. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1678. /* Always return DID_OK, bsg will send the vendor specific response
  1679. * in this case only */
  1680. sp->done(vha, sp, (DID_OK << 6));
  1681. }
  1682. /**
  1683. * qla2x00_status_entry() - Process a Status IOCB entry.
  1684. * @ha: SCSI driver HA context
  1685. * @pkt: Entry pointer
  1686. */
  1687. static void
  1688. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1689. {
  1690. srb_t *sp;
  1691. fc_port_t *fcport;
  1692. struct scsi_cmnd *cp;
  1693. sts_entry_t *sts;
  1694. struct sts_entry_24xx *sts24;
  1695. uint16_t comp_status;
  1696. uint16_t scsi_status;
  1697. uint16_t ox_id;
  1698. uint8_t lscsi_status;
  1699. int32_t resid;
  1700. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1701. fw_resid_len;
  1702. uint8_t *rsp_info, *sense_data;
  1703. struct qla_hw_data *ha = vha->hw;
  1704. uint32_t handle;
  1705. uint16_t que;
  1706. struct req_que *req;
  1707. int logit = 1;
  1708. int res = 0;
  1709. uint16_t state_flags = 0;
  1710. sts = (sts_entry_t *) pkt;
  1711. sts24 = (struct sts_entry_24xx *) pkt;
  1712. if (IS_FWI2_CAPABLE(ha)) {
  1713. comp_status = le16_to_cpu(sts24->comp_status);
  1714. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1715. state_flags = le16_to_cpu(sts24->state_flags);
  1716. } else {
  1717. comp_status = le16_to_cpu(sts->comp_status);
  1718. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1719. }
  1720. handle = (uint32_t) LSW(sts->handle);
  1721. que = MSW(sts->handle);
  1722. req = ha->req_q_map[que];
  1723. /* Check for invalid queue pointer */
  1724. if (req == NULL ||
  1725. que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
  1726. ql_dbg(ql_dbg_io, vha, 0x3059,
  1727. "Invalid status handle (0x%x): Bad req pointer. req=%p, "
  1728. "que=%u.\n", sts->handle, req, que);
  1729. return;
  1730. }
  1731. /* Validate handle. */
  1732. if (handle < req->num_outstanding_cmds)
  1733. sp = req->outstanding_cmds[handle];
  1734. else
  1735. sp = NULL;
  1736. if (sp == NULL) {
  1737. ql_dbg(ql_dbg_io, vha, 0x3017,
  1738. "Invalid status handle (0x%x).\n", sts->handle);
  1739. if (IS_P3P_TYPE(ha))
  1740. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1741. else
  1742. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1743. qla2xxx_wake_dpc(vha);
  1744. return;
  1745. }
  1746. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1747. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1748. return;
  1749. }
  1750. /* Fast path completion. */
  1751. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1752. qla2x00_do_host_ramp_up(vha);
  1753. qla2x00_process_completed_request(vha, req, handle);
  1754. return;
  1755. }
  1756. req->outstanding_cmds[handle] = NULL;
  1757. cp = GET_CMD_SP(sp);
  1758. if (cp == NULL) {
  1759. ql_dbg(ql_dbg_io, vha, 0x3018,
  1760. "Command already returned (0x%x/%p).\n",
  1761. sts->handle, sp);
  1762. return;
  1763. }
  1764. lscsi_status = scsi_status & STATUS_MASK;
  1765. fcport = sp->fcport;
  1766. ox_id = 0;
  1767. sense_len = par_sense_len = rsp_info_len = resid_len =
  1768. fw_resid_len = 0;
  1769. if (IS_FWI2_CAPABLE(ha)) {
  1770. if (scsi_status & SS_SENSE_LEN_VALID)
  1771. sense_len = le32_to_cpu(sts24->sense_len);
  1772. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1773. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1774. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1775. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1776. if (comp_status == CS_DATA_UNDERRUN)
  1777. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1778. rsp_info = sts24->data;
  1779. sense_data = sts24->data;
  1780. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1781. ox_id = le16_to_cpu(sts24->ox_id);
  1782. par_sense_len = sizeof(sts24->data);
  1783. } else {
  1784. if (scsi_status & SS_SENSE_LEN_VALID)
  1785. sense_len = le16_to_cpu(sts->req_sense_length);
  1786. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1787. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1788. resid_len = le32_to_cpu(sts->residual_length);
  1789. rsp_info = sts->rsp_info;
  1790. sense_data = sts->req_sense_data;
  1791. par_sense_len = sizeof(sts->req_sense_data);
  1792. }
  1793. /* Check for any FCP transport errors. */
  1794. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1795. /* Sense data lies beyond any FCP RESPONSE data. */
  1796. if (IS_FWI2_CAPABLE(ha)) {
  1797. sense_data += rsp_info_len;
  1798. par_sense_len -= rsp_info_len;
  1799. }
  1800. if (rsp_info_len > 3 && rsp_info[3]) {
  1801. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1802. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1803. rsp_info_len, rsp_info[3]);
  1804. res = DID_BUS_BUSY << 16;
  1805. goto out;
  1806. }
  1807. }
  1808. /* Check for overrun. */
  1809. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1810. scsi_status & SS_RESIDUAL_OVER)
  1811. comp_status = CS_DATA_OVERRUN;
  1812. /*
  1813. * Based on Host and scsi status generate status code for Linux
  1814. */
  1815. switch (comp_status) {
  1816. case CS_COMPLETE:
  1817. case CS_QUEUE_FULL:
  1818. if (scsi_status == 0) {
  1819. res = DID_OK << 16;
  1820. break;
  1821. }
  1822. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1823. resid = resid_len;
  1824. scsi_set_resid(cp, resid);
  1825. if (!lscsi_status &&
  1826. ((unsigned)(scsi_bufflen(cp) - resid) <
  1827. cp->underflow)) {
  1828. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1829. "Mid-layer underflow "
  1830. "detected (0x%x of 0x%x bytes).\n",
  1831. resid, scsi_bufflen(cp));
  1832. res = DID_ERROR << 16;
  1833. break;
  1834. }
  1835. }
  1836. res = DID_OK << 16 | lscsi_status;
  1837. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1838. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1839. "QUEUE FULL detected.\n");
  1840. break;
  1841. }
  1842. logit = 0;
  1843. if (lscsi_status != SS_CHECK_CONDITION)
  1844. break;
  1845. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1846. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1847. break;
  1848. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1849. rsp, res);
  1850. break;
  1851. case CS_DATA_UNDERRUN:
  1852. /* Use F/W calculated residual length. */
  1853. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1854. scsi_set_resid(cp, resid);
  1855. if (scsi_status & SS_RESIDUAL_UNDER) {
  1856. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1857. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1858. "Dropped frame(s) detected "
  1859. "(0x%x of 0x%x bytes).\n",
  1860. resid, scsi_bufflen(cp));
  1861. res = DID_ERROR << 16 | lscsi_status;
  1862. goto check_scsi_status;
  1863. }
  1864. if (!lscsi_status &&
  1865. ((unsigned)(scsi_bufflen(cp) - resid) <
  1866. cp->underflow)) {
  1867. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1868. "Mid-layer underflow "
  1869. "detected (0x%x of 0x%x bytes).\n",
  1870. resid, scsi_bufflen(cp));
  1871. res = DID_ERROR << 16;
  1872. break;
  1873. }
  1874. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1875. lscsi_status != SAM_STAT_BUSY) {
  1876. /*
  1877. * scsi status of task set and busy are considered to be
  1878. * task not completed.
  1879. */
  1880. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1881. "Dropped frame(s) detected (0x%x "
  1882. "of 0x%x bytes).\n", resid,
  1883. scsi_bufflen(cp));
  1884. res = DID_ERROR << 16 | lscsi_status;
  1885. goto check_scsi_status;
  1886. } else {
  1887. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1888. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1889. scsi_status, lscsi_status);
  1890. }
  1891. res = DID_OK << 16 | lscsi_status;
  1892. logit = 0;
  1893. check_scsi_status:
  1894. /*
  1895. * Check to see if SCSI Status is non zero. If so report SCSI
  1896. * Status.
  1897. */
  1898. if (lscsi_status != 0) {
  1899. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1900. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1901. "QUEUE FULL detected.\n");
  1902. logit = 1;
  1903. break;
  1904. }
  1905. if (lscsi_status != SS_CHECK_CONDITION)
  1906. break;
  1907. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1908. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1909. break;
  1910. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1911. sense_len, rsp, res);
  1912. }
  1913. break;
  1914. case CS_PORT_LOGGED_OUT:
  1915. case CS_PORT_CONFIG_CHG:
  1916. case CS_PORT_BUSY:
  1917. case CS_INCOMPLETE:
  1918. case CS_PORT_UNAVAILABLE:
  1919. case CS_TIMEOUT:
  1920. case CS_RESET:
  1921. /*
  1922. * We are going to have the fc class block the rport
  1923. * while we try to recover so instruct the mid layer
  1924. * to requeue until the class decides how to handle this.
  1925. */
  1926. res = DID_TRANSPORT_DISRUPTED << 16;
  1927. if (comp_status == CS_TIMEOUT) {
  1928. if (IS_FWI2_CAPABLE(ha))
  1929. break;
  1930. else if ((le16_to_cpu(sts->status_flags) &
  1931. SF_LOGOUT_SENT) == 0)
  1932. break;
  1933. }
  1934. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1935. "Port to be marked lost on fcport=%02x%02x%02x, current "
  1936. "port state= %s.\n", fcport->d_id.b.domain,
  1937. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1938. port_state_str[atomic_read(&fcport->state)]);
  1939. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1940. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1941. break;
  1942. case CS_ABORTED:
  1943. res = DID_RESET << 16;
  1944. break;
  1945. case CS_DIF_ERROR:
  1946. logit = qla2x00_handle_dif_error(sp, sts24);
  1947. res = cp->result;
  1948. break;
  1949. case CS_TRANSPORT:
  1950. res = DID_ERROR << 16;
  1951. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1952. break;
  1953. if (state_flags & BIT_4)
  1954. scmd_printk(KERN_WARNING, cp,
  1955. "Unsupported device '%s' found.\n",
  1956. cp->device->vendor);
  1957. break;
  1958. default:
  1959. res = DID_ERROR << 16;
  1960. break;
  1961. }
  1962. out:
  1963. if (logit)
  1964. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1965. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  1966. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  1967. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1968. comp_status, scsi_status, res, vha->host_no,
  1969. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1970. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1971. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  1972. resid_len, fw_resid_len);
  1973. if (!res)
  1974. qla2x00_do_host_ramp_up(vha);
  1975. if (rsp->status_srb == NULL)
  1976. sp->done(ha, sp, res);
  1977. }
  1978. /**
  1979. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1980. * @ha: SCSI driver HA context
  1981. * @pkt: Entry pointer
  1982. *
  1983. * Extended sense data.
  1984. */
  1985. static void
  1986. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1987. {
  1988. uint8_t sense_sz = 0;
  1989. struct qla_hw_data *ha = rsp->hw;
  1990. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1991. srb_t *sp = rsp->status_srb;
  1992. struct scsi_cmnd *cp;
  1993. uint32_t sense_len;
  1994. uint8_t *sense_ptr;
  1995. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1996. return;
  1997. sense_len = GET_CMD_SENSE_LEN(sp);
  1998. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1999. cp = GET_CMD_SP(sp);
  2000. if (cp == NULL) {
  2001. ql_log(ql_log_warn, vha, 0x3025,
  2002. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2003. rsp->status_srb = NULL;
  2004. return;
  2005. }
  2006. if (sense_len > sizeof(pkt->data))
  2007. sense_sz = sizeof(pkt->data);
  2008. else
  2009. sense_sz = sense_len;
  2010. /* Move sense data. */
  2011. if (IS_FWI2_CAPABLE(ha))
  2012. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  2013. memcpy(sense_ptr, pkt->data, sense_sz);
  2014. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2015. sense_ptr, sense_sz);
  2016. sense_len -= sense_sz;
  2017. sense_ptr += sense_sz;
  2018. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2019. SET_CMD_SENSE_LEN(sp, sense_len);
  2020. /* Place command on done queue. */
  2021. if (sense_len == 0) {
  2022. rsp->status_srb = NULL;
  2023. sp->done(ha, sp, cp->result);
  2024. }
  2025. }
  2026. /**
  2027. * qla2x00_error_entry() - Process an error entry.
  2028. * @ha: SCSI driver HA context
  2029. * @pkt: Entry pointer
  2030. */
  2031. static void
  2032. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2033. {
  2034. srb_t *sp;
  2035. struct qla_hw_data *ha = vha->hw;
  2036. const char func[] = "ERROR-IOCB";
  2037. uint16_t que = MSW(pkt->handle);
  2038. struct req_que *req = NULL;
  2039. int res = DID_ERROR << 16;
  2040. ql_dbg(ql_dbg_async, vha, 0x502a,
  2041. "type of error status in response: 0x%x\n", pkt->entry_status);
  2042. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2043. goto fatal;
  2044. req = ha->req_q_map[que];
  2045. if (pkt->entry_status & RF_BUSY)
  2046. res = DID_BUS_BUSY << 16;
  2047. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2048. if (sp) {
  2049. sp->done(ha, sp, res);
  2050. return;
  2051. }
  2052. fatal:
  2053. ql_log(ql_log_warn, vha, 0x5030,
  2054. "Error entry - invalid handle/queue.\n");
  2055. if (IS_P3P_TYPE(ha))
  2056. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2057. else
  2058. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2059. qla2xxx_wake_dpc(vha);
  2060. }
  2061. /**
  2062. * qla24xx_mbx_completion() - Process mailbox command completions.
  2063. * @ha: SCSI driver HA context
  2064. * @mb0: Mailbox0 register
  2065. */
  2066. static void
  2067. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2068. {
  2069. uint16_t cnt;
  2070. uint32_t mboxes;
  2071. uint16_t __iomem *wptr;
  2072. struct qla_hw_data *ha = vha->hw;
  2073. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2074. /* Read all mbox registers? */
  2075. mboxes = (1 << ha->mbx_count) - 1;
  2076. if (!ha->mcp)
  2077. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2078. else
  2079. mboxes = ha->mcp->in_mb;
  2080. /* Load return mailbox registers. */
  2081. ha->flags.mbox_int = 1;
  2082. ha->mailbox_out[0] = mb0;
  2083. mboxes >>= 1;
  2084. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2085. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2086. if (mboxes & BIT_0)
  2087. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2088. mboxes >>= 1;
  2089. wptr++;
  2090. }
  2091. }
  2092. /**
  2093. * qla24xx_process_response_queue() - Process response queue entries.
  2094. * @ha: SCSI driver HA context
  2095. */
  2096. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2097. struct rsp_que *rsp)
  2098. {
  2099. struct sts_entry_24xx *pkt;
  2100. struct qla_hw_data *ha = vha->hw;
  2101. if (!vha->flags.online)
  2102. return;
  2103. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2104. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2105. rsp->ring_index++;
  2106. if (rsp->ring_index == rsp->length) {
  2107. rsp->ring_index = 0;
  2108. rsp->ring_ptr = rsp->ring;
  2109. } else {
  2110. rsp->ring_ptr++;
  2111. }
  2112. if (pkt->entry_status != 0) {
  2113. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2114. (void)qlt_24xx_process_response_error(vha, pkt);
  2115. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2116. wmb();
  2117. continue;
  2118. }
  2119. switch (pkt->entry_type) {
  2120. case STATUS_TYPE:
  2121. qla2x00_status_entry(vha, rsp, pkt);
  2122. break;
  2123. case STATUS_CONT_TYPE:
  2124. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2125. break;
  2126. case VP_RPT_ID_IOCB_TYPE:
  2127. qla24xx_report_id_acquisition(vha,
  2128. (struct vp_rpt_id_entry_24xx *)pkt);
  2129. break;
  2130. case LOGINOUT_PORT_IOCB_TYPE:
  2131. qla24xx_logio_entry(vha, rsp->req,
  2132. (struct logio_entry_24xx *)pkt);
  2133. break;
  2134. case TSK_MGMT_IOCB_TYPE:
  2135. qla24xx_tm_iocb_entry(vha, rsp->req,
  2136. (struct tsk_mgmt_entry *)pkt);
  2137. break;
  2138. case CT_IOCB_TYPE:
  2139. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2140. break;
  2141. case ELS_IOCB_TYPE:
  2142. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2143. break;
  2144. case ABTS_RECV_24XX:
  2145. /* ensure that the ATIO queue is empty */
  2146. qlt_24xx_process_atio_queue(vha);
  2147. case ABTS_RESP_24XX:
  2148. case CTIO_TYPE7:
  2149. case NOTIFY_ACK_TYPE:
  2150. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2151. break;
  2152. case MARKER_TYPE:
  2153. /* Do nothing in this case, this check is to prevent it
  2154. * from falling into default case
  2155. */
  2156. break;
  2157. default:
  2158. /* Type Not Supported. */
  2159. ql_dbg(ql_dbg_async, vha, 0x5042,
  2160. "Received unknown response pkt type %x "
  2161. "entry status=%x.\n",
  2162. pkt->entry_type, pkt->entry_status);
  2163. break;
  2164. }
  2165. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2166. wmb();
  2167. }
  2168. /* Adjust ring index */
  2169. if (IS_P3P_TYPE(ha)) {
  2170. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2171. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2172. } else
  2173. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2174. }
  2175. static void
  2176. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2177. {
  2178. int rval;
  2179. uint32_t cnt;
  2180. struct qla_hw_data *ha = vha->hw;
  2181. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2182. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2183. return;
  2184. rval = QLA_SUCCESS;
  2185. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2186. RD_REG_DWORD(&reg->iobase_addr);
  2187. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2188. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2189. rval == QLA_SUCCESS; cnt--) {
  2190. if (cnt) {
  2191. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2192. udelay(10);
  2193. } else
  2194. rval = QLA_FUNCTION_TIMEOUT;
  2195. }
  2196. if (rval == QLA_SUCCESS)
  2197. goto next_test;
  2198. rval = QLA_SUCCESS;
  2199. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2200. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2201. rval == QLA_SUCCESS; cnt--) {
  2202. if (cnt) {
  2203. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2204. udelay(10);
  2205. } else
  2206. rval = QLA_FUNCTION_TIMEOUT;
  2207. }
  2208. if (rval != QLA_SUCCESS)
  2209. goto done;
  2210. next_test:
  2211. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2212. ql_log(ql_log_info, vha, 0x504c,
  2213. "Additional code -- 0x55AA.\n");
  2214. done:
  2215. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2216. RD_REG_DWORD(&reg->iobase_window);
  2217. }
  2218. /**
  2219. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2220. * @irq:
  2221. * @dev_id: SCSI driver HA context
  2222. *
  2223. * Called by system whenever the host adapter generates an interrupt.
  2224. *
  2225. * Returns handled flag.
  2226. */
  2227. irqreturn_t
  2228. qla24xx_intr_handler(int irq, void *dev_id)
  2229. {
  2230. scsi_qla_host_t *vha;
  2231. struct qla_hw_data *ha;
  2232. struct device_reg_24xx __iomem *reg;
  2233. int status;
  2234. unsigned long iter;
  2235. uint32_t stat;
  2236. uint32_t hccr;
  2237. uint16_t mb[8];
  2238. struct rsp_que *rsp;
  2239. unsigned long flags;
  2240. rsp = (struct rsp_que *) dev_id;
  2241. if (!rsp) {
  2242. ql_log(ql_log_info, NULL, 0x5059,
  2243. "%s: NULL response queue pointer.\n", __func__);
  2244. return IRQ_NONE;
  2245. }
  2246. ha = rsp->hw;
  2247. reg = &ha->iobase->isp24;
  2248. status = 0;
  2249. if (unlikely(pci_channel_offline(ha->pdev)))
  2250. return IRQ_HANDLED;
  2251. spin_lock_irqsave(&ha->hardware_lock, flags);
  2252. vha = pci_get_drvdata(ha->pdev);
  2253. for (iter = 50; iter--; ) {
  2254. stat = RD_REG_DWORD(&reg->host_status);
  2255. if (stat & HSRX_RISC_PAUSED) {
  2256. if (unlikely(pci_channel_offline(ha->pdev)))
  2257. break;
  2258. hccr = RD_REG_DWORD(&reg->hccr);
  2259. ql_log(ql_log_warn, vha, 0x504b,
  2260. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2261. hccr);
  2262. qla2xxx_check_risc_status(vha);
  2263. ha->isp_ops->fw_dump(vha, 1);
  2264. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2265. break;
  2266. } else if ((stat & HSRX_RISC_INT) == 0)
  2267. break;
  2268. switch (stat & 0xff) {
  2269. case INTR_ROM_MB_SUCCESS:
  2270. case INTR_ROM_MB_FAILED:
  2271. case INTR_MB_SUCCESS:
  2272. case INTR_MB_FAILED:
  2273. qla24xx_mbx_completion(vha, MSW(stat));
  2274. status |= MBX_INTERRUPT;
  2275. break;
  2276. case INTR_ASYNC_EVENT:
  2277. mb[0] = MSW(stat);
  2278. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2279. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2280. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2281. qla2x00_async_event(vha, rsp, mb);
  2282. break;
  2283. case INTR_RSP_QUE_UPDATE:
  2284. case INTR_RSP_QUE_UPDATE_83XX:
  2285. qla24xx_process_response_queue(vha, rsp);
  2286. break;
  2287. case INTR_ATIO_QUE_UPDATE:
  2288. qlt_24xx_process_atio_queue(vha);
  2289. break;
  2290. case INTR_ATIO_RSP_QUE_UPDATE:
  2291. qlt_24xx_process_atio_queue(vha);
  2292. qla24xx_process_response_queue(vha, rsp);
  2293. break;
  2294. default:
  2295. ql_dbg(ql_dbg_async, vha, 0x504f,
  2296. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2297. break;
  2298. }
  2299. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2300. RD_REG_DWORD_RELAXED(&reg->hccr);
  2301. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2302. ndelay(3500);
  2303. }
  2304. qla2x00_handle_mbx_completion(ha, status);
  2305. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2306. return IRQ_HANDLED;
  2307. }
  2308. static irqreturn_t
  2309. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2310. {
  2311. struct qla_hw_data *ha;
  2312. struct rsp_que *rsp;
  2313. struct device_reg_24xx __iomem *reg;
  2314. struct scsi_qla_host *vha;
  2315. unsigned long flags;
  2316. rsp = (struct rsp_que *) dev_id;
  2317. if (!rsp) {
  2318. ql_log(ql_log_info, NULL, 0x505a,
  2319. "%s: NULL response queue pointer.\n", __func__);
  2320. return IRQ_NONE;
  2321. }
  2322. ha = rsp->hw;
  2323. reg = &ha->iobase->isp24;
  2324. spin_lock_irqsave(&ha->hardware_lock, flags);
  2325. vha = pci_get_drvdata(ha->pdev);
  2326. qla24xx_process_response_queue(vha, rsp);
  2327. if (!ha->flags.disable_msix_handshake) {
  2328. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2329. RD_REG_DWORD_RELAXED(&reg->hccr);
  2330. }
  2331. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2332. return IRQ_HANDLED;
  2333. }
  2334. static irqreturn_t
  2335. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2336. {
  2337. struct qla_hw_data *ha;
  2338. struct rsp_que *rsp;
  2339. struct device_reg_24xx __iomem *reg;
  2340. unsigned long flags;
  2341. rsp = (struct rsp_que *) dev_id;
  2342. if (!rsp) {
  2343. ql_log(ql_log_info, NULL, 0x505b,
  2344. "%s: NULL response queue pointer.\n", __func__);
  2345. return IRQ_NONE;
  2346. }
  2347. ha = rsp->hw;
  2348. /* Clear the interrupt, if enabled, for this response queue */
  2349. if (!ha->flags.disable_msix_handshake) {
  2350. reg = &ha->iobase->isp24;
  2351. spin_lock_irqsave(&ha->hardware_lock, flags);
  2352. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2353. RD_REG_DWORD_RELAXED(&reg->hccr);
  2354. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2355. }
  2356. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2357. return IRQ_HANDLED;
  2358. }
  2359. static irqreturn_t
  2360. qla24xx_msix_default(int irq, void *dev_id)
  2361. {
  2362. scsi_qla_host_t *vha;
  2363. struct qla_hw_data *ha;
  2364. struct rsp_que *rsp;
  2365. struct device_reg_24xx __iomem *reg;
  2366. int status;
  2367. uint32_t stat;
  2368. uint32_t hccr;
  2369. uint16_t mb[8];
  2370. unsigned long flags;
  2371. rsp = (struct rsp_que *) dev_id;
  2372. if (!rsp) {
  2373. ql_log(ql_log_info, NULL, 0x505c,
  2374. "%s: NULL response queue pointer.\n", __func__);
  2375. return IRQ_NONE;
  2376. }
  2377. ha = rsp->hw;
  2378. reg = &ha->iobase->isp24;
  2379. status = 0;
  2380. spin_lock_irqsave(&ha->hardware_lock, flags);
  2381. vha = pci_get_drvdata(ha->pdev);
  2382. do {
  2383. stat = RD_REG_DWORD(&reg->host_status);
  2384. if (stat & HSRX_RISC_PAUSED) {
  2385. if (unlikely(pci_channel_offline(ha->pdev)))
  2386. break;
  2387. hccr = RD_REG_DWORD(&reg->hccr);
  2388. ql_log(ql_log_info, vha, 0x5050,
  2389. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2390. hccr);
  2391. qla2xxx_check_risc_status(vha);
  2392. ha->isp_ops->fw_dump(vha, 1);
  2393. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2394. break;
  2395. } else if ((stat & HSRX_RISC_INT) == 0)
  2396. break;
  2397. switch (stat & 0xff) {
  2398. case INTR_ROM_MB_SUCCESS:
  2399. case INTR_ROM_MB_FAILED:
  2400. case INTR_MB_SUCCESS:
  2401. case INTR_MB_FAILED:
  2402. qla24xx_mbx_completion(vha, MSW(stat));
  2403. status |= MBX_INTERRUPT;
  2404. break;
  2405. case INTR_ASYNC_EVENT:
  2406. mb[0] = MSW(stat);
  2407. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2408. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2409. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2410. qla2x00_async_event(vha, rsp, mb);
  2411. break;
  2412. case INTR_RSP_QUE_UPDATE:
  2413. case INTR_RSP_QUE_UPDATE_83XX:
  2414. qla24xx_process_response_queue(vha, rsp);
  2415. break;
  2416. case INTR_ATIO_QUE_UPDATE:
  2417. qlt_24xx_process_atio_queue(vha);
  2418. break;
  2419. case INTR_ATIO_RSP_QUE_UPDATE:
  2420. qlt_24xx_process_atio_queue(vha);
  2421. qla24xx_process_response_queue(vha, rsp);
  2422. break;
  2423. default:
  2424. ql_dbg(ql_dbg_async, vha, 0x5051,
  2425. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2426. break;
  2427. }
  2428. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2429. } while (0);
  2430. qla2x00_handle_mbx_completion(ha, status);
  2431. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2432. return IRQ_HANDLED;
  2433. }
  2434. /* Interrupt handling helpers. */
  2435. struct qla_init_msix_entry {
  2436. const char *name;
  2437. irq_handler_t handler;
  2438. };
  2439. static struct qla_init_msix_entry msix_entries[3] = {
  2440. { "qla2xxx (default)", qla24xx_msix_default },
  2441. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2442. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2443. };
  2444. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2445. { "qla2xxx (default)", qla82xx_msix_default },
  2446. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2447. };
  2448. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2449. { "qla2xxx (default)", qla24xx_msix_default },
  2450. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2451. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2452. };
  2453. static void
  2454. qla24xx_disable_msix(struct qla_hw_data *ha)
  2455. {
  2456. int i;
  2457. struct qla_msix_entry *qentry;
  2458. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2459. for (i = 0; i < ha->msix_count; i++) {
  2460. qentry = &ha->msix_entries[i];
  2461. if (qentry->have_irq)
  2462. free_irq(qentry->vector, qentry->rsp);
  2463. }
  2464. pci_disable_msix(ha->pdev);
  2465. kfree(ha->msix_entries);
  2466. ha->msix_entries = NULL;
  2467. ha->flags.msix_enabled = 0;
  2468. ql_dbg(ql_dbg_init, vha, 0x0042,
  2469. "Disabled the MSI.\n");
  2470. }
  2471. static int
  2472. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2473. {
  2474. #define MIN_MSIX_COUNT 2
  2475. int i, ret;
  2476. struct msix_entry *entries;
  2477. struct qla_msix_entry *qentry;
  2478. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2479. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2480. GFP_KERNEL);
  2481. if (!entries) {
  2482. ql_log(ql_log_warn, vha, 0x00bc,
  2483. "Failed to allocate memory for msix_entry.\n");
  2484. return -ENOMEM;
  2485. }
  2486. for (i = 0; i < ha->msix_count; i++)
  2487. entries[i].entry = i;
  2488. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2489. if (ret) {
  2490. if (ret < MIN_MSIX_COUNT)
  2491. goto msix_failed;
  2492. ql_log(ql_log_warn, vha, 0x00c6,
  2493. "MSI-X: Failed to enable support "
  2494. "-- %d/%d\n Retry with %d vectors.\n",
  2495. ha->msix_count, ret, ret);
  2496. ha->msix_count = ret;
  2497. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2498. if (ret) {
  2499. msix_failed:
  2500. ql_log(ql_log_fatal, vha, 0x00c7,
  2501. "MSI-X: Failed to enable support, "
  2502. "giving up -- %d/%d.\n",
  2503. ha->msix_count, ret);
  2504. goto msix_out;
  2505. }
  2506. ha->max_rsp_queues = ha->msix_count - 1;
  2507. }
  2508. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2509. ha->msix_count, GFP_KERNEL);
  2510. if (!ha->msix_entries) {
  2511. ql_log(ql_log_fatal, vha, 0x00c8,
  2512. "Failed to allocate memory for ha->msix_entries.\n");
  2513. ret = -ENOMEM;
  2514. goto msix_out;
  2515. }
  2516. ha->flags.msix_enabled = 1;
  2517. for (i = 0; i < ha->msix_count; i++) {
  2518. qentry = &ha->msix_entries[i];
  2519. qentry->vector = entries[i].vector;
  2520. qentry->entry = entries[i].entry;
  2521. qentry->have_irq = 0;
  2522. qentry->rsp = NULL;
  2523. }
  2524. /* Enable MSI-X vectors for the base queue */
  2525. for (i = 0; i < ha->msix_count; i++) {
  2526. qentry = &ha->msix_entries[i];
  2527. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2528. ret = request_irq(qentry->vector,
  2529. qla83xx_msix_entries[i].handler,
  2530. 0, qla83xx_msix_entries[i].name, rsp);
  2531. } else if (IS_P3P_TYPE(ha)) {
  2532. ret = request_irq(qentry->vector,
  2533. qla82xx_msix_entries[i].handler,
  2534. 0, qla82xx_msix_entries[i].name, rsp);
  2535. } else {
  2536. ret = request_irq(qentry->vector,
  2537. msix_entries[i].handler,
  2538. 0, msix_entries[i].name, rsp);
  2539. }
  2540. if (ret) {
  2541. ql_log(ql_log_fatal, vha, 0x00cb,
  2542. "MSI-X: unable to register handler -- %x/%d.\n",
  2543. qentry->vector, ret);
  2544. qla24xx_disable_msix(ha);
  2545. ha->mqenable = 0;
  2546. goto msix_out;
  2547. }
  2548. qentry->have_irq = 1;
  2549. qentry->rsp = rsp;
  2550. rsp->msix = qentry;
  2551. }
  2552. /* Enable MSI-X vector for response queue update for queue 0 */
  2553. if (IS_QLA83XX(ha)) {
  2554. if (ha->msixbase && ha->mqiobase &&
  2555. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2556. ha->mqenable = 1;
  2557. } else
  2558. if (ha->mqiobase
  2559. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2560. ha->mqenable = 1;
  2561. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2562. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2563. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2564. ql_dbg(ql_dbg_init, vha, 0x0055,
  2565. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2566. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2567. msix_out:
  2568. kfree(entries);
  2569. return ret;
  2570. }
  2571. int
  2572. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2573. {
  2574. int ret;
  2575. device_reg_t __iomem *reg = ha->iobase;
  2576. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2577. /* If possible, enable MSI-X. */
  2578. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2579. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha))
  2580. goto skip_msi;
  2581. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2582. (ha->pdev->subsystem_device == 0x7040 ||
  2583. ha->pdev->subsystem_device == 0x7041 ||
  2584. ha->pdev->subsystem_device == 0x1705)) {
  2585. ql_log(ql_log_warn, vha, 0x0034,
  2586. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2587. ha->pdev->subsystem_vendor,
  2588. ha->pdev->subsystem_device);
  2589. goto skip_msi;
  2590. }
  2591. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2592. ql_log(ql_log_warn, vha, 0x0035,
  2593. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2594. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2595. goto skip_msix;
  2596. }
  2597. ret = qla24xx_enable_msix(ha, rsp);
  2598. if (!ret) {
  2599. ql_dbg(ql_dbg_init, vha, 0x0036,
  2600. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2601. ha->chip_revision, ha->fw_attributes);
  2602. goto clear_risc_ints;
  2603. }
  2604. ql_log(ql_log_info, vha, 0x0037,
  2605. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2606. skip_msix:
  2607. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2608. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha))
  2609. goto skip_msi;
  2610. ret = pci_enable_msi(ha->pdev);
  2611. if (!ret) {
  2612. ql_dbg(ql_dbg_init, vha, 0x0038,
  2613. "MSI: Enabled.\n");
  2614. ha->flags.msi_enabled = 1;
  2615. } else
  2616. ql_log(ql_log_warn, vha, 0x0039,
  2617. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2618. /* Skip INTx on ISP82xx. */
  2619. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2620. return QLA_FUNCTION_FAILED;
  2621. skip_msi:
  2622. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2623. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2624. QLA2XXX_DRIVER_NAME, rsp);
  2625. if (ret) {
  2626. ql_log(ql_log_warn, vha, 0x003a,
  2627. "Failed to reserve interrupt %d already in use.\n",
  2628. ha->pdev->irq);
  2629. goto fail;
  2630. } else if (!ha->flags.msi_enabled) {
  2631. ql_dbg(ql_dbg_init, vha, 0x0125,
  2632. "INTa mode: Enabled.\n");
  2633. ha->flags.mr_intr_valid = 1;
  2634. }
  2635. clear_risc_ints:
  2636. spin_lock_irq(&ha->hardware_lock);
  2637. if (!IS_FWI2_CAPABLE(ha))
  2638. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2639. spin_unlock_irq(&ha->hardware_lock);
  2640. fail:
  2641. return ret;
  2642. }
  2643. void
  2644. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2645. {
  2646. struct qla_hw_data *ha = vha->hw;
  2647. struct rsp_que *rsp;
  2648. /*
  2649. * We need to check that ha->rsp_q_map is valid in case we are called
  2650. * from a probe failure context.
  2651. */
  2652. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2653. return;
  2654. rsp = ha->rsp_q_map[0];
  2655. if (ha->flags.msix_enabled)
  2656. qla24xx_disable_msix(ha);
  2657. else if (ha->flags.msi_enabled) {
  2658. free_irq(ha->pdev->irq, rsp);
  2659. pci_disable_msi(ha->pdev);
  2660. } else
  2661. free_irq(ha->pdev->irq, rsp);
  2662. }
  2663. int qla25xx_request_irq(struct rsp_que *rsp)
  2664. {
  2665. struct qla_hw_data *ha = rsp->hw;
  2666. struct qla_init_msix_entry *intr = &msix_entries[2];
  2667. struct qla_msix_entry *msix = rsp->msix;
  2668. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2669. int ret;
  2670. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2671. if (ret) {
  2672. ql_log(ql_log_fatal, vha, 0x00e6,
  2673. "MSI-X: Unable to register handler -- %x/%d.\n",
  2674. msix->vector, ret);
  2675. return ret;
  2676. }
  2677. msix->have_irq = 1;
  2678. msix->rsp = rsp;
  2679. return ret;
  2680. }