main.c 45 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #include "reg.h"
  20. #define ATH_PCI_VERSION "0.1"
  21. static char *dev_info = "ath9k";
  22. MODULE_AUTHOR("Atheros Communications");
  23. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25. MODULE_LICENSE("Dual BSD/GPL");
  26. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  27. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  28. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  31. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32. { 0 }
  33. };
  34. static void ath_detach(struct ath_softc *sc);
  35. static int ath_get_channel(struct ath_softc *sc,
  36. struct ieee80211_channel *chan)
  37. {
  38. int i;
  39. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  40. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  41. return i;
  42. }
  43. return -1;
  44. }
  45. static u32 ath_get_extchanmode(struct ath_softc *sc,
  46. struct ieee80211_channel *chan)
  47. {
  48. u32 chanmode = 0;
  49. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  50. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  51. switch (chan->band) {
  52. case IEEE80211_BAND_2GHZ:
  53. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  54. (tx_chan_width == ATH9K_HT_MACMODE_20))
  55. chanmode = CHANNEL_G_HT20;
  56. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  57. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  58. chanmode = CHANNEL_G_HT40PLUS;
  59. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  60. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  61. chanmode = CHANNEL_G_HT40MINUS;
  62. break;
  63. case IEEE80211_BAND_5GHZ:
  64. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  65. (tx_chan_width == ATH9K_HT_MACMODE_20))
  66. chanmode = CHANNEL_A_HT20;
  67. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  68. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  69. chanmode = CHANNEL_A_HT40PLUS;
  70. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  71. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  72. chanmode = CHANNEL_A_HT40MINUS;
  73. break;
  74. default:
  75. break;
  76. }
  77. return chanmode;
  78. }
  79. static int ath_setkey_tkip(struct ath_softc *sc,
  80. struct ieee80211_key_conf *key,
  81. struct ath9k_keyval *hk,
  82. const u8 *addr)
  83. {
  84. u8 *key_rxmic = NULL;
  85. u8 *key_txmic = NULL;
  86. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  87. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  88. if (addr == NULL) {
  89. /* Group key installation */
  90. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  91. return ath_keyset(sc, key->keyidx, hk, addr);
  92. }
  93. if (!sc->sc_splitmic) {
  94. /*
  95. * data key goes at first index,
  96. * the hal handles the MIC keys at index+64.
  97. */
  98. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  99. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  100. return ath_keyset(sc, key->keyidx, hk, addr);
  101. }
  102. /*
  103. * TX key goes at first index, RX key at +32.
  104. * The hal handles the MIC keys at index+64.
  105. */
  106. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  107. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  108. /* Txmic entry failed. No need to proceed further */
  109. DPRINTF(sc, ATH_DBG_KEYCACHE,
  110. "%s Setting TX MIC Key Failed\n", __func__);
  111. return 0;
  112. }
  113. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  114. /* XXX delete tx key on failure? */
  115. return ath_keyset(sc, key->keyidx+32, hk, addr);
  116. }
  117. static int ath_key_config(struct ath_softc *sc,
  118. const u8 *addr,
  119. struct ieee80211_key_conf *key)
  120. {
  121. struct ieee80211_vif *vif;
  122. struct ath9k_keyval hk;
  123. const u8 *mac = NULL;
  124. int ret = 0;
  125. enum nl80211_iftype opmode;
  126. memset(&hk, 0, sizeof(hk));
  127. switch (key->alg) {
  128. case ALG_WEP:
  129. hk.kv_type = ATH9K_CIPHER_WEP;
  130. break;
  131. case ALG_TKIP:
  132. hk.kv_type = ATH9K_CIPHER_TKIP;
  133. break;
  134. case ALG_CCMP:
  135. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  136. break;
  137. default:
  138. return -EINVAL;
  139. }
  140. hk.kv_len = key->keylen;
  141. memcpy(hk.kv_val, key->key, key->keylen);
  142. if (!sc->sc_vaps[0])
  143. return -EIO;
  144. vif = sc->sc_vaps[0];
  145. opmode = vif->type;
  146. /*
  147. * Strategy:
  148. * For _M_STA mc tx, we will not setup a key at all since we never
  149. * tx mc.
  150. * _M_STA mc rx, we will use the keyID.
  151. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  152. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  153. * peer node. BUT we will plumb a cleartext key so that we can do
  154. * perSta default key table lookup in software.
  155. */
  156. if (is_broadcast_ether_addr(addr)) {
  157. switch (opmode) {
  158. case NL80211_IFTYPE_STATION:
  159. /* default key: could be group WPA key
  160. * or could be static WEP key */
  161. mac = NULL;
  162. break;
  163. case NL80211_IFTYPE_ADHOC:
  164. break;
  165. case NL80211_IFTYPE_AP:
  166. break;
  167. default:
  168. ASSERT(0);
  169. break;
  170. }
  171. } else {
  172. mac = addr;
  173. }
  174. if (key->alg == ALG_TKIP)
  175. ret = ath_setkey_tkip(sc, key, &hk, mac);
  176. else
  177. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  178. if (!ret)
  179. return -EIO;
  180. return 0;
  181. }
  182. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  183. {
  184. int freeslot;
  185. freeslot = (key->keyidx >= 4) ? 1 : 0;
  186. ath_key_reset(sc, key->keyidx, freeslot);
  187. }
  188. static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
  189. {
  190. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  191. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  192. ht_info->ht_supported = true;
  193. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  194. IEEE80211_HT_CAP_SM_PS |
  195. IEEE80211_HT_CAP_SGI_40 |
  196. IEEE80211_HT_CAP_DSSSCCK40;
  197. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  198. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  199. /* set up supported mcs set */
  200. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  201. ht_info->mcs.rx_mask[0] = 0xff;
  202. ht_info->mcs.rx_mask[1] = 0xff;
  203. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  204. }
  205. static int ath_rate2idx(struct ath_softc *sc, int rate)
  206. {
  207. int i = 0, cur_band, n_rates;
  208. struct ieee80211_hw *hw = sc->hw;
  209. cur_band = hw->conf.channel->band;
  210. n_rates = sc->sbands[cur_band].n_bitrates;
  211. for (i = 0; i < n_rates; i++) {
  212. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  213. break;
  214. }
  215. /*
  216. * NB:mac80211 validates rx rate index against the supported legacy rate
  217. * index only (should be done against ht rates also), return the highest
  218. * legacy rate index for rx rate which does not match any one of the
  219. * supported basic and extended rates to make mac80211 happy.
  220. * The following hack will be cleaned up once the issue with
  221. * the rx rate index validation in mac80211 is fixed.
  222. */
  223. if (i == n_rates)
  224. return n_rates - 1;
  225. return i;
  226. }
  227. static void ath9k_rx_prepare(struct ath_softc *sc,
  228. struct sk_buff *skb,
  229. struct ath_recv_status *status,
  230. struct ieee80211_rx_status *rx_status)
  231. {
  232. struct ieee80211_hw *hw = sc->hw;
  233. struct ieee80211_channel *curchan = hw->conf.channel;
  234. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  235. rx_status->mactime = status->tsf;
  236. rx_status->band = curchan->band;
  237. rx_status->freq = curchan->center_freq;
  238. rx_status->noise = sc->sc_ani.sc_noise_floor;
  239. rx_status->signal = rx_status->noise + status->rssi;
  240. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  241. rx_status->antenna = status->antenna;
  242. /* at 45 you will be able to use MCS 15 reliably. A more elaborate
  243. * scheme can be used here but it requires tables of SNR/throughput for
  244. * each possible mode used. */
  245. rx_status->qual = status->rssi * 100 / 45;
  246. /* rssi can be more than 45 though, anything above that
  247. * should be considered at 100% */
  248. if (rx_status->qual > 100)
  249. rx_status->qual = 100;
  250. if (status->flags & ATH_RX_MIC_ERROR)
  251. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  252. if (status->flags & ATH_RX_FCS_ERROR)
  253. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  254. rx_status->flag |= RX_FLAG_TSFT;
  255. }
  256. static void ath9k_ht_conf(struct ath_softc *sc,
  257. struct ieee80211_bss_conf *bss_conf)
  258. {
  259. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  260. if (sc->hw->conf.ht.enabled) {
  261. ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
  262. if (bss_conf->ht.width_40_ok)
  263. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  264. else
  265. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  266. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  267. }
  268. }
  269. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  270. struct ieee80211_vif *vif,
  271. struct ieee80211_bss_conf *bss_conf)
  272. {
  273. struct ieee80211_hw *hw = sc->hw;
  274. struct ieee80211_channel *curchan = hw->conf.channel;
  275. struct ath_vap *avp = (void *)vif->drv_priv;
  276. int pos;
  277. if (bss_conf->assoc) {
  278. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  279. __func__,
  280. bss_conf->aid);
  281. /* New association, store aid */
  282. if (avp->av_opmode == ATH9K_M_STA) {
  283. sc->sc_curaid = bss_conf->aid;
  284. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  285. sc->sc_curaid);
  286. }
  287. /* Configure the beacon */
  288. ath_beacon_config(sc, 0);
  289. sc->sc_flags |= SC_OP_BEACONS;
  290. /* Reset rssi stats */
  291. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  292. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  293. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  294. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  295. /* Update chainmask */
  296. ath_update_chainmask(sc, hw->conf.ht.enabled);
  297. DPRINTF(sc, ATH_DBG_CONFIG,
  298. "%s: bssid %pM aid 0x%x\n",
  299. __func__,
  300. sc->sc_curbssid, sc->sc_curaid);
  301. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  302. __func__,
  303. curchan->center_freq);
  304. pos = ath_get_channel(sc, curchan);
  305. if (pos == -1) {
  306. DPRINTF(sc, ATH_DBG_FATAL,
  307. "%s: Invalid channel\n", __func__);
  308. return;
  309. }
  310. if (hw->conf.ht.enabled)
  311. sc->sc_ah->ah_channels[pos].chanmode =
  312. ath_get_extchanmode(sc, curchan);
  313. else
  314. sc->sc_ah->ah_channels[pos].chanmode =
  315. (curchan->band == IEEE80211_BAND_2GHZ) ?
  316. CHANNEL_G : CHANNEL_A;
  317. /* set h/w channel */
  318. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  319. DPRINTF(sc, ATH_DBG_FATAL,
  320. "%s: Unable to set channel\n",
  321. __func__);
  322. ath_rate_newstate(sc, avp);
  323. /* Update ratectrl about the new state */
  324. ath_rc_node_update(hw, avp->rc_node);
  325. /* Start ANI */
  326. mod_timer(&sc->sc_ani.timer,
  327. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  328. } else {
  329. DPRINTF(sc, ATH_DBG_CONFIG,
  330. "%s: Bss Info DISSOC\n", __func__);
  331. sc->sc_curaid = 0;
  332. }
  333. }
  334. void ath_get_beaconconfig(struct ath_softc *sc,
  335. int if_id,
  336. struct ath_beacon_config *conf)
  337. {
  338. struct ieee80211_hw *hw = sc->hw;
  339. /* fill in beacon config data */
  340. conf->beacon_interval = hw->conf.beacon_int;
  341. conf->listen_interval = 100;
  342. conf->dtim_count = 1;
  343. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  344. }
  345. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  346. struct ath_xmit_status *tx_status)
  347. {
  348. struct ieee80211_hw *hw = sc->hw;
  349. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  350. DPRINTF(sc, ATH_DBG_XMIT,
  351. "%s: TX complete: skb: %p\n", __func__, skb);
  352. ieee80211_tx_info_clear_status(tx_info);
  353. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  354. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  355. /* free driver's private data area of tx_info, XXX: HACK! */
  356. if (tx_info->control.vif != NULL)
  357. kfree(tx_info->control.vif);
  358. tx_info->control.vif = NULL;
  359. }
  360. if (tx_status->flags & ATH_TX_BAR) {
  361. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  362. tx_status->flags &= ~ATH_TX_BAR;
  363. }
  364. if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
  365. /* Frame was ACKed */
  366. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  367. }
  368. tx_info->status.rates[0].count = tx_status->retries + 1;
  369. ieee80211_tx_status(hw, skb);
  370. }
  371. int _ath_rx_indicate(struct ath_softc *sc,
  372. struct sk_buff *skb,
  373. struct ath_recv_status *status,
  374. u16 keyix)
  375. {
  376. struct ieee80211_hw *hw = sc->hw;
  377. struct ieee80211_rx_status rx_status;
  378. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  379. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  380. int padsize;
  381. /* see if any padding is done by the hw and remove it */
  382. if (hdrlen & 3) {
  383. padsize = hdrlen % 4;
  384. memmove(skb->data + padsize, skb->data, hdrlen);
  385. skb_pull(skb, padsize);
  386. }
  387. /* Prepare rx status */
  388. ath9k_rx_prepare(sc, skb, status, &rx_status);
  389. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  390. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  391. rx_status.flag |= RX_FLAG_DECRYPTED;
  392. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  393. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  394. && skb->len >= hdrlen + 4) {
  395. keyix = skb->data[hdrlen + 3] >> 6;
  396. if (test_bit(keyix, sc->sc_keymap))
  397. rx_status.flag |= RX_FLAG_DECRYPTED;
  398. }
  399. __ieee80211_rx(hw, skb, &rx_status);
  400. return 0;
  401. }
  402. /********************************/
  403. /* LED functions */
  404. /********************************/
  405. static void ath_led_brightness(struct led_classdev *led_cdev,
  406. enum led_brightness brightness)
  407. {
  408. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  409. struct ath_softc *sc = led->sc;
  410. switch (brightness) {
  411. case LED_OFF:
  412. if (led->led_type == ATH_LED_ASSOC ||
  413. led->led_type == ATH_LED_RADIO)
  414. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  415. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  416. (led->led_type == ATH_LED_RADIO) ? 1 :
  417. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  418. break;
  419. case LED_FULL:
  420. if (led->led_type == ATH_LED_ASSOC)
  421. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  422. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  423. break;
  424. default:
  425. break;
  426. }
  427. }
  428. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  429. char *trigger)
  430. {
  431. int ret;
  432. led->sc = sc;
  433. led->led_cdev.name = led->name;
  434. led->led_cdev.default_trigger = trigger;
  435. led->led_cdev.brightness_set = ath_led_brightness;
  436. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  437. if (ret)
  438. DPRINTF(sc, ATH_DBG_FATAL,
  439. "Failed to register led:%s", led->name);
  440. else
  441. led->registered = 1;
  442. return ret;
  443. }
  444. static void ath_unregister_led(struct ath_led *led)
  445. {
  446. if (led->registered) {
  447. led_classdev_unregister(&led->led_cdev);
  448. led->registered = 0;
  449. }
  450. }
  451. static void ath_deinit_leds(struct ath_softc *sc)
  452. {
  453. ath_unregister_led(&sc->assoc_led);
  454. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  455. ath_unregister_led(&sc->tx_led);
  456. ath_unregister_led(&sc->rx_led);
  457. ath_unregister_led(&sc->radio_led);
  458. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  459. }
  460. static void ath_init_leds(struct ath_softc *sc)
  461. {
  462. char *trigger;
  463. int ret;
  464. /* Configure gpio 1 for output */
  465. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  466. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  467. /* LED off, active low */
  468. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  469. trigger = ieee80211_get_radio_led_name(sc->hw);
  470. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  471. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  472. ret = ath_register_led(sc, &sc->radio_led, trigger);
  473. sc->radio_led.led_type = ATH_LED_RADIO;
  474. if (ret)
  475. goto fail;
  476. trigger = ieee80211_get_assoc_led_name(sc->hw);
  477. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  478. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  479. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  480. sc->assoc_led.led_type = ATH_LED_ASSOC;
  481. if (ret)
  482. goto fail;
  483. trigger = ieee80211_get_tx_led_name(sc->hw);
  484. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  485. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  486. ret = ath_register_led(sc, &sc->tx_led, trigger);
  487. sc->tx_led.led_type = ATH_LED_TX;
  488. if (ret)
  489. goto fail;
  490. trigger = ieee80211_get_rx_led_name(sc->hw);
  491. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  492. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  493. ret = ath_register_led(sc, &sc->rx_led, trigger);
  494. sc->rx_led.led_type = ATH_LED_RX;
  495. if (ret)
  496. goto fail;
  497. return;
  498. fail:
  499. ath_deinit_leds(sc);
  500. }
  501. #ifdef CONFIG_RFKILL
  502. /*******************/
  503. /* Rfkill */
  504. /*******************/
  505. static void ath_radio_enable(struct ath_softc *sc)
  506. {
  507. struct ath_hal *ah = sc->sc_ah;
  508. int status;
  509. spin_lock_bh(&sc->sc_resetlock);
  510. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  511. sc->sc_ht_info.tx_chan_width,
  512. sc->sc_tx_chainmask,
  513. sc->sc_rx_chainmask,
  514. sc->sc_ht_extprotspacing,
  515. false, &status)) {
  516. DPRINTF(sc, ATH_DBG_FATAL,
  517. "%s: unable to reset channel %u (%uMhz) "
  518. "flags 0x%x hal status %u\n", __func__,
  519. ath9k_hw_mhz2ieee(ah,
  520. ah->ah_curchan->channel,
  521. ah->ah_curchan->channelFlags),
  522. ah->ah_curchan->channel,
  523. ah->ah_curchan->channelFlags, status);
  524. }
  525. spin_unlock_bh(&sc->sc_resetlock);
  526. ath_update_txpow(sc);
  527. if (ath_startrecv(sc) != 0) {
  528. DPRINTF(sc, ATH_DBG_FATAL,
  529. "%s: unable to restart recv logic\n", __func__);
  530. return;
  531. }
  532. if (sc->sc_flags & SC_OP_BEACONS)
  533. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  534. /* Re-Enable interrupts */
  535. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  536. /* Enable LED */
  537. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  538. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  539. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  540. ieee80211_wake_queues(sc->hw);
  541. }
  542. static void ath_radio_disable(struct ath_softc *sc)
  543. {
  544. struct ath_hal *ah = sc->sc_ah;
  545. int status;
  546. ieee80211_stop_queues(sc->hw);
  547. /* Disable LED */
  548. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  549. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  550. /* Disable interrupts */
  551. ath9k_hw_set_interrupts(ah, 0);
  552. ath_draintxq(sc, false); /* clear pending tx frames */
  553. ath_stoprecv(sc); /* turn off frame recv */
  554. ath_flushrecv(sc); /* flush recv queue */
  555. spin_lock_bh(&sc->sc_resetlock);
  556. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  557. sc->sc_ht_info.tx_chan_width,
  558. sc->sc_tx_chainmask,
  559. sc->sc_rx_chainmask,
  560. sc->sc_ht_extprotspacing,
  561. false, &status)) {
  562. DPRINTF(sc, ATH_DBG_FATAL,
  563. "%s: unable to reset channel %u (%uMhz) "
  564. "flags 0x%x hal status %u\n", __func__,
  565. ath9k_hw_mhz2ieee(ah,
  566. ah->ah_curchan->channel,
  567. ah->ah_curchan->channelFlags),
  568. ah->ah_curchan->channel,
  569. ah->ah_curchan->channelFlags, status);
  570. }
  571. spin_unlock_bh(&sc->sc_resetlock);
  572. ath9k_hw_phy_disable(ah);
  573. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  574. }
  575. static bool ath_is_rfkill_set(struct ath_softc *sc)
  576. {
  577. struct ath_hal *ah = sc->sc_ah;
  578. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  579. ah->ah_rfkill_polarity;
  580. }
  581. /* h/w rfkill poll function */
  582. static void ath_rfkill_poll(struct work_struct *work)
  583. {
  584. struct ath_softc *sc = container_of(work, struct ath_softc,
  585. rf_kill.rfkill_poll.work);
  586. bool radio_on;
  587. if (sc->sc_flags & SC_OP_INVALID)
  588. return;
  589. radio_on = !ath_is_rfkill_set(sc);
  590. /*
  591. * enable/disable radio only when there is a
  592. * state change in RF switch
  593. */
  594. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  595. enum rfkill_state state;
  596. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  597. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  598. : RFKILL_STATE_HARD_BLOCKED;
  599. } else if (radio_on) {
  600. ath_radio_enable(sc);
  601. state = RFKILL_STATE_UNBLOCKED;
  602. } else {
  603. ath_radio_disable(sc);
  604. state = RFKILL_STATE_HARD_BLOCKED;
  605. }
  606. if (state == RFKILL_STATE_HARD_BLOCKED)
  607. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  608. else
  609. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  610. rfkill_force_state(sc->rf_kill.rfkill, state);
  611. }
  612. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  613. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  614. }
  615. /* s/w rfkill handler */
  616. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  617. {
  618. struct ath_softc *sc = data;
  619. switch (state) {
  620. case RFKILL_STATE_SOFT_BLOCKED:
  621. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  622. SC_OP_RFKILL_SW_BLOCKED)))
  623. ath_radio_disable(sc);
  624. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  625. return 0;
  626. case RFKILL_STATE_UNBLOCKED:
  627. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  628. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  629. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  630. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  631. "radio as it is disabled by h/w \n");
  632. return -EPERM;
  633. }
  634. ath_radio_enable(sc);
  635. }
  636. return 0;
  637. default:
  638. return -EINVAL;
  639. }
  640. }
  641. /* Init s/w rfkill */
  642. static int ath_init_sw_rfkill(struct ath_softc *sc)
  643. {
  644. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  645. RFKILL_TYPE_WLAN);
  646. if (!sc->rf_kill.rfkill) {
  647. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  648. return -ENOMEM;
  649. }
  650. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  651. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  652. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  653. sc->rf_kill.rfkill->data = sc;
  654. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  655. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  656. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  657. return 0;
  658. }
  659. /* Deinitialize rfkill */
  660. static void ath_deinit_rfkill(struct ath_softc *sc)
  661. {
  662. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  663. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  664. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  665. rfkill_unregister(sc->rf_kill.rfkill);
  666. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  667. sc->rf_kill.rfkill = NULL;
  668. }
  669. }
  670. static int ath_start_rfkill_poll(struct ath_softc *sc)
  671. {
  672. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  673. queue_delayed_work(sc->hw->workqueue,
  674. &sc->rf_kill.rfkill_poll, 0);
  675. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  676. if (rfkill_register(sc->rf_kill.rfkill)) {
  677. DPRINTF(sc, ATH_DBG_FATAL,
  678. "Unable to register rfkill\n");
  679. rfkill_free(sc->rf_kill.rfkill);
  680. /* Deinitialize the device */
  681. if (sc->pdev->irq)
  682. free_irq(sc->pdev->irq, sc);
  683. ath_detach(sc);
  684. pci_iounmap(sc->pdev, sc->mem);
  685. pci_release_region(sc->pdev, 0);
  686. pci_disable_device(sc->pdev);
  687. ieee80211_free_hw(sc->hw);
  688. return -EIO;
  689. } else {
  690. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  691. }
  692. }
  693. return 0;
  694. }
  695. #endif /* CONFIG_RFKILL */
  696. static void ath_detach(struct ath_softc *sc)
  697. {
  698. struct ieee80211_hw *hw = sc->hw;
  699. int i = 0;
  700. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  701. ieee80211_unregister_hw(hw);
  702. ath_deinit_leds(sc);
  703. #ifdef CONFIG_RFKILL
  704. ath_deinit_rfkill(sc);
  705. #endif
  706. ath_rate_control_unregister();
  707. ath_rate_detach(sc->sc_rc);
  708. ath_rx_cleanup(sc);
  709. ath_tx_cleanup(sc);
  710. tasklet_kill(&sc->intr_tq);
  711. tasklet_kill(&sc->bcon_tasklet);
  712. if (!(sc->sc_flags & SC_OP_INVALID))
  713. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  714. /* cleanup tx queues */
  715. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  716. if (ATH_TXQ_SETUP(sc, i))
  717. ath_tx_cleanupq(sc, &sc->sc_txq[i]);
  718. ath9k_hw_detach(sc->sc_ah);
  719. }
  720. static int ath_attach(u16 devid, struct ath_softc *sc)
  721. {
  722. struct ieee80211_hw *hw = sc->hw;
  723. int error = 0;
  724. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  725. error = ath_init(devid, sc);
  726. if (error != 0)
  727. return error;
  728. /* get mac address from hardware and set in mac80211 */
  729. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  730. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  731. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  732. IEEE80211_HW_SIGNAL_DBM |
  733. IEEE80211_HW_AMPDU_AGGREGATION;
  734. hw->wiphy->interface_modes =
  735. BIT(NL80211_IFTYPE_AP) |
  736. BIT(NL80211_IFTYPE_STATION) |
  737. BIT(NL80211_IFTYPE_ADHOC);
  738. hw->queues = 4;
  739. hw->sta_data_size = sizeof(struct ath_node);
  740. hw->vif_data_size = sizeof(struct ath_vap);
  741. /* Register rate control */
  742. hw->rate_control_algorithm = "ath9k_rate_control";
  743. error = ath_rate_control_register();
  744. if (error != 0) {
  745. DPRINTF(sc, ATH_DBG_FATAL,
  746. "%s: Unable to register rate control "
  747. "algorithm:%d\n", __func__, error);
  748. ath_rate_control_unregister();
  749. goto bad;
  750. }
  751. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
  752. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  753. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  754. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  755. }
  756. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
  757. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  758. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  759. &sc->sbands[IEEE80211_BAND_5GHZ];
  760. error = ieee80211_register_hw(hw);
  761. if (error != 0) {
  762. ath_rate_control_unregister();
  763. goto bad;
  764. }
  765. /* Initialize LED control */
  766. ath_init_leds(sc);
  767. #ifdef CONFIG_RFKILL
  768. /* Initialze h/w Rfkill */
  769. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  770. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  771. /* Initialize s/w rfkill */
  772. if (ath_init_sw_rfkill(sc))
  773. goto detach;
  774. #endif
  775. /* initialize tx/rx engine */
  776. error = ath_tx_init(sc, ATH_TXBUF);
  777. if (error != 0)
  778. goto detach;
  779. error = ath_rx_init(sc, ATH_RXBUF);
  780. if (error != 0)
  781. goto detach;
  782. return 0;
  783. detach:
  784. ath_detach(sc);
  785. bad:
  786. return error;
  787. }
  788. static int ath9k_start(struct ieee80211_hw *hw)
  789. {
  790. struct ath_softc *sc = hw->priv;
  791. struct ieee80211_channel *curchan = hw->conf.channel;
  792. int error = 0, pos;
  793. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  794. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  795. memset(&sc->sc_ht_info, 0, sizeof(struct ath_ht_info));
  796. /* setup initial channel */
  797. pos = ath_get_channel(sc, curchan);
  798. if (pos == -1) {
  799. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  800. error = -EINVAL;
  801. goto exit;
  802. }
  803. sc->sc_ah->ah_channels[pos].chanmode =
  804. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  805. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  806. if (error) {
  807. DPRINTF(sc, ATH_DBG_FATAL,
  808. "%s: Unable to complete ath_open\n", __func__);
  809. goto exit;
  810. }
  811. #ifdef CONFIG_RFKILL
  812. error = ath_start_rfkill_poll(sc);
  813. #endif
  814. exit:
  815. return error;
  816. }
  817. static int ath9k_tx(struct ieee80211_hw *hw,
  818. struct sk_buff *skb)
  819. {
  820. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  821. struct ath_softc *sc = hw->priv;
  822. struct ath_tx_control txctl;
  823. int hdrlen, padsize;
  824. memset(&txctl, 0, sizeof(struct ath_tx_control));
  825. /*
  826. * As a temporary workaround, assign seq# here; this will likely need
  827. * to be cleaned up to work better with Beacon transmission and virtual
  828. * BSSes.
  829. */
  830. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  831. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  832. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  833. sc->seq_no += 0x10;
  834. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  835. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  836. }
  837. /* Add the padding after the header if this is not already done */
  838. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  839. if (hdrlen & 3) {
  840. padsize = hdrlen % 4;
  841. if (skb_headroom(skb) < padsize)
  842. return -1;
  843. skb_push(skb, padsize);
  844. memmove(skb->data, skb->data + padsize, hdrlen);
  845. }
  846. /* Check if a tx queue is available */
  847. txctl.txq = ath_test_get_txq(sc, skb);
  848. if (!txctl.txq)
  849. goto exit;
  850. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  851. __func__,
  852. skb);
  853. if (ath_tx_start(sc, skb, &txctl) != 0) {
  854. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  855. goto exit;
  856. }
  857. return 0;
  858. exit:
  859. dev_kfree_skb_any(skb);
  860. return 0;
  861. }
  862. static void ath9k_stop(struct ieee80211_hw *hw)
  863. {
  864. struct ath_softc *sc = hw->priv;
  865. if (sc->sc_flags & SC_OP_INVALID) {
  866. DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
  867. return;
  868. }
  869. ath_stop(sc);
  870. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  871. }
  872. static int ath9k_add_interface(struct ieee80211_hw *hw,
  873. struct ieee80211_if_init_conf *conf)
  874. {
  875. struct ath_softc *sc = hw->priv;
  876. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  877. int ic_opmode = 0;
  878. /* Support only vap for now */
  879. if (sc->sc_nvaps)
  880. return -ENOBUFS;
  881. switch (conf->type) {
  882. case NL80211_IFTYPE_STATION:
  883. ic_opmode = ATH9K_M_STA;
  884. break;
  885. case NL80211_IFTYPE_ADHOC:
  886. ic_opmode = ATH9K_M_IBSS;
  887. break;
  888. case NL80211_IFTYPE_AP:
  889. ic_opmode = ATH9K_M_HOSTAP;
  890. break;
  891. default:
  892. DPRINTF(sc, ATH_DBG_FATAL,
  893. "%s: Interface type %d not yet supported\n",
  894. __func__, conf->type);
  895. return -EOPNOTSUPP;
  896. }
  897. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  898. __func__,
  899. ic_opmode);
  900. /* Set the VAP opmode */
  901. avp->av_opmode = ic_opmode;
  902. avp->av_bslot = -1;
  903. if (ic_opmode == ATH9K_M_HOSTAP)
  904. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  905. sc->sc_vaps[0] = conf->vif;
  906. sc->sc_nvaps++;
  907. /* Set the device opmode */
  908. sc->sc_ah->ah_opmode = ic_opmode;
  909. /* default VAP configuration */
  910. avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
  911. avp->av_config.av_fixed_retryset = 0x03030303;
  912. if (conf->type == NL80211_IFTYPE_AP) {
  913. /* TODO: is this a suitable place to start ANI for AP mode? */
  914. /* Start ANI */
  915. mod_timer(&sc->sc_ani.timer,
  916. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  917. }
  918. return 0;
  919. }
  920. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  921. struct ieee80211_if_init_conf *conf)
  922. {
  923. struct ath_softc *sc = hw->priv;
  924. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  925. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  926. #ifdef CONFIG_SLOW_ANT_DIV
  927. ath_slow_ant_div_stop(&sc->sc_antdiv);
  928. #endif
  929. /* Stop ANI */
  930. del_timer_sync(&sc->sc_ani.timer);
  931. /* Reclaim beacon resources */
  932. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  933. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  934. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  935. ath_beacon_return(sc, avp);
  936. }
  937. sc->sc_flags &= ~SC_OP_BEACONS;
  938. sc->sc_vaps[0] = NULL;
  939. sc->sc_nvaps--;
  940. }
  941. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  942. {
  943. struct ath_softc *sc = hw->priv;
  944. struct ieee80211_channel *curchan = hw->conf.channel;
  945. struct ieee80211_conf *conf = &hw->conf;
  946. int pos;
  947. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  948. __func__,
  949. curchan->center_freq);
  950. /* Update chainmask */
  951. ath_update_chainmask(sc, conf->ht.enabled);
  952. pos = ath_get_channel(sc, curchan);
  953. if (pos == -1) {
  954. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  955. return -EINVAL;
  956. }
  957. sc->sc_ah->ah_channels[pos].chanmode =
  958. (curchan->band == IEEE80211_BAND_2GHZ) ?
  959. CHANNEL_G : CHANNEL_A;
  960. if (sc->sc_curaid && hw->conf.ht.enabled)
  961. sc->sc_ah->ah_channels[pos].chanmode =
  962. ath_get_extchanmode(sc, curchan);
  963. if (changed & IEEE80211_CONF_CHANGE_POWER)
  964. sc->sc_config.txpowlimit = 2 * conf->power_level;
  965. /* set h/w channel */
  966. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  967. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  968. __func__);
  969. return 0;
  970. }
  971. static int ath9k_config_interface(struct ieee80211_hw *hw,
  972. struct ieee80211_vif *vif,
  973. struct ieee80211_if_conf *conf)
  974. {
  975. struct ath_softc *sc = hw->priv;
  976. struct ath_hal *ah = sc->sc_ah;
  977. struct ath_vap *avp = (void *)vif->drv_priv;
  978. u32 rfilt = 0;
  979. int error, i;
  980. /* TODO: Need to decide which hw opmode to use for multi-interface
  981. * cases */
  982. if (vif->type == NL80211_IFTYPE_AP &&
  983. ah->ah_opmode != ATH9K_M_HOSTAP) {
  984. ah->ah_opmode = ATH9K_M_HOSTAP;
  985. ath9k_hw_setopmode(ah);
  986. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  987. /* Request full reset to get hw opmode changed properly */
  988. sc->sc_flags |= SC_OP_FULL_RESET;
  989. }
  990. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  991. !is_zero_ether_addr(conf->bssid)) {
  992. switch (vif->type) {
  993. case NL80211_IFTYPE_STATION:
  994. case NL80211_IFTYPE_ADHOC:
  995. /* Update ratectrl about the new state */
  996. ath_rate_newstate(sc, avp);
  997. /* Set BSSID */
  998. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  999. sc->sc_curaid = 0;
  1000. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  1001. sc->sc_curaid);
  1002. /* Set aggregation protection mode parameters */
  1003. sc->sc_config.ath_aggr_prot = 0;
  1004. DPRINTF(sc, ATH_DBG_CONFIG,
  1005. "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
  1006. __func__, rfilt,
  1007. sc->sc_curbssid, sc->sc_curaid);
  1008. /* need to reconfigure the beacon */
  1009. sc->sc_flags &= ~SC_OP_BEACONS ;
  1010. break;
  1011. default:
  1012. break;
  1013. }
  1014. }
  1015. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  1016. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  1017. (vif->type == NL80211_IFTYPE_AP))) {
  1018. /*
  1019. * Allocate and setup the beacon frame.
  1020. *
  1021. * Stop any previous beacon DMA. This may be
  1022. * necessary, for example, when an ibss merge
  1023. * causes reconfiguration; we may be called
  1024. * with beacon transmission active.
  1025. */
  1026. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1027. error = ath_beacon_alloc(sc, 0);
  1028. if (error != 0)
  1029. return error;
  1030. ath_beacon_sync(sc, 0);
  1031. }
  1032. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  1033. if ((avp->av_opmode != ATH9K_M_STA)) {
  1034. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  1035. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  1036. ath9k_hw_keysetmac(sc->sc_ah,
  1037. (u16)i,
  1038. sc->sc_curbssid);
  1039. }
  1040. /* Only legacy IBSS for now */
  1041. if (vif->type == NL80211_IFTYPE_ADHOC)
  1042. ath_update_chainmask(sc, 0);
  1043. return 0;
  1044. }
  1045. #define SUPPORTED_FILTERS \
  1046. (FIF_PROMISC_IN_BSS | \
  1047. FIF_ALLMULTI | \
  1048. FIF_CONTROL | \
  1049. FIF_OTHER_BSS | \
  1050. FIF_BCN_PRBRESP_PROMISC | \
  1051. FIF_FCSFAIL)
  1052. /* FIXME: sc->sc_full_reset ? */
  1053. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1054. unsigned int changed_flags,
  1055. unsigned int *total_flags,
  1056. int mc_count,
  1057. struct dev_mc_list *mclist)
  1058. {
  1059. struct ath_softc *sc = hw->priv;
  1060. u32 rfilt;
  1061. changed_flags &= SUPPORTED_FILTERS;
  1062. *total_flags &= SUPPORTED_FILTERS;
  1063. sc->rx_filter = *total_flags;
  1064. rfilt = ath_calcrxfilter(sc);
  1065. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1066. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1067. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1068. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  1069. }
  1070. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  1071. __func__, sc->rx_filter);
  1072. }
  1073. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1074. struct ieee80211_vif *vif,
  1075. enum sta_notify_cmd cmd,
  1076. struct ieee80211_sta *sta)
  1077. {
  1078. struct ath_softc *sc = hw->priv;
  1079. switch (cmd) {
  1080. case STA_NOTIFY_ADD:
  1081. ath_node_attach(sc, sta);
  1082. break;
  1083. case STA_NOTIFY_REMOVE:
  1084. ath_node_detach(sc, sta);
  1085. break;
  1086. default:
  1087. break;
  1088. }
  1089. }
  1090. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1091. u16 queue,
  1092. const struct ieee80211_tx_queue_params *params)
  1093. {
  1094. struct ath_softc *sc = hw->priv;
  1095. struct ath9k_tx_queue_info qi;
  1096. int ret = 0, qnum;
  1097. if (queue >= WME_NUM_AC)
  1098. return 0;
  1099. qi.tqi_aifs = params->aifs;
  1100. qi.tqi_cwmin = params->cw_min;
  1101. qi.tqi_cwmax = params->cw_max;
  1102. qi.tqi_burstTime = params->txop;
  1103. qnum = ath_get_hal_qnum(queue, sc);
  1104. DPRINTF(sc, ATH_DBG_CONFIG,
  1105. "%s: Configure tx [queue/halq] [%d/%d], "
  1106. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1107. __func__,
  1108. queue,
  1109. qnum,
  1110. params->aifs,
  1111. params->cw_min,
  1112. params->cw_max,
  1113. params->txop);
  1114. ret = ath_txq_update(sc, qnum, &qi);
  1115. if (ret)
  1116. DPRINTF(sc, ATH_DBG_FATAL,
  1117. "%s: TXQ Update failed\n", __func__);
  1118. return ret;
  1119. }
  1120. static int ath9k_set_key(struct ieee80211_hw *hw,
  1121. enum set_key_cmd cmd,
  1122. const u8 *local_addr,
  1123. const u8 *addr,
  1124. struct ieee80211_key_conf *key)
  1125. {
  1126. struct ath_softc *sc = hw->priv;
  1127. int ret = 0;
  1128. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1129. switch (cmd) {
  1130. case SET_KEY:
  1131. ret = ath_key_config(sc, addr, key);
  1132. if (!ret) {
  1133. set_bit(key->keyidx, sc->sc_keymap);
  1134. key->hw_key_idx = key->keyidx;
  1135. /* push IV and Michael MIC generation to stack */
  1136. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1137. if (key->alg == ALG_TKIP)
  1138. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1139. }
  1140. break;
  1141. case DISABLE_KEY:
  1142. ath_key_delete(sc, key);
  1143. clear_bit(key->keyidx, sc->sc_keymap);
  1144. break;
  1145. default:
  1146. ret = -EINVAL;
  1147. }
  1148. return ret;
  1149. }
  1150. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1151. struct ieee80211_vif *vif,
  1152. struct ieee80211_bss_conf *bss_conf,
  1153. u32 changed)
  1154. {
  1155. struct ath_softc *sc = hw->priv;
  1156. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1157. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1158. __func__,
  1159. bss_conf->use_short_preamble);
  1160. if (bss_conf->use_short_preamble)
  1161. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1162. else
  1163. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1164. }
  1165. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1166. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1167. __func__,
  1168. bss_conf->use_cts_prot);
  1169. if (bss_conf->use_cts_prot &&
  1170. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1171. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1172. else
  1173. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1174. }
  1175. if (changed & BSS_CHANGED_HT) {
  1176. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
  1177. __func__);
  1178. ath9k_ht_conf(sc, bss_conf);
  1179. }
  1180. if (changed & BSS_CHANGED_ASSOC) {
  1181. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1182. __func__,
  1183. bss_conf->assoc);
  1184. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1185. }
  1186. }
  1187. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1188. {
  1189. u64 tsf;
  1190. struct ath_softc *sc = hw->priv;
  1191. struct ath_hal *ah = sc->sc_ah;
  1192. tsf = ath9k_hw_gettsf64(ah);
  1193. return tsf;
  1194. }
  1195. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1196. {
  1197. struct ath_softc *sc = hw->priv;
  1198. struct ath_hal *ah = sc->sc_ah;
  1199. ath9k_hw_reset_tsf(ah);
  1200. }
  1201. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1202. enum ieee80211_ampdu_mlme_action action,
  1203. struct ieee80211_sta *sta,
  1204. u16 tid, u16 *ssn)
  1205. {
  1206. struct ath_softc *sc = hw->priv;
  1207. int ret = 0;
  1208. switch (action) {
  1209. case IEEE80211_AMPDU_RX_START:
  1210. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1211. ret = -ENOTSUPP;
  1212. break;
  1213. case IEEE80211_AMPDU_RX_STOP:
  1214. break;
  1215. case IEEE80211_AMPDU_TX_START:
  1216. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1217. if (ret < 0)
  1218. DPRINTF(sc, ATH_DBG_FATAL,
  1219. "%s: Unable to start TX aggregation\n",
  1220. __func__);
  1221. else
  1222. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1223. break;
  1224. case IEEE80211_AMPDU_TX_STOP:
  1225. ret = ath_tx_aggr_stop(sc, sta, tid);
  1226. if (ret < 0)
  1227. DPRINTF(sc, ATH_DBG_FATAL,
  1228. "%s: Unable to stop TX aggregation\n",
  1229. __func__);
  1230. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1231. break;
  1232. case IEEE80211_AMPDU_TX_RESUME:
  1233. ath_tx_aggr_resume(sc, sta, tid);
  1234. break;
  1235. default:
  1236. DPRINTF(sc, ATH_DBG_FATAL,
  1237. "%s: Unknown AMPDU action\n", __func__);
  1238. }
  1239. return ret;
  1240. }
  1241. static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
  1242. {
  1243. return -EOPNOTSUPP;
  1244. }
  1245. static struct ieee80211_ops ath9k_ops = {
  1246. .tx = ath9k_tx,
  1247. .start = ath9k_start,
  1248. .stop = ath9k_stop,
  1249. .add_interface = ath9k_add_interface,
  1250. .remove_interface = ath9k_remove_interface,
  1251. .config = ath9k_config,
  1252. .config_interface = ath9k_config_interface,
  1253. .configure_filter = ath9k_configure_filter,
  1254. .sta_notify = ath9k_sta_notify,
  1255. .conf_tx = ath9k_conf_tx,
  1256. .bss_info_changed = ath9k_bss_info_changed,
  1257. .set_key = ath9k_set_key,
  1258. .get_tsf = ath9k_get_tsf,
  1259. .reset_tsf = ath9k_reset_tsf,
  1260. .ampdu_action = ath9k_ampdu_action,
  1261. .set_frag_threshold = ath9k_no_fragmentation,
  1262. };
  1263. static struct {
  1264. u32 version;
  1265. const char * name;
  1266. } ath_mac_bb_names[] = {
  1267. { AR_SREV_VERSION_5416_PCI, "5416" },
  1268. { AR_SREV_VERSION_5416_PCIE, "5418" },
  1269. { AR_SREV_VERSION_9100, "9100" },
  1270. { AR_SREV_VERSION_9160, "9160" },
  1271. { AR_SREV_VERSION_9280, "9280" },
  1272. { AR_SREV_VERSION_9285, "9285" }
  1273. };
  1274. static struct {
  1275. u16 version;
  1276. const char * name;
  1277. } ath_rf_names[] = {
  1278. { 0, "5133" },
  1279. { AR_RAD5133_SREV_MAJOR, "5133" },
  1280. { AR_RAD5122_SREV_MAJOR, "5122" },
  1281. { AR_RAD2133_SREV_MAJOR, "2133" },
  1282. { AR_RAD2122_SREV_MAJOR, "2122" }
  1283. };
  1284. /*
  1285. * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
  1286. */
  1287. static const char *
  1288. ath_mac_bb_name(u32 mac_bb_version)
  1289. {
  1290. int i;
  1291. for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
  1292. if (ath_mac_bb_names[i].version == mac_bb_version) {
  1293. return ath_mac_bb_names[i].name;
  1294. }
  1295. }
  1296. return "????";
  1297. }
  1298. /*
  1299. * Return the RF name. "????" is returned if the RF is unknown.
  1300. */
  1301. static const char *
  1302. ath_rf_name(u16 rf_version)
  1303. {
  1304. int i;
  1305. for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
  1306. if (ath_rf_names[i].version == rf_version) {
  1307. return ath_rf_names[i].name;
  1308. }
  1309. }
  1310. return "????";
  1311. }
  1312. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1313. {
  1314. void __iomem *mem;
  1315. struct ath_softc *sc;
  1316. struct ieee80211_hw *hw;
  1317. u8 csz;
  1318. u32 val;
  1319. int ret = 0;
  1320. struct ath_hal *ah;
  1321. if (pci_enable_device(pdev))
  1322. return -EIO;
  1323. /* XXX 32-bit addressing only */
  1324. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1325. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1326. ret = -ENODEV;
  1327. goto bad;
  1328. }
  1329. /*
  1330. * Cache line size is used to size and align various
  1331. * structures used to communicate with the hardware.
  1332. */
  1333. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1334. if (csz == 0) {
  1335. /*
  1336. * Linux 2.4.18 (at least) writes the cache line size
  1337. * register as a 16-bit wide register which is wrong.
  1338. * We must have this setup properly for rx buffer
  1339. * DMA to work so force a reasonable value here if it
  1340. * comes up zero.
  1341. */
  1342. csz = L1_CACHE_BYTES / sizeof(u32);
  1343. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1344. }
  1345. /*
  1346. * The default setting of latency timer yields poor results,
  1347. * set it to the value used by other systems. It may be worth
  1348. * tweaking this setting more.
  1349. */
  1350. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1351. pci_set_master(pdev);
  1352. /*
  1353. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1354. * PCI Tx retries from interfering with C3 CPU state.
  1355. */
  1356. pci_read_config_dword(pdev, 0x40, &val);
  1357. if ((val & 0x0000ff00) != 0)
  1358. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1359. ret = pci_request_region(pdev, 0, "ath9k");
  1360. if (ret) {
  1361. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1362. ret = -ENODEV;
  1363. goto bad;
  1364. }
  1365. mem = pci_iomap(pdev, 0, 0);
  1366. if (!mem) {
  1367. printk(KERN_ERR "PCI memory map error\n") ;
  1368. ret = -EIO;
  1369. goto bad1;
  1370. }
  1371. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1372. if (hw == NULL) {
  1373. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1374. goto bad2;
  1375. }
  1376. SET_IEEE80211_DEV(hw, &pdev->dev);
  1377. pci_set_drvdata(pdev, hw);
  1378. sc = hw->priv;
  1379. sc->hw = hw;
  1380. sc->pdev = pdev;
  1381. sc->mem = mem;
  1382. if (ath_attach(id->device, sc) != 0) {
  1383. ret = -ENODEV;
  1384. goto bad3;
  1385. }
  1386. /* setup interrupt service routine */
  1387. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1388. printk(KERN_ERR "%s: request_irq failed\n",
  1389. wiphy_name(hw->wiphy));
  1390. ret = -EIO;
  1391. goto bad4;
  1392. }
  1393. ah = sc->sc_ah;
  1394. printk(KERN_INFO
  1395. "%s: Atheros AR%s MAC/BB Rev:%x "
  1396. "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
  1397. wiphy_name(hw->wiphy),
  1398. ath_mac_bb_name(ah->ah_macVersion),
  1399. ah->ah_macRev,
  1400. ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
  1401. ah->ah_phyRev,
  1402. (unsigned long)mem, pdev->irq);
  1403. return 0;
  1404. bad4:
  1405. ath_detach(sc);
  1406. bad3:
  1407. ieee80211_free_hw(hw);
  1408. bad2:
  1409. pci_iounmap(pdev, mem);
  1410. bad1:
  1411. pci_release_region(pdev, 0);
  1412. bad:
  1413. pci_disable_device(pdev);
  1414. return ret;
  1415. }
  1416. static void ath_pci_remove(struct pci_dev *pdev)
  1417. {
  1418. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1419. struct ath_softc *sc = hw->priv;
  1420. ath_detach(sc);
  1421. if (pdev->irq)
  1422. free_irq(pdev->irq, sc);
  1423. pci_iounmap(pdev, sc->mem);
  1424. pci_release_region(pdev, 0);
  1425. pci_disable_device(pdev);
  1426. ieee80211_free_hw(hw);
  1427. }
  1428. #ifdef CONFIG_PM
  1429. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1430. {
  1431. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1432. struct ath_softc *sc = hw->priv;
  1433. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1434. #ifdef CONFIG_RFKILL
  1435. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1436. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1437. #endif
  1438. pci_save_state(pdev);
  1439. pci_disable_device(pdev);
  1440. pci_set_power_state(pdev, 3);
  1441. return 0;
  1442. }
  1443. static int ath_pci_resume(struct pci_dev *pdev)
  1444. {
  1445. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1446. struct ath_softc *sc = hw->priv;
  1447. u32 val;
  1448. int err;
  1449. err = pci_enable_device(pdev);
  1450. if (err)
  1451. return err;
  1452. pci_restore_state(pdev);
  1453. /*
  1454. * Suspend/Resume resets the PCI configuration space, so we have to
  1455. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1456. * PCI Tx retries from interfering with C3 CPU state
  1457. */
  1458. pci_read_config_dword(pdev, 0x40, &val);
  1459. if ((val & 0x0000ff00) != 0)
  1460. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1461. /* Enable LED */
  1462. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1463. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1464. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1465. #ifdef CONFIG_RFKILL
  1466. /*
  1467. * check the h/w rfkill state on resume
  1468. * and start the rfkill poll timer
  1469. */
  1470. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1471. queue_delayed_work(sc->hw->workqueue,
  1472. &sc->rf_kill.rfkill_poll, 0);
  1473. #endif
  1474. return 0;
  1475. }
  1476. #endif /* CONFIG_PM */
  1477. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1478. static struct pci_driver ath_pci_driver = {
  1479. .name = "ath9k",
  1480. .id_table = ath_pci_id_table,
  1481. .probe = ath_pci_probe,
  1482. .remove = ath_pci_remove,
  1483. #ifdef CONFIG_PM
  1484. .suspend = ath_pci_suspend,
  1485. .resume = ath_pci_resume,
  1486. #endif /* CONFIG_PM */
  1487. };
  1488. static int __init init_ath_pci(void)
  1489. {
  1490. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1491. if (pci_register_driver(&ath_pci_driver) < 0) {
  1492. printk(KERN_ERR
  1493. "ath_pci: No devices found, driver not installed.\n");
  1494. pci_unregister_driver(&ath_pci_driver);
  1495. return -ENODEV;
  1496. }
  1497. return 0;
  1498. }
  1499. module_init(init_ath_pci);
  1500. static void __exit exit_ath_pci(void)
  1501. {
  1502. pci_unregister_driver(&ath_pci_driver);
  1503. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1504. }
  1505. module_exit(exit_ath_pci);