gianfar.c 86 KB

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  1. /* drivers/net/ethernet/freescale/gianfar.c
  2. *
  3. * Gianfar Ethernet Driver
  4. * This driver is designed for the non-CPM ethernet controllers
  5. * on the 85xx and 83xx family of integrated processors
  6. * Based on 8260_io/fcc_enet.c
  7. *
  8. * Author: Andy Fleming
  9. * Maintainer: Kumar Gala
  10. * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11. *
  12. * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13. * Copyright 2007 MontaVista Software, Inc.
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * Gianfar: AKA Lambda Draconis, "Dragon"
  21. * RA 11 31 24.2
  22. * Dec +69 19 52
  23. * V 3.84
  24. * B-V +1.62
  25. *
  26. * Theory of operation
  27. *
  28. * The driver is initialized through of_device. Configuration information
  29. * is therefore conveyed through an OF-style device tree.
  30. *
  31. * The Gianfar Ethernet Controller uses a ring of buffer
  32. * descriptors. The beginning is indicated by a register
  33. * pointing to the physical address of the start of the ring.
  34. * The end is determined by a "wrap" bit being set in the
  35. * last descriptor of the ring.
  36. *
  37. * When a packet is received, the RXF bit in the
  38. * IEVENT register is set, triggering an interrupt when the
  39. * corresponding bit in the IMASK register is also set (if
  40. * interrupt coalescing is active, then the interrupt may not
  41. * happen immediately, but will wait until either a set number
  42. * of frames or amount of time have passed). In NAPI, the
  43. * interrupt handler will signal there is work to be done, and
  44. * exit. This method will start at the last known empty
  45. * descriptor, and process every subsequent descriptor until there
  46. * are none left with data (NAPI will stop after a set number of
  47. * packets to give time to other tasks, but will eventually
  48. * process all the packets). The data arrives inside a
  49. * pre-allocated skb, and so after the skb is passed up to the
  50. * stack, a new skb must be allocated, and the address field in
  51. * the buffer descriptor must be updated to indicate this new
  52. * skb.
  53. *
  54. * When the kernel requests that a packet be transmitted, the
  55. * driver starts where it left off last time, and points the
  56. * descriptor at the buffer which was passed in. The driver
  57. * then informs the DMA engine that there are packets ready to
  58. * be transmitted. Once the controller is finished transmitting
  59. * the packet, an interrupt may be triggered (under the same
  60. * conditions as for reception, but depending on the TXF bit).
  61. * The driver then cleans up the buffer.
  62. */
  63. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  64. #define DEBUG
  65. #include <linux/kernel.h>
  66. #include <linux/string.h>
  67. #include <linux/errno.h>
  68. #include <linux/unistd.h>
  69. #include <linux/slab.h>
  70. #include <linux/interrupt.h>
  71. #include <linux/init.h>
  72. #include <linux/delay.h>
  73. #include <linux/netdevice.h>
  74. #include <linux/etherdevice.h>
  75. #include <linux/skbuff.h>
  76. #include <linux/if_vlan.h>
  77. #include <linux/spinlock.h>
  78. #include <linux/mm.h>
  79. #include <linux/of_mdio.h>
  80. #include <linux/of_platform.h>
  81. #include <linux/ip.h>
  82. #include <linux/tcp.h>
  83. #include <linux/udp.h>
  84. #include <linux/in.h>
  85. #include <linux/net_tstamp.h>
  86. #include <asm/io.h>
  87. #include <asm/reg.h>
  88. #include <asm/irq.h>
  89. #include <asm/uaccess.h>
  90. #include <linux/module.h>
  91. #include <linux/dma-mapping.h>
  92. #include <linux/crc32.h>
  93. #include <linux/mii.h>
  94. #include <linux/phy.h>
  95. #include <linux/phy_fixed.h>
  96. #include <linux/of.h>
  97. #include <linux/of_net.h>
  98. #include "gianfar.h"
  99. #define TX_TIMEOUT (1*HZ)
  100. const char gfar_driver_version[] = "1.3";
  101. static int gfar_enet_open(struct net_device *dev);
  102. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
  103. static void gfar_reset_task(struct work_struct *work);
  104. static void gfar_timeout(struct net_device *dev);
  105. static int gfar_close(struct net_device *dev);
  106. struct sk_buff *gfar_new_skb(struct net_device *dev);
  107. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  108. struct sk_buff *skb);
  109. static int gfar_set_mac_address(struct net_device *dev);
  110. static int gfar_change_mtu(struct net_device *dev, int new_mtu);
  111. static irqreturn_t gfar_error(int irq, void *dev_id);
  112. static irqreturn_t gfar_transmit(int irq, void *dev_id);
  113. static irqreturn_t gfar_interrupt(int irq, void *dev_id);
  114. static void adjust_link(struct net_device *dev);
  115. static void init_registers(struct net_device *dev);
  116. static int init_phy(struct net_device *dev);
  117. static int gfar_probe(struct platform_device *ofdev);
  118. static int gfar_remove(struct platform_device *ofdev);
  119. static void free_skb_resources(struct gfar_private *priv);
  120. static void gfar_set_multi(struct net_device *dev);
  121. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
  122. static void gfar_configure_serdes(struct net_device *dev);
  123. static int gfar_poll(struct napi_struct *napi, int budget);
  124. #ifdef CONFIG_NET_POLL_CONTROLLER
  125. static void gfar_netpoll(struct net_device *dev);
  126. #endif
  127. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
  128. static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
  129. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  130. int amount_pull, struct napi_struct *napi);
  131. void gfar_halt(struct net_device *dev);
  132. static void gfar_halt_nodisable(struct net_device *dev);
  133. void gfar_start(struct net_device *dev);
  134. static void gfar_clear_exact_match(struct net_device *dev);
  135. static void gfar_set_mac_for_addr(struct net_device *dev, int num,
  136. const u8 *addr);
  137. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  138. MODULE_AUTHOR("Freescale Semiconductor, Inc");
  139. MODULE_DESCRIPTION("Gianfar Ethernet Driver");
  140. MODULE_LICENSE("GPL");
  141. static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  142. dma_addr_t buf)
  143. {
  144. u32 lstatus;
  145. bdp->bufPtr = buf;
  146. lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
  147. if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
  148. lstatus |= BD_LFLAG(RXBD_WRAP);
  149. eieio();
  150. bdp->lstatus = lstatus;
  151. }
  152. static int gfar_init_bds(struct net_device *ndev)
  153. {
  154. struct gfar_private *priv = netdev_priv(ndev);
  155. struct gfar_priv_tx_q *tx_queue = NULL;
  156. struct gfar_priv_rx_q *rx_queue = NULL;
  157. struct txbd8 *txbdp;
  158. struct rxbd8 *rxbdp;
  159. int i, j;
  160. for (i = 0; i < priv->num_tx_queues; i++) {
  161. tx_queue = priv->tx_queue[i];
  162. /* Initialize some variables in our dev structure */
  163. tx_queue->num_txbdfree = tx_queue->tx_ring_size;
  164. tx_queue->dirty_tx = tx_queue->tx_bd_base;
  165. tx_queue->cur_tx = tx_queue->tx_bd_base;
  166. tx_queue->skb_curtx = 0;
  167. tx_queue->skb_dirtytx = 0;
  168. /* Initialize Transmit Descriptor Ring */
  169. txbdp = tx_queue->tx_bd_base;
  170. for (j = 0; j < tx_queue->tx_ring_size; j++) {
  171. txbdp->lstatus = 0;
  172. txbdp->bufPtr = 0;
  173. txbdp++;
  174. }
  175. /* Set the last descriptor in the ring to indicate wrap */
  176. txbdp--;
  177. txbdp->status |= TXBD_WRAP;
  178. }
  179. for (i = 0; i < priv->num_rx_queues; i++) {
  180. rx_queue = priv->rx_queue[i];
  181. rx_queue->cur_rx = rx_queue->rx_bd_base;
  182. rx_queue->skb_currx = 0;
  183. rxbdp = rx_queue->rx_bd_base;
  184. for (j = 0; j < rx_queue->rx_ring_size; j++) {
  185. struct sk_buff *skb = rx_queue->rx_skbuff[j];
  186. if (skb) {
  187. gfar_init_rxbdp(rx_queue, rxbdp,
  188. rxbdp->bufPtr);
  189. } else {
  190. skb = gfar_new_skb(ndev);
  191. if (!skb) {
  192. netdev_err(ndev, "Can't allocate RX buffers\n");
  193. return -ENOMEM;
  194. }
  195. rx_queue->rx_skbuff[j] = skb;
  196. gfar_new_rxbdp(rx_queue, rxbdp, skb);
  197. }
  198. rxbdp++;
  199. }
  200. }
  201. return 0;
  202. }
  203. static int gfar_alloc_skb_resources(struct net_device *ndev)
  204. {
  205. void *vaddr;
  206. dma_addr_t addr;
  207. int i, j, k;
  208. struct gfar_private *priv = netdev_priv(ndev);
  209. struct device *dev = &priv->ofdev->dev;
  210. struct gfar_priv_tx_q *tx_queue = NULL;
  211. struct gfar_priv_rx_q *rx_queue = NULL;
  212. priv->total_tx_ring_size = 0;
  213. for (i = 0; i < priv->num_tx_queues; i++)
  214. priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
  215. priv->total_rx_ring_size = 0;
  216. for (i = 0; i < priv->num_rx_queues; i++)
  217. priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
  218. /* Allocate memory for the buffer descriptors */
  219. vaddr = dma_alloc_coherent(dev,
  220. sizeof(struct txbd8) * priv->total_tx_ring_size +
  221. sizeof(struct rxbd8) * priv->total_rx_ring_size,
  222. &addr, GFP_KERNEL);
  223. if (!vaddr) {
  224. netif_err(priv, ifup, ndev,
  225. "Could not allocate buffer descriptors!\n");
  226. return -ENOMEM;
  227. }
  228. for (i = 0; i < priv->num_tx_queues; i++) {
  229. tx_queue = priv->tx_queue[i];
  230. tx_queue->tx_bd_base = vaddr;
  231. tx_queue->tx_bd_dma_base = addr;
  232. tx_queue->dev = ndev;
  233. /* enet DMA only understands physical addresses */
  234. addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
  235. vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
  236. }
  237. /* Start the rx descriptor ring where the tx ring leaves off */
  238. for (i = 0; i < priv->num_rx_queues; i++) {
  239. rx_queue = priv->rx_queue[i];
  240. rx_queue->rx_bd_base = vaddr;
  241. rx_queue->rx_bd_dma_base = addr;
  242. rx_queue->dev = ndev;
  243. addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
  244. vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
  245. }
  246. /* Setup the skbuff rings */
  247. for (i = 0; i < priv->num_tx_queues; i++) {
  248. tx_queue = priv->tx_queue[i];
  249. tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
  250. tx_queue->tx_ring_size,
  251. GFP_KERNEL);
  252. if (!tx_queue->tx_skbuff) {
  253. netif_err(priv, ifup, ndev,
  254. "Could not allocate tx_skbuff\n");
  255. goto cleanup;
  256. }
  257. for (k = 0; k < tx_queue->tx_ring_size; k++)
  258. tx_queue->tx_skbuff[k] = NULL;
  259. }
  260. for (i = 0; i < priv->num_rx_queues; i++) {
  261. rx_queue = priv->rx_queue[i];
  262. rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
  263. rx_queue->rx_ring_size,
  264. GFP_KERNEL);
  265. if (!rx_queue->rx_skbuff) {
  266. netif_err(priv, ifup, ndev,
  267. "Could not allocate rx_skbuff\n");
  268. goto cleanup;
  269. }
  270. for (j = 0; j < rx_queue->rx_ring_size; j++)
  271. rx_queue->rx_skbuff[j] = NULL;
  272. }
  273. if (gfar_init_bds(ndev))
  274. goto cleanup;
  275. return 0;
  276. cleanup:
  277. free_skb_resources(priv);
  278. return -ENOMEM;
  279. }
  280. static void gfar_init_tx_rx_base(struct gfar_private *priv)
  281. {
  282. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  283. u32 __iomem *baddr;
  284. int i;
  285. baddr = &regs->tbase0;
  286. for (i = 0; i < priv->num_tx_queues; i++) {
  287. gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
  288. baddr += 2;
  289. }
  290. baddr = &regs->rbase0;
  291. for (i = 0; i < priv->num_rx_queues; i++) {
  292. gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
  293. baddr += 2;
  294. }
  295. }
  296. static void gfar_init_mac(struct net_device *ndev)
  297. {
  298. struct gfar_private *priv = netdev_priv(ndev);
  299. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  300. u32 rctrl = 0;
  301. u32 tctrl = 0;
  302. u32 attrs = 0;
  303. /* write the tx/rx base registers */
  304. gfar_init_tx_rx_base(priv);
  305. /* Configure the coalescing support */
  306. gfar_configure_coalescing(priv, 0xFF, 0xFF);
  307. if (priv->rx_filer_enable) {
  308. rctrl |= RCTRL_FILREN;
  309. /* Program the RIR0 reg with the required distribution */
  310. gfar_write(&regs->rir0, DEFAULT_RIR0);
  311. }
  312. /* Restore PROMISC mode */
  313. if (ndev->flags & IFF_PROMISC)
  314. rctrl |= RCTRL_PROM;
  315. if (ndev->features & NETIF_F_RXCSUM)
  316. rctrl |= RCTRL_CHECKSUMMING;
  317. if (priv->extended_hash) {
  318. rctrl |= RCTRL_EXTHASH;
  319. gfar_clear_exact_match(ndev);
  320. rctrl |= RCTRL_EMEN;
  321. }
  322. if (priv->padding) {
  323. rctrl &= ~RCTRL_PAL_MASK;
  324. rctrl |= RCTRL_PADDING(priv->padding);
  325. }
  326. /* Insert receive time stamps into padding alignment bytes */
  327. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
  328. rctrl &= ~RCTRL_PAL_MASK;
  329. rctrl |= RCTRL_PADDING(8);
  330. priv->padding = 8;
  331. }
  332. /* Enable HW time stamping if requested from user space */
  333. if (priv->hwts_rx_en)
  334. rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
  335. if (ndev->features & NETIF_F_HW_VLAN_RX)
  336. rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
  337. /* Init rctrl based on our settings */
  338. gfar_write(&regs->rctrl, rctrl);
  339. if (ndev->features & NETIF_F_IP_CSUM)
  340. tctrl |= TCTRL_INIT_CSUM;
  341. if (priv->prio_sched_en)
  342. tctrl |= TCTRL_TXSCHED_PRIO;
  343. else {
  344. tctrl |= TCTRL_TXSCHED_WRRS;
  345. gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
  346. gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
  347. }
  348. gfar_write(&regs->tctrl, tctrl);
  349. /* Set the extraction length and index */
  350. attrs = ATTRELI_EL(priv->rx_stash_size) |
  351. ATTRELI_EI(priv->rx_stash_index);
  352. gfar_write(&regs->attreli, attrs);
  353. /* Start with defaults, and add stashing or locking
  354. * depending on the approprate variables
  355. */
  356. attrs = ATTR_INIT_SETTINGS;
  357. if (priv->bd_stash_en)
  358. attrs |= ATTR_BDSTASH;
  359. if (priv->rx_stash_size != 0)
  360. attrs |= ATTR_BUFSTASH;
  361. gfar_write(&regs->attr, attrs);
  362. gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
  363. gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
  364. gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
  365. }
  366. static struct net_device_stats *gfar_get_stats(struct net_device *dev)
  367. {
  368. struct gfar_private *priv = netdev_priv(dev);
  369. unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
  370. unsigned long tx_packets = 0, tx_bytes = 0;
  371. int i;
  372. for (i = 0; i < priv->num_rx_queues; i++) {
  373. rx_packets += priv->rx_queue[i]->stats.rx_packets;
  374. rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
  375. rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
  376. }
  377. dev->stats.rx_packets = rx_packets;
  378. dev->stats.rx_bytes = rx_bytes;
  379. dev->stats.rx_dropped = rx_dropped;
  380. for (i = 0; i < priv->num_tx_queues; i++) {
  381. tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
  382. tx_packets += priv->tx_queue[i]->stats.tx_packets;
  383. }
  384. dev->stats.tx_bytes = tx_bytes;
  385. dev->stats.tx_packets = tx_packets;
  386. return &dev->stats;
  387. }
  388. static const struct net_device_ops gfar_netdev_ops = {
  389. .ndo_open = gfar_enet_open,
  390. .ndo_start_xmit = gfar_start_xmit,
  391. .ndo_stop = gfar_close,
  392. .ndo_change_mtu = gfar_change_mtu,
  393. .ndo_set_features = gfar_set_features,
  394. .ndo_set_rx_mode = gfar_set_multi,
  395. .ndo_tx_timeout = gfar_timeout,
  396. .ndo_do_ioctl = gfar_ioctl,
  397. .ndo_get_stats = gfar_get_stats,
  398. .ndo_set_mac_address = eth_mac_addr,
  399. .ndo_validate_addr = eth_validate_addr,
  400. #ifdef CONFIG_NET_POLL_CONTROLLER
  401. .ndo_poll_controller = gfar_netpoll,
  402. #endif
  403. };
  404. void lock_rx_qs(struct gfar_private *priv)
  405. {
  406. int i;
  407. for (i = 0; i < priv->num_rx_queues; i++)
  408. spin_lock(&priv->rx_queue[i]->rxlock);
  409. }
  410. void lock_tx_qs(struct gfar_private *priv)
  411. {
  412. int i;
  413. for (i = 0; i < priv->num_tx_queues; i++)
  414. spin_lock(&priv->tx_queue[i]->txlock);
  415. }
  416. void unlock_rx_qs(struct gfar_private *priv)
  417. {
  418. int i;
  419. for (i = 0; i < priv->num_rx_queues; i++)
  420. spin_unlock(&priv->rx_queue[i]->rxlock);
  421. }
  422. void unlock_tx_qs(struct gfar_private *priv)
  423. {
  424. int i;
  425. for (i = 0; i < priv->num_tx_queues; i++)
  426. spin_unlock(&priv->tx_queue[i]->txlock);
  427. }
  428. static bool gfar_is_vlan_on(struct gfar_private *priv)
  429. {
  430. return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
  431. (priv->ndev->features & NETIF_F_HW_VLAN_TX);
  432. }
  433. /* Returns 1 if incoming frames use an FCB */
  434. static inline int gfar_uses_fcb(struct gfar_private *priv)
  435. {
  436. return gfar_is_vlan_on(priv) ||
  437. (priv->ndev->features & NETIF_F_RXCSUM) ||
  438. (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
  439. }
  440. static void free_tx_pointers(struct gfar_private *priv)
  441. {
  442. int i;
  443. for (i = 0; i < priv->num_tx_queues; i++)
  444. kfree(priv->tx_queue[i]);
  445. }
  446. static void free_rx_pointers(struct gfar_private *priv)
  447. {
  448. int i;
  449. for (i = 0; i < priv->num_rx_queues; i++)
  450. kfree(priv->rx_queue[i]);
  451. }
  452. static void unmap_group_regs(struct gfar_private *priv)
  453. {
  454. int i;
  455. for (i = 0; i < MAXGROUPS; i++)
  456. if (priv->gfargrp[i].regs)
  457. iounmap(priv->gfargrp[i].regs);
  458. }
  459. static void disable_napi(struct gfar_private *priv)
  460. {
  461. int i;
  462. for (i = 0; i < priv->num_grps; i++)
  463. napi_disable(&priv->gfargrp[i].napi);
  464. }
  465. static void enable_napi(struct gfar_private *priv)
  466. {
  467. int i;
  468. for (i = 0; i < priv->num_grps; i++)
  469. napi_enable(&priv->gfargrp[i].napi);
  470. }
  471. static int gfar_parse_group(struct device_node *np,
  472. struct gfar_private *priv, const char *model)
  473. {
  474. u32 *queue_mask;
  475. priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
  476. if (!priv->gfargrp[priv->num_grps].regs)
  477. return -ENOMEM;
  478. priv->gfargrp[priv->num_grps].interruptTransmit =
  479. irq_of_parse_and_map(np, 0);
  480. /* If we aren't the FEC we have multiple interrupts */
  481. if (model && strcasecmp(model, "FEC")) {
  482. priv->gfargrp[priv->num_grps].interruptReceive =
  483. irq_of_parse_and_map(np, 1);
  484. priv->gfargrp[priv->num_grps].interruptError =
  485. irq_of_parse_and_map(np,2);
  486. if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
  487. priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
  488. priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
  489. return -EINVAL;
  490. }
  491. priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
  492. priv->gfargrp[priv->num_grps].priv = priv;
  493. spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
  494. if (priv->mode == MQ_MG_MODE) {
  495. queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
  496. priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
  497. *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
  498. queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
  499. priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
  500. *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
  501. } else {
  502. priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
  503. priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
  504. }
  505. priv->num_grps++;
  506. return 0;
  507. }
  508. static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
  509. {
  510. const char *model;
  511. const char *ctype;
  512. const void *mac_addr;
  513. int err = 0, i;
  514. struct net_device *dev = NULL;
  515. struct gfar_private *priv = NULL;
  516. struct device_node *np = ofdev->dev.of_node;
  517. struct device_node *child = NULL;
  518. const u32 *stash;
  519. const u32 *stash_len;
  520. const u32 *stash_idx;
  521. unsigned int num_tx_qs, num_rx_qs;
  522. u32 *tx_queues, *rx_queues;
  523. if (!np || !of_device_is_available(np))
  524. return -ENODEV;
  525. /* parse the num of tx and rx queues */
  526. tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
  527. num_tx_qs = tx_queues ? *tx_queues : 1;
  528. if (num_tx_qs > MAX_TX_QS) {
  529. pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
  530. num_tx_qs, MAX_TX_QS);
  531. pr_err("Cannot do alloc_etherdev, aborting\n");
  532. return -EINVAL;
  533. }
  534. rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
  535. num_rx_qs = rx_queues ? *rx_queues : 1;
  536. if (num_rx_qs > MAX_RX_QS) {
  537. pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
  538. num_rx_qs, MAX_RX_QS);
  539. pr_err("Cannot do alloc_etherdev, aborting\n");
  540. return -EINVAL;
  541. }
  542. *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
  543. dev = *pdev;
  544. if (NULL == dev)
  545. return -ENOMEM;
  546. priv = netdev_priv(dev);
  547. priv->node = ofdev->dev.of_node;
  548. priv->ndev = dev;
  549. priv->num_tx_queues = num_tx_qs;
  550. netif_set_real_num_rx_queues(dev, num_rx_qs);
  551. priv->num_rx_queues = num_rx_qs;
  552. priv->num_grps = 0x0;
  553. /* Init Rx queue filer rule set linked list */
  554. INIT_LIST_HEAD(&priv->rx_list.list);
  555. priv->rx_list.count = 0;
  556. mutex_init(&priv->rx_queue_access);
  557. model = of_get_property(np, "model", NULL);
  558. for (i = 0; i < MAXGROUPS; i++)
  559. priv->gfargrp[i].regs = NULL;
  560. /* Parse and initialize group specific information */
  561. if (of_device_is_compatible(np, "fsl,etsec2")) {
  562. priv->mode = MQ_MG_MODE;
  563. for_each_child_of_node(np, child) {
  564. err = gfar_parse_group(child, priv, model);
  565. if (err)
  566. goto err_grp_init;
  567. }
  568. } else {
  569. priv->mode = SQ_SG_MODE;
  570. err = gfar_parse_group(np, priv, model);
  571. if (err)
  572. goto err_grp_init;
  573. }
  574. for (i = 0; i < priv->num_tx_queues; i++)
  575. priv->tx_queue[i] = NULL;
  576. for (i = 0; i < priv->num_rx_queues; i++)
  577. priv->rx_queue[i] = NULL;
  578. for (i = 0; i < priv->num_tx_queues; i++) {
  579. priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
  580. GFP_KERNEL);
  581. if (!priv->tx_queue[i]) {
  582. err = -ENOMEM;
  583. goto tx_alloc_failed;
  584. }
  585. priv->tx_queue[i]->tx_skbuff = NULL;
  586. priv->tx_queue[i]->qindex = i;
  587. priv->tx_queue[i]->dev = dev;
  588. spin_lock_init(&(priv->tx_queue[i]->txlock));
  589. }
  590. for (i = 0; i < priv->num_rx_queues; i++) {
  591. priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
  592. GFP_KERNEL);
  593. if (!priv->rx_queue[i]) {
  594. err = -ENOMEM;
  595. goto rx_alloc_failed;
  596. }
  597. priv->rx_queue[i]->rx_skbuff = NULL;
  598. priv->rx_queue[i]->qindex = i;
  599. priv->rx_queue[i]->dev = dev;
  600. spin_lock_init(&(priv->rx_queue[i]->rxlock));
  601. }
  602. stash = of_get_property(np, "bd-stash", NULL);
  603. if (stash) {
  604. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
  605. priv->bd_stash_en = 1;
  606. }
  607. stash_len = of_get_property(np, "rx-stash-len", NULL);
  608. if (stash_len)
  609. priv->rx_stash_size = *stash_len;
  610. stash_idx = of_get_property(np, "rx-stash-idx", NULL);
  611. if (stash_idx)
  612. priv->rx_stash_index = *stash_idx;
  613. if (stash_len || stash_idx)
  614. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
  615. mac_addr = of_get_mac_address(np);
  616. if (mac_addr)
  617. memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
  618. if (model && !strcasecmp(model, "TSEC"))
  619. priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
  620. FSL_GIANFAR_DEV_HAS_COALESCE |
  621. FSL_GIANFAR_DEV_HAS_RMON |
  622. FSL_GIANFAR_DEV_HAS_MULTI_INTR;
  623. if (model && !strcasecmp(model, "eTSEC"))
  624. priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
  625. FSL_GIANFAR_DEV_HAS_COALESCE |
  626. FSL_GIANFAR_DEV_HAS_RMON |
  627. FSL_GIANFAR_DEV_HAS_MULTI_INTR |
  628. FSL_GIANFAR_DEV_HAS_PADDING |
  629. FSL_GIANFAR_DEV_HAS_CSUM |
  630. FSL_GIANFAR_DEV_HAS_VLAN |
  631. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
  632. FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
  633. FSL_GIANFAR_DEV_HAS_TIMER;
  634. ctype = of_get_property(np, "phy-connection-type", NULL);
  635. /* We only care about rgmii-id. The rest are autodetected */
  636. if (ctype && !strcmp(ctype, "rgmii-id"))
  637. priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
  638. else
  639. priv->interface = PHY_INTERFACE_MODE_MII;
  640. if (of_get_property(np, "fsl,magic-packet", NULL))
  641. priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
  642. priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
  643. /* Find the TBI PHY. If it's not there, we don't support SGMII */
  644. priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
  645. return 0;
  646. rx_alloc_failed:
  647. free_rx_pointers(priv);
  648. tx_alloc_failed:
  649. free_tx_pointers(priv);
  650. err_grp_init:
  651. unmap_group_regs(priv);
  652. free_netdev(dev);
  653. return err;
  654. }
  655. static int gfar_hwtstamp_ioctl(struct net_device *netdev,
  656. struct ifreq *ifr, int cmd)
  657. {
  658. struct hwtstamp_config config;
  659. struct gfar_private *priv = netdev_priv(netdev);
  660. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  661. return -EFAULT;
  662. /* reserved for future extensions */
  663. if (config.flags)
  664. return -EINVAL;
  665. switch (config.tx_type) {
  666. case HWTSTAMP_TX_OFF:
  667. priv->hwts_tx_en = 0;
  668. break;
  669. case HWTSTAMP_TX_ON:
  670. if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
  671. return -ERANGE;
  672. priv->hwts_tx_en = 1;
  673. break;
  674. default:
  675. return -ERANGE;
  676. }
  677. switch (config.rx_filter) {
  678. case HWTSTAMP_FILTER_NONE:
  679. if (priv->hwts_rx_en) {
  680. stop_gfar(netdev);
  681. priv->hwts_rx_en = 0;
  682. startup_gfar(netdev);
  683. }
  684. break;
  685. default:
  686. if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
  687. return -ERANGE;
  688. if (!priv->hwts_rx_en) {
  689. stop_gfar(netdev);
  690. priv->hwts_rx_en = 1;
  691. startup_gfar(netdev);
  692. }
  693. config.rx_filter = HWTSTAMP_FILTER_ALL;
  694. break;
  695. }
  696. return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
  697. -EFAULT : 0;
  698. }
  699. /* Ioctl MII Interface */
  700. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  701. {
  702. struct gfar_private *priv = netdev_priv(dev);
  703. if (!netif_running(dev))
  704. return -EINVAL;
  705. if (cmd == SIOCSHWTSTAMP)
  706. return gfar_hwtstamp_ioctl(dev, rq, cmd);
  707. if (!priv->phydev)
  708. return -ENODEV;
  709. return phy_mii_ioctl(priv->phydev, rq, cmd);
  710. }
  711. static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
  712. {
  713. unsigned int new_bit_map = 0x0;
  714. int mask = 0x1 << (max_qs - 1), i;
  715. for (i = 0; i < max_qs; i++) {
  716. if (bit_map & mask)
  717. new_bit_map = new_bit_map + (1 << i);
  718. mask = mask >> 0x1;
  719. }
  720. return new_bit_map;
  721. }
  722. static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
  723. u32 class)
  724. {
  725. u32 rqfpr = FPR_FILER_MASK;
  726. u32 rqfcr = 0x0;
  727. rqfar--;
  728. rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
  729. priv->ftp_rqfpr[rqfar] = rqfpr;
  730. priv->ftp_rqfcr[rqfar] = rqfcr;
  731. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  732. rqfar--;
  733. rqfcr = RQFCR_CMP_NOMATCH;
  734. priv->ftp_rqfpr[rqfar] = rqfpr;
  735. priv->ftp_rqfcr[rqfar] = rqfcr;
  736. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  737. rqfar--;
  738. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
  739. rqfpr = class;
  740. priv->ftp_rqfcr[rqfar] = rqfcr;
  741. priv->ftp_rqfpr[rqfar] = rqfpr;
  742. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  743. rqfar--;
  744. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
  745. rqfpr = class;
  746. priv->ftp_rqfcr[rqfar] = rqfcr;
  747. priv->ftp_rqfpr[rqfar] = rqfpr;
  748. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  749. return rqfar;
  750. }
  751. static void gfar_init_filer_table(struct gfar_private *priv)
  752. {
  753. int i = 0x0;
  754. u32 rqfar = MAX_FILER_IDX;
  755. u32 rqfcr = 0x0;
  756. u32 rqfpr = FPR_FILER_MASK;
  757. /* Default rule */
  758. rqfcr = RQFCR_CMP_MATCH;
  759. priv->ftp_rqfcr[rqfar] = rqfcr;
  760. priv->ftp_rqfpr[rqfar] = rqfpr;
  761. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  762. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
  763. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
  764. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
  765. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
  766. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
  767. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
  768. /* cur_filer_idx indicated the first non-masked rule */
  769. priv->cur_filer_idx = rqfar;
  770. /* Rest are masked rules */
  771. rqfcr = RQFCR_CMP_NOMATCH;
  772. for (i = 0; i < rqfar; i++) {
  773. priv->ftp_rqfcr[i] = rqfcr;
  774. priv->ftp_rqfpr[i] = rqfpr;
  775. gfar_write_filer(priv, i, rqfcr, rqfpr);
  776. }
  777. }
  778. static void gfar_detect_errata(struct gfar_private *priv)
  779. {
  780. struct device *dev = &priv->ofdev->dev;
  781. unsigned int pvr = mfspr(SPRN_PVR);
  782. unsigned int svr = mfspr(SPRN_SVR);
  783. unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
  784. unsigned int rev = svr & 0xffff;
  785. /* MPC8313 Rev 2.0 and higher; All MPC837x */
  786. if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
  787. (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
  788. priv->errata |= GFAR_ERRATA_74;
  789. /* MPC8313 and MPC837x all rev */
  790. if ((pvr == 0x80850010 && mod == 0x80b0) ||
  791. (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
  792. priv->errata |= GFAR_ERRATA_76;
  793. /* MPC8313 and MPC837x all rev */
  794. if ((pvr == 0x80850010 && mod == 0x80b0) ||
  795. (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
  796. priv->errata |= GFAR_ERRATA_A002;
  797. /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
  798. if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
  799. (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
  800. priv->errata |= GFAR_ERRATA_12;
  801. if (priv->errata)
  802. dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
  803. priv->errata);
  804. }
  805. /* Set up the ethernet device structure, private data,
  806. * and anything else we need before we start
  807. */
  808. static int gfar_probe(struct platform_device *ofdev)
  809. {
  810. u32 tempval;
  811. struct net_device *dev = NULL;
  812. struct gfar_private *priv = NULL;
  813. struct gfar __iomem *regs = NULL;
  814. int err = 0, i, grp_idx = 0;
  815. u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
  816. u32 isrg = 0;
  817. u32 __iomem *baddr;
  818. err = gfar_of_init(ofdev, &dev);
  819. if (err)
  820. return err;
  821. priv = netdev_priv(dev);
  822. priv->ndev = dev;
  823. priv->ofdev = ofdev;
  824. priv->node = ofdev->dev.of_node;
  825. SET_NETDEV_DEV(dev, &ofdev->dev);
  826. spin_lock_init(&priv->bflock);
  827. INIT_WORK(&priv->reset_task, gfar_reset_task);
  828. dev_set_drvdata(&ofdev->dev, priv);
  829. regs = priv->gfargrp[0].regs;
  830. gfar_detect_errata(priv);
  831. /* Stop the DMA engine now, in case it was running before
  832. * (The firmware could have used it, and left it running).
  833. */
  834. gfar_halt(dev);
  835. /* Reset MAC layer */
  836. gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
  837. /* We need to delay at least 3 TX clocks */
  838. udelay(2);
  839. tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
  840. gfar_write(&regs->maccfg1, tempval);
  841. /* Initialize MACCFG2. */
  842. tempval = MACCFG2_INIT_SETTINGS;
  843. if (gfar_has_errata(priv, GFAR_ERRATA_74))
  844. tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
  845. gfar_write(&regs->maccfg2, tempval);
  846. /* Initialize ECNTRL */
  847. gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  848. /* Set the dev->base_addr to the gfar reg region */
  849. dev->base_addr = (unsigned long) regs;
  850. SET_NETDEV_DEV(dev, &ofdev->dev);
  851. /* Fill in the dev structure */
  852. dev->watchdog_timeo = TX_TIMEOUT;
  853. dev->mtu = 1500;
  854. dev->netdev_ops = &gfar_netdev_ops;
  855. dev->ethtool_ops = &gfar_ethtool_ops;
  856. /* Register for napi ...We are registering NAPI for each grp */
  857. for (i = 0; i < priv->num_grps; i++)
  858. netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
  859. GFAR_DEV_WEIGHT);
  860. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
  861. dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
  862. NETIF_F_RXCSUM;
  863. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
  864. NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
  865. }
  866. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
  867. dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  868. dev->features |= NETIF_F_HW_VLAN_RX;
  869. }
  870. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
  871. priv->extended_hash = 1;
  872. priv->hash_width = 9;
  873. priv->hash_regs[0] = &regs->igaddr0;
  874. priv->hash_regs[1] = &regs->igaddr1;
  875. priv->hash_regs[2] = &regs->igaddr2;
  876. priv->hash_regs[3] = &regs->igaddr3;
  877. priv->hash_regs[4] = &regs->igaddr4;
  878. priv->hash_regs[5] = &regs->igaddr5;
  879. priv->hash_regs[6] = &regs->igaddr6;
  880. priv->hash_regs[7] = &regs->igaddr7;
  881. priv->hash_regs[8] = &regs->gaddr0;
  882. priv->hash_regs[9] = &regs->gaddr1;
  883. priv->hash_regs[10] = &regs->gaddr2;
  884. priv->hash_regs[11] = &regs->gaddr3;
  885. priv->hash_regs[12] = &regs->gaddr4;
  886. priv->hash_regs[13] = &regs->gaddr5;
  887. priv->hash_regs[14] = &regs->gaddr6;
  888. priv->hash_regs[15] = &regs->gaddr7;
  889. } else {
  890. priv->extended_hash = 0;
  891. priv->hash_width = 8;
  892. priv->hash_regs[0] = &regs->gaddr0;
  893. priv->hash_regs[1] = &regs->gaddr1;
  894. priv->hash_regs[2] = &regs->gaddr2;
  895. priv->hash_regs[3] = &regs->gaddr3;
  896. priv->hash_regs[4] = &regs->gaddr4;
  897. priv->hash_regs[5] = &regs->gaddr5;
  898. priv->hash_regs[6] = &regs->gaddr6;
  899. priv->hash_regs[7] = &regs->gaddr7;
  900. }
  901. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
  902. priv->padding = DEFAULT_PADDING;
  903. else
  904. priv->padding = 0;
  905. if (dev->features & NETIF_F_IP_CSUM ||
  906. priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
  907. dev->needed_headroom = GMAC_FCB_LEN;
  908. /* Program the isrg regs only if number of grps > 1 */
  909. if (priv->num_grps > 1) {
  910. baddr = &regs->isrg0;
  911. for (i = 0; i < priv->num_grps; i++) {
  912. isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
  913. isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
  914. gfar_write(baddr, isrg);
  915. baddr++;
  916. isrg = 0x0;
  917. }
  918. }
  919. /* Need to reverse the bit maps as bit_map's MSB is q0
  920. * but, for_each_set_bit parses from right to left, which
  921. * basically reverses the queue numbers
  922. */
  923. for (i = 0; i< priv->num_grps; i++) {
  924. priv->gfargrp[i].tx_bit_map =
  925. reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
  926. priv->gfargrp[i].rx_bit_map =
  927. reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
  928. }
  929. /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
  930. * also assign queues to groups
  931. */
  932. for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
  933. priv->gfargrp[grp_idx].num_rx_queues = 0x0;
  934. for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
  935. priv->num_rx_queues) {
  936. priv->gfargrp[grp_idx].num_rx_queues++;
  937. priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
  938. rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
  939. rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
  940. }
  941. priv->gfargrp[grp_idx].num_tx_queues = 0x0;
  942. for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
  943. priv->num_tx_queues) {
  944. priv->gfargrp[grp_idx].num_tx_queues++;
  945. priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
  946. tstat = tstat | (TSTAT_CLEAR_THALT >> i);
  947. tqueue = tqueue | (TQUEUE_EN0 >> i);
  948. }
  949. priv->gfargrp[grp_idx].rstat = rstat;
  950. priv->gfargrp[grp_idx].tstat = tstat;
  951. rstat = tstat =0;
  952. }
  953. gfar_write(&regs->rqueue, rqueue);
  954. gfar_write(&regs->tqueue, tqueue);
  955. priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
  956. /* Initializing some of the rx/tx queue level parameters */
  957. for (i = 0; i < priv->num_tx_queues; i++) {
  958. priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
  959. priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
  960. priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
  961. priv->tx_queue[i]->txic = DEFAULT_TXIC;
  962. }
  963. for (i = 0; i < priv->num_rx_queues; i++) {
  964. priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
  965. priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
  966. priv->rx_queue[i]->rxic = DEFAULT_RXIC;
  967. }
  968. /* always enable rx filer */
  969. priv->rx_filer_enable = 1;
  970. /* Enable most messages by default */
  971. priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  972. /* use pritority h/w tx queue scheduling for single queue devices */
  973. if (priv->num_tx_queues == 1)
  974. priv->prio_sched_en = 1;
  975. /* Carrier starts down, phylib will bring it up */
  976. netif_carrier_off(dev);
  977. err = register_netdev(dev);
  978. if (err) {
  979. pr_err("%s: Cannot register net device, aborting\n", dev->name);
  980. goto register_fail;
  981. }
  982. device_init_wakeup(&dev->dev,
  983. priv->device_flags &
  984. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  985. /* fill out IRQ number and name fields */
  986. for (i = 0; i < priv->num_grps; i++) {
  987. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  988. sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
  989. dev->name, "_g", '0' + i, "_tx");
  990. sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
  991. dev->name, "_g", '0' + i, "_rx");
  992. sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
  993. dev->name, "_g", '0' + i, "_er");
  994. } else
  995. strcpy(priv->gfargrp[i].int_name_tx, dev->name);
  996. }
  997. /* Initialize the filer table */
  998. gfar_init_filer_table(priv);
  999. /* Create all the sysfs files */
  1000. gfar_init_sysfs(dev);
  1001. /* Print out the device info */
  1002. netdev_info(dev, "mac: %pM\n", dev->dev_addr);
  1003. /* Even more device info helps when determining which kernel
  1004. * provided which set of benchmarks.
  1005. */
  1006. netdev_info(dev, "Running with NAPI enabled\n");
  1007. for (i = 0; i < priv->num_rx_queues; i++)
  1008. netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
  1009. i, priv->rx_queue[i]->rx_ring_size);
  1010. for (i = 0; i < priv->num_tx_queues; i++)
  1011. netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
  1012. i, priv->tx_queue[i]->tx_ring_size);
  1013. return 0;
  1014. register_fail:
  1015. unmap_group_regs(priv);
  1016. free_tx_pointers(priv);
  1017. free_rx_pointers(priv);
  1018. if (priv->phy_node)
  1019. of_node_put(priv->phy_node);
  1020. if (priv->tbi_node)
  1021. of_node_put(priv->tbi_node);
  1022. free_netdev(dev);
  1023. return err;
  1024. }
  1025. static int gfar_remove(struct platform_device *ofdev)
  1026. {
  1027. struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
  1028. if (priv->phy_node)
  1029. of_node_put(priv->phy_node);
  1030. if (priv->tbi_node)
  1031. of_node_put(priv->tbi_node);
  1032. dev_set_drvdata(&ofdev->dev, NULL);
  1033. unregister_netdev(priv->ndev);
  1034. unmap_group_regs(priv);
  1035. free_netdev(priv->ndev);
  1036. return 0;
  1037. }
  1038. #ifdef CONFIG_PM
  1039. static int gfar_suspend(struct device *dev)
  1040. {
  1041. struct gfar_private *priv = dev_get_drvdata(dev);
  1042. struct net_device *ndev = priv->ndev;
  1043. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1044. unsigned long flags;
  1045. u32 tempval;
  1046. int magic_packet = priv->wol_en &&
  1047. (priv->device_flags &
  1048. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1049. netif_device_detach(ndev);
  1050. if (netif_running(ndev)) {
  1051. local_irq_save(flags);
  1052. lock_tx_qs(priv);
  1053. lock_rx_qs(priv);
  1054. gfar_halt_nodisable(ndev);
  1055. /* Disable Tx, and Rx if wake-on-LAN is disabled. */
  1056. tempval = gfar_read(&regs->maccfg1);
  1057. tempval &= ~MACCFG1_TX_EN;
  1058. if (!magic_packet)
  1059. tempval &= ~MACCFG1_RX_EN;
  1060. gfar_write(&regs->maccfg1, tempval);
  1061. unlock_rx_qs(priv);
  1062. unlock_tx_qs(priv);
  1063. local_irq_restore(flags);
  1064. disable_napi(priv);
  1065. if (magic_packet) {
  1066. /* Enable interrupt on Magic Packet */
  1067. gfar_write(&regs->imask, IMASK_MAG);
  1068. /* Enable Magic Packet mode */
  1069. tempval = gfar_read(&regs->maccfg2);
  1070. tempval |= MACCFG2_MPEN;
  1071. gfar_write(&regs->maccfg2, tempval);
  1072. } else {
  1073. phy_stop(priv->phydev);
  1074. }
  1075. }
  1076. return 0;
  1077. }
  1078. static int gfar_resume(struct device *dev)
  1079. {
  1080. struct gfar_private *priv = dev_get_drvdata(dev);
  1081. struct net_device *ndev = priv->ndev;
  1082. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1083. unsigned long flags;
  1084. u32 tempval;
  1085. int magic_packet = priv->wol_en &&
  1086. (priv->device_flags &
  1087. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1088. if (!netif_running(ndev)) {
  1089. netif_device_attach(ndev);
  1090. return 0;
  1091. }
  1092. if (!magic_packet && priv->phydev)
  1093. phy_start(priv->phydev);
  1094. /* Disable Magic Packet mode, in case something
  1095. * else woke us up.
  1096. */
  1097. local_irq_save(flags);
  1098. lock_tx_qs(priv);
  1099. lock_rx_qs(priv);
  1100. tempval = gfar_read(&regs->maccfg2);
  1101. tempval &= ~MACCFG2_MPEN;
  1102. gfar_write(&regs->maccfg2, tempval);
  1103. gfar_start(ndev);
  1104. unlock_rx_qs(priv);
  1105. unlock_tx_qs(priv);
  1106. local_irq_restore(flags);
  1107. netif_device_attach(ndev);
  1108. enable_napi(priv);
  1109. return 0;
  1110. }
  1111. static int gfar_restore(struct device *dev)
  1112. {
  1113. struct gfar_private *priv = dev_get_drvdata(dev);
  1114. struct net_device *ndev = priv->ndev;
  1115. if (!netif_running(ndev)) {
  1116. netif_device_attach(ndev);
  1117. return 0;
  1118. }
  1119. if (gfar_init_bds(ndev)) {
  1120. free_skb_resources(priv);
  1121. return -ENOMEM;
  1122. }
  1123. init_registers(ndev);
  1124. gfar_set_mac_address(ndev);
  1125. gfar_init_mac(ndev);
  1126. gfar_start(ndev);
  1127. priv->oldlink = 0;
  1128. priv->oldspeed = 0;
  1129. priv->oldduplex = -1;
  1130. if (priv->phydev)
  1131. phy_start(priv->phydev);
  1132. netif_device_attach(ndev);
  1133. enable_napi(priv);
  1134. return 0;
  1135. }
  1136. static struct dev_pm_ops gfar_pm_ops = {
  1137. .suspend = gfar_suspend,
  1138. .resume = gfar_resume,
  1139. .freeze = gfar_suspend,
  1140. .thaw = gfar_resume,
  1141. .restore = gfar_restore,
  1142. };
  1143. #define GFAR_PM_OPS (&gfar_pm_ops)
  1144. #else
  1145. #define GFAR_PM_OPS NULL
  1146. #endif
  1147. /* Reads the controller's registers to determine what interface
  1148. * connects it to the PHY.
  1149. */
  1150. static phy_interface_t gfar_get_interface(struct net_device *dev)
  1151. {
  1152. struct gfar_private *priv = netdev_priv(dev);
  1153. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1154. u32 ecntrl;
  1155. ecntrl = gfar_read(&regs->ecntrl);
  1156. if (ecntrl & ECNTRL_SGMII_MODE)
  1157. return PHY_INTERFACE_MODE_SGMII;
  1158. if (ecntrl & ECNTRL_TBI_MODE) {
  1159. if (ecntrl & ECNTRL_REDUCED_MODE)
  1160. return PHY_INTERFACE_MODE_RTBI;
  1161. else
  1162. return PHY_INTERFACE_MODE_TBI;
  1163. }
  1164. if (ecntrl & ECNTRL_REDUCED_MODE) {
  1165. if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
  1166. return PHY_INTERFACE_MODE_RMII;
  1167. }
  1168. else {
  1169. phy_interface_t interface = priv->interface;
  1170. /* This isn't autodetected right now, so it must
  1171. * be set by the device tree or platform code.
  1172. */
  1173. if (interface == PHY_INTERFACE_MODE_RGMII_ID)
  1174. return PHY_INTERFACE_MODE_RGMII_ID;
  1175. return PHY_INTERFACE_MODE_RGMII;
  1176. }
  1177. }
  1178. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
  1179. return PHY_INTERFACE_MODE_GMII;
  1180. return PHY_INTERFACE_MODE_MII;
  1181. }
  1182. /* Initializes driver's PHY state, and attaches to the PHY.
  1183. * Returns 0 on success.
  1184. */
  1185. static int init_phy(struct net_device *dev)
  1186. {
  1187. struct gfar_private *priv = netdev_priv(dev);
  1188. uint gigabit_support =
  1189. priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
  1190. SUPPORTED_1000baseT_Full : 0;
  1191. phy_interface_t interface;
  1192. priv->oldlink = 0;
  1193. priv->oldspeed = 0;
  1194. priv->oldduplex = -1;
  1195. interface = gfar_get_interface(dev);
  1196. priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
  1197. interface);
  1198. if (!priv->phydev)
  1199. priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
  1200. interface);
  1201. if (!priv->phydev) {
  1202. dev_err(&dev->dev, "could not attach to PHY\n");
  1203. return -ENODEV;
  1204. }
  1205. if (interface == PHY_INTERFACE_MODE_SGMII)
  1206. gfar_configure_serdes(dev);
  1207. /* Remove any features not supported by the controller */
  1208. priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
  1209. priv->phydev->advertising = priv->phydev->supported;
  1210. return 0;
  1211. }
  1212. /* Initialize TBI PHY interface for communicating with the
  1213. * SERDES lynx PHY on the chip. We communicate with this PHY
  1214. * through the MDIO bus on each controller, treating it as a
  1215. * "normal" PHY at the address found in the TBIPA register. We assume
  1216. * that the TBIPA register is valid. Either the MDIO bus code will set
  1217. * it to a value that doesn't conflict with other PHYs on the bus, or the
  1218. * value doesn't matter, as there are no other PHYs on the bus.
  1219. */
  1220. static void gfar_configure_serdes(struct net_device *dev)
  1221. {
  1222. struct gfar_private *priv = netdev_priv(dev);
  1223. struct phy_device *tbiphy;
  1224. if (!priv->tbi_node) {
  1225. dev_warn(&dev->dev, "error: SGMII mode requires that the "
  1226. "device tree specify a tbi-handle\n");
  1227. return;
  1228. }
  1229. tbiphy = of_phy_find_device(priv->tbi_node);
  1230. if (!tbiphy) {
  1231. dev_err(&dev->dev, "error: Could not get TBI device\n");
  1232. return;
  1233. }
  1234. /* If the link is already up, we must already be ok, and don't need to
  1235. * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
  1236. * everything for us? Resetting it takes the link down and requires
  1237. * several seconds for it to come back.
  1238. */
  1239. if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
  1240. return;
  1241. /* Single clk mode, mii mode off(for serdes communication) */
  1242. phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
  1243. phy_write(tbiphy, MII_ADVERTISE,
  1244. ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
  1245. ADVERTISE_1000XPSE_ASYM);
  1246. phy_write(tbiphy, MII_BMCR,
  1247. BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
  1248. BMCR_SPEED1000);
  1249. }
  1250. static void init_registers(struct net_device *dev)
  1251. {
  1252. struct gfar_private *priv = netdev_priv(dev);
  1253. struct gfar __iomem *regs = NULL;
  1254. int i;
  1255. for (i = 0; i < priv->num_grps; i++) {
  1256. regs = priv->gfargrp[i].regs;
  1257. /* Clear IEVENT */
  1258. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1259. /* Initialize IMASK */
  1260. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1261. }
  1262. regs = priv->gfargrp[0].regs;
  1263. /* Init hash registers to zero */
  1264. gfar_write(&regs->igaddr0, 0);
  1265. gfar_write(&regs->igaddr1, 0);
  1266. gfar_write(&regs->igaddr2, 0);
  1267. gfar_write(&regs->igaddr3, 0);
  1268. gfar_write(&regs->igaddr4, 0);
  1269. gfar_write(&regs->igaddr5, 0);
  1270. gfar_write(&regs->igaddr6, 0);
  1271. gfar_write(&regs->igaddr7, 0);
  1272. gfar_write(&regs->gaddr0, 0);
  1273. gfar_write(&regs->gaddr1, 0);
  1274. gfar_write(&regs->gaddr2, 0);
  1275. gfar_write(&regs->gaddr3, 0);
  1276. gfar_write(&regs->gaddr4, 0);
  1277. gfar_write(&regs->gaddr5, 0);
  1278. gfar_write(&regs->gaddr6, 0);
  1279. gfar_write(&regs->gaddr7, 0);
  1280. /* Zero out the rmon mib registers if it has them */
  1281. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
  1282. memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
  1283. /* Mask off the CAM interrupts */
  1284. gfar_write(&regs->rmon.cam1, 0xffffffff);
  1285. gfar_write(&regs->rmon.cam2, 0xffffffff);
  1286. }
  1287. /* Initialize the max receive buffer length */
  1288. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  1289. /* Initialize the Minimum Frame Length Register */
  1290. gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
  1291. }
  1292. static int __gfar_is_rx_idle(struct gfar_private *priv)
  1293. {
  1294. u32 res;
  1295. /* Normaly TSEC should not hang on GRS commands, so we should
  1296. * actually wait for IEVENT_GRSC flag.
  1297. */
  1298. if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
  1299. return 0;
  1300. /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
  1301. * the same as bits 23-30, the eTSEC Rx is assumed to be idle
  1302. * and the Rx can be safely reset.
  1303. */
  1304. res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
  1305. res &= 0x7f807f80;
  1306. if ((res & 0xffff) == (res >> 16))
  1307. return 1;
  1308. return 0;
  1309. }
  1310. /* Halt the receive and transmit queues */
  1311. static void gfar_halt_nodisable(struct net_device *dev)
  1312. {
  1313. struct gfar_private *priv = netdev_priv(dev);
  1314. struct gfar __iomem *regs = NULL;
  1315. u32 tempval;
  1316. int i;
  1317. for (i = 0; i < priv->num_grps; i++) {
  1318. regs = priv->gfargrp[i].regs;
  1319. /* Mask all interrupts */
  1320. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1321. /* Clear all interrupts */
  1322. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1323. }
  1324. regs = priv->gfargrp[0].regs;
  1325. /* Stop the DMA, and wait for it to stop */
  1326. tempval = gfar_read(&regs->dmactrl);
  1327. if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
  1328. (DMACTRL_GRS | DMACTRL_GTS)) {
  1329. int ret;
  1330. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  1331. gfar_write(&regs->dmactrl, tempval);
  1332. do {
  1333. ret = spin_event_timeout(((gfar_read(&regs->ievent) &
  1334. (IEVENT_GRSC | IEVENT_GTSC)) ==
  1335. (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
  1336. if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
  1337. ret = __gfar_is_rx_idle(priv);
  1338. } while (!ret);
  1339. }
  1340. }
  1341. /* Halt the receive and transmit queues */
  1342. void gfar_halt(struct net_device *dev)
  1343. {
  1344. struct gfar_private *priv = netdev_priv(dev);
  1345. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1346. u32 tempval;
  1347. gfar_halt_nodisable(dev);
  1348. /* Disable Rx and Tx */
  1349. tempval = gfar_read(&regs->maccfg1);
  1350. tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  1351. gfar_write(&regs->maccfg1, tempval);
  1352. }
  1353. static void free_grp_irqs(struct gfar_priv_grp *grp)
  1354. {
  1355. free_irq(grp->interruptError, grp);
  1356. free_irq(grp->interruptTransmit, grp);
  1357. free_irq(grp->interruptReceive, grp);
  1358. }
  1359. void stop_gfar(struct net_device *dev)
  1360. {
  1361. struct gfar_private *priv = netdev_priv(dev);
  1362. unsigned long flags;
  1363. int i;
  1364. phy_stop(priv->phydev);
  1365. /* Lock it down */
  1366. local_irq_save(flags);
  1367. lock_tx_qs(priv);
  1368. lock_rx_qs(priv);
  1369. gfar_halt(dev);
  1370. unlock_rx_qs(priv);
  1371. unlock_tx_qs(priv);
  1372. local_irq_restore(flags);
  1373. /* Free the IRQs */
  1374. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1375. for (i = 0; i < priv->num_grps; i++)
  1376. free_grp_irqs(&priv->gfargrp[i]);
  1377. } else {
  1378. for (i = 0; i < priv->num_grps; i++)
  1379. free_irq(priv->gfargrp[i].interruptTransmit,
  1380. &priv->gfargrp[i]);
  1381. }
  1382. free_skb_resources(priv);
  1383. }
  1384. static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
  1385. {
  1386. struct txbd8 *txbdp;
  1387. struct gfar_private *priv = netdev_priv(tx_queue->dev);
  1388. int i, j;
  1389. txbdp = tx_queue->tx_bd_base;
  1390. for (i = 0; i < tx_queue->tx_ring_size; i++) {
  1391. if (!tx_queue->tx_skbuff[i])
  1392. continue;
  1393. dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
  1394. txbdp->length, DMA_TO_DEVICE);
  1395. txbdp->lstatus = 0;
  1396. for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
  1397. j++) {
  1398. txbdp++;
  1399. dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
  1400. txbdp->length, DMA_TO_DEVICE);
  1401. }
  1402. txbdp++;
  1403. dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
  1404. tx_queue->tx_skbuff[i] = NULL;
  1405. }
  1406. kfree(tx_queue->tx_skbuff);
  1407. tx_queue->tx_skbuff = NULL;
  1408. }
  1409. static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
  1410. {
  1411. struct rxbd8 *rxbdp;
  1412. struct gfar_private *priv = netdev_priv(rx_queue->dev);
  1413. int i;
  1414. rxbdp = rx_queue->rx_bd_base;
  1415. for (i = 0; i < rx_queue->rx_ring_size; i++) {
  1416. if (rx_queue->rx_skbuff[i]) {
  1417. dma_unmap_single(&priv->ofdev->dev,
  1418. rxbdp->bufPtr, priv->rx_buffer_size,
  1419. DMA_FROM_DEVICE);
  1420. dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
  1421. rx_queue->rx_skbuff[i] = NULL;
  1422. }
  1423. rxbdp->lstatus = 0;
  1424. rxbdp->bufPtr = 0;
  1425. rxbdp++;
  1426. }
  1427. kfree(rx_queue->rx_skbuff);
  1428. rx_queue->rx_skbuff = NULL;
  1429. }
  1430. /* If there are any tx skbs or rx skbs still around, free them.
  1431. * Then free tx_skbuff and rx_skbuff
  1432. */
  1433. static void free_skb_resources(struct gfar_private *priv)
  1434. {
  1435. struct gfar_priv_tx_q *tx_queue = NULL;
  1436. struct gfar_priv_rx_q *rx_queue = NULL;
  1437. int i;
  1438. /* Go through all the buffer descriptors and free their data buffers */
  1439. for (i = 0; i < priv->num_tx_queues; i++) {
  1440. struct netdev_queue *txq;
  1441. tx_queue = priv->tx_queue[i];
  1442. txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
  1443. if (tx_queue->tx_skbuff)
  1444. free_skb_tx_queue(tx_queue);
  1445. netdev_tx_reset_queue(txq);
  1446. }
  1447. for (i = 0; i < priv->num_rx_queues; i++) {
  1448. rx_queue = priv->rx_queue[i];
  1449. if (rx_queue->rx_skbuff)
  1450. free_skb_rx_queue(rx_queue);
  1451. }
  1452. dma_free_coherent(&priv->ofdev->dev,
  1453. sizeof(struct txbd8) * priv->total_tx_ring_size +
  1454. sizeof(struct rxbd8) * priv->total_rx_ring_size,
  1455. priv->tx_queue[0]->tx_bd_base,
  1456. priv->tx_queue[0]->tx_bd_dma_base);
  1457. }
  1458. void gfar_start(struct net_device *dev)
  1459. {
  1460. struct gfar_private *priv = netdev_priv(dev);
  1461. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1462. u32 tempval;
  1463. int i = 0;
  1464. /* Enable Rx and Tx in MACCFG1 */
  1465. tempval = gfar_read(&regs->maccfg1);
  1466. tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
  1467. gfar_write(&regs->maccfg1, tempval);
  1468. /* Initialize DMACTRL to have WWR and WOP */
  1469. tempval = gfar_read(&regs->dmactrl);
  1470. tempval |= DMACTRL_INIT_SETTINGS;
  1471. gfar_write(&regs->dmactrl, tempval);
  1472. /* Make sure we aren't stopped */
  1473. tempval = gfar_read(&regs->dmactrl);
  1474. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  1475. gfar_write(&regs->dmactrl, tempval);
  1476. for (i = 0; i < priv->num_grps; i++) {
  1477. regs = priv->gfargrp[i].regs;
  1478. /* Clear THLT/RHLT, so that the DMA starts polling now */
  1479. gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
  1480. gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
  1481. /* Unmask the interrupts we look for */
  1482. gfar_write(&regs->imask, IMASK_DEFAULT);
  1483. }
  1484. dev->trans_start = jiffies; /* prevent tx timeout */
  1485. }
  1486. void gfar_configure_coalescing(struct gfar_private *priv,
  1487. unsigned long tx_mask, unsigned long rx_mask)
  1488. {
  1489. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1490. u32 __iomem *baddr;
  1491. int i = 0;
  1492. /* Backward compatible case ---- even if we enable
  1493. * multiple queues, there's only single reg to program
  1494. */
  1495. gfar_write(&regs->txic, 0);
  1496. if (likely(priv->tx_queue[0]->txcoalescing))
  1497. gfar_write(&regs->txic, priv->tx_queue[0]->txic);
  1498. gfar_write(&regs->rxic, 0);
  1499. if (unlikely(priv->rx_queue[0]->rxcoalescing))
  1500. gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
  1501. if (priv->mode == MQ_MG_MODE) {
  1502. baddr = &regs->txic0;
  1503. for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
  1504. gfar_write(baddr + i, 0);
  1505. if (likely(priv->tx_queue[i]->txcoalescing))
  1506. gfar_write(baddr + i, priv->tx_queue[i]->txic);
  1507. }
  1508. baddr = &regs->rxic0;
  1509. for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
  1510. gfar_write(baddr + i, 0);
  1511. if (likely(priv->rx_queue[i]->rxcoalescing))
  1512. gfar_write(baddr + i, priv->rx_queue[i]->rxic);
  1513. }
  1514. }
  1515. }
  1516. static int register_grp_irqs(struct gfar_priv_grp *grp)
  1517. {
  1518. struct gfar_private *priv = grp->priv;
  1519. struct net_device *dev = priv->ndev;
  1520. int err;
  1521. /* If the device has multiple interrupts, register for
  1522. * them. Otherwise, only register for the one
  1523. */
  1524. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1525. /* Install our interrupt handlers for Error,
  1526. * Transmit, and Receive
  1527. */
  1528. if ((err = request_irq(grp->interruptError, gfar_error,
  1529. 0, grp->int_name_er, grp)) < 0) {
  1530. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1531. grp->interruptError);
  1532. goto err_irq_fail;
  1533. }
  1534. if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
  1535. 0, grp->int_name_tx, grp)) < 0) {
  1536. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1537. grp->interruptTransmit);
  1538. goto tx_irq_fail;
  1539. }
  1540. if ((err = request_irq(grp->interruptReceive, gfar_receive,
  1541. 0, grp->int_name_rx, grp)) < 0) {
  1542. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1543. grp->interruptReceive);
  1544. goto rx_irq_fail;
  1545. }
  1546. } else {
  1547. if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
  1548. 0, grp->int_name_tx, grp)) < 0) {
  1549. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1550. grp->interruptTransmit);
  1551. goto err_irq_fail;
  1552. }
  1553. }
  1554. return 0;
  1555. rx_irq_fail:
  1556. free_irq(grp->interruptTransmit, grp);
  1557. tx_irq_fail:
  1558. free_irq(grp->interruptError, grp);
  1559. err_irq_fail:
  1560. return err;
  1561. }
  1562. /* Bring the controller up and running */
  1563. int startup_gfar(struct net_device *ndev)
  1564. {
  1565. struct gfar_private *priv = netdev_priv(ndev);
  1566. struct gfar __iomem *regs = NULL;
  1567. int err, i, j;
  1568. for (i = 0; i < priv->num_grps; i++) {
  1569. regs= priv->gfargrp[i].regs;
  1570. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1571. }
  1572. regs= priv->gfargrp[0].regs;
  1573. err = gfar_alloc_skb_resources(ndev);
  1574. if (err)
  1575. return err;
  1576. gfar_init_mac(ndev);
  1577. for (i = 0; i < priv->num_grps; i++) {
  1578. err = register_grp_irqs(&priv->gfargrp[i]);
  1579. if (err) {
  1580. for (j = 0; j < i; j++)
  1581. free_grp_irqs(&priv->gfargrp[j]);
  1582. goto irq_fail;
  1583. }
  1584. }
  1585. /* Start the controller */
  1586. gfar_start(ndev);
  1587. phy_start(priv->phydev);
  1588. gfar_configure_coalescing(priv, 0xFF, 0xFF);
  1589. return 0;
  1590. irq_fail:
  1591. free_skb_resources(priv);
  1592. return err;
  1593. }
  1594. /* Called when something needs to use the ethernet device
  1595. * Returns 0 for success.
  1596. */
  1597. static int gfar_enet_open(struct net_device *dev)
  1598. {
  1599. struct gfar_private *priv = netdev_priv(dev);
  1600. int err;
  1601. enable_napi(priv);
  1602. /* Initialize a bunch of registers */
  1603. init_registers(dev);
  1604. gfar_set_mac_address(dev);
  1605. err = init_phy(dev);
  1606. if (err) {
  1607. disable_napi(priv);
  1608. return err;
  1609. }
  1610. err = startup_gfar(dev);
  1611. if (err) {
  1612. disable_napi(priv);
  1613. return err;
  1614. }
  1615. netif_tx_start_all_queues(dev);
  1616. device_set_wakeup_enable(&dev->dev, priv->wol_en);
  1617. return err;
  1618. }
  1619. static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
  1620. {
  1621. struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
  1622. memset(fcb, 0, GMAC_FCB_LEN);
  1623. return fcb;
  1624. }
  1625. static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
  1626. int fcb_length)
  1627. {
  1628. /* If we're here, it's a IP packet with a TCP or UDP
  1629. * payload. We set it to checksum, using a pseudo-header
  1630. * we provide
  1631. */
  1632. u8 flags = TXFCB_DEFAULT;
  1633. /* Tell the controller what the protocol is
  1634. * And provide the already calculated phcs
  1635. */
  1636. if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  1637. flags |= TXFCB_UDP;
  1638. fcb->phcs = udp_hdr(skb)->check;
  1639. } else
  1640. fcb->phcs = tcp_hdr(skb)->check;
  1641. /* l3os is the distance between the start of the
  1642. * frame (skb->data) and the start of the IP hdr.
  1643. * l4os is the distance between the start of the
  1644. * l3 hdr and the l4 hdr
  1645. */
  1646. fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
  1647. fcb->l4os = skb_network_header_len(skb);
  1648. fcb->flags = flags;
  1649. }
  1650. void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
  1651. {
  1652. fcb->flags |= TXFCB_VLN;
  1653. fcb->vlctl = vlan_tx_tag_get(skb);
  1654. }
  1655. static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
  1656. struct txbd8 *base, int ring_size)
  1657. {
  1658. struct txbd8 *new_bd = bdp + stride;
  1659. return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
  1660. }
  1661. static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
  1662. int ring_size)
  1663. {
  1664. return skip_txbd(bdp, 1, base, ring_size);
  1665. }
  1666. /* This is called by the kernel when a frame is ready for transmission.
  1667. * It is pointed to by the dev->hard_start_xmit function pointer
  1668. */
  1669. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1670. {
  1671. struct gfar_private *priv = netdev_priv(dev);
  1672. struct gfar_priv_tx_q *tx_queue = NULL;
  1673. struct netdev_queue *txq;
  1674. struct gfar __iomem *regs = NULL;
  1675. struct txfcb *fcb = NULL;
  1676. struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
  1677. u32 lstatus;
  1678. int i, rq = 0, do_tstamp = 0;
  1679. u32 bufaddr;
  1680. unsigned long flags;
  1681. unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
  1682. /* TOE=1 frames larger than 2500 bytes may see excess delays
  1683. * before start of transmission.
  1684. */
  1685. if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
  1686. skb->ip_summed == CHECKSUM_PARTIAL &&
  1687. skb->len > 2500)) {
  1688. int ret;
  1689. ret = skb_checksum_help(skb);
  1690. if (ret)
  1691. return ret;
  1692. }
  1693. rq = skb->queue_mapping;
  1694. tx_queue = priv->tx_queue[rq];
  1695. txq = netdev_get_tx_queue(dev, rq);
  1696. base = tx_queue->tx_bd_base;
  1697. regs = tx_queue->grp->regs;
  1698. /* check if time stamp should be generated */
  1699. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  1700. priv->hwts_tx_en)) {
  1701. do_tstamp = 1;
  1702. fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
  1703. }
  1704. /* make space for additional header when fcb is needed */
  1705. if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
  1706. vlan_tx_tag_present(skb) ||
  1707. unlikely(do_tstamp)) &&
  1708. (skb_headroom(skb) < fcb_length)) {
  1709. struct sk_buff *skb_new;
  1710. skb_new = skb_realloc_headroom(skb, fcb_length);
  1711. if (!skb_new) {
  1712. dev->stats.tx_errors++;
  1713. kfree_skb(skb);
  1714. return NETDEV_TX_OK;
  1715. }
  1716. if (skb->sk)
  1717. skb_set_owner_w(skb_new, skb->sk);
  1718. consume_skb(skb);
  1719. skb = skb_new;
  1720. }
  1721. /* total number of fragments in the SKB */
  1722. nr_frags = skb_shinfo(skb)->nr_frags;
  1723. /* calculate the required number of TxBDs for this skb */
  1724. if (unlikely(do_tstamp))
  1725. nr_txbds = nr_frags + 2;
  1726. else
  1727. nr_txbds = nr_frags + 1;
  1728. /* check if there is space to queue this packet */
  1729. if (nr_txbds > tx_queue->num_txbdfree) {
  1730. /* no space, stop the queue */
  1731. netif_tx_stop_queue(txq);
  1732. dev->stats.tx_fifo_errors++;
  1733. return NETDEV_TX_BUSY;
  1734. }
  1735. /* Update transmit stats */
  1736. tx_queue->stats.tx_bytes += skb->len;
  1737. tx_queue->stats.tx_packets++;
  1738. txbdp = txbdp_start = tx_queue->cur_tx;
  1739. lstatus = txbdp->lstatus;
  1740. /* Time stamp insertion requires one additional TxBD */
  1741. if (unlikely(do_tstamp))
  1742. txbdp_tstamp = txbdp = next_txbd(txbdp, base,
  1743. tx_queue->tx_ring_size);
  1744. if (nr_frags == 0) {
  1745. if (unlikely(do_tstamp))
  1746. txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
  1747. TXBD_INTERRUPT);
  1748. else
  1749. lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1750. } else {
  1751. /* Place the fragment addresses and lengths into the TxBDs */
  1752. for (i = 0; i < nr_frags; i++) {
  1753. /* Point at the next BD, wrapping as needed */
  1754. txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1755. length = skb_shinfo(skb)->frags[i].size;
  1756. lstatus = txbdp->lstatus | length |
  1757. BD_LFLAG(TXBD_READY);
  1758. /* Handle the last BD specially */
  1759. if (i == nr_frags - 1)
  1760. lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1761. bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
  1762. &skb_shinfo(skb)->frags[i],
  1763. 0,
  1764. length,
  1765. DMA_TO_DEVICE);
  1766. /* set the TxBD length and buffer pointer */
  1767. txbdp->bufPtr = bufaddr;
  1768. txbdp->lstatus = lstatus;
  1769. }
  1770. lstatus = txbdp_start->lstatus;
  1771. }
  1772. /* Add TxPAL between FCB and frame if required */
  1773. if (unlikely(do_tstamp)) {
  1774. skb_push(skb, GMAC_TXPAL_LEN);
  1775. memset(skb->data, 0, GMAC_TXPAL_LEN);
  1776. }
  1777. /* Set up checksumming */
  1778. if (CHECKSUM_PARTIAL == skb->ip_summed) {
  1779. fcb = gfar_add_fcb(skb);
  1780. /* as specified by errata */
  1781. if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
  1782. ((unsigned long)fcb % 0x20) > 0x18)) {
  1783. __skb_pull(skb, GMAC_FCB_LEN);
  1784. skb_checksum_help(skb);
  1785. } else {
  1786. lstatus |= BD_LFLAG(TXBD_TOE);
  1787. gfar_tx_checksum(skb, fcb, fcb_length);
  1788. }
  1789. }
  1790. if (vlan_tx_tag_present(skb)) {
  1791. if (unlikely(NULL == fcb)) {
  1792. fcb = gfar_add_fcb(skb);
  1793. lstatus |= BD_LFLAG(TXBD_TOE);
  1794. }
  1795. gfar_tx_vlan(skb, fcb);
  1796. }
  1797. /* Setup tx hardware time stamping if requested */
  1798. if (unlikely(do_tstamp)) {
  1799. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1800. if (fcb == NULL)
  1801. fcb = gfar_add_fcb(skb);
  1802. fcb->ptp = 1;
  1803. lstatus |= BD_LFLAG(TXBD_TOE);
  1804. }
  1805. txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
  1806. skb_headlen(skb), DMA_TO_DEVICE);
  1807. /* If time stamping is requested one additional TxBD must be set up. The
  1808. * first TxBD points to the FCB and must have a data length of
  1809. * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
  1810. * the full frame length.
  1811. */
  1812. if (unlikely(do_tstamp)) {
  1813. txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
  1814. txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
  1815. (skb_headlen(skb) - fcb_length);
  1816. lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
  1817. } else {
  1818. lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
  1819. }
  1820. netdev_tx_sent_queue(txq, skb->len);
  1821. /* We can work in parallel with gfar_clean_tx_ring(), except
  1822. * when modifying num_txbdfree. Note that we didn't grab the lock
  1823. * when we were reading the num_txbdfree and checking for available
  1824. * space, that's because outside of this function it can only grow,
  1825. * and once we've got needed space, it cannot suddenly disappear.
  1826. *
  1827. * The lock also protects us from gfar_error(), which can modify
  1828. * regs->tstat and thus retrigger the transfers, which is why we
  1829. * also must grab the lock before setting ready bit for the first
  1830. * to be transmitted BD.
  1831. */
  1832. spin_lock_irqsave(&tx_queue->txlock, flags);
  1833. /* The powerpc-specific eieio() is used, as wmb() has too strong
  1834. * semantics (it requires synchronization between cacheable and
  1835. * uncacheable mappings, which eieio doesn't provide and which we
  1836. * don't need), thus requiring a more expensive sync instruction. At
  1837. * some point, the set of architecture-independent barrier functions
  1838. * should be expanded to include weaker barriers.
  1839. */
  1840. eieio();
  1841. txbdp_start->lstatus = lstatus;
  1842. eieio(); /* force lstatus write before tx_skbuff */
  1843. tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
  1844. /* Update the current skb pointer to the next entry we will use
  1845. * (wrapping if necessary)
  1846. */
  1847. tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
  1848. TX_RING_MOD_MASK(tx_queue->tx_ring_size);
  1849. tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1850. /* reduce TxBD free count */
  1851. tx_queue->num_txbdfree -= (nr_txbds);
  1852. /* If the next BD still needs to be cleaned up, then the bds
  1853. * are full. We need to tell the kernel to stop sending us stuff.
  1854. */
  1855. if (!tx_queue->num_txbdfree) {
  1856. netif_tx_stop_queue(txq);
  1857. dev->stats.tx_fifo_errors++;
  1858. }
  1859. /* Tell the DMA to go go go */
  1860. gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
  1861. /* Unlock priv */
  1862. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  1863. return NETDEV_TX_OK;
  1864. }
  1865. /* Stops the kernel queue, and halts the controller */
  1866. static int gfar_close(struct net_device *dev)
  1867. {
  1868. struct gfar_private *priv = netdev_priv(dev);
  1869. disable_napi(priv);
  1870. cancel_work_sync(&priv->reset_task);
  1871. stop_gfar(dev);
  1872. /* Disconnect from the PHY */
  1873. phy_disconnect(priv->phydev);
  1874. priv->phydev = NULL;
  1875. netif_tx_stop_all_queues(dev);
  1876. return 0;
  1877. }
  1878. /* Changes the mac address if the controller is not running. */
  1879. static int gfar_set_mac_address(struct net_device *dev)
  1880. {
  1881. gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
  1882. return 0;
  1883. }
  1884. /* Check if rx parser should be activated */
  1885. void gfar_check_rx_parser_mode(struct gfar_private *priv)
  1886. {
  1887. struct gfar __iomem *regs;
  1888. u32 tempval;
  1889. regs = priv->gfargrp[0].regs;
  1890. tempval = gfar_read(&regs->rctrl);
  1891. /* If parse is no longer required, then disable parser */
  1892. if (tempval & RCTRL_REQ_PARSER)
  1893. tempval |= RCTRL_PRSDEP_INIT;
  1894. else
  1895. tempval &= ~RCTRL_PRSDEP_INIT;
  1896. gfar_write(&regs->rctrl, tempval);
  1897. }
  1898. /* Enables and disables VLAN insertion/extraction */
  1899. void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
  1900. {
  1901. struct gfar_private *priv = netdev_priv(dev);
  1902. struct gfar __iomem *regs = NULL;
  1903. unsigned long flags;
  1904. u32 tempval;
  1905. regs = priv->gfargrp[0].regs;
  1906. local_irq_save(flags);
  1907. lock_rx_qs(priv);
  1908. if (features & NETIF_F_HW_VLAN_TX) {
  1909. /* Enable VLAN tag insertion */
  1910. tempval = gfar_read(&regs->tctrl);
  1911. tempval |= TCTRL_VLINS;
  1912. gfar_write(&regs->tctrl, tempval);
  1913. } else {
  1914. /* Disable VLAN tag insertion */
  1915. tempval = gfar_read(&regs->tctrl);
  1916. tempval &= ~TCTRL_VLINS;
  1917. gfar_write(&regs->tctrl, tempval);
  1918. }
  1919. if (features & NETIF_F_HW_VLAN_RX) {
  1920. /* Enable VLAN tag extraction */
  1921. tempval = gfar_read(&regs->rctrl);
  1922. tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
  1923. gfar_write(&regs->rctrl, tempval);
  1924. } else {
  1925. /* Disable VLAN tag extraction */
  1926. tempval = gfar_read(&regs->rctrl);
  1927. tempval &= ~RCTRL_VLEX;
  1928. gfar_write(&regs->rctrl, tempval);
  1929. gfar_check_rx_parser_mode(priv);
  1930. }
  1931. gfar_change_mtu(dev, dev->mtu);
  1932. unlock_rx_qs(priv);
  1933. local_irq_restore(flags);
  1934. }
  1935. static int gfar_change_mtu(struct net_device *dev, int new_mtu)
  1936. {
  1937. int tempsize, tempval;
  1938. struct gfar_private *priv = netdev_priv(dev);
  1939. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1940. int oldsize = priv->rx_buffer_size;
  1941. int frame_size = new_mtu + ETH_HLEN;
  1942. if (gfar_is_vlan_on(priv))
  1943. frame_size += VLAN_HLEN;
  1944. if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
  1945. netif_err(priv, drv, dev, "Invalid MTU setting\n");
  1946. return -EINVAL;
  1947. }
  1948. if (gfar_uses_fcb(priv))
  1949. frame_size += GMAC_FCB_LEN;
  1950. frame_size += priv->padding;
  1951. tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
  1952. INCREMENTAL_BUFFER_SIZE;
  1953. /* Only stop and start the controller if it isn't already
  1954. * stopped, and we changed something
  1955. */
  1956. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1957. stop_gfar(dev);
  1958. priv->rx_buffer_size = tempsize;
  1959. dev->mtu = new_mtu;
  1960. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  1961. gfar_write(&regs->maxfrm, priv->rx_buffer_size);
  1962. /* If the mtu is larger than the max size for standard
  1963. * ethernet frames (ie, a jumbo frame), then set maccfg2
  1964. * to allow huge frames, and to check the length
  1965. */
  1966. tempval = gfar_read(&regs->maccfg2);
  1967. if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
  1968. gfar_has_errata(priv, GFAR_ERRATA_74))
  1969. tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1970. else
  1971. tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1972. gfar_write(&regs->maccfg2, tempval);
  1973. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1974. startup_gfar(dev);
  1975. return 0;
  1976. }
  1977. /* gfar_reset_task gets scheduled when a packet has not been
  1978. * transmitted after a set amount of time.
  1979. * For now, assume that clearing out all the structures, and
  1980. * starting over will fix the problem.
  1981. */
  1982. static void gfar_reset_task(struct work_struct *work)
  1983. {
  1984. struct gfar_private *priv = container_of(work, struct gfar_private,
  1985. reset_task);
  1986. struct net_device *dev = priv->ndev;
  1987. if (dev->flags & IFF_UP) {
  1988. netif_tx_stop_all_queues(dev);
  1989. stop_gfar(dev);
  1990. startup_gfar(dev);
  1991. netif_tx_start_all_queues(dev);
  1992. }
  1993. netif_tx_schedule_all(dev);
  1994. }
  1995. static void gfar_timeout(struct net_device *dev)
  1996. {
  1997. struct gfar_private *priv = netdev_priv(dev);
  1998. dev->stats.tx_errors++;
  1999. schedule_work(&priv->reset_task);
  2000. }
  2001. static void gfar_align_skb(struct sk_buff *skb)
  2002. {
  2003. /* We need the data buffer to be aligned properly. We will reserve
  2004. * as many bytes as needed to align the data properly
  2005. */
  2006. skb_reserve(skb, RXBUF_ALIGNMENT -
  2007. (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
  2008. }
  2009. /* Interrupt Handler for Transmit complete */
  2010. static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
  2011. {
  2012. struct net_device *dev = tx_queue->dev;
  2013. struct netdev_queue *txq;
  2014. struct gfar_private *priv = netdev_priv(dev);
  2015. struct gfar_priv_rx_q *rx_queue = NULL;
  2016. struct txbd8 *bdp, *next = NULL;
  2017. struct txbd8 *lbdp = NULL;
  2018. struct txbd8 *base = tx_queue->tx_bd_base;
  2019. struct sk_buff *skb;
  2020. int skb_dirtytx;
  2021. int tx_ring_size = tx_queue->tx_ring_size;
  2022. int frags = 0, nr_txbds = 0;
  2023. int i;
  2024. int howmany = 0;
  2025. int tqi = tx_queue->qindex;
  2026. unsigned int bytes_sent = 0;
  2027. u32 lstatus;
  2028. size_t buflen;
  2029. rx_queue = priv->rx_queue[tqi];
  2030. txq = netdev_get_tx_queue(dev, tqi);
  2031. bdp = tx_queue->dirty_tx;
  2032. skb_dirtytx = tx_queue->skb_dirtytx;
  2033. while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
  2034. unsigned long flags;
  2035. frags = skb_shinfo(skb)->nr_frags;
  2036. /* When time stamping, one additional TxBD must be freed.
  2037. * Also, we need to dma_unmap_single() the TxPAL.
  2038. */
  2039. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
  2040. nr_txbds = frags + 2;
  2041. else
  2042. nr_txbds = frags + 1;
  2043. lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
  2044. lstatus = lbdp->lstatus;
  2045. /* Only clean completed frames */
  2046. if ((lstatus & BD_LFLAG(TXBD_READY)) &&
  2047. (lstatus & BD_LENGTH_MASK))
  2048. break;
  2049. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
  2050. next = next_txbd(bdp, base, tx_ring_size);
  2051. buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
  2052. } else
  2053. buflen = bdp->length;
  2054. dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
  2055. buflen, DMA_TO_DEVICE);
  2056. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
  2057. struct skb_shared_hwtstamps shhwtstamps;
  2058. u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
  2059. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  2060. shhwtstamps.hwtstamp = ns_to_ktime(*ns);
  2061. skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
  2062. skb_tstamp_tx(skb, &shhwtstamps);
  2063. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2064. bdp = next;
  2065. }
  2066. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2067. bdp = next_txbd(bdp, base, tx_ring_size);
  2068. for (i = 0; i < frags; i++) {
  2069. dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
  2070. bdp->length, DMA_TO_DEVICE);
  2071. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2072. bdp = next_txbd(bdp, base, tx_ring_size);
  2073. }
  2074. bytes_sent += skb->len;
  2075. dev_kfree_skb_any(skb);
  2076. tx_queue->tx_skbuff[skb_dirtytx] = NULL;
  2077. skb_dirtytx = (skb_dirtytx + 1) &
  2078. TX_RING_MOD_MASK(tx_ring_size);
  2079. howmany++;
  2080. spin_lock_irqsave(&tx_queue->txlock, flags);
  2081. tx_queue->num_txbdfree += nr_txbds;
  2082. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  2083. }
  2084. /* If we freed a buffer, we can restart transmission, if necessary */
  2085. if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
  2086. netif_wake_subqueue(dev, tqi);
  2087. /* Update dirty indicators */
  2088. tx_queue->skb_dirtytx = skb_dirtytx;
  2089. tx_queue->dirty_tx = bdp;
  2090. netdev_tx_completed_queue(txq, howmany, bytes_sent);
  2091. return howmany;
  2092. }
  2093. static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
  2094. {
  2095. unsigned long flags;
  2096. spin_lock_irqsave(&gfargrp->grplock, flags);
  2097. if (napi_schedule_prep(&gfargrp->napi)) {
  2098. gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
  2099. __napi_schedule(&gfargrp->napi);
  2100. } else {
  2101. /* Clear IEVENT, so interrupts aren't called again
  2102. * because of the packets that have already arrived.
  2103. */
  2104. gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
  2105. }
  2106. spin_unlock_irqrestore(&gfargrp->grplock, flags);
  2107. }
  2108. /* Interrupt Handler for Transmit complete */
  2109. static irqreturn_t gfar_transmit(int irq, void *grp_id)
  2110. {
  2111. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  2112. return IRQ_HANDLED;
  2113. }
  2114. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  2115. struct sk_buff *skb)
  2116. {
  2117. struct net_device *dev = rx_queue->dev;
  2118. struct gfar_private *priv = netdev_priv(dev);
  2119. dma_addr_t buf;
  2120. buf = dma_map_single(&priv->ofdev->dev, skb->data,
  2121. priv->rx_buffer_size, DMA_FROM_DEVICE);
  2122. gfar_init_rxbdp(rx_queue, bdp, buf);
  2123. }
  2124. static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
  2125. {
  2126. struct gfar_private *priv = netdev_priv(dev);
  2127. struct sk_buff *skb;
  2128. skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
  2129. if (!skb)
  2130. return NULL;
  2131. gfar_align_skb(skb);
  2132. return skb;
  2133. }
  2134. struct sk_buff *gfar_new_skb(struct net_device *dev)
  2135. {
  2136. return gfar_alloc_skb(dev);
  2137. }
  2138. static inline void count_errors(unsigned short status, struct net_device *dev)
  2139. {
  2140. struct gfar_private *priv = netdev_priv(dev);
  2141. struct net_device_stats *stats = &dev->stats;
  2142. struct gfar_extra_stats *estats = &priv->extra_stats;
  2143. /* If the packet was truncated, none of the other errors matter */
  2144. if (status & RXBD_TRUNCATED) {
  2145. stats->rx_length_errors++;
  2146. estats->rx_trunc++;
  2147. return;
  2148. }
  2149. /* Count the errors, if there were any */
  2150. if (status & (RXBD_LARGE | RXBD_SHORT)) {
  2151. stats->rx_length_errors++;
  2152. if (status & RXBD_LARGE)
  2153. estats->rx_large++;
  2154. else
  2155. estats->rx_short++;
  2156. }
  2157. if (status & RXBD_NONOCTET) {
  2158. stats->rx_frame_errors++;
  2159. estats->rx_nonoctet++;
  2160. }
  2161. if (status & RXBD_CRCERR) {
  2162. estats->rx_crcerr++;
  2163. stats->rx_crc_errors++;
  2164. }
  2165. if (status & RXBD_OVERRUN) {
  2166. estats->rx_overrun++;
  2167. stats->rx_crc_errors++;
  2168. }
  2169. }
  2170. irqreturn_t gfar_receive(int irq, void *grp_id)
  2171. {
  2172. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  2173. return IRQ_HANDLED;
  2174. }
  2175. static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
  2176. {
  2177. /* If valid headers were found, and valid sums
  2178. * were verified, then we tell the kernel that no
  2179. * checksumming is necessary. Otherwise, it is [FIXME]
  2180. */
  2181. if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
  2182. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2183. else
  2184. skb_checksum_none_assert(skb);
  2185. }
  2186. /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
  2187. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  2188. int amount_pull, struct napi_struct *napi)
  2189. {
  2190. struct gfar_private *priv = netdev_priv(dev);
  2191. struct rxfcb *fcb = NULL;
  2192. gro_result_t ret;
  2193. /* fcb is at the beginning if exists */
  2194. fcb = (struct rxfcb *)skb->data;
  2195. /* Remove the FCB from the skb
  2196. * Remove the padded bytes, if there are any
  2197. */
  2198. if (amount_pull) {
  2199. skb_record_rx_queue(skb, fcb->rq);
  2200. skb_pull(skb, amount_pull);
  2201. }
  2202. /* Get receive timestamp from the skb */
  2203. if (priv->hwts_rx_en) {
  2204. struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
  2205. u64 *ns = (u64 *) skb->data;
  2206. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  2207. shhwtstamps->hwtstamp = ns_to_ktime(*ns);
  2208. }
  2209. if (priv->padding)
  2210. skb_pull(skb, priv->padding);
  2211. if (dev->features & NETIF_F_RXCSUM)
  2212. gfar_rx_checksum(skb, fcb);
  2213. /* Tell the skb what kind of packet this is */
  2214. skb->protocol = eth_type_trans(skb, dev);
  2215. /* There's need to check for NETIF_F_HW_VLAN_RX here.
  2216. * Even if vlan rx accel is disabled, on some chips
  2217. * RXFCB_VLN is pseudo randomly set.
  2218. */
  2219. if (dev->features & NETIF_F_HW_VLAN_RX &&
  2220. fcb->flags & RXFCB_VLN)
  2221. __vlan_hwaccel_put_tag(skb, fcb->vlctl);
  2222. /* Send the packet up the stack */
  2223. ret = napi_gro_receive(napi, skb);
  2224. if (GRO_DROP == ret)
  2225. priv->extra_stats.kernel_dropped++;
  2226. return 0;
  2227. }
  2228. /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  2229. * until the budget/quota has been reached. Returns the number
  2230. * of frames handled
  2231. */
  2232. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
  2233. {
  2234. struct net_device *dev = rx_queue->dev;
  2235. struct rxbd8 *bdp, *base;
  2236. struct sk_buff *skb;
  2237. int pkt_len;
  2238. int amount_pull;
  2239. int howmany = 0;
  2240. struct gfar_private *priv = netdev_priv(dev);
  2241. /* Get the first full descriptor */
  2242. bdp = rx_queue->cur_rx;
  2243. base = rx_queue->rx_bd_base;
  2244. amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
  2245. while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
  2246. struct sk_buff *newskb;
  2247. rmb();
  2248. /* Add another skb for the future */
  2249. newskb = gfar_new_skb(dev);
  2250. skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
  2251. dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
  2252. priv->rx_buffer_size, DMA_FROM_DEVICE);
  2253. if (unlikely(!(bdp->status & RXBD_ERR) &&
  2254. bdp->length > priv->rx_buffer_size))
  2255. bdp->status = RXBD_LARGE;
  2256. /* We drop the frame if we failed to allocate a new buffer */
  2257. if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
  2258. bdp->status & RXBD_ERR)) {
  2259. count_errors(bdp->status, dev);
  2260. if (unlikely(!newskb))
  2261. newskb = skb;
  2262. else if (skb)
  2263. dev_kfree_skb(skb);
  2264. } else {
  2265. /* Increment the number of packets */
  2266. rx_queue->stats.rx_packets++;
  2267. howmany++;
  2268. if (likely(skb)) {
  2269. pkt_len = bdp->length - ETH_FCS_LEN;
  2270. /* Remove the FCS from the packet length */
  2271. skb_put(skb, pkt_len);
  2272. rx_queue->stats.rx_bytes += pkt_len;
  2273. skb_record_rx_queue(skb, rx_queue->qindex);
  2274. gfar_process_frame(dev, skb, amount_pull,
  2275. &rx_queue->grp->napi);
  2276. } else {
  2277. netif_warn(priv, rx_err, dev, "Missing skb!\n");
  2278. rx_queue->stats.rx_dropped++;
  2279. priv->extra_stats.rx_skbmissing++;
  2280. }
  2281. }
  2282. rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
  2283. /* Setup the new bdp */
  2284. gfar_new_rxbdp(rx_queue, bdp, newskb);
  2285. /* Update to the next pointer */
  2286. bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
  2287. /* update to point at the next skb */
  2288. rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
  2289. RX_RING_MOD_MASK(rx_queue->rx_ring_size);
  2290. }
  2291. /* Update the current rxbd pointer to be the next one */
  2292. rx_queue->cur_rx = bdp;
  2293. return howmany;
  2294. }
  2295. static int gfar_poll(struct napi_struct *napi, int budget)
  2296. {
  2297. struct gfar_priv_grp *gfargrp =
  2298. container_of(napi, struct gfar_priv_grp, napi);
  2299. struct gfar_private *priv = gfargrp->priv;
  2300. struct gfar __iomem *regs = gfargrp->regs;
  2301. struct gfar_priv_tx_q *tx_queue = NULL;
  2302. struct gfar_priv_rx_q *rx_queue = NULL;
  2303. int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
  2304. int tx_cleaned = 0, i, left_over_budget = budget;
  2305. unsigned long serviced_queues = 0;
  2306. int num_queues = 0;
  2307. num_queues = gfargrp->num_rx_queues;
  2308. budget_per_queue = budget/num_queues;
  2309. /* Clear IEVENT, so interrupts aren't called again
  2310. * because of the packets that have already arrived
  2311. */
  2312. gfar_write(&regs->ievent, IEVENT_RTX_MASK);
  2313. while (num_queues && left_over_budget) {
  2314. budget_per_queue = left_over_budget/num_queues;
  2315. left_over_budget = 0;
  2316. for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
  2317. if (test_bit(i, &serviced_queues))
  2318. continue;
  2319. rx_queue = priv->rx_queue[i];
  2320. tx_queue = priv->tx_queue[rx_queue->qindex];
  2321. tx_cleaned += gfar_clean_tx_ring(tx_queue);
  2322. rx_cleaned_per_queue =
  2323. gfar_clean_rx_ring(rx_queue, budget_per_queue);
  2324. rx_cleaned += rx_cleaned_per_queue;
  2325. if (rx_cleaned_per_queue < budget_per_queue) {
  2326. left_over_budget = left_over_budget +
  2327. (budget_per_queue -
  2328. rx_cleaned_per_queue);
  2329. set_bit(i, &serviced_queues);
  2330. num_queues--;
  2331. }
  2332. }
  2333. }
  2334. if (tx_cleaned)
  2335. return budget;
  2336. if (rx_cleaned < budget) {
  2337. napi_complete(napi);
  2338. /* Clear the halt bit in RSTAT */
  2339. gfar_write(&regs->rstat, gfargrp->rstat);
  2340. gfar_write(&regs->imask, IMASK_DEFAULT);
  2341. /* If we are coalescing interrupts, update the timer
  2342. * Otherwise, clear it
  2343. */
  2344. gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
  2345. gfargrp->tx_bit_map);
  2346. }
  2347. return rx_cleaned;
  2348. }
  2349. #ifdef CONFIG_NET_POLL_CONTROLLER
  2350. /* Polling 'interrupt' - used by things like netconsole to send skbs
  2351. * without having to re-enable interrupts. It's not called while
  2352. * the interrupt routine is executing.
  2353. */
  2354. static void gfar_netpoll(struct net_device *dev)
  2355. {
  2356. struct gfar_private *priv = netdev_priv(dev);
  2357. int i;
  2358. /* If the device has multiple interrupts, run tx/rx */
  2359. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  2360. for (i = 0; i < priv->num_grps; i++) {
  2361. disable_irq(priv->gfargrp[i].interruptTransmit);
  2362. disable_irq(priv->gfargrp[i].interruptReceive);
  2363. disable_irq(priv->gfargrp[i].interruptError);
  2364. gfar_interrupt(priv->gfargrp[i].interruptTransmit,
  2365. &priv->gfargrp[i]);
  2366. enable_irq(priv->gfargrp[i].interruptError);
  2367. enable_irq(priv->gfargrp[i].interruptReceive);
  2368. enable_irq(priv->gfargrp[i].interruptTransmit);
  2369. }
  2370. } else {
  2371. for (i = 0; i < priv->num_grps; i++) {
  2372. disable_irq(priv->gfargrp[i].interruptTransmit);
  2373. gfar_interrupt(priv->gfargrp[i].interruptTransmit,
  2374. &priv->gfargrp[i]);
  2375. enable_irq(priv->gfargrp[i].interruptTransmit);
  2376. }
  2377. }
  2378. }
  2379. #endif
  2380. /* The interrupt handler for devices with one interrupt */
  2381. static irqreturn_t gfar_interrupt(int irq, void *grp_id)
  2382. {
  2383. struct gfar_priv_grp *gfargrp = grp_id;
  2384. /* Save ievent for future reference */
  2385. u32 events = gfar_read(&gfargrp->regs->ievent);
  2386. /* Check for reception */
  2387. if (events & IEVENT_RX_MASK)
  2388. gfar_receive(irq, grp_id);
  2389. /* Check for transmit completion */
  2390. if (events & IEVENT_TX_MASK)
  2391. gfar_transmit(irq, grp_id);
  2392. /* Check for errors */
  2393. if (events & IEVENT_ERR_MASK)
  2394. gfar_error(irq, grp_id);
  2395. return IRQ_HANDLED;
  2396. }
  2397. /* Called every time the controller might need to be made
  2398. * aware of new link state. The PHY code conveys this
  2399. * information through variables in the phydev structure, and this
  2400. * function converts those variables into the appropriate
  2401. * register values, and can bring down the device if needed.
  2402. */
  2403. static void adjust_link(struct net_device *dev)
  2404. {
  2405. struct gfar_private *priv = netdev_priv(dev);
  2406. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2407. unsigned long flags;
  2408. struct phy_device *phydev = priv->phydev;
  2409. int new_state = 0;
  2410. local_irq_save(flags);
  2411. lock_tx_qs(priv);
  2412. if (phydev->link) {
  2413. u32 tempval = gfar_read(&regs->maccfg2);
  2414. u32 ecntrl = gfar_read(&regs->ecntrl);
  2415. /* Now we make sure that we can be in full duplex mode.
  2416. * If not, we operate in half-duplex mode.
  2417. */
  2418. if (phydev->duplex != priv->oldduplex) {
  2419. new_state = 1;
  2420. if (!(phydev->duplex))
  2421. tempval &= ~(MACCFG2_FULL_DUPLEX);
  2422. else
  2423. tempval |= MACCFG2_FULL_DUPLEX;
  2424. priv->oldduplex = phydev->duplex;
  2425. }
  2426. if (phydev->speed != priv->oldspeed) {
  2427. new_state = 1;
  2428. switch (phydev->speed) {
  2429. case 1000:
  2430. tempval =
  2431. ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
  2432. ecntrl &= ~(ECNTRL_R100);
  2433. break;
  2434. case 100:
  2435. case 10:
  2436. tempval =
  2437. ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
  2438. /* Reduced mode distinguishes
  2439. * between 10 and 100
  2440. */
  2441. if (phydev->speed == SPEED_100)
  2442. ecntrl |= ECNTRL_R100;
  2443. else
  2444. ecntrl &= ~(ECNTRL_R100);
  2445. break;
  2446. default:
  2447. netif_warn(priv, link, dev,
  2448. "Ack! Speed (%d) is not 10/100/1000!\n",
  2449. phydev->speed);
  2450. break;
  2451. }
  2452. priv->oldspeed = phydev->speed;
  2453. }
  2454. gfar_write(&regs->maccfg2, tempval);
  2455. gfar_write(&regs->ecntrl, ecntrl);
  2456. if (!priv->oldlink) {
  2457. new_state = 1;
  2458. priv->oldlink = 1;
  2459. }
  2460. } else if (priv->oldlink) {
  2461. new_state = 1;
  2462. priv->oldlink = 0;
  2463. priv->oldspeed = 0;
  2464. priv->oldduplex = -1;
  2465. }
  2466. if (new_state && netif_msg_link(priv))
  2467. phy_print_status(phydev);
  2468. unlock_tx_qs(priv);
  2469. local_irq_restore(flags);
  2470. }
  2471. /* Update the hash table based on the current list of multicast
  2472. * addresses we subscribe to. Also, change the promiscuity of
  2473. * the device based on the flags (this function is called
  2474. * whenever dev->flags is changed
  2475. */
  2476. static void gfar_set_multi(struct net_device *dev)
  2477. {
  2478. struct netdev_hw_addr *ha;
  2479. struct gfar_private *priv = netdev_priv(dev);
  2480. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2481. u32 tempval;
  2482. if (dev->flags & IFF_PROMISC) {
  2483. /* Set RCTRL to PROM */
  2484. tempval = gfar_read(&regs->rctrl);
  2485. tempval |= RCTRL_PROM;
  2486. gfar_write(&regs->rctrl, tempval);
  2487. } else {
  2488. /* Set RCTRL to not PROM */
  2489. tempval = gfar_read(&regs->rctrl);
  2490. tempval &= ~(RCTRL_PROM);
  2491. gfar_write(&regs->rctrl, tempval);
  2492. }
  2493. if (dev->flags & IFF_ALLMULTI) {
  2494. /* Set the hash to rx all multicast frames */
  2495. gfar_write(&regs->igaddr0, 0xffffffff);
  2496. gfar_write(&regs->igaddr1, 0xffffffff);
  2497. gfar_write(&regs->igaddr2, 0xffffffff);
  2498. gfar_write(&regs->igaddr3, 0xffffffff);
  2499. gfar_write(&regs->igaddr4, 0xffffffff);
  2500. gfar_write(&regs->igaddr5, 0xffffffff);
  2501. gfar_write(&regs->igaddr6, 0xffffffff);
  2502. gfar_write(&regs->igaddr7, 0xffffffff);
  2503. gfar_write(&regs->gaddr0, 0xffffffff);
  2504. gfar_write(&regs->gaddr1, 0xffffffff);
  2505. gfar_write(&regs->gaddr2, 0xffffffff);
  2506. gfar_write(&regs->gaddr3, 0xffffffff);
  2507. gfar_write(&regs->gaddr4, 0xffffffff);
  2508. gfar_write(&regs->gaddr5, 0xffffffff);
  2509. gfar_write(&regs->gaddr6, 0xffffffff);
  2510. gfar_write(&regs->gaddr7, 0xffffffff);
  2511. } else {
  2512. int em_num;
  2513. int idx;
  2514. /* zero out the hash */
  2515. gfar_write(&regs->igaddr0, 0x0);
  2516. gfar_write(&regs->igaddr1, 0x0);
  2517. gfar_write(&regs->igaddr2, 0x0);
  2518. gfar_write(&regs->igaddr3, 0x0);
  2519. gfar_write(&regs->igaddr4, 0x0);
  2520. gfar_write(&regs->igaddr5, 0x0);
  2521. gfar_write(&regs->igaddr6, 0x0);
  2522. gfar_write(&regs->igaddr7, 0x0);
  2523. gfar_write(&regs->gaddr0, 0x0);
  2524. gfar_write(&regs->gaddr1, 0x0);
  2525. gfar_write(&regs->gaddr2, 0x0);
  2526. gfar_write(&regs->gaddr3, 0x0);
  2527. gfar_write(&regs->gaddr4, 0x0);
  2528. gfar_write(&regs->gaddr5, 0x0);
  2529. gfar_write(&regs->gaddr6, 0x0);
  2530. gfar_write(&regs->gaddr7, 0x0);
  2531. /* If we have extended hash tables, we need to
  2532. * clear the exact match registers to prepare for
  2533. * setting them
  2534. */
  2535. if (priv->extended_hash) {
  2536. em_num = GFAR_EM_NUM + 1;
  2537. gfar_clear_exact_match(dev);
  2538. idx = 1;
  2539. } else {
  2540. idx = 0;
  2541. em_num = 0;
  2542. }
  2543. if (netdev_mc_empty(dev))
  2544. return;
  2545. /* Parse the list, and set the appropriate bits */
  2546. netdev_for_each_mc_addr(ha, dev) {
  2547. if (idx < em_num) {
  2548. gfar_set_mac_for_addr(dev, idx, ha->addr);
  2549. idx++;
  2550. } else
  2551. gfar_set_hash_for_addr(dev, ha->addr);
  2552. }
  2553. }
  2554. }
  2555. /* Clears each of the exact match registers to zero, so they
  2556. * don't interfere with normal reception
  2557. */
  2558. static void gfar_clear_exact_match(struct net_device *dev)
  2559. {
  2560. int idx;
  2561. static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2562. for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
  2563. gfar_set_mac_for_addr(dev, idx, zero_arr);
  2564. }
  2565. /* Set the appropriate hash bit for the given addr */
  2566. /* The algorithm works like so:
  2567. * 1) Take the Destination Address (ie the multicast address), and
  2568. * do a CRC on it (little endian), and reverse the bits of the
  2569. * result.
  2570. * 2) Use the 8 most significant bits as a hash into a 256-entry
  2571. * table. The table is controlled through 8 32-bit registers:
  2572. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  2573. * gaddr7. This means that the 3 most significant bits in the
  2574. * hash index which gaddr register to use, and the 5 other bits
  2575. * indicate which bit (assuming an IBM numbering scheme, which
  2576. * for PowerPC (tm) is usually the case) in the register holds
  2577. * the entry.
  2578. */
  2579. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
  2580. {
  2581. u32 tempval;
  2582. struct gfar_private *priv = netdev_priv(dev);
  2583. u32 result = ether_crc(ETH_ALEN, addr);
  2584. int width = priv->hash_width;
  2585. u8 whichbit = (result >> (32 - width)) & 0x1f;
  2586. u8 whichreg = result >> (32 - width + 5);
  2587. u32 value = (1 << (31-whichbit));
  2588. tempval = gfar_read(priv->hash_regs[whichreg]);
  2589. tempval |= value;
  2590. gfar_write(priv->hash_regs[whichreg], tempval);
  2591. }
  2592. /* There are multiple MAC Address register pairs on some controllers
  2593. * This function sets the numth pair to a given address
  2594. */
  2595. static void gfar_set_mac_for_addr(struct net_device *dev, int num,
  2596. const u8 *addr)
  2597. {
  2598. struct gfar_private *priv = netdev_priv(dev);
  2599. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2600. int idx;
  2601. char tmpbuf[ETH_ALEN];
  2602. u32 tempval;
  2603. u32 __iomem *macptr = &regs->macstnaddr1;
  2604. macptr += num*2;
  2605. /* Now copy it into the mac registers backwards, cuz
  2606. * little endian is silly
  2607. */
  2608. for (idx = 0; idx < ETH_ALEN; idx++)
  2609. tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
  2610. gfar_write(macptr, *((u32 *) (tmpbuf)));
  2611. tempval = *((u32 *) (tmpbuf + 4));
  2612. gfar_write(macptr+1, tempval);
  2613. }
  2614. /* GFAR error interrupt handler */
  2615. static irqreturn_t gfar_error(int irq, void *grp_id)
  2616. {
  2617. struct gfar_priv_grp *gfargrp = grp_id;
  2618. struct gfar __iomem *regs = gfargrp->regs;
  2619. struct gfar_private *priv= gfargrp->priv;
  2620. struct net_device *dev = priv->ndev;
  2621. /* Save ievent for future reference */
  2622. u32 events = gfar_read(&regs->ievent);
  2623. /* Clear IEVENT */
  2624. gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
  2625. /* Magic Packet is not an error. */
  2626. if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
  2627. (events & IEVENT_MAG))
  2628. events &= ~IEVENT_MAG;
  2629. /* Hmm... */
  2630. if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
  2631. netdev_dbg(dev,
  2632. "error interrupt (ievent=0x%08x imask=0x%08x)\n",
  2633. events, gfar_read(&regs->imask));
  2634. /* Update the error counters */
  2635. if (events & IEVENT_TXE) {
  2636. dev->stats.tx_errors++;
  2637. if (events & IEVENT_LC)
  2638. dev->stats.tx_window_errors++;
  2639. if (events & IEVENT_CRL)
  2640. dev->stats.tx_aborted_errors++;
  2641. if (events & IEVENT_XFUN) {
  2642. unsigned long flags;
  2643. netif_dbg(priv, tx_err, dev,
  2644. "TX FIFO underrun, packet dropped\n");
  2645. dev->stats.tx_dropped++;
  2646. priv->extra_stats.tx_underrun++;
  2647. local_irq_save(flags);
  2648. lock_tx_qs(priv);
  2649. /* Reactivate the Tx Queues */
  2650. gfar_write(&regs->tstat, gfargrp->tstat);
  2651. unlock_tx_qs(priv);
  2652. local_irq_restore(flags);
  2653. }
  2654. netif_dbg(priv, tx_err, dev, "Transmit Error\n");
  2655. }
  2656. if (events & IEVENT_BSY) {
  2657. dev->stats.rx_errors++;
  2658. priv->extra_stats.rx_bsy++;
  2659. gfar_receive(irq, grp_id);
  2660. netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
  2661. gfar_read(&regs->rstat));
  2662. }
  2663. if (events & IEVENT_BABR) {
  2664. dev->stats.rx_errors++;
  2665. priv->extra_stats.rx_babr++;
  2666. netif_dbg(priv, rx_err, dev, "babbling RX error\n");
  2667. }
  2668. if (events & IEVENT_EBERR) {
  2669. priv->extra_stats.eberr++;
  2670. netif_dbg(priv, rx_err, dev, "bus error\n");
  2671. }
  2672. if (events & IEVENT_RXC)
  2673. netif_dbg(priv, rx_status, dev, "control frame\n");
  2674. if (events & IEVENT_BABT) {
  2675. priv->extra_stats.tx_babt++;
  2676. netif_dbg(priv, tx_err, dev, "babbling TX error\n");
  2677. }
  2678. return IRQ_HANDLED;
  2679. }
  2680. static struct of_device_id gfar_match[] =
  2681. {
  2682. {
  2683. .type = "network",
  2684. .compatible = "gianfar",
  2685. },
  2686. {
  2687. .compatible = "fsl,etsec2",
  2688. },
  2689. {},
  2690. };
  2691. MODULE_DEVICE_TABLE(of, gfar_match);
  2692. /* Structure for a device driver */
  2693. static struct platform_driver gfar_driver = {
  2694. .driver = {
  2695. .name = "fsl-gianfar",
  2696. .owner = THIS_MODULE,
  2697. .pm = GFAR_PM_OPS,
  2698. .of_match_table = gfar_match,
  2699. },
  2700. .probe = gfar_probe,
  2701. .remove = gfar_remove,
  2702. };
  2703. module_platform_driver(gfar_driver);