fec.c 49 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * Right now, I am very wasteful with the buffers. I allocate memory
  6. * pages and then divide them into 2K frame buffers. This way I know I
  7. * have buffers large enough to hold one frame within one buffer descriptor.
  8. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  9. * will be much more memory efficient and will easily handle lots of
  10. * small packets.
  11. *
  12. * Much better multiple PHY support by Magnus Damm.
  13. * Copyright (c) 2000 Ericsson Radio Systems AB.
  14. *
  15. * Support for FEC controller of ColdFire processors.
  16. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  17. *
  18. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  19. * Copyright (c) 2004-2006 Macq Electronique SA.
  20. *
  21. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/string.h>
  26. #include <linux/ptrace.h>
  27. #include <linux/errno.h>
  28. #include <linux/ioport.h>
  29. #include <linux/slab.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/pci.h>
  32. #include <linux/init.h>
  33. #include <linux/delay.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/etherdevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/bitops.h>
  40. #include <linux/io.h>
  41. #include <linux/irq.h>
  42. #include <linux/clk.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/phy.h>
  45. #include <linux/fec.h>
  46. #include <linux/of.h>
  47. #include <linux/of_device.h>
  48. #include <linux/of_gpio.h>
  49. #include <linux/of_net.h>
  50. #include <linux/pinctrl/consumer.h>
  51. #include <linux/regulator/consumer.h>
  52. #include <asm/cacheflush.h>
  53. #ifndef CONFIG_ARM
  54. #include <asm/coldfire.h>
  55. #include <asm/mcfsim.h>
  56. #endif
  57. #include "fec.h"
  58. #if defined(CONFIG_ARM)
  59. #define FEC_ALIGNMENT 0xf
  60. #else
  61. #define FEC_ALIGNMENT 0x3
  62. #endif
  63. #define DRIVER_NAME "fec"
  64. /* Pause frame feild and FIFO threshold */
  65. #define FEC_ENET_FCE (1 << 5)
  66. #define FEC_ENET_RSEM_V 0x84
  67. #define FEC_ENET_RSFL_V 16
  68. #define FEC_ENET_RAEM_V 0x8
  69. #define FEC_ENET_RAFL_V 0x8
  70. #define FEC_ENET_OPD_V 0xFFF0
  71. /* Controller is ENET-MAC */
  72. #define FEC_QUIRK_ENET_MAC (1 << 0)
  73. /* Controller needs driver to swap frame */
  74. #define FEC_QUIRK_SWAP_FRAME (1 << 1)
  75. /* Controller uses gasket */
  76. #define FEC_QUIRK_USE_GASKET (1 << 2)
  77. /* Controller has GBIT support */
  78. #define FEC_QUIRK_HAS_GBIT (1 << 3)
  79. /* Controller has extend desc buffer */
  80. #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
  81. static struct platform_device_id fec_devtype[] = {
  82. {
  83. /* keep it for coldfire */
  84. .name = DRIVER_NAME,
  85. .driver_data = 0,
  86. }, {
  87. .name = "imx25-fec",
  88. .driver_data = FEC_QUIRK_USE_GASKET,
  89. }, {
  90. .name = "imx27-fec",
  91. .driver_data = 0,
  92. }, {
  93. .name = "imx28-fec",
  94. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
  95. }, {
  96. .name = "imx6q-fec",
  97. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
  98. FEC_QUIRK_HAS_BUFDESC_EX,
  99. }, {
  100. /* sentinel */
  101. }
  102. };
  103. MODULE_DEVICE_TABLE(platform, fec_devtype);
  104. enum imx_fec_type {
  105. IMX25_FEC = 1, /* runs on i.mx25/50/53 */
  106. IMX27_FEC, /* runs on i.mx27/35/51 */
  107. IMX28_FEC,
  108. IMX6Q_FEC,
  109. };
  110. static const struct of_device_id fec_dt_ids[] = {
  111. { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
  112. { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
  113. { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
  114. { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
  115. { /* sentinel */ }
  116. };
  117. MODULE_DEVICE_TABLE(of, fec_dt_ids);
  118. static unsigned char macaddr[ETH_ALEN];
  119. module_param_array(macaddr, byte, NULL, 0);
  120. MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
  121. #if defined(CONFIG_M5272)
  122. /*
  123. * Some hardware gets it MAC address out of local flash memory.
  124. * if this is non-zero then assume it is the address to get MAC from.
  125. */
  126. #if defined(CONFIG_NETtel)
  127. #define FEC_FLASHMAC 0xf0006006
  128. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  129. #define FEC_FLASHMAC 0xf0006000
  130. #elif defined(CONFIG_CANCam)
  131. #define FEC_FLASHMAC 0xf0020000
  132. #elif defined (CONFIG_M5272C3)
  133. #define FEC_FLASHMAC (0xffe04000 + 4)
  134. #elif defined(CONFIG_MOD5272)
  135. #define FEC_FLASHMAC 0xffc0406b
  136. #else
  137. #define FEC_FLASHMAC 0
  138. #endif
  139. #endif /* CONFIG_M5272 */
  140. #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
  141. #error "FEC: descriptor ring size constants too large"
  142. #endif
  143. /* Interrupt events/masks. */
  144. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  145. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  146. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  147. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  148. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  149. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  150. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  151. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  152. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  153. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  154. #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
  155. /* The FEC stores dest/src/type, data, and checksum for receive packets.
  156. */
  157. #define PKT_MAXBUF_SIZE 1518
  158. #define PKT_MINBUF_SIZE 64
  159. #define PKT_MAXBLR_SIZE 1520
  160. /*
  161. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  162. * size bits. Other FEC hardware does not, so we need to take that into
  163. * account when setting it.
  164. */
  165. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  166. defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
  167. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  168. #else
  169. #define OPT_FRAME_SIZE 0
  170. #endif
  171. /* FEC MII MMFR bits definition */
  172. #define FEC_MMFR_ST (1 << 30)
  173. #define FEC_MMFR_OP_READ (2 << 28)
  174. #define FEC_MMFR_OP_WRITE (1 << 28)
  175. #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
  176. #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
  177. #define FEC_MMFR_TA (2 << 16)
  178. #define FEC_MMFR_DATA(v) (v & 0xffff)
  179. #define FEC_MII_TIMEOUT 30000 /* us */
  180. /* Transmitter timeout */
  181. #define TX_TIMEOUT (2 * HZ)
  182. #define FEC_PAUSE_FLAG_AUTONEG 0x1
  183. #define FEC_PAUSE_FLAG_ENABLE 0x2
  184. static int mii_cnt;
  185. static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
  186. {
  187. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  188. if (is_ex)
  189. return (struct bufdesc *)(ex + 1);
  190. else
  191. return bdp + 1;
  192. }
  193. static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
  194. {
  195. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  196. if (is_ex)
  197. return (struct bufdesc *)(ex - 1);
  198. else
  199. return bdp - 1;
  200. }
  201. static void *swap_buffer(void *bufaddr, int len)
  202. {
  203. int i;
  204. unsigned int *buf = bufaddr;
  205. for (i = 0; i < (len + 3) / 4; i++, buf++)
  206. *buf = cpu_to_be32(*buf);
  207. return bufaddr;
  208. }
  209. static netdev_tx_t
  210. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  211. {
  212. struct fec_enet_private *fep = netdev_priv(ndev);
  213. const struct platform_device_id *id_entry =
  214. platform_get_device_id(fep->pdev);
  215. struct bufdesc *bdp;
  216. void *bufaddr;
  217. unsigned short status;
  218. unsigned long flags;
  219. if (!fep->link) {
  220. /* Link is down or autonegotiation is in progress. */
  221. return NETDEV_TX_BUSY;
  222. }
  223. spin_lock_irqsave(&fep->hw_lock, flags);
  224. /* Fill in a Tx ring entry */
  225. bdp = fep->cur_tx;
  226. status = bdp->cbd_sc;
  227. if (status & BD_ENET_TX_READY) {
  228. /* Ooops. All transmit buffers are full. Bail out.
  229. * This should not happen, since ndev->tbusy should be set.
  230. */
  231. printk("%s: tx queue full!.\n", ndev->name);
  232. spin_unlock_irqrestore(&fep->hw_lock, flags);
  233. return NETDEV_TX_BUSY;
  234. }
  235. /* Clear all of the status flags */
  236. status &= ~BD_ENET_TX_STATS;
  237. /* Set buffer length and buffer pointer */
  238. bufaddr = skb->data;
  239. bdp->cbd_datlen = skb->len;
  240. /*
  241. * On some FEC implementations data must be aligned on
  242. * 4-byte boundaries. Use bounce buffers to copy data
  243. * and get it aligned. Ugh.
  244. */
  245. if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
  246. unsigned int index;
  247. if (fep->bufdesc_ex)
  248. index = (struct bufdesc_ex *)bdp -
  249. (struct bufdesc_ex *)fep->tx_bd_base;
  250. else
  251. index = bdp - fep->tx_bd_base;
  252. memcpy(fep->tx_bounce[index], skb->data, skb->len);
  253. bufaddr = fep->tx_bounce[index];
  254. }
  255. /*
  256. * Some design made an incorrect assumption on endian mode of
  257. * the system that it's running on. As the result, driver has to
  258. * swap every frame going to and coming from the controller.
  259. */
  260. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  261. swap_buffer(bufaddr, skb->len);
  262. /* Save skb pointer */
  263. fep->tx_skbuff[fep->skb_cur] = skb;
  264. ndev->stats.tx_bytes += skb->len;
  265. fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
  266. /* Push the data cache so the CPM does not get stale memory
  267. * data.
  268. */
  269. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
  270. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  271. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  272. * it's the last BD of the frame, and to put the CRC on the end.
  273. */
  274. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  275. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  276. bdp->cbd_sc = status;
  277. if (fep->bufdesc_ex) {
  278. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  279. ebdp->cbd_bdu = 0;
  280. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  281. fep->hwts_tx_en)) {
  282. ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
  283. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  284. } else {
  285. ebdp->cbd_esc = BD_ENET_TX_INT;
  286. }
  287. }
  288. /* Trigger transmission start */
  289. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  290. /* If this was the last BD in the ring, start at the beginning again. */
  291. if (status & BD_ENET_TX_WRAP)
  292. bdp = fep->tx_bd_base;
  293. else
  294. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  295. if (bdp == fep->dirty_tx) {
  296. fep->tx_full = 1;
  297. netif_stop_queue(ndev);
  298. }
  299. fep->cur_tx = bdp;
  300. skb_tx_timestamp(skb);
  301. spin_unlock_irqrestore(&fep->hw_lock, flags);
  302. return NETDEV_TX_OK;
  303. }
  304. /* This function is called to start or restart the FEC during a link
  305. * change. This only happens when switching between half and full
  306. * duplex.
  307. */
  308. static void
  309. fec_restart(struct net_device *ndev, int duplex)
  310. {
  311. struct fec_enet_private *fep = netdev_priv(ndev);
  312. const struct platform_device_id *id_entry =
  313. platform_get_device_id(fep->pdev);
  314. int i;
  315. u32 temp_mac[2];
  316. u32 rcntl = OPT_FRAME_SIZE | 0x04;
  317. u32 ecntl = 0x2; /* ETHEREN */
  318. /* Whack a reset. We should wait for this. */
  319. writel(1, fep->hwp + FEC_ECNTRL);
  320. udelay(10);
  321. /*
  322. * enet-mac reset will reset mac address registers too,
  323. * so need to reconfigure it.
  324. */
  325. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  326. memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
  327. writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
  328. writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
  329. }
  330. /* Clear any outstanding interrupt. */
  331. writel(0xffc00000, fep->hwp + FEC_IEVENT);
  332. /* Reset all multicast. */
  333. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  334. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  335. #ifndef CONFIG_M5272
  336. writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
  337. writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
  338. #endif
  339. /* Set maximum receive buffer size. */
  340. writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  341. /* Set receive and transmit descriptor base. */
  342. writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
  343. if (fep->bufdesc_ex)
  344. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
  345. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  346. else
  347. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
  348. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  349. fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
  350. fep->cur_rx = fep->rx_bd_base;
  351. /* Reset SKB transmit buffers. */
  352. fep->skb_cur = fep->skb_dirty = 0;
  353. for (i = 0; i <= TX_RING_MOD_MASK; i++) {
  354. if (fep->tx_skbuff[i]) {
  355. dev_kfree_skb_any(fep->tx_skbuff[i]);
  356. fep->tx_skbuff[i] = NULL;
  357. }
  358. }
  359. /* Enable MII mode */
  360. if (duplex) {
  361. /* FD enable */
  362. writel(0x04, fep->hwp + FEC_X_CNTRL);
  363. } else {
  364. /* No Rcv on Xmit */
  365. rcntl |= 0x02;
  366. writel(0x0, fep->hwp + FEC_X_CNTRL);
  367. }
  368. fep->full_duplex = duplex;
  369. /* Set MII speed */
  370. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  371. /*
  372. * The phy interface and speed need to get configured
  373. * differently on enet-mac.
  374. */
  375. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  376. /* Enable flow control and length check */
  377. rcntl |= 0x40000000 | 0x00000020;
  378. /* RGMII, RMII or MII */
  379. if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
  380. rcntl |= (1 << 6);
  381. else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  382. rcntl |= (1 << 8);
  383. else
  384. rcntl &= ~(1 << 8);
  385. /* 1G, 100M or 10M */
  386. if (fep->phy_dev) {
  387. if (fep->phy_dev->speed == SPEED_1000)
  388. ecntl |= (1 << 5);
  389. else if (fep->phy_dev->speed == SPEED_100)
  390. rcntl &= ~(1 << 9);
  391. else
  392. rcntl |= (1 << 9);
  393. }
  394. } else {
  395. #ifdef FEC_MIIGSK_ENR
  396. if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
  397. u32 cfgr;
  398. /* disable the gasket and wait */
  399. writel(0, fep->hwp + FEC_MIIGSK_ENR);
  400. while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
  401. udelay(1);
  402. /*
  403. * configure the gasket:
  404. * RMII, 50 MHz, no loopback, no echo
  405. * MII, 25 MHz, no loopback, no echo
  406. */
  407. cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  408. ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
  409. if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
  410. cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
  411. writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
  412. /* re-enable the gasket */
  413. writel(2, fep->hwp + FEC_MIIGSK_ENR);
  414. }
  415. #endif
  416. }
  417. /* enable pause frame*/
  418. if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
  419. ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
  420. fep->phy_dev && fep->phy_dev->pause)) {
  421. rcntl |= FEC_ENET_FCE;
  422. /* set FIFO thresh hold parameter to reduce overrun */
  423. writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
  424. writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
  425. writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
  426. writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
  427. /* OPD */
  428. writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
  429. } else {
  430. rcntl &= ~FEC_ENET_FCE;
  431. }
  432. writel(rcntl, fep->hwp + FEC_R_CNTRL);
  433. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  434. /* enable ENET endian swap */
  435. ecntl |= (1 << 8);
  436. /* enable ENET store and forward mode */
  437. writel(1 << 8, fep->hwp + FEC_X_WMRK);
  438. }
  439. if (fep->bufdesc_ex)
  440. ecntl |= (1 << 4);
  441. /* And last, enable the transmit and receive processing */
  442. writel(ecntl, fep->hwp + FEC_ECNTRL);
  443. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  444. if (fep->bufdesc_ex)
  445. fec_ptp_start_cyclecounter(ndev);
  446. /* Enable interrupts we wish to service */
  447. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  448. }
  449. static void
  450. fec_stop(struct net_device *ndev)
  451. {
  452. struct fec_enet_private *fep = netdev_priv(ndev);
  453. const struct platform_device_id *id_entry =
  454. platform_get_device_id(fep->pdev);
  455. u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
  456. /* We cannot expect a graceful transmit stop without link !!! */
  457. if (fep->link) {
  458. writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
  459. udelay(10);
  460. if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
  461. printk("fec_stop : Graceful transmit stop did not complete !\n");
  462. }
  463. /* Whack a reset. We should wait for this. */
  464. writel(1, fep->hwp + FEC_ECNTRL);
  465. udelay(10);
  466. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  467. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  468. /* We have to keep ENET enabled to have MII interrupt stay working */
  469. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  470. writel(2, fep->hwp + FEC_ECNTRL);
  471. writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
  472. }
  473. }
  474. static void
  475. fec_timeout(struct net_device *ndev)
  476. {
  477. struct fec_enet_private *fep = netdev_priv(ndev);
  478. ndev->stats.tx_errors++;
  479. fec_restart(ndev, fep->full_duplex);
  480. netif_wake_queue(ndev);
  481. }
  482. static void
  483. fec_enet_tx(struct net_device *ndev)
  484. {
  485. struct fec_enet_private *fep;
  486. struct bufdesc *bdp;
  487. unsigned short status;
  488. struct sk_buff *skb;
  489. fep = netdev_priv(ndev);
  490. spin_lock(&fep->hw_lock);
  491. bdp = fep->dirty_tx;
  492. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  493. if (bdp == fep->cur_tx && fep->tx_full == 0)
  494. break;
  495. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  496. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  497. bdp->cbd_bufaddr = 0;
  498. skb = fep->tx_skbuff[fep->skb_dirty];
  499. /* Check for errors. */
  500. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  501. BD_ENET_TX_RL | BD_ENET_TX_UN |
  502. BD_ENET_TX_CSL)) {
  503. ndev->stats.tx_errors++;
  504. if (status & BD_ENET_TX_HB) /* No heartbeat */
  505. ndev->stats.tx_heartbeat_errors++;
  506. if (status & BD_ENET_TX_LC) /* Late collision */
  507. ndev->stats.tx_window_errors++;
  508. if (status & BD_ENET_TX_RL) /* Retrans limit */
  509. ndev->stats.tx_aborted_errors++;
  510. if (status & BD_ENET_TX_UN) /* Underrun */
  511. ndev->stats.tx_fifo_errors++;
  512. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  513. ndev->stats.tx_carrier_errors++;
  514. } else {
  515. ndev->stats.tx_packets++;
  516. }
  517. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
  518. fep->bufdesc_ex) {
  519. struct skb_shared_hwtstamps shhwtstamps;
  520. unsigned long flags;
  521. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  522. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  523. spin_lock_irqsave(&fep->tmreg_lock, flags);
  524. shhwtstamps.hwtstamp = ns_to_ktime(
  525. timecounter_cyc2time(&fep->tc, ebdp->ts));
  526. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  527. skb_tstamp_tx(skb, &shhwtstamps);
  528. }
  529. if (status & BD_ENET_TX_READY)
  530. printk("HEY! Enet xmit interrupt and TX_READY.\n");
  531. /* Deferred means some collisions occurred during transmit,
  532. * but we eventually sent the packet OK.
  533. */
  534. if (status & BD_ENET_TX_DEF)
  535. ndev->stats.collisions++;
  536. /* Free the sk buffer associated with this last transmit */
  537. dev_kfree_skb_any(skb);
  538. fep->tx_skbuff[fep->skb_dirty] = NULL;
  539. fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
  540. /* Update pointer to next buffer descriptor to be transmitted */
  541. if (status & BD_ENET_TX_WRAP)
  542. bdp = fep->tx_bd_base;
  543. else
  544. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  545. /* Since we have freed up a buffer, the ring is no longer full
  546. */
  547. if (fep->tx_full) {
  548. fep->tx_full = 0;
  549. if (netif_queue_stopped(ndev))
  550. netif_wake_queue(ndev);
  551. }
  552. }
  553. fep->dirty_tx = bdp;
  554. spin_unlock(&fep->hw_lock);
  555. }
  556. /* During a receive, the cur_rx points to the current incoming buffer.
  557. * When we update through the ring, if the next incoming buffer has
  558. * not been given to the system, we just set the empty indicator,
  559. * effectively tossing the packet.
  560. */
  561. static void
  562. fec_enet_rx(struct net_device *ndev)
  563. {
  564. struct fec_enet_private *fep = netdev_priv(ndev);
  565. const struct platform_device_id *id_entry =
  566. platform_get_device_id(fep->pdev);
  567. struct bufdesc *bdp;
  568. unsigned short status;
  569. struct sk_buff *skb;
  570. ushort pkt_len;
  571. __u8 *data;
  572. #ifdef CONFIG_M532x
  573. flush_cache_all();
  574. #endif
  575. spin_lock(&fep->hw_lock);
  576. /* First, grab all of the stats for the incoming packet.
  577. * These get messed up if we get called due to a busy condition.
  578. */
  579. bdp = fep->cur_rx;
  580. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  581. /* Since we have allocated space to hold a complete frame,
  582. * the last indicator should be set.
  583. */
  584. if ((status & BD_ENET_RX_LAST) == 0)
  585. printk("FEC ENET: rcv is not +last\n");
  586. if (!fep->opened)
  587. goto rx_processing_done;
  588. /* Check for errors. */
  589. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  590. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  591. ndev->stats.rx_errors++;
  592. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  593. /* Frame too long or too short. */
  594. ndev->stats.rx_length_errors++;
  595. }
  596. if (status & BD_ENET_RX_NO) /* Frame alignment */
  597. ndev->stats.rx_frame_errors++;
  598. if (status & BD_ENET_RX_CR) /* CRC Error */
  599. ndev->stats.rx_crc_errors++;
  600. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  601. ndev->stats.rx_fifo_errors++;
  602. }
  603. /* Report late collisions as a frame error.
  604. * On this error, the BD is closed, but we don't know what we
  605. * have in the buffer. So, just drop this frame on the floor.
  606. */
  607. if (status & BD_ENET_RX_CL) {
  608. ndev->stats.rx_errors++;
  609. ndev->stats.rx_frame_errors++;
  610. goto rx_processing_done;
  611. }
  612. /* Process the incoming frame. */
  613. ndev->stats.rx_packets++;
  614. pkt_len = bdp->cbd_datlen;
  615. ndev->stats.rx_bytes += pkt_len;
  616. data = (__u8*)__va(bdp->cbd_bufaddr);
  617. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  618. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  619. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  620. swap_buffer(data, pkt_len);
  621. /* This does 16 byte alignment, exactly what we need.
  622. * The packet length includes FCS, but we don't want to
  623. * include that when passing upstream as it messes up
  624. * bridging applications.
  625. */
  626. skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
  627. if (unlikely(!skb)) {
  628. printk("%s: Memory squeeze, dropping packet.\n",
  629. ndev->name);
  630. ndev->stats.rx_dropped++;
  631. } else {
  632. skb_reserve(skb, NET_IP_ALIGN);
  633. skb_put(skb, pkt_len - 4); /* Make room */
  634. skb_copy_to_linear_data(skb, data, pkt_len - 4);
  635. skb->protocol = eth_type_trans(skb, ndev);
  636. /* Get receive timestamp from the skb */
  637. if (fep->hwts_rx_en && fep->bufdesc_ex) {
  638. struct skb_shared_hwtstamps *shhwtstamps =
  639. skb_hwtstamps(skb);
  640. unsigned long flags;
  641. struct bufdesc_ex *ebdp =
  642. (struct bufdesc_ex *)bdp;
  643. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  644. spin_lock_irqsave(&fep->tmreg_lock, flags);
  645. shhwtstamps->hwtstamp = ns_to_ktime(
  646. timecounter_cyc2time(&fep->tc, ebdp->ts));
  647. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  648. }
  649. if (!skb_defer_rx_timestamp(skb))
  650. netif_rx(skb);
  651. }
  652. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
  653. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  654. rx_processing_done:
  655. /* Clear the status flags for this buffer */
  656. status &= ~BD_ENET_RX_STATS;
  657. /* Mark the buffer empty */
  658. status |= BD_ENET_RX_EMPTY;
  659. bdp->cbd_sc = status;
  660. if (fep->bufdesc_ex) {
  661. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  662. ebdp->cbd_esc = BD_ENET_RX_INT;
  663. ebdp->cbd_prot = 0;
  664. ebdp->cbd_bdu = 0;
  665. }
  666. /* Update BD pointer to next entry */
  667. if (status & BD_ENET_RX_WRAP)
  668. bdp = fep->rx_bd_base;
  669. else
  670. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  671. /* Doing this here will keep the FEC running while we process
  672. * incoming frames. On a heavily loaded network, we should be
  673. * able to keep up at the expense of system resources.
  674. */
  675. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  676. }
  677. fep->cur_rx = bdp;
  678. spin_unlock(&fep->hw_lock);
  679. }
  680. static irqreturn_t
  681. fec_enet_interrupt(int irq, void *dev_id)
  682. {
  683. struct net_device *ndev = dev_id;
  684. struct fec_enet_private *fep = netdev_priv(ndev);
  685. uint int_events;
  686. irqreturn_t ret = IRQ_NONE;
  687. do {
  688. int_events = readl(fep->hwp + FEC_IEVENT);
  689. writel(int_events, fep->hwp + FEC_IEVENT);
  690. if (int_events & FEC_ENET_RXF) {
  691. ret = IRQ_HANDLED;
  692. fec_enet_rx(ndev);
  693. }
  694. /* Transmit OK, or non-fatal error. Update the buffer
  695. * descriptors. FEC handles all errors, we just discover
  696. * them as part of the transmit process.
  697. */
  698. if (int_events & FEC_ENET_TXF) {
  699. ret = IRQ_HANDLED;
  700. fec_enet_tx(ndev);
  701. }
  702. if (int_events & FEC_ENET_MII) {
  703. ret = IRQ_HANDLED;
  704. complete(&fep->mdio_done);
  705. }
  706. } while (int_events);
  707. return ret;
  708. }
  709. /* ------------------------------------------------------------------------- */
  710. static void fec_get_mac(struct net_device *ndev)
  711. {
  712. struct fec_enet_private *fep = netdev_priv(ndev);
  713. struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
  714. unsigned char *iap, tmpaddr[ETH_ALEN];
  715. /*
  716. * try to get mac address in following order:
  717. *
  718. * 1) module parameter via kernel command line in form
  719. * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
  720. */
  721. iap = macaddr;
  722. #ifdef CONFIG_OF
  723. /*
  724. * 2) from device tree data
  725. */
  726. if (!is_valid_ether_addr(iap)) {
  727. struct device_node *np = fep->pdev->dev.of_node;
  728. if (np) {
  729. const char *mac = of_get_mac_address(np);
  730. if (mac)
  731. iap = (unsigned char *) mac;
  732. }
  733. }
  734. #endif
  735. /*
  736. * 3) from flash or fuse (via platform data)
  737. */
  738. if (!is_valid_ether_addr(iap)) {
  739. #ifdef CONFIG_M5272
  740. if (FEC_FLASHMAC)
  741. iap = (unsigned char *)FEC_FLASHMAC;
  742. #else
  743. if (pdata)
  744. iap = (unsigned char *)&pdata->mac;
  745. #endif
  746. }
  747. /*
  748. * 4) FEC mac registers set by bootloader
  749. */
  750. if (!is_valid_ether_addr(iap)) {
  751. *((unsigned long *) &tmpaddr[0]) =
  752. be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
  753. *((unsigned short *) &tmpaddr[4]) =
  754. be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
  755. iap = &tmpaddr[0];
  756. }
  757. memcpy(ndev->dev_addr, iap, ETH_ALEN);
  758. /* Adjust MAC if using macaddr */
  759. if (iap == macaddr)
  760. ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
  761. }
  762. /* ------------------------------------------------------------------------- */
  763. /*
  764. * Phy section
  765. */
  766. static void fec_enet_adjust_link(struct net_device *ndev)
  767. {
  768. struct fec_enet_private *fep = netdev_priv(ndev);
  769. struct phy_device *phy_dev = fep->phy_dev;
  770. unsigned long flags;
  771. int status_change = 0;
  772. spin_lock_irqsave(&fep->hw_lock, flags);
  773. /* Prevent a state halted on mii error */
  774. if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
  775. phy_dev->state = PHY_RESUMING;
  776. goto spin_unlock;
  777. }
  778. /* Duplex link change */
  779. if (phy_dev->link) {
  780. if (fep->full_duplex != phy_dev->duplex) {
  781. fec_restart(ndev, phy_dev->duplex);
  782. /* prevent unnecessary second fec_restart() below */
  783. fep->link = phy_dev->link;
  784. status_change = 1;
  785. }
  786. }
  787. /* Link on or off change */
  788. if (phy_dev->link != fep->link) {
  789. fep->link = phy_dev->link;
  790. if (phy_dev->link)
  791. fec_restart(ndev, phy_dev->duplex);
  792. else
  793. fec_stop(ndev);
  794. status_change = 1;
  795. }
  796. spin_unlock:
  797. spin_unlock_irqrestore(&fep->hw_lock, flags);
  798. if (status_change)
  799. phy_print_status(phy_dev);
  800. }
  801. static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  802. {
  803. struct fec_enet_private *fep = bus->priv;
  804. unsigned long time_left;
  805. fep->mii_timeout = 0;
  806. init_completion(&fep->mdio_done);
  807. /* start a read op */
  808. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  809. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  810. FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
  811. /* wait for end of transfer */
  812. time_left = wait_for_completion_timeout(&fep->mdio_done,
  813. usecs_to_jiffies(FEC_MII_TIMEOUT));
  814. if (time_left == 0) {
  815. fep->mii_timeout = 1;
  816. printk(KERN_ERR "FEC: MDIO read timeout\n");
  817. return -ETIMEDOUT;
  818. }
  819. /* return value */
  820. return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
  821. }
  822. static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  823. u16 value)
  824. {
  825. struct fec_enet_private *fep = bus->priv;
  826. unsigned long time_left;
  827. fep->mii_timeout = 0;
  828. init_completion(&fep->mdio_done);
  829. /* start a write op */
  830. writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
  831. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  832. FEC_MMFR_TA | FEC_MMFR_DATA(value),
  833. fep->hwp + FEC_MII_DATA);
  834. /* wait for end of transfer */
  835. time_left = wait_for_completion_timeout(&fep->mdio_done,
  836. usecs_to_jiffies(FEC_MII_TIMEOUT));
  837. if (time_left == 0) {
  838. fep->mii_timeout = 1;
  839. printk(KERN_ERR "FEC: MDIO write timeout\n");
  840. return -ETIMEDOUT;
  841. }
  842. return 0;
  843. }
  844. static int fec_enet_mdio_reset(struct mii_bus *bus)
  845. {
  846. return 0;
  847. }
  848. static int fec_enet_mii_probe(struct net_device *ndev)
  849. {
  850. struct fec_enet_private *fep = netdev_priv(ndev);
  851. const struct platform_device_id *id_entry =
  852. platform_get_device_id(fep->pdev);
  853. struct phy_device *phy_dev = NULL;
  854. char mdio_bus_id[MII_BUS_ID_SIZE];
  855. char phy_name[MII_BUS_ID_SIZE + 3];
  856. int phy_id;
  857. int dev_id = fep->dev_id;
  858. fep->phy_dev = NULL;
  859. /* check for attached phy */
  860. for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
  861. if ((fep->mii_bus->phy_mask & (1 << phy_id)))
  862. continue;
  863. if (fep->mii_bus->phy_map[phy_id] == NULL)
  864. continue;
  865. if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
  866. continue;
  867. if (dev_id--)
  868. continue;
  869. strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
  870. break;
  871. }
  872. if (phy_id >= PHY_MAX_ADDR) {
  873. printk(KERN_INFO
  874. "%s: no PHY, assuming direct connection to switch\n",
  875. ndev->name);
  876. strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
  877. phy_id = 0;
  878. }
  879. snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
  880. phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
  881. fep->phy_interface);
  882. if (IS_ERR(phy_dev)) {
  883. printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
  884. return PTR_ERR(phy_dev);
  885. }
  886. /* mask with MAC supported features */
  887. if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
  888. phy_dev->supported &= PHY_GBIT_FEATURES;
  889. phy_dev->supported |= SUPPORTED_Pause;
  890. }
  891. else
  892. phy_dev->supported &= PHY_BASIC_FEATURES;
  893. phy_dev->advertising = phy_dev->supported;
  894. fep->phy_dev = phy_dev;
  895. fep->link = 0;
  896. fep->full_duplex = 0;
  897. printk(KERN_INFO
  898. "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  899. ndev->name,
  900. fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
  901. fep->phy_dev->irq);
  902. return 0;
  903. }
  904. static int fec_enet_mii_init(struct platform_device *pdev)
  905. {
  906. static struct mii_bus *fec0_mii_bus;
  907. struct net_device *ndev = platform_get_drvdata(pdev);
  908. struct fec_enet_private *fep = netdev_priv(ndev);
  909. const struct platform_device_id *id_entry =
  910. platform_get_device_id(fep->pdev);
  911. int err = -ENXIO, i;
  912. /*
  913. * The dual fec interfaces are not equivalent with enet-mac.
  914. * Here are the differences:
  915. *
  916. * - fec0 supports MII & RMII modes while fec1 only supports RMII
  917. * - fec0 acts as the 1588 time master while fec1 is slave
  918. * - external phys can only be configured by fec0
  919. *
  920. * That is to say fec1 can not work independently. It only works
  921. * when fec0 is working. The reason behind this design is that the
  922. * second interface is added primarily for Switch mode.
  923. *
  924. * Because of the last point above, both phys are attached on fec0
  925. * mdio interface in board design, and need to be configured by
  926. * fec0 mii_bus.
  927. */
  928. if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
  929. /* fec1 uses fec0 mii_bus */
  930. if (mii_cnt && fec0_mii_bus) {
  931. fep->mii_bus = fec0_mii_bus;
  932. mii_cnt++;
  933. return 0;
  934. }
  935. return -ENOENT;
  936. }
  937. fep->mii_timeout = 0;
  938. /*
  939. * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
  940. *
  941. * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
  942. * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
  943. * Reference Manual has an error on this, and gets fixed on i.MX6Q
  944. * document.
  945. */
  946. fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
  947. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  948. fep->phy_speed--;
  949. fep->phy_speed <<= 1;
  950. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  951. fep->mii_bus = mdiobus_alloc();
  952. if (fep->mii_bus == NULL) {
  953. err = -ENOMEM;
  954. goto err_out;
  955. }
  956. fep->mii_bus->name = "fec_enet_mii_bus";
  957. fep->mii_bus->read = fec_enet_mdio_read;
  958. fep->mii_bus->write = fec_enet_mdio_write;
  959. fep->mii_bus->reset = fec_enet_mdio_reset;
  960. snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  961. pdev->name, fep->dev_id + 1);
  962. fep->mii_bus->priv = fep;
  963. fep->mii_bus->parent = &pdev->dev;
  964. fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  965. if (!fep->mii_bus->irq) {
  966. err = -ENOMEM;
  967. goto err_out_free_mdiobus;
  968. }
  969. for (i = 0; i < PHY_MAX_ADDR; i++)
  970. fep->mii_bus->irq[i] = PHY_POLL;
  971. if (mdiobus_register(fep->mii_bus))
  972. goto err_out_free_mdio_irq;
  973. mii_cnt++;
  974. /* save fec0 mii_bus */
  975. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  976. fec0_mii_bus = fep->mii_bus;
  977. return 0;
  978. err_out_free_mdio_irq:
  979. kfree(fep->mii_bus->irq);
  980. err_out_free_mdiobus:
  981. mdiobus_free(fep->mii_bus);
  982. err_out:
  983. return err;
  984. }
  985. static void fec_enet_mii_remove(struct fec_enet_private *fep)
  986. {
  987. if (--mii_cnt == 0) {
  988. mdiobus_unregister(fep->mii_bus);
  989. kfree(fep->mii_bus->irq);
  990. mdiobus_free(fep->mii_bus);
  991. }
  992. }
  993. static int fec_enet_get_settings(struct net_device *ndev,
  994. struct ethtool_cmd *cmd)
  995. {
  996. struct fec_enet_private *fep = netdev_priv(ndev);
  997. struct phy_device *phydev = fep->phy_dev;
  998. if (!phydev)
  999. return -ENODEV;
  1000. return phy_ethtool_gset(phydev, cmd);
  1001. }
  1002. static int fec_enet_set_settings(struct net_device *ndev,
  1003. struct ethtool_cmd *cmd)
  1004. {
  1005. struct fec_enet_private *fep = netdev_priv(ndev);
  1006. struct phy_device *phydev = fep->phy_dev;
  1007. if (!phydev)
  1008. return -ENODEV;
  1009. return phy_ethtool_sset(phydev, cmd);
  1010. }
  1011. static void fec_enet_get_drvinfo(struct net_device *ndev,
  1012. struct ethtool_drvinfo *info)
  1013. {
  1014. struct fec_enet_private *fep = netdev_priv(ndev);
  1015. strlcpy(info->driver, fep->pdev->dev.driver->name,
  1016. sizeof(info->driver));
  1017. strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
  1018. strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
  1019. }
  1020. static int fec_enet_get_ts_info(struct net_device *ndev,
  1021. struct ethtool_ts_info *info)
  1022. {
  1023. struct fec_enet_private *fep = netdev_priv(ndev);
  1024. if (fep->bufdesc_ex) {
  1025. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  1026. SOF_TIMESTAMPING_RX_SOFTWARE |
  1027. SOF_TIMESTAMPING_SOFTWARE |
  1028. SOF_TIMESTAMPING_TX_HARDWARE |
  1029. SOF_TIMESTAMPING_RX_HARDWARE |
  1030. SOF_TIMESTAMPING_RAW_HARDWARE;
  1031. if (fep->ptp_clock)
  1032. info->phc_index = ptp_clock_index(fep->ptp_clock);
  1033. else
  1034. info->phc_index = -1;
  1035. info->tx_types = (1 << HWTSTAMP_TX_OFF) |
  1036. (1 << HWTSTAMP_TX_ON);
  1037. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  1038. (1 << HWTSTAMP_FILTER_ALL);
  1039. return 0;
  1040. } else {
  1041. return ethtool_op_get_ts_info(ndev, info);
  1042. }
  1043. }
  1044. static void fec_enet_get_pauseparam(struct net_device *ndev,
  1045. struct ethtool_pauseparam *pause)
  1046. {
  1047. struct fec_enet_private *fep = netdev_priv(ndev);
  1048. pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
  1049. pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
  1050. pause->rx_pause = pause->tx_pause;
  1051. }
  1052. static int fec_enet_set_pauseparam(struct net_device *ndev,
  1053. struct ethtool_pauseparam *pause)
  1054. {
  1055. struct fec_enet_private *fep = netdev_priv(ndev);
  1056. if (pause->tx_pause != pause->rx_pause) {
  1057. netdev_info(ndev,
  1058. "hardware only support enable/disable both tx and rx");
  1059. return -EINVAL;
  1060. }
  1061. fep->pause_flag = 0;
  1062. /* tx pause must be same as rx pause */
  1063. fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
  1064. fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
  1065. if (pause->rx_pause || pause->autoneg) {
  1066. fep->phy_dev->supported |= ADVERTISED_Pause;
  1067. fep->phy_dev->advertising |= ADVERTISED_Pause;
  1068. } else {
  1069. fep->phy_dev->supported &= ~ADVERTISED_Pause;
  1070. fep->phy_dev->advertising &= ~ADVERTISED_Pause;
  1071. }
  1072. if (pause->autoneg) {
  1073. if (netif_running(ndev))
  1074. fec_stop(ndev);
  1075. phy_start_aneg(fep->phy_dev);
  1076. }
  1077. if (netif_running(ndev))
  1078. fec_restart(ndev, 0);
  1079. return 0;
  1080. }
  1081. static const struct ethtool_ops fec_enet_ethtool_ops = {
  1082. .get_pauseparam = fec_enet_get_pauseparam,
  1083. .set_pauseparam = fec_enet_set_pauseparam,
  1084. .get_settings = fec_enet_get_settings,
  1085. .set_settings = fec_enet_set_settings,
  1086. .get_drvinfo = fec_enet_get_drvinfo,
  1087. .get_link = ethtool_op_get_link,
  1088. .get_ts_info = fec_enet_get_ts_info,
  1089. };
  1090. static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
  1091. {
  1092. struct fec_enet_private *fep = netdev_priv(ndev);
  1093. struct phy_device *phydev = fep->phy_dev;
  1094. if (!netif_running(ndev))
  1095. return -EINVAL;
  1096. if (!phydev)
  1097. return -ENODEV;
  1098. if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
  1099. return fec_ptp_ioctl(ndev, rq, cmd);
  1100. return phy_mii_ioctl(phydev, rq, cmd);
  1101. }
  1102. static void fec_enet_free_buffers(struct net_device *ndev)
  1103. {
  1104. struct fec_enet_private *fep = netdev_priv(ndev);
  1105. int i;
  1106. struct sk_buff *skb;
  1107. struct bufdesc *bdp;
  1108. bdp = fep->rx_bd_base;
  1109. for (i = 0; i < RX_RING_SIZE; i++) {
  1110. skb = fep->rx_skbuff[i];
  1111. if (bdp->cbd_bufaddr)
  1112. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  1113. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1114. if (skb)
  1115. dev_kfree_skb(skb);
  1116. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1117. }
  1118. bdp = fep->tx_bd_base;
  1119. for (i = 0; i < TX_RING_SIZE; i++)
  1120. kfree(fep->tx_bounce[i]);
  1121. }
  1122. static int fec_enet_alloc_buffers(struct net_device *ndev)
  1123. {
  1124. struct fec_enet_private *fep = netdev_priv(ndev);
  1125. int i;
  1126. struct sk_buff *skb;
  1127. struct bufdesc *bdp;
  1128. bdp = fep->rx_bd_base;
  1129. for (i = 0; i < RX_RING_SIZE; i++) {
  1130. skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
  1131. if (!skb) {
  1132. fec_enet_free_buffers(ndev);
  1133. return -ENOMEM;
  1134. }
  1135. fep->rx_skbuff[i] = skb;
  1136. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
  1137. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1138. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  1139. if (fep->bufdesc_ex) {
  1140. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1141. ebdp->cbd_esc = BD_ENET_RX_INT;
  1142. }
  1143. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1144. }
  1145. /* Set the last buffer to wrap. */
  1146. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1147. bdp->cbd_sc |= BD_SC_WRAP;
  1148. bdp = fep->tx_bd_base;
  1149. for (i = 0; i < TX_RING_SIZE; i++) {
  1150. fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
  1151. bdp->cbd_sc = 0;
  1152. bdp->cbd_bufaddr = 0;
  1153. if (fep->bufdesc_ex) {
  1154. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1155. ebdp->cbd_esc = BD_ENET_RX_INT;
  1156. }
  1157. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1158. }
  1159. /* Set the last buffer to wrap. */
  1160. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1161. bdp->cbd_sc |= BD_SC_WRAP;
  1162. return 0;
  1163. }
  1164. static int
  1165. fec_enet_open(struct net_device *ndev)
  1166. {
  1167. struct fec_enet_private *fep = netdev_priv(ndev);
  1168. int ret;
  1169. /* I should reset the ring buffers here, but I don't yet know
  1170. * a simple way to do that.
  1171. */
  1172. ret = fec_enet_alloc_buffers(ndev);
  1173. if (ret)
  1174. return ret;
  1175. /* Probe and connect to PHY when open the interface */
  1176. ret = fec_enet_mii_probe(ndev);
  1177. if (ret) {
  1178. fec_enet_free_buffers(ndev);
  1179. return ret;
  1180. }
  1181. phy_start(fep->phy_dev);
  1182. netif_start_queue(ndev);
  1183. fep->opened = 1;
  1184. return 0;
  1185. }
  1186. static int
  1187. fec_enet_close(struct net_device *ndev)
  1188. {
  1189. struct fec_enet_private *fep = netdev_priv(ndev);
  1190. /* Don't know what to do yet. */
  1191. fep->opened = 0;
  1192. netif_stop_queue(ndev);
  1193. fec_stop(ndev);
  1194. if (fep->phy_dev) {
  1195. phy_stop(fep->phy_dev);
  1196. phy_disconnect(fep->phy_dev);
  1197. }
  1198. fec_enet_free_buffers(ndev);
  1199. return 0;
  1200. }
  1201. /* Set or clear the multicast filter for this adaptor.
  1202. * Skeleton taken from sunlance driver.
  1203. * The CPM Ethernet implementation allows Multicast as well as individual
  1204. * MAC address filtering. Some of the drivers check to make sure it is
  1205. * a group multicast address, and discard those that are not. I guess I
  1206. * will do the same for now, but just remove the test if you want
  1207. * individual filtering as well (do the upper net layers want or support
  1208. * this kind of feature?).
  1209. */
  1210. #define HASH_BITS 6 /* #bits in hash */
  1211. #define CRC32_POLY 0xEDB88320
  1212. static void set_multicast_list(struct net_device *ndev)
  1213. {
  1214. struct fec_enet_private *fep = netdev_priv(ndev);
  1215. struct netdev_hw_addr *ha;
  1216. unsigned int i, bit, data, crc, tmp;
  1217. unsigned char hash;
  1218. if (ndev->flags & IFF_PROMISC) {
  1219. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1220. tmp |= 0x8;
  1221. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1222. return;
  1223. }
  1224. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1225. tmp &= ~0x8;
  1226. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1227. if (ndev->flags & IFF_ALLMULTI) {
  1228. /* Catch all multicast addresses, so set the
  1229. * filter to all 1's
  1230. */
  1231. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1232. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1233. return;
  1234. }
  1235. /* Clear filter and add the addresses in hash register
  1236. */
  1237. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1238. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1239. netdev_for_each_mc_addr(ha, ndev) {
  1240. /* calculate crc32 value of mac address */
  1241. crc = 0xffffffff;
  1242. for (i = 0; i < ndev->addr_len; i++) {
  1243. data = ha->addr[i];
  1244. for (bit = 0; bit < 8; bit++, data >>= 1) {
  1245. crc = (crc >> 1) ^
  1246. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  1247. }
  1248. }
  1249. /* only upper 6 bits (HASH_BITS) are used
  1250. * which point to specific bit in he hash registers
  1251. */
  1252. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  1253. if (hash > 31) {
  1254. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1255. tmp |= 1 << (hash - 32);
  1256. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1257. } else {
  1258. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1259. tmp |= 1 << hash;
  1260. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1261. }
  1262. }
  1263. }
  1264. /* Set a MAC change in hardware. */
  1265. static int
  1266. fec_set_mac_address(struct net_device *ndev, void *p)
  1267. {
  1268. struct fec_enet_private *fep = netdev_priv(ndev);
  1269. struct sockaddr *addr = p;
  1270. if (!is_valid_ether_addr(addr->sa_data))
  1271. return -EADDRNOTAVAIL;
  1272. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  1273. writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
  1274. (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
  1275. fep->hwp + FEC_ADDR_LOW);
  1276. writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
  1277. fep->hwp + FEC_ADDR_HIGH);
  1278. return 0;
  1279. }
  1280. #ifdef CONFIG_NET_POLL_CONTROLLER
  1281. /**
  1282. * fec_poll_controller - FEC Poll controller function
  1283. * @dev: The FEC network adapter
  1284. *
  1285. * Polled functionality used by netconsole and others in non interrupt mode
  1286. *
  1287. */
  1288. void fec_poll_controller(struct net_device *dev)
  1289. {
  1290. int i;
  1291. struct fec_enet_private *fep = netdev_priv(dev);
  1292. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1293. if (fep->irq[i] > 0) {
  1294. disable_irq(fep->irq[i]);
  1295. fec_enet_interrupt(fep->irq[i], dev);
  1296. enable_irq(fep->irq[i]);
  1297. }
  1298. }
  1299. }
  1300. #endif
  1301. static const struct net_device_ops fec_netdev_ops = {
  1302. .ndo_open = fec_enet_open,
  1303. .ndo_stop = fec_enet_close,
  1304. .ndo_start_xmit = fec_enet_start_xmit,
  1305. .ndo_set_rx_mode = set_multicast_list,
  1306. .ndo_change_mtu = eth_change_mtu,
  1307. .ndo_validate_addr = eth_validate_addr,
  1308. .ndo_tx_timeout = fec_timeout,
  1309. .ndo_set_mac_address = fec_set_mac_address,
  1310. .ndo_do_ioctl = fec_enet_ioctl,
  1311. #ifdef CONFIG_NET_POLL_CONTROLLER
  1312. .ndo_poll_controller = fec_poll_controller,
  1313. #endif
  1314. };
  1315. /*
  1316. * XXX: We need to clean up on failure exits here.
  1317. *
  1318. */
  1319. static int fec_enet_init(struct net_device *ndev)
  1320. {
  1321. struct fec_enet_private *fep = netdev_priv(ndev);
  1322. struct bufdesc *cbd_base;
  1323. struct bufdesc *bdp;
  1324. int i;
  1325. /* Allocate memory for buffer descriptors. */
  1326. cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
  1327. GFP_KERNEL);
  1328. if (!cbd_base) {
  1329. printk("FEC: allocate descriptor memory failed?\n");
  1330. return -ENOMEM;
  1331. }
  1332. spin_lock_init(&fep->hw_lock);
  1333. fep->netdev = ndev;
  1334. /* Get the Ethernet address */
  1335. fec_get_mac(ndev);
  1336. /* Set receive and transmit descriptor base. */
  1337. fep->rx_bd_base = cbd_base;
  1338. if (fep->bufdesc_ex)
  1339. fep->tx_bd_base = (struct bufdesc *)
  1340. (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
  1341. else
  1342. fep->tx_bd_base = cbd_base + RX_RING_SIZE;
  1343. /* The FEC Ethernet specific entries in the device structure */
  1344. ndev->watchdog_timeo = TX_TIMEOUT;
  1345. ndev->netdev_ops = &fec_netdev_ops;
  1346. ndev->ethtool_ops = &fec_enet_ethtool_ops;
  1347. /* Initialize the receive buffer descriptors. */
  1348. bdp = fep->rx_bd_base;
  1349. for (i = 0; i < RX_RING_SIZE; i++) {
  1350. /* Initialize the BD for every fragment in the page. */
  1351. bdp->cbd_sc = 0;
  1352. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1353. }
  1354. /* Set the last buffer to wrap */
  1355. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1356. bdp->cbd_sc |= BD_SC_WRAP;
  1357. /* ...and the same for transmit */
  1358. bdp = fep->tx_bd_base;
  1359. for (i = 0; i < TX_RING_SIZE; i++) {
  1360. /* Initialize the BD for every fragment in the page. */
  1361. bdp->cbd_sc = 0;
  1362. bdp->cbd_bufaddr = 0;
  1363. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1364. }
  1365. /* Set the last buffer to wrap */
  1366. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1367. bdp->cbd_sc |= BD_SC_WRAP;
  1368. fec_restart(ndev, 0);
  1369. return 0;
  1370. }
  1371. #ifdef CONFIG_OF
  1372. static int fec_get_phy_mode_dt(struct platform_device *pdev)
  1373. {
  1374. struct device_node *np = pdev->dev.of_node;
  1375. if (np)
  1376. return of_get_phy_mode(np);
  1377. return -ENODEV;
  1378. }
  1379. static void fec_reset_phy(struct platform_device *pdev)
  1380. {
  1381. int err, phy_reset;
  1382. int msec = 1;
  1383. struct device_node *np = pdev->dev.of_node;
  1384. if (!np)
  1385. return;
  1386. of_property_read_u32(np, "phy-reset-duration", &msec);
  1387. /* A sane reset duration should not be longer than 1s */
  1388. if (msec > 1000)
  1389. msec = 1;
  1390. phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
  1391. err = devm_gpio_request_one(&pdev->dev, phy_reset,
  1392. GPIOF_OUT_INIT_LOW, "phy-reset");
  1393. if (err) {
  1394. pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
  1395. return;
  1396. }
  1397. msleep(msec);
  1398. gpio_set_value(phy_reset, 1);
  1399. }
  1400. #else /* CONFIG_OF */
  1401. static int fec_get_phy_mode_dt(struct platform_device *pdev)
  1402. {
  1403. return -ENODEV;
  1404. }
  1405. static void fec_reset_phy(struct platform_device *pdev)
  1406. {
  1407. /*
  1408. * In case of platform probe, the reset has been done
  1409. * by machine code.
  1410. */
  1411. }
  1412. #endif /* CONFIG_OF */
  1413. static int
  1414. fec_probe(struct platform_device *pdev)
  1415. {
  1416. struct fec_enet_private *fep;
  1417. struct fec_platform_data *pdata;
  1418. struct net_device *ndev;
  1419. int i, irq, ret = 0;
  1420. struct resource *r;
  1421. const struct of_device_id *of_id;
  1422. static int dev_id;
  1423. struct pinctrl *pinctrl;
  1424. struct regulator *reg_phy;
  1425. of_id = of_match_device(fec_dt_ids, &pdev->dev);
  1426. if (of_id)
  1427. pdev->id_entry = of_id->data;
  1428. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1429. if (!r)
  1430. return -ENXIO;
  1431. r = request_mem_region(r->start, resource_size(r), pdev->name);
  1432. if (!r)
  1433. return -EBUSY;
  1434. /* Init network device */
  1435. ndev = alloc_etherdev(sizeof(struct fec_enet_private));
  1436. if (!ndev) {
  1437. ret = -ENOMEM;
  1438. goto failed_alloc_etherdev;
  1439. }
  1440. SET_NETDEV_DEV(ndev, &pdev->dev);
  1441. /* setup board info structure */
  1442. fep = netdev_priv(ndev);
  1443. /* default enable pause frame auto negotiation */
  1444. if (pdev->id_entry &&
  1445. (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
  1446. fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
  1447. fep->hwp = ioremap(r->start, resource_size(r));
  1448. fep->pdev = pdev;
  1449. fep->dev_id = dev_id++;
  1450. fep->bufdesc_ex = 0;
  1451. if (!fep->hwp) {
  1452. ret = -ENOMEM;
  1453. goto failed_ioremap;
  1454. }
  1455. platform_set_drvdata(pdev, ndev);
  1456. ret = fec_get_phy_mode_dt(pdev);
  1457. if (ret < 0) {
  1458. pdata = pdev->dev.platform_data;
  1459. if (pdata)
  1460. fep->phy_interface = pdata->phy;
  1461. else
  1462. fep->phy_interface = PHY_INTERFACE_MODE_MII;
  1463. } else {
  1464. fep->phy_interface = ret;
  1465. }
  1466. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1467. irq = platform_get_irq(pdev, i);
  1468. if (irq < 0) {
  1469. if (i)
  1470. break;
  1471. ret = irq;
  1472. goto failed_irq;
  1473. }
  1474. ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
  1475. if (ret) {
  1476. while (--i >= 0) {
  1477. irq = platform_get_irq(pdev, i);
  1478. free_irq(irq, ndev);
  1479. }
  1480. goto failed_irq;
  1481. }
  1482. }
  1483. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  1484. if (IS_ERR(pinctrl)) {
  1485. ret = PTR_ERR(pinctrl);
  1486. goto failed_pin;
  1487. }
  1488. fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1489. if (IS_ERR(fep->clk_ipg)) {
  1490. ret = PTR_ERR(fep->clk_ipg);
  1491. goto failed_clk;
  1492. }
  1493. fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1494. if (IS_ERR(fep->clk_ahb)) {
  1495. ret = PTR_ERR(fep->clk_ahb);
  1496. goto failed_clk;
  1497. }
  1498. fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
  1499. fep->bufdesc_ex =
  1500. pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
  1501. if (IS_ERR(fep->clk_ptp)) {
  1502. ret = PTR_ERR(fep->clk_ptp);
  1503. fep->bufdesc_ex = 0;
  1504. }
  1505. clk_prepare_enable(fep->clk_ahb);
  1506. clk_prepare_enable(fep->clk_ipg);
  1507. if (!IS_ERR(fep->clk_ptp))
  1508. clk_prepare_enable(fep->clk_ptp);
  1509. reg_phy = devm_regulator_get(&pdev->dev, "phy");
  1510. if (!IS_ERR(reg_phy)) {
  1511. ret = regulator_enable(reg_phy);
  1512. if (ret) {
  1513. dev_err(&pdev->dev,
  1514. "Failed to enable phy regulator: %d\n", ret);
  1515. goto failed_regulator;
  1516. }
  1517. }
  1518. fec_reset_phy(pdev);
  1519. ret = fec_enet_init(ndev);
  1520. if (ret)
  1521. goto failed_init;
  1522. ret = fec_enet_mii_init(pdev);
  1523. if (ret)
  1524. goto failed_mii_init;
  1525. /* Carrier starts down, phylib will bring it up */
  1526. netif_carrier_off(ndev);
  1527. ret = register_netdev(ndev);
  1528. if (ret)
  1529. goto failed_register;
  1530. if (fep->bufdesc_ex)
  1531. fec_ptp_init(ndev, pdev);
  1532. return 0;
  1533. failed_register:
  1534. fec_enet_mii_remove(fep);
  1535. failed_mii_init:
  1536. failed_init:
  1537. failed_regulator:
  1538. clk_disable_unprepare(fep->clk_ahb);
  1539. clk_disable_unprepare(fep->clk_ipg);
  1540. if (!IS_ERR(fep->clk_ptp))
  1541. clk_disable_unprepare(fep->clk_ptp);
  1542. failed_pin:
  1543. failed_clk:
  1544. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1545. irq = platform_get_irq(pdev, i);
  1546. if (irq > 0)
  1547. free_irq(irq, ndev);
  1548. }
  1549. failed_irq:
  1550. iounmap(fep->hwp);
  1551. failed_ioremap:
  1552. free_netdev(ndev);
  1553. failed_alloc_etherdev:
  1554. release_mem_region(r->start, resource_size(r));
  1555. return ret;
  1556. }
  1557. static int
  1558. fec_drv_remove(struct platform_device *pdev)
  1559. {
  1560. struct net_device *ndev = platform_get_drvdata(pdev);
  1561. struct fec_enet_private *fep = netdev_priv(ndev);
  1562. struct resource *r;
  1563. int i;
  1564. unregister_netdev(ndev);
  1565. fec_enet_mii_remove(fep);
  1566. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1567. int irq = platform_get_irq(pdev, i);
  1568. if (irq > 0)
  1569. free_irq(irq, ndev);
  1570. }
  1571. del_timer_sync(&fep->time_keep);
  1572. clk_disable_unprepare(fep->clk_ptp);
  1573. if (fep->ptp_clock)
  1574. ptp_clock_unregister(fep->ptp_clock);
  1575. clk_disable_unprepare(fep->clk_ahb);
  1576. clk_disable_unprepare(fep->clk_ipg);
  1577. iounmap(fep->hwp);
  1578. free_netdev(ndev);
  1579. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1580. BUG_ON(!r);
  1581. release_mem_region(r->start, resource_size(r));
  1582. platform_set_drvdata(pdev, NULL);
  1583. return 0;
  1584. }
  1585. #ifdef CONFIG_PM
  1586. static int
  1587. fec_suspend(struct device *dev)
  1588. {
  1589. struct net_device *ndev = dev_get_drvdata(dev);
  1590. struct fec_enet_private *fep = netdev_priv(ndev);
  1591. if (netif_running(ndev)) {
  1592. fec_stop(ndev);
  1593. netif_device_detach(ndev);
  1594. }
  1595. clk_disable_unprepare(fep->clk_ahb);
  1596. clk_disable_unprepare(fep->clk_ipg);
  1597. return 0;
  1598. }
  1599. static int
  1600. fec_resume(struct device *dev)
  1601. {
  1602. struct net_device *ndev = dev_get_drvdata(dev);
  1603. struct fec_enet_private *fep = netdev_priv(ndev);
  1604. clk_prepare_enable(fep->clk_ahb);
  1605. clk_prepare_enable(fep->clk_ipg);
  1606. if (netif_running(ndev)) {
  1607. fec_restart(ndev, fep->full_duplex);
  1608. netif_device_attach(ndev);
  1609. }
  1610. return 0;
  1611. }
  1612. static const struct dev_pm_ops fec_pm_ops = {
  1613. .suspend = fec_suspend,
  1614. .resume = fec_resume,
  1615. .freeze = fec_suspend,
  1616. .thaw = fec_resume,
  1617. .poweroff = fec_suspend,
  1618. .restore = fec_resume,
  1619. };
  1620. #endif
  1621. static struct platform_driver fec_driver = {
  1622. .driver = {
  1623. .name = DRIVER_NAME,
  1624. .owner = THIS_MODULE,
  1625. #ifdef CONFIG_PM
  1626. .pm = &fec_pm_ops,
  1627. #endif
  1628. .of_match_table = fec_dt_ids,
  1629. },
  1630. .id_table = fec_devtype,
  1631. .probe = fec_probe,
  1632. .remove = fec_drv_remove,
  1633. };
  1634. module_platform_driver(fec_driver);
  1635. MODULE_LICENSE("GPL");