dma.h 6.1 KB

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  1. /*
  2. * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. #ifndef IOATDMA_H
  22. #define IOATDMA_H
  23. #include <linux/dmaengine.h>
  24. #include "hw.h"
  25. #include <linux/init.h>
  26. #include <linux/dmapool.h>
  27. #include <linux/cache.h>
  28. #include <linux/pci_ids.h>
  29. #include <net/tcp.h>
  30. #define IOAT_DMA_VERSION "3.64"
  31. #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
  32. #define IOAT_DMA_DCA_ANY_CPU ~0
  33. #define IOAT_WATCHDOG_PERIOD (2 * HZ)
  34. #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  35. #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  36. #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  37. #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  38. #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  39. #define RESET_DELAY msecs_to_jiffies(100)
  40. #define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
  41. /*
  42. * workaround for IOAT ver.3.0 null descriptor issue
  43. * (channel returns error when size is 0)
  44. */
  45. #define NULL_DESC_BUFFER_SIZE 1
  46. /**
  47. * struct ioatdma_device - internal representation of a IOAT device
  48. * @pdev: PCI-Express device
  49. * @reg_base: MMIO register space base address
  50. * @dma_pool: for allocating DMA descriptors
  51. * @common: embedded struct dma_device
  52. * @version: version of ioatdma device
  53. * @msix_entries: irq handlers
  54. * @idx: per channel data
  55. * @dca: direct cache access context
  56. * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
  57. * @enumerate_channels: hw version specific channel enumeration
  58. */
  59. struct ioatdma_device {
  60. struct pci_dev *pdev;
  61. void __iomem *reg_base;
  62. struct pci_pool *dma_pool;
  63. struct pci_pool *completion_pool;
  64. struct dma_device common;
  65. u8 version;
  66. struct delayed_work work;
  67. struct msix_entry msix_entries[4];
  68. struct ioat_chan_common *idx[4];
  69. struct dca_provider *dca;
  70. void (*intr_quirk)(struct ioatdma_device *device);
  71. int (*enumerate_channels)(struct ioatdma_device *device);
  72. };
  73. struct ioat_chan_common {
  74. void __iomem *reg_base;
  75. unsigned long last_completion;
  76. unsigned long last_completion_time;
  77. spinlock_t cleanup_lock;
  78. dma_cookie_t completed_cookie;
  79. unsigned long watchdog_completion;
  80. int watchdog_tcp_cookie;
  81. u32 watchdog_last_tcp_cookie;
  82. struct delayed_work work;
  83. struct ioatdma_device *device;
  84. struct dma_chan common;
  85. dma_addr_t completion_addr;
  86. union {
  87. u64 full; /* HW completion writeback */
  88. struct {
  89. u32 low;
  90. u32 high;
  91. };
  92. } *completion_virt;
  93. unsigned long last_compl_desc_addr_hw;
  94. struct tasklet_struct cleanup_task;
  95. };
  96. /**
  97. * struct ioat_dma_chan - internal representation of a DMA channel
  98. */
  99. struct ioat_dma_chan {
  100. struct ioat_chan_common base;
  101. size_t xfercap; /* XFERCAP register value expanded out */
  102. spinlock_t desc_lock;
  103. struct list_head free_desc;
  104. struct list_head used_desc;
  105. int pending;
  106. u16 desccount;
  107. };
  108. static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
  109. {
  110. return container_of(c, struct ioat_chan_common, common);
  111. }
  112. static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
  113. {
  114. struct ioat_chan_common *chan = to_chan_common(c);
  115. return container_of(chan, struct ioat_dma_chan, base);
  116. }
  117. /**
  118. * ioat_is_complete - poll the status of an ioat transaction
  119. * @c: channel handle
  120. * @cookie: transaction identifier
  121. * @done: if set, updated with last completed transaction
  122. * @used: if set, updated with last used transaction
  123. */
  124. static inline enum dma_status
  125. ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
  126. dma_cookie_t *done, dma_cookie_t *used)
  127. {
  128. struct ioat_chan_common *chan = to_chan_common(c);
  129. dma_cookie_t last_used;
  130. dma_cookie_t last_complete;
  131. last_used = c->cookie;
  132. last_complete = chan->completed_cookie;
  133. chan->watchdog_tcp_cookie = cookie;
  134. if (done)
  135. *done = last_complete;
  136. if (used)
  137. *used = last_used;
  138. return dma_async_is_complete(cookie, last_complete, last_used);
  139. }
  140. /* wrapper around hardware descriptor format + additional software fields */
  141. /**
  142. * struct ioat_desc_sw - wrapper around hardware descriptor
  143. * @hw: hardware DMA descriptor
  144. * @node: this descriptor will either be on the free list,
  145. * or attached to a transaction list (async_tx.tx_list)
  146. * @tx_cnt: number of descriptors required to complete the transaction
  147. * @txd: the generic software descriptor for all engines
  148. */
  149. struct ioat_desc_sw {
  150. struct ioat_dma_descriptor *hw;
  151. struct list_head node;
  152. int tx_cnt;
  153. size_t len;
  154. struct dma_async_tx_descriptor txd;
  155. };
  156. static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
  157. {
  158. #ifdef CONFIG_NET_DMA
  159. sysctl_tcp_dma_copybreak = copybreak;
  160. #endif
  161. }
  162. static inline struct ioat_chan_common *
  163. ioat_chan_by_index(struct ioatdma_device *device, int index)
  164. {
  165. return device->idx[index];
  166. }
  167. int ioat_probe(struct ioatdma_device *device);
  168. int ioat_register(struct ioatdma_device *device);
  169. int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
  170. void ioat_dma_remove(struct ioatdma_device *device);
  171. struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  172. unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
  173. void ioat_init_channel(struct ioatdma_device *device,
  174. struct ioat_chan_common *chan, int idx,
  175. work_func_t work_fn, void (*tasklet)(unsigned long),
  176. unsigned long tasklet_data);
  177. void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
  178. size_t len, struct ioat_dma_descriptor *hw);
  179. #endif /* IOATDMA_H */