fsi.c 28 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/io.h>
  17. #include <linux/slab.h>
  18. #include <sound/soc.h>
  19. #include <sound/sh_fsi.h>
  20. #define DO_FMT 0x0000
  21. #define DOFF_CTL 0x0004
  22. #define DOFF_ST 0x0008
  23. #define DI_FMT 0x000C
  24. #define DIFF_CTL 0x0010
  25. #define DIFF_ST 0x0014
  26. #define CKG1 0x0018
  27. #define CKG2 0x001C
  28. #define DIDT 0x0020
  29. #define DODT 0x0024
  30. #define MUTE_ST 0x0028
  31. #define OUT_SEL 0x0030
  32. #define REG_END OUT_SEL
  33. #define A_MST_CTLR 0x0180
  34. #define B_MST_CTLR 0x01A0
  35. #define CPU_INT_ST 0x01F4
  36. #define CPU_IEMSK 0x01F8
  37. #define CPU_IMSK 0x01FC
  38. #define INT_ST 0x0200
  39. #define IEMSK 0x0204
  40. #define IMSK 0x0208
  41. #define MUTE 0x020C
  42. #define CLK_RST 0x0210
  43. #define SOFT_RST 0x0214
  44. #define FIFO_SZ 0x0218
  45. #define MREG_START A_MST_CTLR
  46. #define MREG_END FIFO_SZ
  47. /* DO_FMT */
  48. /* DI_FMT */
  49. #define CR_MONO (0x0 << 4)
  50. #define CR_MONO_D (0x1 << 4)
  51. #define CR_PCM (0x2 << 4)
  52. #define CR_I2S (0x3 << 4)
  53. #define CR_TDM (0x4 << 4)
  54. #define CR_TDM_D (0x5 << 4)
  55. #define CR_SPDIF 0x00100120
  56. /* DOFF_CTL */
  57. /* DIFF_CTL */
  58. #define IRQ_HALF 0x00100000
  59. #define FIFO_CLR 0x00000001
  60. /* DOFF_ST */
  61. #define ERR_OVER 0x00000010
  62. #define ERR_UNDER 0x00000001
  63. #define ST_ERR (ERR_OVER | ERR_UNDER)
  64. /* CKG1 */
  65. #define ACKMD_MASK 0x00007000
  66. #define BPFMD_MASK 0x00000700
  67. /* A/B MST_CTLR */
  68. #define BP (1 << 4) /* Fix the signal of Biphase output */
  69. #define SE (1 << 0) /* Fix the master clock */
  70. /* CLK_RST */
  71. #define B_CLK 0x00000010
  72. #define A_CLK 0x00000001
  73. /* INT_ST */
  74. #define INT_B_IN (1 << 12)
  75. #define INT_B_OUT (1 << 8)
  76. #define INT_A_IN (1 << 4)
  77. #define INT_A_OUT (1 << 0)
  78. /* SOFT_RST */
  79. #define PBSR (1 << 12) /* Port B Software Reset */
  80. #define PASR (1 << 8) /* Port A Software Reset */
  81. #define IR (1 << 4) /* Interrupt Reset */
  82. #define FSISR (1 << 0) /* Software Reset */
  83. /* FIFO_SZ */
  84. #define OUT_SZ_MASK 0x7
  85. #define BO_SZ_SHIFT 8
  86. #define AO_SZ_SHIFT 0
  87. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  88. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  89. /************************************************************************
  90. struct
  91. ************************************************************************/
  92. struct fsi_priv {
  93. void __iomem *base;
  94. struct snd_pcm_substream *substream;
  95. struct fsi_master *master;
  96. int fifo_max;
  97. int chan;
  98. int byte_offset;
  99. int period_len;
  100. int buffer_len;
  101. int periods;
  102. u32 mst_ctrl;
  103. };
  104. struct fsi_core {
  105. int ver;
  106. u32 int_st;
  107. u32 iemsk;
  108. u32 imsk;
  109. };
  110. struct fsi_master {
  111. void __iomem *base;
  112. int irq;
  113. struct fsi_priv fsia;
  114. struct fsi_priv fsib;
  115. struct fsi_core *core;
  116. struct sh_fsi_platform_info *info;
  117. spinlock_t lock;
  118. };
  119. /************************************************************************
  120. basic read write function
  121. ************************************************************************/
  122. static void __fsi_reg_write(u32 reg, u32 data)
  123. {
  124. /* valid data area is 24bit */
  125. data &= 0x00ffffff;
  126. __raw_writel(data, reg);
  127. }
  128. static u32 __fsi_reg_read(u32 reg)
  129. {
  130. return __raw_readl(reg);
  131. }
  132. static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
  133. {
  134. u32 val = __fsi_reg_read(reg);
  135. val &= ~mask;
  136. val |= data & mask;
  137. __fsi_reg_write(reg, val);
  138. }
  139. static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
  140. {
  141. if (reg > REG_END) {
  142. pr_err("fsi: register access err (%s)\n", __func__);
  143. return;
  144. }
  145. __fsi_reg_write((u32)(fsi->base + reg), data);
  146. }
  147. static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
  148. {
  149. if (reg > REG_END) {
  150. pr_err("fsi: register access err (%s)\n", __func__);
  151. return 0;
  152. }
  153. return __fsi_reg_read((u32)(fsi->base + reg));
  154. }
  155. static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
  156. {
  157. if (reg > REG_END) {
  158. pr_err("fsi: register access err (%s)\n", __func__);
  159. return;
  160. }
  161. __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
  162. }
  163. static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
  164. {
  165. unsigned long flags;
  166. if ((reg < MREG_START) ||
  167. (reg > MREG_END)) {
  168. pr_err("fsi: register access err (%s)\n", __func__);
  169. return;
  170. }
  171. spin_lock_irqsave(&master->lock, flags);
  172. __fsi_reg_write((u32)(master->base + reg), data);
  173. spin_unlock_irqrestore(&master->lock, flags);
  174. }
  175. static u32 fsi_master_read(struct fsi_master *master, u32 reg)
  176. {
  177. u32 ret;
  178. unsigned long flags;
  179. if ((reg < MREG_START) ||
  180. (reg > MREG_END)) {
  181. pr_err("fsi: register access err (%s)\n", __func__);
  182. return 0;
  183. }
  184. spin_lock_irqsave(&master->lock, flags);
  185. ret = __fsi_reg_read((u32)(master->base + reg));
  186. spin_unlock_irqrestore(&master->lock, flags);
  187. return ret;
  188. }
  189. static void fsi_master_mask_set(struct fsi_master *master,
  190. u32 reg, u32 mask, u32 data)
  191. {
  192. unsigned long flags;
  193. if ((reg < MREG_START) ||
  194. (reg > MREG_END)) {
  195. pr_err("fsi: register access err (%s)\n", __func__);
  196. return;
  197. }
  198. spin_lock_irqsave(&master->lock, flags);
  199. __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
  200. spin_unlock_irqrestore(&master->lock, flags);
  201. }
  202. /************************************************************************
  203. basic function
  204. ************************************************************************/
  205. static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
  206. {
  207. return fsi->master;
  208. }
  209. static int fsi_is_port_a(struct fsi_priv *fsi)
  210. {
  211. return fsi->master->base == fsi->base;
  212. }
  213. static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
  214. {
  215. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  216. struct snd_soc_dai_link *machine = rtd->dai;
  217. return machine->cpu_dai;
  218. }
  219. static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
  220. {
  221. struct snd_soc_dai *dai = fsi_get_dai(substream);
  222. return dai->private_data;
  223. }
  224. static u32 fsi_get_info_flags(struct fsi_priv *fsi)
  225. {
  226. int is_porta = fsi_is_port_a(fsi);
  227. struct fsi_master *master = fsi_get_master(fsi);
  228. return is_porta ? master->info->porta_flags :
  229. master->info->portb_flags;
  230. }
  231. static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
  232. {
  233. u32 mode;
  234. u32 flags = fsi_get_info_flags(fsi);
  235. mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
  236. /* return
  237. * 1 : master mode
  238. * 0 : slave mode
  239. */
  240. return (mode & flags) != mode;
  241. }
  242. static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
  243. {
  244. int is_porta = fsi_is_port_a(fsi);
  245. u32 data;
  246. if (is_porta)
  247. data = is_play ? (1 << 0) : (1 << 4);
  248. else
  249. data = is_play ? (1 << 8) : (1 << 12);
  250. return data;
  251. }
  252. static void fsi_stream_push(struct fsi_priv *fsi,
  253. struct snd_pcm_substream *substream,
  254. u32 buffer_len,
  255. u32 period_len)
  256. {
  257. fsi->substream = substream;
  258. fsi->buffer_len = buffer_len;
  259. fsi->period_len = period_len;
  260. fsi->byte_offset = 0;
  261. fsi->periods = 0;
  262. }
  263. static void fsi_stream_pop(struct fsi_priv *fsi)
  264. {
  265. fsi->substream = NULL;
  266. fsi->buffer_len = 0;
  267. fsi->period_len = 0;
  268. fsi->byte_offset = 0;
  269. fsi->periods = 0;
  270. }
  271. static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
  272. {
  273. u32 status;
  274. u32 reg = is_play ? DOFF_ST : DIFF_ST;
  275. int residue;
  276. status = fsi_reg_read(fsi, reg);
  277. residue = 0x1ff & (status >> 8);
  278. residue *= fsi->chan;
  279. return residue;
  280. }
  281. /************************************************************************
  282. irq function
  283. ************************************************************************/
  284. static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
  285. {
  286. u32 data = fsi_port_ab_io_bit(fsi, is_play);
  287. struct fsi_master *master = fsi_get_master(fsi);
  288. fsi_master_mask_set(master, master->core->imsk, data, data);
  289. fsi_master_mask_set(master, master->core->iemsk, data, data);
  290. }
  291. static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
  292. {
  293. u32 data = fsi_port_ab_io_bit(fsi, is_play);
  294. struct fsi_master *master = fsi_get_master(fsi);
  295. fsi_master_mask_set(master, master->core->imsk, data, 0);
  296. fsi_master_mask_set(master, master->core->iemsk, data, 0);
  297. }
  298. static u32 fsi_irq_get_status(struct fsi_master *master)
  299. {
  300. return fsi_master_read(master, master->core->int_st);
  301. }
  302. static void fsi_irq_clear_all_status(struct fsi_master *master)
  303. {
  304. fsi_master_write(master, master->core->int_st, 0);
  305. }
  306. static void fsi_irq_clear_status(struct fsi_priv *fsi)
  307. {
  308. u32 data = 0;
  309. struct fsi_master *master = fsi_get_master(fsi);
  310. data |= fsi_port_ab_io_bit(fsi, 0);
  311. data |= fsi_port_ab_io_bit(fsi, 1);
  312. /* clear interrupt factor */
  313. fsi_master_mask_set(master, master->core->int_st, data, 0);
  314. }
  315. /************************************************************************
  316. SPDIF master clock function
  317. These functions are used later FSI2
  318. ************************************************************************/
  319. static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
  320. {
  321. struct fsi_master *master = fsi_get_master(fsi);
  322. u32 val = BP | SE;
  323. if (master->core->ver < 2) {
  324. pr_err("fsi: register access err (%s)\n", __func__);
  325. return;
  326. }
  327. if (enable)
  328. fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
  329. else
  330. fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
  331. }
  332. /************************************************************************
  333. ctrl function
  334. ************************************************************************/
  335. static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
  336. {
  337. u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
  338. struct fsi_master *master = fsi_get_master(fsi);
  339. if (enable)
  340. fsi_master_mask_set(master, CLK_RST, val, val);
  341. else
  342. fsi_master_mask_set(master, CLK_RST, val, 0);
  343. }
  344. static void fsi_fifo_init(struct fsi_priv *fsi,
  345. int is_play,
  346. struct snd_soc_dai *dai)
  347. {
  348. struct fsi_master *master = fsi_get_master(fsi);
  349. u32 ctrl, shift, i;
  350. /* get on-chip RAM capacity */
  351. shift = fsi_master_read(master, FIFO_SZ);
  352. shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
  353. shift &= OUT_SZ_MASK;
  354. fsi->fifo_max = 256 << shift;
  355. dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max);
  356. /*
  357. * The maximum number of sample data varies depending
  358. * on the number of channels selected for the format.
  359. *
  360. * FIFOs are used in 4-channel units in 3-channel mode
  361. * and in 8-channel units in 5- to 7-channel mode
  362. * meaning that more FIFOs than the required size of DPRAM
  363. * are used.
  364. *
  365. * ex) if 256 words of DP-RAM is connected
  366. * 1 channel: 256 (256 x 1 = 256)
  367. * 2 channels: 128 (128 x 2 = 256)
  368. * 3 channels: 64 ( 64 x 3 = 192)
  369. * 4 channels: 64 ( 64 x 4 = 256)
  370. * 5 channels: 32 ( 32 x 5 = 160)
  371. * 6 channels: 32 ( 32 x 6 = 192)
  372. * 7 channels: 32 ( 32 x 7 = 224)
  373. * 8 channels: 32 ( 32 x 8 = 256)
  374. */
  375. for (i = 1; i < fsi->chan; i <<= 1)
  376. fsi->fifo_max >>= 1;
  377. dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max);
  378. ctrl = is_play ? DOFF_CTL : DIFF_CTL;
  379. /* set interrupt generation factor */
  380. fsi_reg_write(fsi, ctrl, IRQ_HALF);
  381. /* clear FIFO */
  382. fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
  383. }
  384. static void fsi_soft_all_reset(struct fsi_master *master)
  385. {
  386. /* port AB reset */
  387. fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
  388. mdelay(10);
  389. /* soft reset */
  390. fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
  391. fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
  392. mdelay(10);
  393. }
  394. /* playback interrupt */
  395. static int fsi_data_push(struct fsi_priv *fsi, int startup)
  396. {
  397. struct snd_pcm_runtime *runtime;
  398. struct snd_pcm_substream *substream = NULL;
  399. u32 status;
  400. int send;
  401. int fifo_free;
  402. int width;
  403. u8 *start;
  404. int i, over_period;
  405. if (!fsi ||
  406. !fsi->substream ||
  407. !fsi->substream->runtime)
  408. return -EINVAL;
  409. over_period = 0;
  410. substream = fsi->substream;
  411. runtime = substream->runtime;
  412. /* FSI FIFO has limit.
  413. * So, this driver can not send periods data at a time
  414. */
  415. if (fsi->byte_offset >=
  416. fsi->period_len * (fsi->periods + 1)) {
  417. over_period = 1;
  418. fsi->periods = (fsi->periods + 1) % runtime->periods;
  419. if (0 == fsi->periods)
  420. fsi->byte_offset = 0;
  421. }
  422. /* get 1 channel data width */
  423. width = frames_to_bytes(runtime, 1) / fsi->chan;
  424. /* get send size for alsa */
  425. send = (fsi->buffer_len - fsi->byte_offset) / width;
  426. /* get FIFO free size */
  427. fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
  428. /* size check */
  429. if (fifo_free < send)
  430. send = fifo_free;
  431. start = runtime->dma_area;
  432. start += fsi->byte_offset;
  433. switch (width) {
  434. case 2:
  435. for (i = 0; i < send; i++)
  436. fsi_reg_write(fsi, DODT,
  437. ((u32)*((u16 *)start + i) << 8));
  438. break;
  439. case 4:
  440. for (i = 0; i < send; i++)
  441. fsi_reg_write(fsi, DODT, *((u32 *)start + i));
  442. break;
  443. default:
  444. return -EINVAL;
  445. }
  446. fsi->byte_offset += send * width;
  447. status = fsi_reg_read(fsi, DOFF_ST);
  448. if (!startup) {
  449. struct snd_soc_dai *dai = fsi_get_dai(substream);
  450. if (status & ERR_OVER)
  451. dev_err(dai->dev, "over run\n");
  452. if (status & ERR_UNDER)
  453. dev_err(dai->dev, "under run\n");
  454. }
  455. fsi_reg_write(fsi, DOFF_ST, 0);
  456. fsi_irq_enable(fsi, 1);
  457. if (over_period)
  458. snd_pcm_period_elapsed(substream);
  459. return 0;
  460. }
  461. static int fsi_data_pop(struct fsi_priv *fsi, int startup)
  462. {
  463. struct snd_pcm_runtime *runtime;
  464. struct snd_pcm_substream *substream = NULL;
  465. u32 status;
  466. int free;
  467. int fifo_fill;
  468. int width;
  469. u8 *start;
  470. int i, over_period;
  471. if (!fsi ||
  472. !fsi->substream ||
  473. !fsi->substream->runtime)
  474. return -EINVAL;
  475. over_period = 0;
  476. substream = fsi->substream;
  477. runtime = substream->runtime;
  478. /* FSI FIFO has limit.
  479. * So, this driver can not send periods data at a time
  480. */
  481. if (fsi->byte_offset >=
  482. fsi->period_len * (fsi->periods + 1)) {
  483. over_period = 1;
  484. fsi->periods = (fsi->periods + 1) % runtime->periods;
  485. if (0 == fsi->periods)
  486. fsi->byte_offset = 0;
  487. }
  488. /* get 1 channel data width */
  489. width = frames_to_bytes(runtime, 1) / fsi->chan;
  490. /* get free space for alsa */
  491. free = (fsi->buffer_len - fsi->byte_offset) / width;
  492. /* get recv size */
  493. fifo_fill = fsi_get_fifo_residue(fsi, 0);
  494. if (free < fifo_fill)
  495. fifo_fill = free;
  496. start = runtime->dma_area;
  497. start += fsi->byte_offset;
  498. switch (width) {
  499. case 2:
  500. for (i = 0; i < fifo_fill; i++)
  501. *((u16 *)start + i) =
  502. (u16)(fsi_reg_read(fsi, DIDT) >> 8);
  503. break;
  504. case 4:
  505. for (i = 0; i < fifo_fill; i++)
  506. *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
  507. break;
  508. default:
  509. return -EINVAL;
  510. }
  511. fsi->byte_offset += fifo_fill * width;
  512. status = fsi_reg_read(fsi, DIFF_ST);
  513. if (!startup) {
  514. struct snd_soc_dai *dai = fsi_get_dai(substream);
  515. if (status & ERR_OVER)
  516. dev_err(dai->dev, "over run\n");
  517. if (status & ERR_UNDER)
  518. dev_err(dai->dev, "under run\n");
  519. }
  520. fsi_reg_write(fsi, DIFF_ST, 0);
  521. fsi_irq_enable(fsi, 0);
  522. if (over_period)
  523. snd_pcm_period_elapsed(substream);
  524. return 0;
  525. }
  526. static irqreturn_t fsi_interrupt(int irq, void *data)
  527. {
  528. struct fsi_master *master = data;
  529. u32 int_st = fsi_irq_get_status(master);
  530. /* clear irq status */
  531. fsi_master_mask_set(master, SOFT_RST, IR, 0);
  532. fsi_master_mask_set(master, SOFT_RST, IR, IR);
  533. if (int_st & INT_A_OUT)
  534. fsi_data_push(&master->fsia, 0);
  535. if (int_st & INT_B_OUT)
  536. fsi_data_push(&master->fsib, 0);
  537. if (int_st & INT_A_IN)
  538. fsi_data_pop(&master->fsia, 0);
  539. if (int_st & INT_B_IN)
  540. fsi_data_pop(&master->fsib, 0);
  541. fsi_irq_clear_all_status(master);
  542. return IRQ_HANDLED;
  543. }
  544. /************************************************************************
  545. dai ops
  546. ************************************************************************/
  547. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  548. struct snd_soc_dai *dai)
  549. {
  550. struct fsi_priv *fsi = fsi_get_priv(substream);
  551. u32 flags = fsi_get_info_flags(fsi);
  552. struct fsi_master *master = fsi_get_master(fsi);
  553. u32 fmt;
  554. u32 reg;
  555. u32 data;
  556. int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  557. int is_master;
  558. int ret = 0;
  559. pm_runtime_get_sync(dai->dev);
  560. /* CKG1 */
  561. data = is_play ? (1 << 0) : (1 << 4);
  562. is_master = fsi_is_master_mode(fsi, is_play);
  563. if (is_master)
  564. fsi_reg_mask_set(fsi, CKG1, data, data);
  565. else
  566. fsi_reg_mask_set(fsi, CKG1, data, 0);
  567. /* clock inversion (CKG2) */
  568. data = 0;
  569. if (SH_FSI_LRM_INV & flags)
  570. data |= 1 << 12;
  571. if (SH_FSI_BRM_INV & flags)
  572. data |= 1 << 8;
  573. if (SH_FSI_LRS_INV & flags)
  574. data |= 1 << 4;
  575. if (SH_FSI_BRS_INV & flags)
  576. data |= 1 << 0;
  577. fsi_reg_write(fsi, CKG2, data);
  578. /* do fmt, di fmt */
  579. data = 0;
  580. reg = is_play ? DO_FMT : DI_FMT;
  581. fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
  582. switch (fmt) {
  583. case SH_FSI_FMT_MONO:
  584. data = CR_MONO;
  585. fsi->chan = 1;
  586. break;
  587. case SH_FSI_FMT_MONO_DELAY:
  588. data = CR_MONO_D;
  589. fsi->chan = 1;
  590. break;
  591. case SH_FSI_FMT_PCM:
  592. data = CR_PCM;
  593. fsi->chan = 2;
  594. break;
  595. case SH_FSI_FMT_I2S:
  596. data = CR_I2S;
  597. fsi->chan = 2;
  598. break;
  599. case SH_FSI_FMT_TDM:
  600. fsi->chan = is_play ?
  601. SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
  602. data = CR_TDM | (fsi->chan - 1);
  603. break;
  604. case SH_FSI_FMT_TDM_DELAY:
  605. fsi->chan = is_play ?
  606. SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
  607. data = CR_TDM_D | (fsi->chan - 1);
  608. break;
  609. case SH_FSI_FMT_SPDIF:
  610. if (master->core->ver < 2) {
  611. dev_err(dai->dev, "This FSI can not use SPDIF\n");
  612. return -EINVAL;
  613. }
  614. data = CR_SPDIF;
  615. fsi->chan = 2;
  616. fsi_spdif_clk_ctrl(fsi, 1);
  617. fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
  618. break;
  619. default:
  620. dev_err(dai->dev, "unknown format.\n");
  621. return -EINVAL;
  622. }
  623. fsi_reg_write(fsi, reg, data);
  624. /* irq clear */
  625. fsi_irq_disable(fsi, is_play);
  626. fsi_irq_clear_status(fsi);
  627. /* fifo init */
  628. fsi_fifo_init(fsi, is_play, dai);
  629. return ret;
  630. }
  631. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  632. struct snd_soc_dai *dai)
  633. {
  634. struct fsi_priv *fsi = fsi_get_priv(substream);
  635. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  636. fsi_irq_disable(fsi, is_play);
  637. fsi_clk_ctrl(fsi, 0);
  638. pm_runtime_put_sync(dai->dev);
  639. }
  640. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  641. struct snd_soc_dai *dai)
  642. {
  643. struct fsi_priv *fsi = fsi_get_priv(substream);
  644. struct snd_pcm_runtime *runtime = substream->runtime;
  645. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  646. int ret = 0;
  647. switch (cmd) {
  648. case SNDRV_PCM_TRIGGER_START:
  649. fsi_stream_push(fsi, substream,
  650. frames_to_bytes(runtime, runtime->buffer_size),
  651. frames_to_bytes(runtime, runtime->period_size));
  652. ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
  653. break;
  654. case SNDRV_PCM_TRIGGER_STOP:
  655. fsi_irq_disable(fsi, is_play);
  656. fsi_stream_pop(fsi);
  657. break;
  658. }
  659. return ret;
  660. }
  661. static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
  662. struct snd_pcm_hw_params *params,
  663. struct snd_soc_dai *dai)
  664. {
  665. struct fsi_priv *fsi = fsi_get_priv(substream);
  666. struct fsi_master *master = fsi_get_master(fsi);
  667. int (*set_rate)(int is_porta, int rate) = master->info->set_rate;
  668. int fsi_ver = master->core->ver;
  669. int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  670. int ret;
  671. /* if slave mode, set_rate is not needed */
  672. if (!fsi_is_master_mode(fsi, is_play))
  673. return 0;
  674. /* it is error if no set_rate */
  675. if (!set_rate)
  676. return -EIO;
  677. ret = set_rate(fsi_is_port_a(fsi), params_rate(params));
  678. if (ret > 0) {
  679. u32 data = 0;
  680. switch (ret & SH_FSI_ACKMD_MASK) {
  681. default:
  682. /* FALL THROUGH */
  683. case SH_FSI_ACKMD_512:
  684. data |= (0x0 << 12);
  685. break;
  686. case SH_FSI_ACKMD_256:
  687. data |= (0x1 << 12);
  688. break;
  689. case SH_FSI_ACKMD_128:
  690. data |= (0x2 << 12);
  691. break;
  692. case SH_FSI_ACKMD_64:
  693. data |= (0x3 << 12);
  694. break;
  695. case SH_FSI_ACKMD_32:
  696. if (fsi_ver < 2)
  697. dev_err(dai->dev, "unsupported ACKMD\n");
  698. else
  699. data |= (0x4 << 12);
  700. break;
  701. }
  702. switch (ret & SH_FSI_BPFMD_MASK) {
  703. default:
  704. /* FALL THROUGH */
  705. case SH_FSI_BPFMD_32:
  706. data |= (0x0 << 8);
  707. break;
  708. case SH_FSI_BPFMD_64:
  709. data |= (0x1 << 8);
  710. break;
  711. case SH_FSI_BPFMD_128:
  712. data |= (0x2 << 8);
  713. break;
  714. case SH_FSI_BPFMD_256:
  715. data |= (0x3 << 8);
  716. break;
  717. case SH_FSI_BPFMD_512:
  718. data |= (0x4 << 8);
  719. break;
  720. case SH_FSI_BPFMD_16:
  721. if (fsi_ver < 2)
  722. dev_err(dai->dev, "unsupported ACKMD\n");
  723. else
  724. data |= (0x7 << 8);
  725. break;
  726. }
  727. fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
  728. udelay(10);
  729. fsi_clk_ctrl(fsi, 1);
  730. ret = 0;
  731. }
  732. return ret;
  733. }
  734. static struct snd_soc_dai_ops fsi_dai_ops = {
  735. .startup = fsi_dai_startup,
  736. .shutdown = fsi_dai_shutdown,
  737. .trigger = fsi_dai_trigger,
  738. .hw_params = fsi_dai_hw_params,
  739. };
  740. /************************************************************************
  741. pcm ops
  742. ************************************************************************/
  743. static struct snd_pcm_hardware fsi_pcm_hardware = {
  744. .info = SNDRV_PCM_INFO_INTERLEAVED |
  745. SNDRV_PCM_INFO_MMAP |
  746. SNDRV_PCM_INFO_MMAP_VALID |
  747. SNDRV_PCM_INFO_PAUSE,
  748. .formats = FSI_FMTS,
  749. .rates = FSI_RATES,
  750. .rate_min = 8000,
  751. .rate_max = 192000,
  752. .channels_min = 1,
  753. .channels_max = 2,
  754. .buffer_bytes_max = 64 * 1024,
  755. .period_bytes_min = 32,
  756. .period_bytes_max = 8192,
  757. .periods_min = 1,
  758. .periods_max = 32,
  759. .fifo_size = 256,
  760. };
  761. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  762. {
  763. struct snd_pcm_runtime *runtime = substream->runtime;
  764. int ret = 0;
  765. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  766. ret = snd_pcm_hw_constraint_integer(runtime,
  767. SNDRV_PCM_HW_PARAM_PERIODS);
  768. return ret;
  769. }
  770. static int fsi_hw_params(struct snd_pcm_substream *substream,
  771. struct snd_pcm_hw_params *hw_params)
  772. {
  773. return snd_pcm_lib_malloc_pages(substream,
  774. params_buffer_bytes(hw_params));
  775. }
  776. static int fsi_hw_free(struct snd_pcm_substream *substream)
  777. {
  778. return snd_pcm_lib_free_pages(substream);
  779. }
  780. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  781. {
  782. struct snd_pcm_runtime *runtime = substream->runtime;
  783. struct fsi_priv *fsi = fsi_get_priv(substream);
  784. long location;
  785. location = (fsi->byte_offset - 1);
  786. if (location < 0)
  787. location = 0;
  788. return bytes_to_frames(runtime, location);
  789. }
  790. static struct snd_pcm_ops fsi_pcm_ops = {
  791. .open = fsi_pcm_open,
  792. .ioctl = snd_pcm_lib_ioctl,
  793. .hw_params = fsi_hw_params,
  794. .hw_free = fsi_hw_free,
  795. .pointer = fsi_pointer,
  796. };
  797. /************************************************************************
  798. snd_soc_platform
  799. ************************************************************************/
  800. #define PREALLOC_BUFFER (32 * 1024)
  801. #define PREALLOC_BUFFER_MAX (32 * 1024)
  802. static void fsi_pcm_free(struct snd_pcm *pcm)
  803. {
  804. snd_pcm_lib_preallocate_free_for_all(pcm);
  805. }
  806. static int fsi_pcm_new(struct snd_card *card,
  807. struct snd_soc_dai *dai,
  808. struct snd_pcm *pcm)
  809. {
  810. /*
  811. * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
  812. * in MMAP mode (i.e. aplay -M)
  813. */
  814. return snd_pcm_lib_preallocate_pages_for_all(
  815. pcm,
  816. SNDRV_DMA_TYPE_CONTINUOUS,
  817. snd_dma_continuous_data(GFP_KERNEL),
  818. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  819. }
  820. /************************************************************************
  821. alsa struct
  822. ************************************************************************/
  823. struct snd_soc_dai fsi_soc_dai[] = {
  824. {
  825. .name = "FSIA",
  826. .id = 0,
  827. .playback = {
  828. .rates = FSI_RATES,
  829. .formats = FSI_FMTS,
  830. .channels_min = 1,
  831. .channels_max = 8,
  832. },
  833. .capture = {
  834. .rates = FSI_RATES,
  835. .formats = FSI_FMTS,
  836. .channels_min = 1,
  837. .channels_max = 8,
  838. },
  839. .ops = &fsi_dai_ops,
  840. },
  841. {
  842. .name = "FSIB",
  843. .id = 1,
  844. .playback = {
  845. .rates = FSI_RATES,
  846. .formats = FSI_FMTS,
  847. .channels_min = 1,
  848. .channels_max = 8,
  849. },
  850. .capture = {
  851. .rates = FSI_RATES,
  852. .formats = FSI_FMTS,
  853. .channels_min = 1,
  854. .channels_max = 8,
  855. },
  856. .ops = &fsi_dai_ops,
  857. },
  858. };
  859. EXPORT_SYMBOL_GPL(fsi_soc_dai);
  860. struct snd_soc_platform fsi_soc_platform = {
  861. .name = "fsi-pcm",
  862. .pcm_ops = &fsi_pcm_ops,
  863. .pcm_new = fsi_pcm_new,
  864. .pcm_free = fsi_pcm_free,
  865. };
  866. EXPORT_SYMBOL_GPL(fsi_soc_platform);
  867. /************************************************************************
  868. platform function
  869. ************************************************************************/
  870. static int fsi_probe(struct platform_device *pdev)
  871. {
  872. struct fsi_master *master;
  873. const struct platform_device_id *id_entry;
  874. struct resource *res;
  875. unsigned int irq;
  876. int ret;
  877. id_entry = pdev->id_entry;
  878. if (!id_entry) {
  879. dev_err(&pdev->dev, "unknown fsi device\n");
  880. return -ENODEV;
  881. }
  882. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  883. irq = platform_get_irq(pdev, 0);
  884. if (!res || (int)irq <= 0) {
  885. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  886. ret = -ENODEV;
  887. goto exit;
  888. }
  889. master = kzalloc(sizeof(*master), GFP_KERNEL);
  890. if (!master) {
  891. dev_err(&pdev->dev, "Could not allocate master\n");
  892. ret = -ENOMEM;
  893. goto exit;
  894. }
  895. master->base = ioremap_nocache(res->start, resource_size(res));
  896. if (!master->base) {
  897. ret = -ENXIO;
  898. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  899. goto exit_kfree;
  900. }
  901. /* master setting */
  902. master->irq = irq;
  903. master->info = pdev->dev.platform_data;
  904. master->core = (struct fsi_core *)id_entry->driver_data;
  905. spin_lock_init(&master->lock);
  906. /* FSI A setting */
  907. master->fsia.base = master->base;
  908. master->fsia.master = master;
  909. master->fsia.mst_ctrl = A_MST_CTLR;
  910. /* FSI B setting */
  911. master->fsib.base = master->base + 0x40;
  912. master->fsib.master = master;
  913. master->fsib.mst_ctrl = B_MST_CTLR;
  914. pm_runtime_enable(&pdev->dev);
  915. pm_runtime_resume(&pdev->dev);
  916. fsi_soc_dai[0].dev = &pdev->dev;
  917. fsi_soc_dai[0].private_data = &master->fsia;
  918. fsi_soc_dai[1].dev = &pdev->dev;
  919. fsi_soc_dai[1].private_data = &master->fsib;
  920. fsi_soft_all_reset(master);
  921. ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
  922. id_entry->name, master);
  923. if (ret) {
  924. dev_err(&pdev->dev, "irq request err\n");
  925. goto exit_iounmap;
  926. }
  927. ret = snd_soc_register_platform(&fsi_soc_platform);
  928. if (ret < 0) {
  929. dev_err(&pdev->dev, "cannot snd soc register\n");
  930. goto exit_free_irq;
  931. }
  932. return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  933. exit_free_irq:
  934. free_irq(irq, master);
  935. exit_iounmap:
  936. iounmap(master->base);
  937. pm_runtime_disable(&pdev->dev);
  938. exit_kfree:
  939. kfree(master);
  940. master = NULL;
  941. exit:
  942. return ret;
  943. }
  944. static int fsi_remove(struct platform_device *pdev)
  945. {
  946. struct fsi_master *master;
  947. master = fsi_get_master(fsi_soc_dai[0].private_data);
  948. snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  949. snd_soc_unregister_platform(&fsi_soc_platform);
  950. pm_runtime_disable(&pdev->dev);
  951. free_irq(master->irq, master);
  952. iounmap(master->base);
  953. kfree(master);
  954. fsi_soc_dai[0].dev = NULL;
  955. fsi_soc_dai[0].private_data = NULL;
  956. fsi_soc_dai[1].dev = NULL;
  957. fsi_soc_dai[1].private_data = NULL;
  958. return 0;
  959. }
  960. static int fsi_runtime_nop(struct device *dev)
  961. {
  962. /* Runtime PM callback shared between ->runtime_suspend()
  963. * and ->runtime_resume(). Simply returns success.
  964. *
  965. * This driver re-initializes all registers after
  966. * pm_runtime_get_sync() anyway so there is no need
  967. * to save and restore registers here.
  968. */
  969. return 0;
  970. }
  971. static struct dev_pm_ops fsi_pm_ops = {
  972. .runtime_suspend = fsi_runtime_nop,
  973. .runtime_resume = fsi_runtime_nop,
  974. };
  975. static struct fsi_core fsi1_core = {
  976. .ver = 1,
  977. /* Interrupt */
  978. .int_st = INT_ST,
  979. .iemsk = IEMSK,
  980. .imsk = IMSK,
  981. };
  982. static struct fsi_core fsi2_core = {
  983. .ver = 2,
  984. /* Interrupt */
  985. .int_st = CPU_INT_ST,
  986. .iemsk = CPU_IEMSK,
  987. .imsk = CPU_IMSK,
  988. };
  989. static struct platform_device_id fsi_id_table[] = {
  990. { "sh_fsi", (kernel_ulong_t)&fsi1_core },
  991. { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
  992. };
  993. static struct platform_driver fsi_driver = {
  994. .driver = {
  995. .name = "sh_fsi",
  996. .pm = &fsi_pm_ops,
  997. },
  998. .probe = fsi_probe,
  999. .remove = fsi_remove,
  1000. .id_table = fsi_id_table,
  1001. };
  1002. static int __init fsi_mobile_init(void)
  1003. {
  1004. return platform_driver_register(&fsi_driver);
  1005. }
  1006. static void __exit fsi_mobile_exit(void)
  1007. {
  1008. platform_driver_unregister(&fsi_driver);
  1009. }
  1010. module_init(fsi_mobile_init);
  1011. module_exit(fsi_mobile_exit);
  1012. MODULE_LICENSE("GPL");
  1013. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  1014. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");