omap-mcbsp.c 26 KB

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  1. /*
  2. * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
  3. *
  4. * Copyright (C) 2008 Nokia Corporation
  5. *
  6. * Contact: Jarkko Nikula <jhnikula@gmail.com>
  7. * Peter Ujfalusi <peter.ujfalusi@nokia.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21. * 02110-1301 USA
  22. *
  23. */
  24. #include <linux/init.h>
  25. #include <linux/module.h>
  26. #include <linux/device.h>
  27. #include <sound/core.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/initval.h>
  31. #include <sound/soc.h>
  32. #include <plat/control.h>
  33. #include <plat/dma.h>
  34. #include <plat/mcbsp.h>
  35. #include "omap-mcbsp.h"
  36. #include "omap-pcm.h"
  37. #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
  38. #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  39. xhandler_get, xhandler_put) \
  40. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  41. .info = omap_mcbsp_st_info_volsw, \
  42. .get = xhandler_get, .put = xhandler_put, \
  43. .private_value = (unsigned long) &(struct soc_mixer_control) \
  44. {.min = xmin, .max = xmax} }
  45. struct omap_mcbsp_data {
  46. unsigned int bus_id;
  47. struct omap_mcbsp_reg_cfg regs;
  48. unsigned int fmt;
  49. /*
  50. * Flags indicating is the bus already activated and configured by
  51. * another substream
  52. */
  53. int active;
  54. int configured;
  55. unsigned int in_freq;
  56. int clk_div;
  57. int wlen;
  58. };
  59. #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
  60. static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  61. /*
  62. * Stream DMA parameters. DMA request line and port address are set runtime
  63. * since they are different between OMAP1 and later OMAPs
  64. */
  65. static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  66. #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  67. static const int omap1_dma_reqs[][2] = {
  68. { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  69. { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  70. { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  71. };
  72. static const unsigned long omap1_mcbsp_port[][2] = {
  73. { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  74. OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  75. { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  76. OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  77. { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  78. OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  79. };
  80. #else
  81. static const int omap1_dma_reqs[][2] = {};
  82. static const unsigned long omap1_mcbsp_port[][2] = {};
  83. #endif
  84. #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  85. static const int omap24xx_dma_reqs[][2] = {
  86. { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  87. { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  88. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  89. { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  90. { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  91. { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  92. #endif
  93. };
  94. #else
  95. static const int omap24xx_dma_reqs[][2] = {};
  96. #endif
  97. #if defined(CONFIG_ARCH_OMAP2420)
  98. static const unsigned long omap2420_mcbsp_port[][2] = {
  99. { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  100. OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  101. { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  102. OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  103. };
  104. #else
  105. static const unsigned long omap2420_mcbsp_port[][2] = {};
  106. #endif
  107. #if defined(CONFIG_ARCH_OMAP2430)
  108. static const unsigned long omap2430_mcbsp_port[][2] = {
  109. { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
  110. OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
  111. { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
  112. OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
  113. { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
  114. OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
  115. { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
  116. OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
  117. { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
  118. OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
  119. };
  120. #else
  121. static const unsigned long omap2430_mcbsp_port[][2] = {};
  122. #endif
  123. #if defined(CONFIG_ARCH_OMAP3)
  124. static const unsigned long omap34xx_mcbsp_port[][2] = {
  125. { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
  126. OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
  127. { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
  128. OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
  129. { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
  130. OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
  131. { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
  132. OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
  133. { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
  134. OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
  135. };
  136. #else
  137. static const unsigned long omap34xx_mcbsp_port[][2] = {};
  138. #endif
  139. static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  140. {
  141. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  142. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  143. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  144. struct omap_pcm_dma_data *dma_data;
  145. int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
  146. int words;
  147. dma_data = snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
  148. /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
  149. if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
  150. /*
  151. * Configure McBSP threshold based on either:
  152. * packet_size, when the sDMA is in packet mode, or
  153. * based on the period size.
  154. */
  155. if (dma_data->packet_size)
  156. words = dma_data->packet_size;
  157. else
  158. words = snd_pcm_lib_period_bytes(substream) /
  159. (mcbsp_data->wlen / 8);
  160. else
  161. words = 1;
  162. /* Configure McBSP internal buffer usage */
  163. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  164. omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
  165. else
  166. omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
  167. }
  168. static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  169. struct snd_pcm_hw_rule *rule)
  170. {
  171. struct snd_interval *buffer_size = hw_param_interval(params,
  172. SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  173. struct snd_interval *channels = hw_param_interval(params,
  174. SNDRV_PCM_HW_PARAM_CHANNELS);
  175. struct omap_mcbsp_data *mcbsp_data = rule->private;
  176. struct snd_interval frames;
  177. int size;
  178. snd_interval_any(&frames);
  179. size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
  180. frames.min = size / channels->min;
  181. frames.integer = 1;
  182. return snd_interval_refine(buffer_size, &frames);
  183. }
  184. static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
  185. struct snd_soc_dai *dai)
  186. {
  187. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  188. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  189. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  190. int bus_id = mcbsp_data->bus_id;
  191. int err = 0;
  192. if (!cpu_dai->active)
  193. err = omap_mcbsp_request(bus_id);
  194. /*
  195. * OMAP3 McBSP FIFO is word structured.
  196. * McBSP2 has 1024 + 256 = 1280 word long buffer,
  197. * McBSP1,3,4,5 has 128 word long buffer
  198. * This means that the size of the FIFO depends on the sample format.
  199. * For example on McBSP3:
  200. * 16bit samples: size is 128 * 2 = 256 bytes
  201. * 32bit samples: size is 128 * 4 = 512 bytes
  202. * It is simpler to place constraint for buffer and period based on
  203. * channels.
  204. * McBSP3 as example again (16 or 32 bit samples):
  205. * 1 channel (mono): size is 128 frames (128 words)
  206. * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
  207. * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
  208. */
  209. if (cpu_is_omap343x()) {
  210. /*
  211. * Rule for the buffer size. We should not allow
  212. * smaller buffer than the FIFO size to avoid underruns
  213. */
  214. snd_pcm_hw_rule_add(substream->runtime, 0,
  215. SNDRV_PCM_HW_PARAM_CHANNELS,
  216. omap_mcbsp_hwrule_min_buffersize,
  217. mcbsp_data,
  218. SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
  219. /* Make sure, that the period size is always even */
  220. snd_pcm_hw_constraint_step(substream->runtime, 0,
  221. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
  222. }
  223. return err;
  224. }
  225. static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
  226. struct snd_soc_dai *dai)
  227. {
  228. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  229. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  230. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  231. if (!cpu_dai->active) {
  232. omap_mcbsp_free(mcbsp_data->bus_id);
  233. mcbsp_data->configured = 0;
  234. }
  235. }
  236. static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  237. struct snd_soc_dai *dai)
  238. {
  239. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  240. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  241. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  242. int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  243. switch (cmd) {
  244. case SNDRV_PCM_TRIGGER_START:
  245. case SNDRV_PCM_TRIGGER_RESUME:
  246. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  247. mcbsp_data->active++;
  248. omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
  249. break;
  250. case SNDRV_PCM_TRIGGER_STOP:
  251. case SNDRV_PCM_TRIGGER_SUSPEND:
  252. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  253. omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
  254. mcbsp_data->active--;
  255. break;
  256. default:
  257. err = -EINVAL;
  258. }
  259. return err;
  260. }
  261. static snd_pcm_sframes_t omap_mcbsp_dai_delay(
  262. struct snd_pcm_substream *substream,
  263. struct snd_soc_dai *dai)
  264. {
  265. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  266. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  267. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  268. u16 fifo_use;
  269. snd_pcm_sframes_t delay;
  270. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  271. fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
  272. else
  273. fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
  274. /*
  275. * Divide the used locations with the channel count to get the
  276. * FIFO usage in samples (don't care about partial samples in the
  277. * buffer).
  278. */
  279. delay = fifo_use / substream->runtime->channels;
  280. return delay;
  281. }
  282. static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
  283. struct snd_pcm_hw_params *params,
  284. struct snd_soc_dai *dai)
  285. {
  286. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  287. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  288. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  289. struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
  290. struct omap_pcm_dma_data *dma_data;
  291. int dma, bus_id = mcbsp_data->bus_id;
  292. int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
  293. int pkt_size = 0;
  294. unsigned long port;
  295. unsigned int format, div, framesize, master;
  296. dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
  297. if (cpu_class_is_omap1()) {
  298. dma = omap1_dma_reqs[bus_id][substream->stream];
  299. port = omap1_mcbsp_port[bus_id][substream->stream];
  300. } else if (cpu_is_omap2420()) {
  301. dma = omap24xx_dma_reqs[bus_id][substream->stream];
  302. port = omap2420_mcbsp_port[bus_id][substream->stream];
  303. } else if (cpu_is_omap2430()) {
  304. dma = omap24xx_dma_reqs[bus_id][substream->stream];
  305. port = omap2430_mcbsp_port[bus_id][substream->stream];
  306. } else if (cpu_is_omap343x()) {
  307. dma = omap24xx_dma_reqs[bus_id][substream->stream];
  308. port = omap34xx_mcbsp_port[bus_id][substream->stream];
  309. } else {
  310. return -ENODEV;
  311. }
  312. switch (params_format(params)) {
  313. case SNDRV_PCM_FORMAT_S16_LE:
  314. dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
  315. wlen = 16;
  316. break;
  317. case SNDRV_PCM_FORMAT_S32_LE:
  318. dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
  319. wlen = 32;
  320. break;
  321. default:
  322. return -EINVAL;
  323. }
  324. if (cpu_is_omap343x()) {
  325. dma_data->set_threshold = omap_mcbsp_set_threshold;
  326. /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
  327. if (omap_mcbsp_get_dma_op_mode(bus_id) ==
  328. MCBSP_DMA_MODE_THRESHOLD) {
  329. int period_words, max_thrsh;
  330. period_words = params_period_bytes(params) / (wlen / 8);
  331. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  332. max_thrsh = omap_mcbsp_get_max_tx_threshold(
  333. mcbsp_data->bus_id);
  334. else
  335. max_thrsh = omap_mcbsp_get_max_rx_threshold(
  336. mcbsp_data->bus_id);
  337. /*
  338. * If the period contains less or equal number of words,
  339. * we are using the original threshold mode setup:
  340. * McBSP threshold = sDMA frame size = period_size
  341. * Otherwise we switch to sDMA packet mode:
  342. * McBSP threshold = sDMA packet size
  343. * sDMA frame size = period size
  344. */
  345. if (period_words > max_thrsh) {
  346. int divider = 0;
  347. /*
  348. * Look for the biggest threshold value, which
  349. * divides the period size evenly.
  350. */
  351. divider = period_words / max_thrsh;
  352. if (period_words % max_thrsh)
  353. divider++;
  354. while (period_words % divider &&
  355. divider < period_words)
  356. divider++;
  357. if (divider == period_words)
  358. return -EINVAL;
  359. pkt_size = period_words / divider;
  360. sync_mode = OMAP_DMA_SYNC_PACKET;
  361. } else {
  362. sync_mode = OMAP_DMA_SYNC_FRAME;
  363. }
  364. }
  365. }
  366. dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
  367. dma_data->dma_req = dma;
  368. dma_data->port_addr = port;
  369. dma_data->sync_mode = sync_mode;
  370. dma_data->packet_size = pkt_size;
  371. snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
  372. if (mcbsp_data->configured) {
  373. /* McBSP already configured by another stream */
  374. return 0;
  375. }
  376. format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  377. wpf = channels = params_channels(params);
  378. if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
  379. format == SND_SOC_DAIFMT_LEFT_J)) {
  380. /* Use dual-phase frames */
  381. regs->rcr2 |= RPHASE;
  382. regs->xcr2 |= XPHASE;
  383. /* Set 1 word per (McBSP) frame for phase1 and phase2 */
  384. wpf--;
  385. regs->rcr2 |= RFRLEN2(wpf - 1);
  386. regs->xcr2 |= XFRLEN2(wpf - 1);
  387. }
  388. regs->rcr1 |= RFRLEN1(wpf - 1);
  389. regs->xcr1 |= XFRLEN1(wpf - 1);
  390. switch (params_format(params)) {
  391. case SNDRV_PCM_FORMAT_S16_LE:
  392. /* Set word lengths */
  393. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
  394. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
  395. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
  396. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
  397. break;
  398. case SNDRV_PCM_FORMAT_S32_LE:
  399. /* Set word lengths */
  400. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
  401. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
  402. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
  403. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
  404. break;
  405. default:
  406. /* Unsupported PCM format */
  407. return -EINVAL;
  408. }
  409. /* In McBSP master modes, FRAME (i.e. sample rate) is generated
  410. * by _counting_ BCLKs. Calculate frame size in BCLKs */
  411. master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
  412. if (master == SND_SOC_DAIFMT_CBS_CFS) {
  413. div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
  414. framesize = (mcbsp_data->in_freq / div) / params_rate(params);
  415. if (framesize < wlen * channels) {
  416. printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
  417. "channels\n", __func__);
  418. return -EINVAL;
  419. }
  420. } else
  421. framesize = wlen * channels;
  422. /* Set FS period and length in terms of bit clock periods */
  423. switch (format) {
  424. case SND_SOC_DAIFMT_I2S:
  425. case SND_SOC_DAIFMT_LEFT_J:
  426. regs->srgr2 |= FPER(framesize - 1);
  427. regs->srgr1 |= FWID((framesize >> 1) - 1);
  428. break;
  429. case SND_SOC_DAIFMT_DSP_A:
  430. case SND_SOC_DAIFMT_DSP_B:
  431. regs->srgr2 |= FPER(framesize - 1);
  432. regs->srgr1 |= FWID(0);
  433. break;
  434. }
  435. omap_mcbsp_config(bus_id, &mcbsp_data->regs);
  436. mcbsp_data->wlen = wlen;
  437. mcbsp_data->configured = 1;
  438. return 0;
  439. }
  440. /*
  441. * This must be called before _set_clkdiv and _set_sysclk since McBSP register
  442. * cache is initialized here
  443. */
  444. static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  445. unsigned int fmt)
  446. {
  447. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  448. struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
  449. unsigned int temp_fmt = fmt;
  450. if (mcbsp_data->configured)
  451. return 0;
  452. mcbsp_data->fmt = fmt;
  453. memset(regs, 0, sizeof(*regs));
  454. /* Generic McBSP register settings */
  455. regs->spcr2 |= XINTM(3) | FREE;
  456. regs->spcr1 |= RINTM(3);
  457. /* RFIG and XFIG are not defined in 34xx */
  458. if (!cpu_is_omap34xx()) {
  459. regs->rcr2 |= RFIG;
  460. regs->xcr2 |= XFIG;
  461. }
  462. if (cpu_is_omap2430() || cpu_is_omap34xx()) {
  463. regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
  464. regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
  465. }
  466. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  467. case SND_SOC_DAIFMT_I2S:
  468. /* 1-bit data delay */
  469. regs->rcr2 |= RDATDLY(1);
  470. regs->xcr2 |= XDATDLY(1);
  471. break;
  472. case SND_SOC_DAIFMT_LEFT_J:
  473. /* 0-bit data delay */
  474. regs->rcr2 |= RDATDLY(0);
  475. regs->xcr2 |= XDATDLY(0);
  476. regs->spcr1 |= RJUST(2);
  477. /* Invert FS polarity configuration */
  478. temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
  479. break;
  480. case SND_SOC_DAIFMT_DSP_A:
  481. /* 1-bit data delay */
  482. regs->rcr2 |= RDATDLY(1);
  483. regs->xcr2 |= XDATDLY(1);
  484. /* Invert FS polarity configuration */
  485. temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
  486. break;
  487. case SND_SOC_DAIFMT_DSP_B:
  488. /* 0-bit data delay */
  489. regs->rcr2 |= RDATDLY(0);
  490. regs->xcr2 |= XDATDLY(0);
  491. /* Invert FS polarity configuration */
  492. temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
  493. break;
  494. default:
  495. /* Unsupported data format */
  496. return -EINVAL;
  497. }
  498. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  499. case SND_SOC_DAIFMT_CBS_CFS:
  500. /* McBSP master. Set FS and bit clocks as outputs */
  501. regs->pcr0 |= FSXM | FSRM |
  502. CLKXM | CLKRM;
  503. /* Sample rate generator drives the FS */
  504. regs->srgr2 |= FSGM;
  505. break;
  506. case SND_SOC_DAIFMT_CBM_CFM:
  507. /* McBSP slave */
  508. break;
  509. default:
  510. /* Unsupported master/slave configuration */
  511. return -EINVAL;
  512. }
  513. /* Set bit clock (CLKX/CLKR) and FS polarities */
  514. switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
  515. case SND_SOC_DAIFMT_NB_NF:
  516. /*
  517. * Normal BCLK + FS.
  518. * FS active low. TX data driven on falling edge of bit clock
  519. * and RX data sampled on rising edge of bit clock.
  520. */
  521. regs->pcr0 |= FSXP | FSRP |
  522. CLKXP | CLKRP;
  523. break;
  524. case SND_SOC_DAIFMT_NB_IF:
  525. regs->pcr0 |= CLKXP | CLKRP;
  526. break;
  527. case SND_SOC_DAIFMT_IB_NF:
  528. regs->pcr0 |= FSXP | FSRP;
  529. break;
  530. case SND_SOC_DAIFMT_IB_IF:
  531. break;
  532. default:
  533. return -EINVAL;
  534. }
  535. return 0;
  536. }
  537. static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  538. int div_id, int div)
  539. {
  540. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  541. struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
  542. if (div_id != OMAP_MCBSP_CLKGDV)
  543. return -ENODEV;
  544. mcbsp_data->clk_div = div;
  545. regs->srgr1 |= CLKGDV(div - 1);
  546. return 0;
  547. }
  548. static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
  549. int clk_id)
  550. {
  551. int sel_bit;
  552. u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
  553. if (cpu_class_is_omap1()) {
  554. /* OMAP1's can use only external source clock */
  555. if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
  556. return -EINVAL;
  557. else
  558. return 0;
  559. }
  560. if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
  561. return -EINVAL;
  562. if (cpu_is_omap343x())
  563. reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
  564. switch (mcbsp_data->bus_id) {
  565. case 0:
  566. reg = OMAP2_CONTROL_DEVCONF0;
  567. sel_bit = 2;
  568. break;
  569. case 1:
  570. reg = OMAP2_CONTROL_DEVCONF0;
  571. sel_bit = 6;
  572. break;
  573. case 2:
  574. reg = reg_devconf1;
  575. sel_bit = 0;
  576. break;
  577. case 3:
  578. reg = reg_devconf1;
  579. sel_bit = 2;
  580. break;
  581. case 4:
  582. reg = reg_devconf1;
  583. sel_bit = 4;
  584. break;
  585. default:
  586. return -EINVAL;
  587. }
  588. if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
  589. omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
  590. else
  591. omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
  592. return 0;
  593. }
  594. static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
  595. int clk_id)
  596. {
  597. int sel_bit, set = 0;
  598. u16 reg = OMAP2_CONTROL_DEVCONF0;
  599. if (cpu_class_is_omap1())
  600. return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
  601. if (mcbsp_data->bus_id != 0)
  602. return -EINVAL;
  603. switch (clk_id) {
  604. case OMAP_MCBSP_CLKR_SRC_CLKX:
  605. set = 1;
  606. case OMAP_MCBSP_CLKR_SRC_CLKR:
  607. sel_bit = 3;
  608. break;
  609. case OMAP_MCBSP_FSR_SRC_FSX:
  610. set = 1;
  611. case OMAP_MCBSP_FSR_SRC_FSR:
  612. sel_bit = 4;
  613. break;
  614. default:
  615. return -EINVAL;
  616. }
  617. if (set)
  618. omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
  619. else
  620. omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
  621. return 0;
  622. }
  623. static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  624. int clk_id, unsigned int freq,
  625. int dir)
  626. {
  627. struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
  628. struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
  629. int err = 0;
  630. mcbsp_data->in_freq = freq;
  631. switch (clk_id) {
  632. case OMAP_MCBSP_SYSCLK_CLK:
  633. regs->srgr2 |= CLKSM;
  634. break;
  635. case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
  636. case OMAP_MCBSP_SYSCLK_CLKS_EXT:
  637. err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
  638. break;
  639. case OMAP_MCBSP_SYSCLK_CLKX_EXT:
  640. regs->srgr2 |= CLKSM;
  641. case OMAP_MCBSP_SYSCLK_CLKR_EXT:
  642. regs->pcr0 |= SCLKME;
  643. break;
  644. case OMAP_MCBSP_CLKR_SRC_CLKR:
  645. case OMAP_MCBSP_CLKR_SRC_CLKX:
  646. case OMAP_MCBSP_FSR_SRC_FSR:
  647. case OMAP_MCBSP_FSR_SRC_FSX:
  648. err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
  649. break;
  650. default:
  651. err = -ENODEV;
  652. }
  653. return err;
  654. }
  655. static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
  656. .startup = omap_mcbsp_dai_startup,
  657. .shutdown = omap_mcbsp_dai_shutdown,
  658. .trigger = omap_mcbsp_dai_trigger,
  659. .delay = omap_mcbsp_dai_delay,
  660. .hw_params = omap_mcbsp_dai_hw_params,
  661. .set_fmt = omap_mcbsp_dai_set_dai_fmt,
  662. .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
  663. .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
  664. };
  665. #define OMAP_MCBSP_DAI_BUILDER(link_id) \
  666. { \
  667. .name = "omap-mcbsp-dai-"#link_id, \
  668. .id = (link_id), \
  669. .playback = { \
  670. .channels_min = 1, \
  671. .channels_max = 16, \
  672. .rates = OMAP_MCBSP_RATES, \
  673. .formats = SNDRV_PCM_FMTBIT_S16_LE | \
  674. SNDRV_PCM_FMTBIT_S32_LE, \
  675. }, \
  676. .capture = { \
  677. .channels_min = 1, \
  678. .channels_max = 16, \
  679. .rates = OMAP_MCBSP_RATES, \
  680. .formats = SNDRV_PCM_FMTBIT_S16_LE | \
  681. SNDRV_PCM_FMTBIT_S32_LE, \
  682. }, \
  683. .ops = &omap_mcbsp_dai_ops, \
  684. .private_data = &mcbsp_data[(link_id)].bus_id, \
  685. }
  686. struct snd_soc_dai omap_mcbsp_dai[] = {
  687. OMAP_MCBSP_DAI_BUILDER(0),
  688. OMAP_MCBSP_DAI_BUILDER(1),
  689. #if NUM_LINKS >= 3
  690. OMAP_MCBSP_DAI_BUILDER(2),
  691. #endif
  692. #if NUM_LINKS == 5
  693. OMAP_MCBSP_DAI_BUILDER(3),
  694. OMAP_MCBSP_DAI_BUILDER(4),
  695. #endif
  696. };
  697. EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
  698. int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
  699. struct snd_ctl_elem_info *uinfo)
  700. {
  701. struct soc_mixer_control *mc =
  702. (struct soc_mixer_control *)kcontrol->private_value;
  703. int max = mc->max;
  704. int min = mc->min;
  705. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  706. uinfo->count = 1;
  707. uinfo->value.integer.min = min;
  708. uinfo->value.integer.max = max;
  709. return 0;
  710. }
  711. #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
  712. static int \
  713. omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
  714. struct snd_ctl_elem_value *uc) \
  715. { \
  716. struct soc_mixer_control *mc = \
  717. (struct soc_mixer_control *)kc->private_value; \
  718. int max = mc->max; \
  719. int min = mc->min; \
  720. int val = uc->value.integer.value[0]; \
  721. \
  722. if (val < min || val > max) \
  723. return -EINVAL; \
  724. \
  725. /* OMAP McBSP implementation uses index values 0..4 */ \
  726. return omap_st_set_chgain((id)-1, channel, val); \
  727. }
  728. #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
  729. static int \
  730. omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
  731. struct snd_ctl_elem_value *uc) \
  732. { \
  733. s16 chgain; \
  734. \
  735. if (omap_st_get_chgain((id)-1, channel, &chgain)) \
  736. return -EAGAIN; \
  737. \
  738. uc->value.integer.value[0] = chgain; \
  739. return 0; \
  740. }
  741. OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
  742. OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
  743. OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
  744. OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
  745. OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
  746. OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
  747. OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
  748. OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
  749. static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
  750. struct snd_ctl_elem_value *ucontrol)
  751. {
  752. struct soc_mixer_control *mc =
  753. (struct soc_mixer_control *)kcontrol->private_value;
  754. u8 value = ucontrol->value.integer.value[0];
  755. if (value == omap_st_is_enabled(mc->reg))
  756. return 0;
  757. if (value)
  758. omap_st_enable(mc->reg);
  759. else
  760. omap_st_disable(mc->reg);
  761. return 1;
  762. }
  763. static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
  764. struct snd_ctl_elem_value *ucontrol)
  765. {
  766. struct soc_mixer_control *mc =
  767. (struct soc_mixer_control *)kcontrol->private_value;
  768. ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
  769. return 0;
  770. }
  771. static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
  772. SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
  773. omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
  774. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
  775. -32768, 32767,
  776. omap_mcbsp2_get_st_ch0_volume,
  777. omap_mcbsp2_set_st_ch0_volume),
  778. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
  779. -32768, 32767,
  780. omap_mcbsp2_get_st_ch1_volume,
  781. omap_mcbsp2_set_st_ch1_volume),
  782. };
  783. static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
  784. SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
  785. omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
  786. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
  787. -32768, 32767,
  788. omap_mcbsp3_get_st_ch0_volume,
  789. omap_mcbsp3_set_st_ch0_volume),
  790. OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
  791. -32768, 32767,
  792. omap_mcbsp3_get_st_ch1_volume,
  793. omap_mcbsp3_set_st_ch1_volume),
  794. };
  795. int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
  796. {
  797. if (!cpu_is_omap34xx())
  798. return -ENODEV;
  799. switch (mcbsp_id) {
  800. case 1: /* McBSP 2 */
  801. return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
  802. ARRAY_SIZE(omap_mcbsp2_st_controls));
  803. case 2: /* McBSP 3 */
  804. return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
  805. ARRAY_SIZE(omap_mcbsp3_st_controls));
  806. default:
  807. break;
  808. }
  809. return -EINVAL;
  810. }
  811. EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
  812. static int __init snd_omap_mcbsp_init(void)
  813. {
  814. return snd_soc_register_dais(omap_mcbsp_dai,
  815. ARRAY_SIZE(omap_mcbsp_dai));
  816. }
  817. module_init(snd_omap_mcbsp_init);
  818. static void __exit snd_omap_mcbsp_exit(void)
  819. {
  820. snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
  821. }
  822. module_exit(snd_omap_mcbsp_exit);
  823. MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
  824. MODULE_DESCRIPTION("OMAP I2S SoC Interface");
  825. MODULE_LICENSE("GPL");