imx-ssi.c 18 KB

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  1. /*
  2. * imx-ssi.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
  5. *
  6. * This code is based on code copyrighted by Freescale,
  7. * Liam Girdwood, Javier Martin and probably others.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. *
  15. * The i.MX SSI core has some nasty limitations in AC97 mode. While most
  16. * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
  17. * one FIFO which combines all valid receive slots. We cannot even select
  18. * which slots we want to receive. The WM9712 with which this driver
  19. * was developped with always sends GPIO status data in slot 12 which
  20. * we receive in our (PCM-) data stream. The only chance we have is to
  21. * manually skip this data in the FIQ handler. With sampling rates different
  22. * from 48000Hz not every frame has valid receive data, so the ratio
  23. * between pcm data and GPIO status data changes. Our FIQ handler is not
  24. * able to handle this, hence this driver only works with 48000Hz sampling
  25. * rate.
  26. * Reading and writing AC97 registers is another challenge. The core
  27. * provides us status bits when the read register is updated with *another*
  28. * value. When we read the same register two times (and the register still
  29. * contains the same value) these status bits are not set. We work
  30. * around this by not polling these bits but only wait a fixed delay.
  31. *
  32. */
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/device.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/init.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/module.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/slab.h>
  42. #include <sound/core.h>
  43. #include <sound/initval.h>
  44. #include <sound/pcm.h>
  45. #include <sound/pcm_params.h>
  46. #include <sound/soc.h>
  47. #include <mach/ssi.h>
  48. #include <mach/hardware.h>
  49. #include "imx-ssi.h"
  50. #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
  51. /*
  52. * SSI Network Mode or TDM slots configuration.
  53. * Should only be called when port is inactive (i.e. SSIEN = 0).
  54. */
  55. static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
  56. unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
  57. {
  58. struct imx_ssi *ssi = cpu_dai->private_data;
  59. u32 sccr;
  60. sccr = readl(ssi->base + SSI_STCCR);
  61. sccr &= ~SSI_STCCR_DC_MASK;
  62. sccr |= SSI_STCCR_DC(slots - 1);
  63. writel(sccr, ssi->base + SSI_STCCR);
  64. sccr = readl(ssi->base + SSI_SRCCR);
  65. sccr &= ~SSI_STCCR_DC_MASK;
  66. sccr |= SSI_STCCR_DC(slots - 1);
  67. writel(sccr, ssi->base + SSI_SRCCR);
  68. writel(tx_mask, ssi->base + SSI_STMSK);
  69. writel(rx_mask, ssi->base + SSI_SRMSK);
  70. return 0;
  71. }
  72. /*
  73. * SSI DAI format configuration.
  74. * Should only be called when port is inactive (i.e. SSIEN = 0).
  75. */
  76. static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  77. {
  78. struct imx_ssi *ssi = cpu_dai->private_data;
  79. u32 strcr = 0, scr;
  80. scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
  81. /* DAI mode */
  82. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  83. case SND_SOC_DAIFMT_I2S:
  84. /* data on rising edge of bclk, frame low 1clk before data */
  85. strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
  86. scr |= SSI_SCR_NET;
  87. if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
  88. scr &= ~SSI_I2S_MODE_MASK;
  89. scr |= SSI_SCR_I2S_MODE_SLAVE;
  90. }
  91. break;
  92. case SND_SOC_DAIFMT_LEFT_J:
  93. /* data on rising edge of bclk, frame high with data */
  94. strcr |= SSI_STCR_TXBIT0;
  95. break;
  96. case SND_SOC_DAIFMT_DSP_B:
  97. /* data on rising edge of bclk, frame high with data */
  98. strcr |= SSI_STCR_TFSL;
  99. break;
  100. case SND_SOC_DAIFMT_DSP_A:
  101. /* data on rising edge of bclk, frame high 1clk before data */
  102. strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
  103. break;
  104. }
  105. /* DAI clock inversion */
  106. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  107. case SND_SOC_DAIFMT_IB_IF:
  108. strcr |= SSI_STCR_TFSI;
  109. strcr &= ~SSI_STCR_TSCKP;
  110. break;
  111. case SND_SOC_DAIFMT_IB_NF:
  112. strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
  113. break;
  114. case SND_SOC_DAIFMT_NB_IF:
  115. strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
  116. break;
  117. case SND_SOC_DAIFMT_NB_NF:
  118. strcr &= ~SSI_STCR_TFSI;
  119. strcr |= SSI_STCR_TSCKP;
  120. break;
  121. }
  122. /* DAI clock master masks */
  123. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  124. case SND_SOC_DAIFMT_CBM_CFM:
  125. break;
  126. default:
  127. /* Master mode not implemented, needs handling of clocks. */
  128. return -EINVAL;
  129. }
  130. strcr |= SSI_STCR_TFEN0;
  131. if (ssi->flags & IMX_SSI_NET)
  132. scr |= SSI_SCR_NET;
  133. if (ssi->flags & IMX_SSI_SYN)
  134. scr |= SSI_SCR_SYN;
  135. writel(strcr, ssi->base + SSI_STCR);
  136. writel(strcr, ssi->base + SSI_SRCR);
  137. writel(scr, ssi->base + SSI_SCR);
  138. return 0;
  139. }
  140. /*
  141. * SSI system clock configuration.
  142. * Should only be called when port is inactive (i.e. SSIEN = 0).
  143. */
  144. static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  145. int clk_id, unsigned int freq, int dir)
  146. {
  147. struct imx_ssi *ssi = cpu_dai->private_data;
  148. u32 scr;
  149. scr = readl(ssi->base + SSI_SCR);
  150. switch (clk_id) {
  151. case IMX_SSP_SYS_CLK:
  152. if (dir == SND_SOC_CLOCK_OUT)
  153. scr |= SSI_SCR_SYS_CLK_EN;
  154. else
  155. scr &= ~SSI_SCR_SYS_CLK_EN;
  156. break;
  157. default:
  158. return -EINVAL;
  159. }
  160. writel(scr, ssi->base + SSI_SCR);
  161. return 0;
  162. }
  163. /*
  164. * SSI Clock dividers
  165. * Should only be called when port is inactive (i.e. SSIEN = 0).
  166. */
  167. static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
  168. int div_id, int div)
  169. {
  170. struct imx_ssi *ssi = cpu_dai->private_data;
  171. u32 stccr, srccr;
  172. stccr = readl(ssi->base + SSI_STCCR);
  173. srccr = readl(ssi->base + SSI_SRCCR);
  174. switch (div_id) {
  175. case IMX_SSI_TX_DIV_2:
  176. stccr &= ~SSI_STCCR_DIV2;
  177. stccr |= div;
  178. break;
  179. case IMX_SSI_TX_DIV_PSR:
  180. stccr &= ~SSI_STCCR_PSR;
  181. stccr |= div;
  182. break;
  183. case IMX_SSI_TX_DIV_PM:
  184. stccr &= ~0xff;
  185. stccr |= SSI_STCCR_PM(div);
  186. break;
  187. case IMX_SSI_RX_DIV_2:
  188. stccr &= ~SSI_STCCR_DIV2;
  189. stccr |= div;
  190. break;
  191. case IMX_SSI_RX_DIV_PSR:
  192. stccr &= ~SSI_STCCR_PSR;
  193. stccr |= div;
  194. break;
  195. case IMX_SSI_RX_DIV_PM:
  196. stccr &= ~0xff;
  197. stccr |= SSI_STCCR_PM(div);
  198. break;
  199. default:
  200. return -EINVAL;
  201. }
  202. writel(stccr, ssi->base + SSI_STCCR);
  203. writel(srccr, ssi->base + SSI_SRCCR);
  204. return 0;
  205. }
  206. /*
  207. * Should only be called when port is inactive (i.e. SSIEN = 0),
  208. * although can be called multiple times by upper layers.
  209. */
  210. static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
  211. struct snd_pcm_hw_params *params,
  212. struct snd_soc_dai *cpu_dai)
  213. {
  214. struct imx_ssi *ssi = cpu_dai->private_data;
  215. struct imx_pcm_dma_params *dma_data;
  216. u32 reg, sccr;
  217. /* Tx/Rx config */
  218. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  219. reg = SSI_STCCR;
  220. dma_data = &ssi->dma_params_tx;
  221. } else {
  222. reg = SSI_SRCCR;
  223. dma_data = &ssi->dma_params_rx;
  224. }
  225. if (ssi->flags & IMX_SSI_SYN)
  226. reg = SSI_STCCR;
  227. snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
  228. sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
  229. /* DAI data (word) size */
  230. switch (params_format(params)) {
  231. case SNDRV_PCM_FORMAT_S16_LE:
  232. sccr |= SSI_SRCCR_WL(16);
  233. break;
  234. case SNDRV_PCM_FORMAT_S20_3LE:
  235. sccr |= SSI_SRCCR_WL(20);
  236. break;
  237. case SNDRV_PCM_FORMAT_S24_LE:
  238. sccr |= SSI_SRCCR_WL(24);
  239. break;
  240. }
  241. writel(sccr, ssi->base + reg);
  242. return 0;
  243. }
  244. static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
  245. struct snd_soc_dai *dai)
  246. {
  247. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  248. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  249. struct imx_ssi *ssi = cpu_dai->private_data;
  250. unsigned int sier_bits, sier;
  251. unsigned int scr;
  252. scr = readl(ssi->base + SSI_SCR);
  253. sier = readl(ssi->base + SSI_SIER);
  254. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  255. if (ssi->flags & IMX_SSI_DMA)
  256. sier_bits = SSI_SIER_TDMAE;
  257. else
  258. sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
  259. } else {
  260. if (ssi->flags & IMX_SSI_DMA)
  261. sier_bits = SSI_SIER_RDMAE;
  262. else
  263. sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
  264. }
  265. switch (cmd) {
  266. case SNDRV_PCM_TRIGGER_START:
  267. case SNDRV_PCM_TRIGGER_RESUME:
  268. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  269. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  270. scr |= SSI_SCR_TE;
  271. else
  272. scr |= SSI_SCR_RE;
  273. sier |= sier_bits;
  274. if (++ssi->enabled == 1)
  275. scr |= SSI_SCR_SSIEN;
  276. break;
  277. case SNDRV_PCM_TRIGGER_STOP:
  278. case SNDRV_PCM_TRIGGER_SUSPEND:
  279. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  280. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  281. scr &= ~SSI_SCR_TE;
  282. else
  283. scr &= ~SSI_SCR_RE;
  284. sier &= ~sier_bits;
  285. if (--ssi->enabled == 0)
  286. scr &= ~SSI_SCR_SSIEN;
  287. break;
  288. default:
  289. return -EINVAL;
  290. }
  291. if (!(ssi->flags & IMX_SSI_USE_AC97))
  292. /* rx/tx are always enabled to access ac97 registers */
  293. writel(scr, ssi->base + SSI_SCR);
  294. writel(sier, ssi->base + SSI_SIER);
  295. return 0;
  296. }
  297. static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
  298. .hw_params = imx_ssi_hw_params,
  299. .set_fmt = imx_ssi_set_dai_fmt,
  300. .set_clkdiv = imx_ssi_set_dai_clkdiv,
  301. .set_sysclk = imx_ssi_set_dai_sysclk,
  302. .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
  303. .trigger = imx_ssi_trigger,
  304. };
  305. static struct snd_soc_dai imx_ssi_dai = {
  306. .playback = {
  307. .channels_min = 2,
  308. .channels_max = 2,
  309. .rates = SNDRV_PCM_RATE_8000_96000,
  310. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  311. },
  312. .capture = {
  313. .channels_min = 2,
  314. .channels_max = 2,
  315. .rates = SNDRV_PCM_RATE_8000_96000,
  316. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  317. },
  318. .ops = &imx_ssi_pcm_dai_ops,
  319. };
  320. int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
  321. struct vm_area_struct *vma)
  322. {
  323. struct snd_pcm_runtime *runtime = substream->runtime;
  324. int ret;
  325. ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
  326. runtime->dma_addr, runtime->dma_bytes);
  327. pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
  328. runtime->dma_area,
  329. runtime->dma_addr,
  330. runtime->dma_bytes);
  331. return ret;
  332. }
  333. static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
  334. {
  335. struct snd_pcm_substream *substream = pcm->streams[stream].substream;
  336. struct snd_dma_buffer *buf = &substream->dma_buffer;
  337. size_t size = IMX_SSI_DMABUF_SIZE;
  338. buf->dev.type = SNDRV_DMA_TYPE_DEV;
  339. buf->dev.dev = pcm->card->dev;
  340. buf->private_data = NULL;
  341. buf->area = dma_alloc_writecombine(pcm->card->dev, size,
  342. &buf->addr, GFP_KERNEL);
  343. if (!buf->area)
  344. return -ENOMEM;
  345. buf->bytes = size;
  346. return 0;
  347. }
  348. static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
  349. int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
  350. struct snd_pcm *pcm)
  351. {
  352. int ret = 0;
  353. if (!card->dev->dma_mask)
  354. card->dev->dma_mask = &imx_pcm_dmamask;
  355. if (!card->dev->coherent_dma_mask)
  356. card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
  357. if (dai->playback.channels_min) {
  358. ret = imx_pcm_preallocate_dma_buffer(pcm,
  359. SNDRV_PCM_STREAM_PLAYBACK);
  360. if (ret)
  361. goto out;
  362. }
  363. if (dai->capture.channels_min) {
  364. ret = imx_pcm_preallocate_dma_buffer(pcm,
  365. SNDRV_PCM_STREAM_CAPTURE);
  366. if (ret)
  367. goto out;
  368. }
  369. out:
  370. return ret;
  371. }
  372. void imx_pcm_free(struct snd_pcm *pcm)
  373. {
  374. struct snd_pcm_substream *substream;
  375. struct snd_dma_buffer *buf;
  376. int stream;
  377. for (stream = 0; stream < 2; stream++) {
  378. substream = pcm->streams[stream].substream;
  379. if (!substream)
  380. continue;
  381. buf = &substream->dma_buffer;
  382. if (!buf->area)
  383. continue;
  384. dma_free_writecombine(pcm->card->dev, buf->bytes,
  385. buf->area, buf->addr);
  386. buf->area = NULL;
  387. }
  388. }
  389. struct snd_soc_platform imx_soc_platform = {
  390. .name = "imx-audio",
  391. };
  392. EXPORT_SYMBOL_GPL(imx_soc_platform);
  393. static struct snd_soc_dai imx_ac97_dai = {
  394. .name = "AC97",
  395. .ac97_control = 1,
  396. .playback = {
  397. .stream_name = "AC97 Playback",
  398. .channels_min = 2,
  399. .channels_max = 2,
  400. .rates = SNDRV_PCM_RATE_48000,
  401. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  402. },
  403. .capture = {
  404. .stream_name = "AC97 Capture",
  405. .channels_min = 2,
  406. .channels_max = 2,
  407. .rates = SNDRV_PCM_RATE_48000,
  408. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  409. },
  410. .ops = &imx_ssi_pcm_dai_ops,
  411. };
  412. static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
  413. {
  414. void __iomem *base = imx_ssi->base;
  415. writel(0x0, base + SSI_SCR);
  416. writel(0x0, base + SSI_STCR);
  417. writel(0x0, base + SSI_SRCR);
  418. writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
  419. writel(SSI_SFCSR_RFWM0(8) |
  420. SSI_SFCSR_TFWM0(8) |
  421. SSI_SFCSR_RFWM1(8) |
  422. SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
  423. writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
  424. writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
  425. writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
  426. writel(SSI_SOR_WAIT(3), base + SSI_SOR);
  427. writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
  428. SSI_SCR_TE | SSI_SCR_RE,
  429. base + SSI_SCR);
  430. writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
  431. writel(0xff, base + SSI_SACCDIS);
  432. writel(0x300, base + SSI_SACCEN);
  433. }
  434. static struct imx_ssi *ac97_ssi;
  435. static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  436. unsigned short val)
  437. {
  438. struct imx_ssi *imx_ssi = ac97_ssi;
  439. void __iomem *base = imx_ssi->base;
  440. unsigned int lreg;
  441. unsigned int lval;
  442. if (reg > 0x7f)
  443. return;
  444. pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
  445. lreg = reg << 12;
  446. writel(lreg, base + SSI_SACADD);
  447. lval = val << 4;
  448. writel(lval , base + SSI_SACDAT);
  449. writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
  450. udelay(100);
  451. }
  452. static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
  453. unsigned short reg)
  454. {
  455. struct imx_ssi *imx_ssi = ac97_ssi;
  456. void __iomem *base = imx_ssi->base;
  457. unsigned short val = -1;
  458. unsigned int lreg;
  459. lreg = (reg & 0x7f) << 12 ;
  460. writel(lreg, base + SSI_SACADD);
  461. writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
  462. udelay(100);
  463. val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
  464. pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
  465. return val;
  466. }
  467. static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
  468. {
  469. struct imx_ssi *imx_ssi = ac97_ssi;
  470. if (imx_ssi->ac97_reset)
  471. imx_ssi->ac97_reset(ac97);
  472. }
  473. static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
  474. {
  475. struct imx_ssi *imx_ssi = ac97_ssi;
  476. if (imx_ssi->ac97_warm_reset)
  477. imx_ssi->ac97_warm_reset(ac97);
  478. }
  479. struct snd_ac97_bus_ops soc_ac97_ops = {
  480. .read = imx_ssi_ac97_read,
  481. .write = imx_ssi_ac97_write,
  482. .reset = imx_ssi_ac97_reset,
  483. .warm_reset = imx_ssi_ac97_warm_reset
  484. };
  485. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  486. struct snd_soc_dai imx_ssi_pcm_dai[2];
  487. EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
  488. static int imx_ssi_probe(struct platform_device *pdev)
  489. {
  490. struct resource *res;
  491. struct imx_ssi *ssi;
  492. struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
  493. struct snd_soc_platform *platform;
  494. int ret = 0;
  495. unsigned int val;
  496. struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
  497. if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
  498. return -EINVAL;
  499. ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
  500. if (!ssi)
  501. return -ENOMEM;
  502. if (pdata) {
  503. ssi->ac97_reset = pdata->ac97_reset;
  504. ssi->ac97_warm_reset = pdata->ac97_warm_reset;
  505. ssi->flags = pdata->flags;
  506. }
  507. ssi->irq = platform_get_irq(pdev, 0);
  508. ssi->clk = clk_get(&pdev->dev, NULL);
  509. if (IS_ERR(ssi->clk)) {
  510. ret = PTR_ERR(ssi->clk);
  511. dev_err(&pdev->dev, "Cannot get the clock: %d\n",
  512. ret);
  513. goto failed_clk;
  514. }
  515. clk_enable(ssi->clk);
  516. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  517. if (!res) {
  518. ret = -ENODEV;
  519. goto failed_get_resource;
  520. }
  521. if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
  522. dev_err(&pdev->dev, "request_mem_region failed\n");
  523. ret = -EBUSY;
  524. goto failed_get_resource;
  525. }
  526. ssi->base = ioremap(res->start, resource_size(res));
  527. if (!ssi->base) {
  528. dev_err(&pdev->dev, "ioremap failed\n");
  529. ret = -ENODEV;
  530. goto failed_ioremap;
  531. }
  532. if (ssi->flags & IMX_SSI_USE_AC97) {
  533. if (ac97_ssi) {
  534. ret = -EBUSY;
  535. goto failed_ac97;
  536. }
  537. ac97_ssi = ssi;
  538. setup_channel_to_ac97(ssi);
  539. memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
  540. } else
  541. memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
  542. writel(0x0, ssi->base + SSI_SIER);
  543. ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
  544. ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
  545. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
  546. if (res)
  547. ssi->dma_params_tx.dma = res->start;
  548. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
  549. if (res)
  550. ssi->dma_params_rx.dma = res->start;
  551. dai->id = pdev->id;
  552. dai->dev = &pdev->dev;
  553. dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
  554. dai->private_data = ssi;
  555. if ((cpu_is_mx27() || cpu_is_mx21()) &&
  556. !(ssi->flags & IMX_SSI_USE_AC97) &&
  557. (ssi->flags & IMX_SSI_DMA)) {
  558. ssi->flags |= IMX_SSI_DMA;
  559. platform = imx_ssi_dma_mx2_init(pdev, ssi);
  560. } else
  561. platform = imx_ssi_fiq_init(pdev, ssi);
  562. imx_soc_platform.pcm_ops = platform->pcm_ops;
  563. imx_soc_platform.pcm_new = platform->pcm_new;
  564. imx_soc_platform.pcm_free = platform->pcm_free;
  565. val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
  566. SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
  567. writel(val, ssi->base + SSI_SFCSR);
  568. ret = snd_soc_register_dai(dai);
  569. if (ret) {
  570. dev_err(&pdev->dev, "register DAI failed\n");
  571. goto failed_register;
  572. }
  573. platform_set_drvdata(pdev, ssi);
  574. return 0;
  575. failed_register:
  576. failed_ac97:
  577. iounmap(ssi->base);
  578. failed_ioremap:
  579. release_mem_region(res->start, resource_size(res));
  580. failed_get_resource:
  581. clk_disable(ssi->clk);
  582. clk_put(ssi->clk);
  583. failed_clk:
  584. kfree(ssi);
  585. return ret;
  586. }
  587. static int __devexit imx_ssi_remove(struct platform_device *pdev)
  588. {
  589. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  590. struct imx_ssi *ssi = platform_get_drvdata(pdev);
  591. struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
  592. snd_soc_unregister_dai(dai);
  593. if (ssi->flags & IMX_SSI_USE_AC97)
  594. ac97_ssi = NULL;
  595. if (!(ssi->flags & IMX_SSI_DMA))
  596. imx_ssi_fiq_exit(pdev, ssi);
  597. iounmap(ssi->base);
  598. release_mem_region(res->start, resource_size(res));
  599. clk_disable(ssi->clk);
  600. clk_put(ssi->clk);
  601. kfree(ssi);
  602. return 0;
  603. }
  604. static struct platform_driver imx_ssi_driver = {
  605. .probe = imx_ssi_probe,
  606. .remove = __devexit_p(imx_ssi_remove),
  607. .driver = {
  608. .name = DRV_NAME,
  609. .owner = THIS_MODULE,
  610. },
  611. };
  612. static int __init imx_ssi_init(void)
  613. {
  614. int ret;
  615. ret = snd_soc_register_platform(&imx_soc_platform);
  616. if (ret) {
  617. pr_err("failed to register soc platform: %d\n", ret);
  618. return ret;
  619. }
  620. ret = platform_driver_register(&imx_ssi_driver);
  621. if (ret) {
  622. snd_soc_unregister_platform(&imx_soc_platform);
  623. return ret;
  624. }
  625. return 0;
  626. }
  627. static void __exit imx_ssi_exit(void)
  628. {
  629. platform_driver_unregister(&imx_ssi_driver);
  630. snd_soc_unregister_platform(&imx_soc_platform);
  631. }
  632. module_init(imx_ssi_init);
  633. module_exit(imx_ssi_exit);
  634. /* Module information */
  635. MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
  636. MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
  637. MODULE_LICENSE("GPL");