ep93xx-i2s.c 12 KB

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  1. /*
  2. * linux/sound/soc/ep93xx-i2s.c
  3. * EP93xx I2S driver
  4. *
  5. * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
  6. *
  7. * Based on the original driver by:
  8. * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
  9. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/slab.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/initval.h>
  25. #include <sound/soc.h>
  26. #include <mach/hardware.h>
  27. #include <mach/ep93xx-regs.h>
  28. #include <mach/dma.h>
  29. #include "ep93xx-pcm.h"
  30. #include "ep93xx-i2s.h"
  31. #define EP93XX_I2S_TXCLKCFG 0x00
  32. #define EP93XX_I2S_RXCLKCFG 0x04
  33. #define EP93XX_I2S_GLCTRL 0x0C
  34. #define EP93XX_I2S_TXLINCTRLDATA 0x28
  35. #define EP93XX_I2S_TXCTRL 0x2C
  36. #define EP93XX_I2S_TXWRDLEN 0x30
  37. #define EP93XX_I2S_TX0EN 0x34
  38. #define EP93XX_I2S_RXLINCTRLDATA 0x58
  39. #define EP93XX_I2S_RXCTRL 0x5C
  40. #define EP93XX_I2S_RXWRDLEN 0x60
  41. #define EP93XX_I2S_RX0EN 0x64
  42. #define EP93XX_I2S_WRDLEN_16 (0 << 0)
  43. #define EP93XX_I2S_WRDLEN_24 (1 << 0)
  44. #define EP93XX_I2S_WRDLEN_32 (2 << 0)
  45. #define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
  46. #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
  47. #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
  48. #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
  49. #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
  50. #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
  51. struct ep93xx_i2s_info {
  52. struct clk *mclk;
  53. struct clk *sclk;
  54. struct clk *lrclk;
  55. struct ep93xx_pcm_dma_params *dma_params;
  56. struct resource *mem;
  57. void __iomem *regs;
  58. };
  59. struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
  60. [SNDRV_PCM_STREAM_PLAYBACK] = {
  61. .name = "i2s-pcm-out",
  62. .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
  63. },
  64. [SNDRV_PCM_STREAM_CAPTURE] = {
  65. .name = "i2s-pcm-in",
  66. .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
  67. },
  68. };
  69. static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
  70. unsigned reg, unsigned val)
  71. {
  72. __raw_writel(val, info->regs + reg);
  73. }
  74. static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
  75. unsigned reg)
  76. {
  77. return __raw_readl(info->regs + reg);
  78. }
  79. static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
  80. {
  81. unsigned base_reg;
  82. int i;
  83. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  84. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  85. /* Enable clocks */
  86. clk_enable(info->mclk);
  87. clk_enable(info->sclk);
  88. clk_enable(info->lrclk);
  89. /* Enable i2s */
  90. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
  91. }
  92. /* Enable fifos */
  93. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  94. base_reg = EP93XX_I2S_TX0EN;
  95. else
  96. base_reg = EP93XX_I2S_RX0EN;
  97. for (i = 0; i < 3; i++)
  98. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
  99. }
  100. static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
  101. {
  102. unsigned base_reg;
  103. int i;
  104. /* Disable fifos */
  105. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  106. base_reg = EP93XX_I2S_TX0EN;
  107. else
  108. base_reg = EP93XX_I2S_RX0EN;
  109. for (i = 0; i < 3; i++)
  110. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
  111. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  112. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  113. /* Disable i2s */
  114. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
  115. /* Disable clocks */
  116. clk_disable(info->lrclk);
  117. clk_disable(info->sclk);
  118. clk_disable(info->mclk);
  119. }
  120. }
  121. static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
  122. struct snd_soc_dai *dai)
  123. {
  124. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  125. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  126. struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
  127. snd_soc_dai_set_dma_data(cpu_dai, substream,
  128. &info->dma_params[substream->stream]);
  129. return 0;
  130. }
  131. static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
  132. struct snd_soc_dai *dai)
  133. {
  134. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  135. struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
  136. ep93xx_i2s_disable(info, substream->stream);
  137. }
  138. static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  139. unsigned int fmt)
  140. {
  141. struct ep93xx_i2s_info *info = cpu_dai->private_data;
  142. unsigned int clk_cfg, lin_ctrl;
  143. clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
  144. lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
  145. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  146. case SND_SOC_DAIFMT_I2S:
  147. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  148. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  149. break;
  150. case SND_SOC_DAIFMT_LEFT_J:
  151. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  152. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  153. break;
  154. case SND_SOC_DAIFMT_RIGHT_J:
  155. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  156. lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
  157. break;
  158. default:
  159. return -EINVAL;
  160. }
  161. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  162. case SND_SOC_DAIFMT_CBS_CFS:
  163. /* CPU is master */
  164. clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
  165. break;
  166. case SND_SOC_DAIFMT_CBM_CFM:
  167. /* Codec is master */
  168. clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
  169. break;
  170. default:
  171. return -EINVAL;
  172. }
  173. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  174. case SND_SOC_DAIFMT_NB_NF:
  175. /* Negative bit clock, lrclk low on left word */
  176. clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
  177. break;
  178. case SND_SOC_DAIFMT_NB_IF:
  179. /* Negative bit clock, lrclk low on right word */
  180. clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
  181. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  182. break;
  183. case SND_SOC_DAIFMT_IB_NF:
  184. /* Positive bit clock, lrclk low on left word */
  185. clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
  186. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  187. break;
  188. case SND_SOC_DAIFMT_IB_IF:
  189. /* Positive bit clock, lrclk low on right word */
  190. clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
  191. break;
  192. }
  193. /* Write new register values */
  194. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
  195. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
  196. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
  197. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
  198. return 0;
  199. }
  200. static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
  201. struct snd_pcm_hw_params *params,
  202. struct snd_soc_dai *dai)
  203. {
  204. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  205. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  206. struct ep93xx_i2s_info *info = cpu_dai->private_data;
  207. unsigned word_len, div, sdiv, lrdiv;
  208. int found = 0, err;
  209. switch (params_format(params)) {
  210. case SNDRV_PCM_FORMAT_S16_LE:
  211. word_len = EP93XX_I2S_WRDLEN_16;
  212. break;
  213. case SNDRV_PCM_FORMAT_S24_LE:
  214. word_len = EP93XX_I2S_WRDLEN_24;
  215. break;
  216. case SNDRV_PCM_FORMAT_S32_LE:
  217. word_len = EP93XX_I2S_WRDLEN_32;
  218. break;
  219. default:
  220. return -EINVAL;
  221. }
  222. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  223. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
  224. else
  225. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
  226. /*
  227. * Calculate the sdiv (bit clock) and lrdiv (left/right clock) values.
  228. * If the lrclk is pulse length is larger than the word size, then the
  229. * bit clock will be gated for the unused bits.
  230. */
  231. div = (clk_get_rate(info->mclk) / params_rate(params)) *
  232. params_channels(params);
  233. for (sdiv = 2; sdiv <= 4; sdiv += 2)
  234. for (lrdiv = 32; lrdiv <= 128; lrdiv <<= 1)
  235. if (sdiv * lrdiv == div) {
  236. found = 1;
  237. goto out;
  238. }
  239. out:
  240. if (!found)
  241. return -EINVAL;
  242. err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
  243. if (err)
  244. return err;
  245. err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
  246. if (err)
  247. return err;
  248. ep93xx_i2s_enable(info, substream->stream);
  249. return 0;
  250. }
  251. static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
  252. unsigned int freq, int dir)
  253. {
  254. struct ep93xx_i2s_info *info = cpu_dai->private_data;
  255. if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
  256. return -EINVAL;
  257. return clk_set_rate(info->mclk, freq);
  258. }
  259. #ifdef CONFIG_PM
  260. static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
  261. {
  262. struct ep93xx_i2s_info *info = dai->private_data;
  263. if (!dai->active)
  264. return;
  265. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
  266. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
  267. }
  268. static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
  269. {
  270. struct ep93xx_i2s_info *info = dai->private_data;
  271. if (!dai->active)
  272. return;
  273. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
  274. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
  275. }
  276. #else
  277. #define ep93xx_i2s_suspend NULL
  278. #define ep93xx_i2s_resume NULL
  279. #endif
  280. static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
  281. .startup = ep93xx_i2s_startup,
  282. .shutdown = ep93xx_i2s_shutdown,
  283. .hw_params = ep93xx_i2s_hw_params,
  284. .set_sysclk = ep93xx_i2s_set_sysclk,
  285. .set_fmt = ep93xx_i2s_set_dai_fmt,
  286. };
  287. #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  288. SNDRV_PCM_FMTBIT_S24_LE | \
  289. SNDRV_PCM_FMTBIT_S32_LE)
  290. struct snd_soc_dai ep93xx_i2s_dai = {
  291. .name = "ep93xx-i2s",
  292. .id = 0,
  293. .symmetric_rates= 1,
  294. .suspend = ep93xx_i2s_suspend,
  295. .resume = ep93xx_i2s_resume,
  296. .playback = {
  297. .channels_min = 2,
  298. .channels_max = 2,
  299. .rates = SNDRV_PCM_RATE_8000_48000,
  300. .formats = EP93XX_I2S_FORMATS,
  301. },
  302. .capture = {
  303. .channels_min = 2,
  304. .channels_max = 2,
  305. .rates = SNDRV_PCM_RATE_8000_48000,
  306. .formats = EP93XX_I2S_FORMATS,
  307. },
  308. .ops = &ep93xx_i2s_dai_ops,
  309. };
  310. EXPORT_SYMBOL_GPL(ep93xx_i2s_dai);
  311. static int ep93xx_i2s_probe(struct platform_device *pdev)
  312. {
  313. struct ep93xx_i2s_info *info;
  314. struct resource *res;
  315. int err;
  316. info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
  317. if (!info) {
  318. err = -ENOMEM;
  319. goto fail;
  320. }
  321. ep93xx_i2s_dai.dev = &pdev->dev;
  322. ep93xx_i2s_dai.private_data = info;
  323. info->dma_params = ep93xx_i2s_dma_params;
  324. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  325. if (!res) {
  326. err = -ENODEV;
  327. goto fail;
  328. }
  329. info->mem = request_mem_region(res->start, resource_size(res),
  330. pdev->name);
  331. if (!info->mem) {
  332. err = -EBUSY;
  333. goto fail;
  334. }
  335. info->regs = ioremap(info->mem->start, resource_size(info->mem));
  336. if (!info->regs) {
  337. err = -ENXIO;
  338. goto fail_release_mem;
  339. }
  340. info->mclk = clk_get(&pdev->dev, "mclk");
  341. if (IS_ERR(info->mclk)) {
  342. err = PTR_ERR(info->mclk);
  343. goto fail_unmap_mem;
  344. }
  345. info->sclk = clk_get(&pdev->dev, "sclk");
  346. if (IS_ERR(info->sclk)) {
  347. err = PTR_ERR(info->sclk);
  348. goto fail_put_mclk;
  349. }
  350. info->lrclk = clk_get(&pdev->dev, "lrclk");
  351. if (IS_ERR(info->lrclk)) {
  352. err = PTR_ERR(info->lrclk);
  353. goto fail_put_sclk;
  354. }
  355. err = snd_soc_register_dai(&ep93xx_i2s_dai);
  356. if (err)
  357. goto fail_put_lrclk;
  358. return 0;
  359. fail_put_lrclk:
  360. clk_put(info->lrclk);
  361. fail_put_sclk:
  362. clk_put(info->sclk);
  363. fail_put_mclk:
  364. clk_put(info->mclk);
  365. fail_unmap_mem:
  366. iounmap(info->regs);
  367. fail_release_mem:
  368. release_mem_region(info->mem->start, resource_size(info->mem));
  369. kfree(info);
  370. fail:
  371. return err;
  372. }
  373. static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
  374. {
  375. struct ep93xx_i2s_info *info = ep93xx_i2s_dai.private_data;
  376. snd_soc_unregister_dai(&ep93xx_i2s_dai);
  377. clk_put(info->lrclk);
  378. clk_put(info->sclk);
  379. clk_put(info->mclk);
  380. iounmap(info->regs);
  381. release_mem_region(info->mem->start, resource_size(info->mem));
  382. kfree(info);
  383. return 0;
  384. }
  385. static struct platform_driver ep93xx_i2s_driver = {
  386. .probe = ep93xx_i2s_probe,
  387. .remove = __devexit_p(ep93xx_i2s_remove),
  388. .driver = {
  389. .name = "ep93xx-i2s",
  390. .owner = THIS_MODULE,
  391. },
  392. };
  393. static int __init ep93xx_i2s_init(void)
  394. {
  395. return platform_driver_register(&ep93xx_i2s_driver);
  396. }
  397. static void __exit ep93xx_i2s_exit(void)
  398. {
  399. platform_driver_unregister(&ep93xx_i2s_driver);
  400. }
  401. module_init(ep93xx_i2s_init);
  402. module_exit(ep93xx_i2s_exit);
  403. MODULE_ALIAS("platform:ep93xx-i2s");
  404. MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com>");
  405. MODULE_DESCRIPTION("EP93XX I2S driver");
  406. MODULE_LICENSE("GPL");