davinci-i2s.c 23 KB

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  1. /*
  2. * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
  3. *
  4. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  5. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/device.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #include <mach/asp.h>
  24. #include "davinci-pcm.h"
  25. #include "davinci-i2s.h"
  26. /*
  27. * NOTE: terminology here is confusing.
  28. *
  29. * - This driver supports the "Audio Serial Port" (ASP),
  30. * found on dm6446, dm355, and other DaVinci chips.
  31. *
  32. * - But it labels it a "Multi-channel Buffered Serial Port"
  33. * (McBSP) as on older chips like the dm642 ... which was
  34. * backward-compatible, possibly explaining that confusion.
  35. *
  36. * - OMAP chips have a controller called McBSP, which is
  37. * incompatible with the DaVinci flavor of McBSP.
  38. *
  39. * - Newer DaVinci chips have a controller called McASP,
  40. * incompatible with ASP and with either McBSP.
  41. *
  42. * In short: this uses ASP to implement I2S, not McBSP.
  43. * And it won't be the only DaVinci implemention of I2S.
  44. */
  45. #define DAVINCI_MCBSP_DRR_REG 0x00
  46. #define DAVINCI_MCBSP_DXR_REG 0x04
  47. #define DAVINCI_MCBSP_SPCR_REG 0x08
  48. #define DAVINCI_MCBSP_RCR_REG 0x0c
  49. #define DAVINCI_MCBSP_XCR_REG 0x10
  50. #define DAVINCI_MCBSP_SRGR_REG 0x14
  51. #define DAVINCI_MCBSP_PCR_REG 0x24
  52. #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
  53. #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
  54. #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
  55. #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
  56. #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
  57. #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
  58. #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
  59. #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
  60. #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
  61. #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
  62. #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
  63. #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
  64. #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
  65. #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
  66. #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
  67. #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
  68. #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
  69. #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
  70. #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
  71. #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
  72. #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
  73. #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
  74. #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
  75. #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
  76. #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
  77. #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
  78. #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
  79. #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
  80. #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
  81. #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
  82. #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
  83. #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
  84. #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
  85. #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
  86. enum {
  87. DAVINCI_MCBSP_WORD_8 = 0,
  88. DAVINCI_MCBSP_WORD_12,
  89. DAVINCI_MCBSP_WORD_16,
  90. DAVINCI_MCBSP_WORD_20,
  91. DAVINCI_MCBSP_WORD_24,
  92. DAVINCI_MCBSP_WORD_32,
  93. };
  94. static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  95. [SNDRV_PCM_FORMAT_S8] = 1,
  96. [SNDRV_PCM_FORMAT_S16_LE] = 2,
  97. [SNDRV_PCM_FORMAT_S32_LE] = 4,
  98. };
  99. static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  100. [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
  101. [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
  102. [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
  103. };
  104. static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  105. [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
  106. [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
  107. };
  108. struct davinci_mcbsp_dev {
  109. struct device *dev;
  110. struct davinci_pcm_dma_params dma_params[2];
  111. void __iomem *base;
  112. #define MOD_DSP_A 0
  113. #define MOD_DSP_B 1
  114. int mode;
  115. u32 pcr;
  116. struct clk *clk;
  117. /*
  118. * Combining both channels into 1 element will at least double the
  119. * amount of time between servicing the dma channel, increase
  120. * effiency, and reduce the chance of overrun/underrun. But,
  121. * it will result in the left & right channels being swapped.
  122. *
  123. * If relabeling the left and right channels is not possible,
  124. * you may want to let the codec know to swap them back.
  125. *
  126. * It may allow x10 the amount of time to service dma requests,
  127. * if the codec is master and is using an unnecessarily fast bit clock
  128. * (ie. tlvaic23b), independent of the sample rate. So, having an
  129. * entire frame at once means it can be serviced at the sample rate
  130. * instead of the bit clock rate.
  131. *
  132. * In the now unlikely case that an underrun still
  133. * occurs, both the left and right samples will be repeated
  134. * so that no pops are heard, and the left and right channels
  135. * won't end up being swapped because of the underrun.
  136. */
  137. unsigned enable_channel_combine:1;
  138. unsigned int fmt;
  139. int clk_div;
  140. int clk_input_pin;
  141. bool i2s_accurate_sck;
  142. };
  143. static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
  144. int reg, u32 val)
  145. {
  146. __raw_writel(val, dev->base + reg);
  147. }
  148. static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
  149. {
  150. return __raw_readl(dev->base + reg);
  151. }
  152. static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
  153. {
  154. u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
  155. /* The clock needs to toggle to complete reset.
  156. * So, fake it by toggling the clk polarity.
  157. */
  158. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
  159. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
  160. }
  161. static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
  162. struct snd_pcm_substream *substream)
  163. {
  164. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  165. struct snd_soc_device *socdev = rtd->socdev;
  166. struct snd_soc_platform *platform = socdev->card->platform;
  167. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  168. u32 spcr;
  169. u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
  170. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  171. if (spcr & mask) {
  172. /* start off disabled */
  173. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
  174. spcr & ~mask);
  175. toggle_clock(dev, playback);
  176. }
  177. if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
  178. DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
  179. /* Start the sample generator */
  180. spcr |= DAVINCI_MCBSP_SPCR_GRST;
  181. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  182. }
  183. if (playback) {
  184. /* Stop the DMA to avoid data loss */
  185. /* while the transmitter is out of reset to handle XSYNCERR */
  186. if (platform->pcm_ops->trigger) {
  187. int ret = platform->pcm_ops->trigger(substream,
  188. SNDRV_PCM_TRIGGER_STOP);
  189. if (ret < 0)
  190. printk(KERN_DEBUG "Playback DMA stop failed\n");
  191. }
  192. /* Enable the transmitter */
  193. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  194. spcr |= DAVINCI_MCBSP_SPCR_XRST;
  195. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  196. /* wait for any unexpected frame sync error to occur */
  197. udelay(100);
  198. /* Disable the transmitter to clear any outstanding XSYNCERR */
  199. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  200. spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
  201. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  202. toggle_clock(dev, playback);
  203. /* Restart the DMA */
  204. if (platform->pcm_ops->trigger) {
  205. int ret = platform->pcm_ops->trigger(substream,
  206. SNDRV_PCM_TRIGGER_START);
  207. if (ret < 0)
  208. printk(KERN_DEBUG "Playback DMA start failed\n");
  209. }
  210. }
  211. /* Enable transmitter or receiver */
  212. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  213. spcr |= mask;
  214. if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
  215. /* Start frame sync */
  216. spcr |= DAVINCI_MCBSP_SPCR_FRST;
  217. }
  218. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  219. }
  220. static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
  221. {
  222. u32 spcr;
  223. /* Reset transmitter/receiver and sample rate/frame sync generators */
  224. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  225. spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
  226. spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
  227. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  228. toggle_clock(dev, playback);
  229. }
  230. #define DEFAULT_BITPERSAMPLE 16
  231. static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  232. unsigned int fmt)
  233. {
  234. struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
  235. unsigned int pcr;
  236. unsigned int srgr;
  237. /* Attention srgr is updated by hw_params! */
  238. srgr = DAVINCI_MCBSP_SRGR_FSGM |
  239. DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
  240. DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
  241. dev->fmt = fmt;
  242. /* set master/slave audio interface */
  243. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  244. case SND_SOC_DAIFMT_CBS_CFS:
  245. /* cpu is master */
  246. pcr = DAVINCI_MCBSP_PCR_FSXM |
  247. DAVINCI_MCBSP_PCR_FSRM |
  248. DAVINCI_MCBSP_PCR_CLKXM |
  249. DAVINCI_MCBSP_PCR_CLKRM;
  250. break;
  251. case SND_SOC_DAIFMT_CBM_CFS:
  252. pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
  253. /*
  254. * Selection of the clock input pin that is the
  255. * input for the Sample Rate Generator.
  256. * McBSP FSR and FSX are driven by the Sample Rate
  257. * Generator.
  258. */
  259. switch (dev->clk_input_pin) {
  260. case MCBSP_CLKS:
  261. pcr |= DAVINCI_MCBSP_PCR_CLKXM |
  262. DAVINCI_MCBSP_PCR_CLKRM;
  263. break;
  264. case MCBSP_CLKR:
  265. pcr |= DAVINCI_MCBSP_PCR_SCLKME;
  266. break;
  267. default:
  268. dev_err(dev->dev, "bad clk_input_pin\n");
  269. return -EINVAL;
  270. }
  271. break;
  272. case SND_SOC_DAIFMT_CBM_CFM:
  273. /* codec is master */
  274. pcr = 0;
  275. break;
  276. default:
  277. printk(KERN_ERR "%s:bad master\n", __func__);
  278. return -EINVAL;
  279. }
  280. /* interface format */
  281. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  282. case SND_SOC_DAIFMT_I2S:
  283. /* Davinci doesn't support TRUE I2S, but some codecs will have
  284. * the left and right channels contiguous. This allows
  285. * dsp_a mode to be used with an inverted normal frame clk.
  286. * If your codec is master and does not have contiguous
  287. * channels, then you will have sound on only one channel.
  288. * Try using a different mode, or codec as slave.
  289. *
  290. * The TLV320AIC33 is an example of a codec where this works.
  291. * It has a variable bit clock frequency allowing it to have
  292. * valid data on every bit clock.
  293. *
  294. * The TLV320AIC23 is an example of a codec where this does not
  295. * work. It has a fixed bit clock frequency with progressively
  296. * more empty bit clock slots between channels as the sample
  297. * rate is lowered.
  298. */
  299. fmt ^= SND_SOC_DAIFMT_NB_IF;
  300. case SND_SOC_DAIFMT_DSP_A:
  301. dev->mode = MOD_DSP_A;
  302. break;
  303. case SND_SOC_DAIFMT_DSP_B:
  304. dev->mode = MOD_DSP_B;
  305. break;
  306. default:
  307. printk(KERN_ERR "%s:bad format\n", __func__);
  308. return -EINVAL;
  309. }
  310. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  311. case SND_SOC_DAIFMT_NB_NF:
  312. /* CLKRP Receive clock polarity,
  313. * 1 - sampled on rising edge of CLKR
  314. * valid on rising edge
  315. * CLKXP Transmit clock polarity,
  316. * 1 - clocked on falling edge of CLKX
  317. * valid on rising edge
  318. * FSRP Receive frame sync pol, 0 - active high
  319. * FSXP Transmit frame sync pol, 0 - active high
  320. */
  321. pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
  322. break;
  323. case SND_SOC_DAIFMT_IB_IF:
  324. /* CLKRP Receive clock polarity,
  325. * 0 - sampled on falling edge of CLKR
  326. * valid on falling edge
  327. * CLKXP Transmit clock polarity,
  328. * 0 - clocked on rising edge of CLKX
  329. * valid on falling edge
  330. * FSRP Receive frame sync pol, 1 - active low
  331. * FSXP Transmit frame sync pol, 1 - active low
  332. */
  333. pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
  334. break;
  335. case SND_SOC_DAIFMT_NB_IF:
  336. /* CLKRP Receive clock polarity,
  337. * 1 - sampled on rising edge of CLKR
  338. * valid on rising edge
  339. * CLKXP Transmit clock polarity,
  340. * 1 - clocked on falling edge of CLKX
  341. * valid on rising edge
  342. * FSRP Receive frame sync pol, 1 - active low
  343. * FSXP Transmit frame sync pol, 1 - active low
  344. */
  345. pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
  346. DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
  347. break;
  348. case SND_SOC_DAIFMT_IB_NF:
  349. /* CLKRP Receive clock polarity,
  350. * 0 - sampled on falling edge of CLKR
  351. * valid on falling edge
  352. * CLKXP Transmit clock polarity,
  353. * 0 - clocked on rising edge of CLKX
  354. * valid on falling edge
  355. * FSRP Receive frame sync pol, 0 - active high
  356. * FSXP Transmit frame sync pol, 0 - active high
  357. */
  358. break;
  359. default:
  360. return -EINVAL;
  361. }
  362. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
  363. dev->pcr = pcr;
  364. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
  365. return 0;
  366. }
  367. static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  368. int div_id, int div)
  369. {
  370. struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
  371. if (div_id != DAVINCI_MCBSP_CLKGDV)
  372. return -ENODEV;
  373. dev->clk_div = div;
  374. return 0;
  375. }
  376. static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
  377. struct snd_pcm_hw_params *params,
  378. struct snd_soc_dai *dai)
  379. {
  380. struct davinci_mcbsp_dev *dev = dai->private_data;
  381. struct davinci_pcm_dma_params *dma_params =
  382. &dev->dma_params[substream->stream];
  383. struct snd_interval *i = NULL;
  384. int mcbsp_word_length, master;
  385. unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
  386. u32 spcr;
  387. snd_pcm_format_t fmt;
  388. unsigned element_cnt = 1;
  389. /* general line settings */
  390. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  391. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  392. spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
  393. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  394. } else {
  395. spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
  396. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  397. }
  398. master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
  399. fmt = params_format(params);
  400. mcbsp_word_length = asp_word_length[fmt];
  401. switch (master) {
  402. case SND_SOC_DAIFMT_CBS_CFS:
  403. freq = clk_get_rate(dev->clk);
  404. srgr = DAVINCI_MCBSP_SRGR_FSGM |
  405. DAVINCI_MCBSP_SRGR_CLKSM;
  406. srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
  407. 8 - 1);
  408. if (dev->i2s_accurate_sck) {
  409. clk_div = 256;
  410. do {
  411. framesize = (freq / (--clk_div)) /
  412. params->rate_num *
  413. params->rate_den;
  414. } while (((framesize < 33) || (framesize > 4095)) &&
  415. (clk_div));
  416. clk_div--;
  417. srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
  418. } else {
  419. /* symmetric waveforms */
  420. clk_div = freq / (mcbsp_word_length * 16) /
  421. params->rate_num * params->rate_den;
  422. srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
  423. 16 - 1);
  424. }
  425. clk_div &= 0xFF;
  426. srgr |= clk_div;
  427. break;
  428. case SND_SOC_DAIFMT_CBM_CFS:
  429. srgr = DAVINCI_MCBSP_SRGR_FSGM;
  430. clk_div = dev->clk_div - 1;
  431. srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
  432. srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
  433. clk_div &= 0xFF;
  434. srgr |= clk_div;
  435. break;
  436. case SND_SOC_DAIFMT_CBM_CFM:
  437. /* Clock and frame sync given from external sources */
  438. i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
  439. srgr = DAVINCI_MCBSP_SRGR_FSGM;
  440. srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
  441. pr_debug("%s - %d FWID set: re-read srgr = %X\n",
  442. __func__, __LINE__, snd_interval_value(i) - 1);
  443. i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
  444. srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
  445. break;
  446. default:
  447. return -EINVAL;
  448. }
  449. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
  450. rcr = DAVINCI_MCBSP_RCR_RFIG;
  451. xcr = DAVINCI_MCBSP_XCR_XFIG;
  452. if (dev->mode == MOD_DSP_B) {
  453. rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
  454. xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
  455. } else {
  456. rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
  457. xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
  458. }
  459. /* Determine xfer data type */
  460. fmt = params_format(params);
  461. if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
  462. printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
  463. return -EINVAL;
  464. }
  465. if (params_channels(params) == 2) {
  466. element_cnt = 2;
  467. if (double_fmt[fmt] && dev->enable_channel_combine) {
  468. element_cnt = 1;
  469. fmt = double_fmt[fmt];
  470. }
  471. switch (master) {
  472. case SND_SOC_DAIFMT_CBS_CFS:
  473. case SND_SOC_DAIFMT_CBS_CFM:
  474. rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
  475. xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
  476. rcr |= DAVINCI_MCBSP_RCR_RPHASE;
  477. xcr |= DAVINCI_MCBSP_XCR_XPHASE;
  478. break;
  479. case SND_SOC_DAIFMT_CBM_CFM:
  480. case SND_SOC_DAIFMT_CBM_CFS:
  481. rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
  482. xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
  483. break;
  484. default:
  485. return -EINVAL;
  486. }
  487. }
  488. dma_params->acnt = dma_params->data_type = data_type[fmt];
  489. dma_params->fifo_level = 0;
  490. mcbsp_word_length = asp_word_length[fmt];
  491. switch (master) {
  492. case SND_SOC_DAIFMT_CBS_CFS:
  493. case SND_SOC_DAIFMT_CBS_CFM:
  494. rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
  495. xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
  496. break;
  497. case SND_SOC_DAIFMT_CBM_CFM:
  498. case SND_SOC_DAIFMT_CBM_CFS:
  499. rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
  500. xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
  501. break;
  502. default:
  503. return -EINVAL;
  504. }
  505. rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
  506. DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
  507. xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
  508. DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
  509. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  510. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
  511. else
  512. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
  513. pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
  514. pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
  515. pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
  516. return 0;
  517. }
  518. static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
  519. struct snd_soc_dai *dai)
  520. {
  521. struct davinci_mcbsp_dev *dev = dai->private_data;
  522. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  523. davinci_mcbsp_stop(dev, playback);
  524. if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
  525. /* codec is master */
  526. davinci_mcbsp_start(dev, substream);
  527. }
  528. return 0;
  529. }
  530. static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  531. struct snd_soc_dai *dai)
  532. {
  533. struct davinci_mcbsp_dev *dev = dai->private_data;
  534. int ret = 0;
  535. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  536. if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
  537. return 0; /* return if codec is master */
  538. switch (cmd) {
  539. case SNDRV_PCM_TRIGGER_START:
  540. case SNDRV_PCM_TRIGGER_RESUME:
  541. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  542. davinci_mcbsp_start(dev, substream);
  543. break;
  544. case SNDRV_PCM_TRIGGER_STOP:
  545. case SNDRV_PCM_TRIGGER_SUSPEND:
  546. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  547. davinci_mcbsp_stop(dev, playback);
  548. break;
  549. default:
  550. ret = -EINVAL;
  551. }
  552. return ret;
  553. }
  554. static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
  555. struct snd_soc_dai *dai)
  556. {
  557. struct davinci_mcbsp_dev *dev = dai->private_data;
  558. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  559. davinci_mcbsp_stop(dev, playback);
  560. }
  561. #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
  562. static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
  563. .shutdown = davinci_i2s_shutdown,
  564. .prepare = davinci_i2s_prepare,
  565. .trigger = davinci_i2s_trigger,
  566. .hw_params = davinci_i2s_hw_params,
  567. .set_fmt = davinci_i2s_set_dai_fmt,
  568. .set_clkdiv = davinci_i2s_dai_set_clkdiv,
  569. };
  570. struct snd_soc_dai davinci_i2s_dai = {
  571. .name = "davinci-i2s",
  572. .id = 0,
  573. .playback = {
  574. .channels_min = 2,
  575. .channels_max = 2,
  576. .rates = DAVINCI_I2S_RATES,
  577. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  578. .capture = {
  579. .channels_min = 2,
  580. .channels_max = 2,
  581. .rates = DAVINCI_I2S_RATES,
  582. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  583. .ops = &davinci_i2s_dai_ops,
  584. };
  585. EXPORT_SYMBOL_GPL(davinci_i2s_dai);
  586. static int davinci_i2s_probe(struct platform_device *pdev)
  587. {
  588. struct snd_platform_data *pdata = pdev->dev.platform_data;
  589. struct davinci_mcbsp_dev *dev;
  590. struct resource *mem, *ioarea, *res;
  591. enum dma_event_q asp_chan_q = EVENTQ_0;
  592. enum dma_event_q ram_chan_q = EVENTQ_1;
  593. int ret;
  594. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  595. if (!mem) {
  596. dev_err(&pdev->dev, "no mem resource?\n");
  597. return -ENODEV;
  598. }
  599. ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
  600. pdev->name);
  601. if (!ioarea) {
  602. dev_err(&pdev->dev, "McBSP region already claimed\n");
  603. return -EBUSY;
  604. }
  605. dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
  606. if (!dev) {
  607. ret = -ENOMEM;
  608. goto err_release_region;
  609. }
  610. if (pdata) {
  611. dev->enable_channel_combine = pdata->enable_channel_combine;
  612. dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
  613. pdata->sram_size_playback;
  614. dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
  615. pdata->sram_size_capture;
  616. dev->clk_input_pin = pdata->clk_input_pin;
  617. dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
  618. asp_chan_q = pdata->asp_chan_q;
  619. ram_chan_q = pdata->ram_chan_q;
  620. }
  621. dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
  622. dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
  623. dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
  624. dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
  625. dev->clk = clk_get(&pdev->dev, NULL);
  626. if (IS_ERR(dev->clk)) {
  627. ret = -ENODEV;
  628. goto err_free_mem;
  629. }
  630. clk_enable(dev->clk);
  631. dev->base = (void __iomem *)IO_ADDRESS(mem->start);
  632. dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
  633. (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
  634. dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
  635. (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
  636. /* first TX, then RX */
  637. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  638. if (!res) {
  639. dev_err(&pdev->dev, "no DMA resource\n");
  640. ret = -ENXIO;
  641. goto err_free_mem;
  642. }
  643. dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
  644. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  645. if (!res) {
  646. dev_err(&pdev->dev, "no DMA resource\n");
  647. ret = -ENXIO;
  648. goto err_free_mem;
  649. }
  650. dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
  651. dev->dev = &pdev->dev;
  652. davinci_i2s_dai.private_data = dev;
  653. davinci_i2s_dai.capture.dma_data = dev->dma_params;
  654. davinci_i2s_dai.playback.dma_data = dev->dma_params;
  655. ret = snd_soc_register_dai(&davinci_i2s_dai);
  656. if (ret != 0)
  657. goto err_free_mem;
  658. return 0;
  659. err_free_mem:
  660. kfree(dev);
  661. err_release_region:
  662. release_mem_region(mem->start, (mem->end - mem->start) + 1);
  663. return ret;
  664. }
  665. static int davinci_i2s_remove(struct platform_device *pdev)
  666. {
  667. struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
  668. struct resource *mem;
  669. snd_soc_unregister_dai(&davinci_i2s_dai);
  670. clk_disable(dev->clk);
  671. clk_put(dev->clk);
  672. dev->clk = NULL;
  673. kfree(dev);
  674. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  675. release_mem_region(mem->start, (mem->end - mem->start) + 1);
  676. return 0;
  677. }
  678. static struct platform_driver davinci_mcbsp_driver = {
  679. .probe = davinci_i2s_probe,
  680. .remove = davinci_i2s_remove,
  681. .driver = {
  682. .name = "davinci-asp",
  683. .owner = THIS_MODULE,
  684. },
  685. };
  686. static int __init davinci_i2s_init(void)
  687. {
  688. return platform_driver_register(&davinci_mcbsp_driver);
  689. }
  690. module_init(davinci_i2s_init);
  691. static void __exit davinci_i2s_exit(void)
  692. {
  693. platform_driver_unregister(&davinci_mcbsp_driver);
  694. }
  695. module_exit(davinci_i2s_exit);
  696. MODULE_AUTHOR("Vladimir Barinov");
  697. MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
  698. MODULE_LICENSE("GPL");