wm8994.c 138 KB

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  1. /*
  2. * wm8994.c -- WM8994 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <linux/mfd/wm8994/core.h>
  30. #include <linux/mfd/wm8994/registers.h>
  31. #include <linux/mfd/wm8994/pdata.h>
  32. #include <linux/mfd/wm8994/gpio.h>
  33. #include "wm8994.h"
  34. #include "wm_hubs.h"
  35. static struct snd_soc_codec *wm8994_codec;
  36. struct snd_soc_codec_device soc_codec_dev_wm8994;
  37. struct fll_config {
  38. int src;
  39. int in;
  40. int out;
  41. };
  42. #define WM8994_NUM_DRC 3
  43. #define WM8994_NUM_EQ 3
  44. static int wm8994_drc_base[] = {
  45. WM8994_AIF1_DRC1_1,
  46. WM8994_AIF1_DRC2_1,
  47. WM8994_AIF2_DRC_1,
  48. };
  49. static int wm8994_retune_mobile_base[] = {
  50. WM8994_AIF1_DAC1_EQ_GAINS_1,
  51. WM8994_AIF1_DAC2_EQ_GAINS_1,
  52. WM8994_AIF2_EQ_GAINS_1,
  53. };
  54. #define WM8994_REG_CACHE_SIZE 0x621
  55. struct wm8994_micdet {
  56. struct snd_soc_jack *jack;
  57. int det;
  58. int shrt;
  59. };
  60. /* codec private data */
  61. struct wm8994_priv {
  62. struct wm_hubs_data hubs;
  63. struct snd_soc_codec codec;
  64. u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
  65. int sysclk[2];
  66. int sysclk_rate[2];
  67. int mclk[2];
  68. int aifclk[2];
  69. struct fll_config fll[2], fll_suspend[2];
  70. int dac_rates[2];
  71. int lrclk_shared[2];
  72. /* Platform dependant DRC configuration */
  73. const char **drc_texts;
  74. int drc_cfg[WM8994_NUM_DRC];
  75. struct soc_enum drc_enum;
  76. /* Platform dependant ReTune mobile configuration */
  77. int num_retune_mobile_texts;
  78. const char **retune_mobile_texts;
  79. int retune_mobile_cfg[WM8994_NUM_EQ];
  80. struct soc_enum retune_mobile_enum;
  81. struct wm8994_micdet micdet[2];
  82. int revision;
  83. struct wm8994_pdata *pdata;
  84. };
  85. static struct {
  86. unsigned short readable; /* Mask of readable bits */
  87. unsigned short writable; /* Mask of writable bits */
  88. unsigned short vol; /* Mask of volatile bits */
  89. } access_masks[] = {
  90. { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */
  91. { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */
  92. { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */
  93. { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */
  94. { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */
  95. { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */
  96. { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */
  97. { 0x0000, 0x0000, 0x0000 }, /* R7 */
  98. { 0x0000, 0x0000, 0x0000 }, /* R8 */
  99. { 0x0000, 0x0000, 0x0000 }, /* R9 */
  100. { 0x0000, 0x0000, 0x0000 }, /* R10 */
  101. { 0x0000, 0x0000, 0x0000 }, /* R11 */
  102. { 0x0000, 0x0000, 0x0000 }, /* R12 */
  103. { 0x0000, 0x0000, 0x0000 }, /* R13 */
  104. { 0x0000, 0x0000, 0x0000 }, /* R14 */
  105. { 0x0000, 0x0000, 0x0000 }, /* R15 */
  106. { 0x0000, 0x0000, 0x0000 }, /* R16 */
  107. { 0x0000, 0x0000, 0x0000 }, /* R17 */
  108. { 0x0000, 0x0000, 0x0000 }, /* R18 */
  109. { 0x0000, 0x0000, 0x0000 }, /* R19 */
  110. { 0x0000, 0x0000, 0x0000 }, /* R20 */
  111. { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */
  112. { 0x0000, 0x0000, 0x0000 }, /* R22 */
  113. { 0x0000, 0x0000, 0x0000 }, /* R23 */
  114. { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */
  115. { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */
  116. { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */
  117. { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */
  118. { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */
  119. { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */
  120. { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */
  121. { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */
  122. { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */
  123. { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */
  124. { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */
  125. { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */
  126. { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */
  127. { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */
  128. { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */
  129. { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */
  130. { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */
  131. { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */
  132. { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */
  133. { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */
  134. { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */
  135. { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */
  136. { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */
  137. { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */
  138. { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */
  139. { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */
  140. { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */
  141. { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */
  142. { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */
  143. { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */
  144. { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */
  145. { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */
  146. { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */
  147. { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */
  148. { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */
  149. { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */
  150. { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */
  151. { 0x0000, 0x0000, 0x0000 }, /* R61 */
  152. { 0x0000, 0x0000, 0x0000 }, /* R62 */
  153. { 0x0000, 0x0000, 0x0000 }, /* R63 */
  154. { 0x0000, 0x0000, 0x0000 }, /* R64 */
  155. { 0x0000, 0x0000, 0x0000 }, /* R65 */
  156. { 0x0000, 0x0000, 0x0000 }, /* R66 */
  157. { 0x0000, 0x0000, 0x0000 }, /* R67 */
  158. { 0x0000, 0x0000, 0x0000 }, /* R68 */
  159. { 0x0000, 0x0000, 0x0000 }, /* R69 */
  160. { 0x0000, 0x0000, 0x0000 }, /* R70 */
  161. { 0x0000, 0x0000, 0x0000 }, /* R71 */
  162. { 0x0000, 0x0000, 0x0000 }, /* R72 */
  163. { 0x0000, 0x0000, 0x0000 }, /* R73 */
  164. { 0x0000, 0x0000, 0x0000 }, /* R74 */
  165. { 0x0000, 0x0000, 0x0000 }, /* R75 */
  166. { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */
  167. { 0x0000, 0x0000, 0x0000 }, /* R77 */
  168. { 0x0000, 0x0000, 0x0000 }, /* R78 */
  169. { 0x0000, 0x0000, 0x0000 }, /* R79 */
  170. { 0x0000, 0x0000, 0x0000 }, /* R80 */
  171. { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */
  172. { 0x0000, 0x0000, 0x0000 }, /* R82 */
  173. { 0x0000, 0x0000, 0x0000 }, /* R83 */
  174. { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */
  175. { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */
  176. { 0x0000, 0x0000, 0x0000 }, /* R86 */
  177. { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */
  178. { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */
  179. { 0x0000, 0x0000, 0x0000 }, /* R89 */
  180. { 0x0000, 0x0000, 0x0000 }, /* R90 */
  181. { 0x0000, 0x0000, 0x0000 }, /* R91 */
  182. { 0x0000, 0x0000, 0x0000 }, /* R92 */
  183. { 0x0000, 0x0000, 0x0000 }, /* R93 */
  184. { 0x0000, 0x0000, 0x0000 }, /* R94 */
  185. { 0x0000, 0x0000, 0x0000 }, /* R95 */
  186. { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */
  187. { 0x0000, 0x0000, 0x0000 }, /* R97 */
  188. { 0x0000, 0x0000, 0x0000 }, /* R98 */
  189. { 0x0000, 0x0000, 0x0000 }, /* R99 */
  190. { 0x0000, 0x0000, 0x0000 }, /* R100 */
  191. { 0x0000, 0x0000, 0x0000 }, /* R101 */
  192. { 0x0000, 0x0000, 0x0000 }, /* R102 */
  193. { 0x0000, 0x0000, 0x0000 }, /* R103 */
  194. { 0x0000, 0x0000, 0x0000 }, /* R104 */
  195. { 0x0000, 0x0000, 0x0000 }, /* R105 */
  196. { 0x0000, 0x0000, 0x0000 }, /* R106 */
  197. { 0x0000, 0x0000, 0x0000 }, /* R107 */
  198. { 0x0000, 0x0000, 0x0000 }, /* R108 */
  199. { 0x0000, 0x0000, 0x0000 }, /* R109 */
  200. { 0x0000, 0x0000, 0x0000 }, /* R110 */
  201. { 0x0000, 0x0000, 0x0000 }, /* R111 */
  202. { 0x0000, 0x0000, 0x0000 }, /* R112 */
  203. { 0x0000, 0x0000, 0x0000 }, /* R113 */
  204. { 0x0000, 0x0000, 0x0000 }, /* R114 */
  205. { 0x0000, 0x0000, 0x0000 }, /* R115 */
  206. { 0x0000, 0x0000, 0x0000 }, /* R116 */
  207. { 0x0000, 0x0000, 0x0000 }, /* R117 */
  208. { 0x0000, 0x0000, 0x0000 }, /* R118 */
  209. { 0x0000, 0x0000, 0x0000 }, /* R119 */
  210. { 0x0000, 0x0000, 0x0000 }, /* R120 */
  211. { 0x0000, 0x0000, 0x0000 }, /* R121 */
  212. { 0x0000, 0x0000, 0x0000 }, /* R122 */
  213. { 0x0000, 0x0000, 0x0000 }, /* R123 */
  214. { 0x0000, 0x0000, 0x0000 }, /* R124 */
  215. { 0x0000, 0x0000, 0x0000 }, /* R125 */
  216. { 0x0000, 0x0000, 0x0000 }, /* R126 */
  217. { 0x0000, 0x0000, 0x0000 }, /* R127 */
  218. { 0x0000, 0x0000, 0x0000 }, /* R128 */
  219. { 0x0000, 0x0000, 0x0000 }, /* R129 */
  220. { 0x0000, 0x0000, 0x0000 }, /* R130 */
  221. { 0x0000, 0x0000, 0x0000 }, /* R131 */
  222. { 0x0000, 0x0000, 0x0000 }, /* R132 */
  223. { 0x0000, 0x0000, 0x0000 }, /* R133 */
  224. { 0x0000, 0x0000, 0x0000 }, /* R134 */
  225. { 0x0000, 0x0000, 0x0000 }, /* R135 */
  226. { 0x0000, 0x0000, 0x0000 }, /* R136 */
  227. { 0x0000, 0x0000, 0x0000 }, /* R137 */
  228. { 0x0000, 0x0000, 0x0000 }, /* R138 */
  229. { 0x0000, 0x0000, 0x0000 }, /* R139 */
  230. { 0x0000, 0x0000, 0x0000 }, /* R140 */
  231. { 0x0000, 0x0000, 0x0000 }, /* R141 */
  232. { 0x0000, 0x0000, 0x0000 }, /* R142 */
  233. { 0x0000, 0x0000, 0x0000 }, /* R143 */
  234. { 0x0000, 0x0000, 0x0000 }, /* R144 */
  235. { 0x0000, 0x0000, 0x0000 }, /* R145 */
  236. { 0x0000, 0x0000, 0x0000 }, /* R146 */
  237. { 0x0000, 0x0000, 0x0000 }, /* R147 */
  238. { 0x0000, 0x0000, 0x0000 }, /* R148 */
  239. { 0x0000, 0x0000, 0x0000 }, /* R149 */
  240. { 0x0000, 0x0000, 0x0000 }, /* R150 */
  241. { 0x0000, 0x0000, 0x0000 }, /* R151 */
  242. { 0x0000, 0x0000, 0x0000 }, /* R152 */
  243. { 0x0000, 0x0000, 0x0000 }, /* R153 */
  244. { 0x0000, 0x0000, 0x0000 }, /* R154 */
  245. { 0x0000, 0x0000, 0x0000 }, /* R155 */
  246. { 0x0000, 0x0000, 0x0000 }, /* R156 */
  247. { 0x0000, 0x0000, 0x0000 }, /* R157 */
  248. { 0x0000, 0x0000, 0x0000 }, /* R158 */
  249. { 0x0000, 0x0000, 0x0000 }, /* R159 */
  250. { 0x0000, 0x0000, 0x0000 }, /* R160 */
  251. { 0x0000, 0x0000, 0x0000 }, /* R161 */
  252. { 0x0000, 0x0000, 0x0000 }, /* R162 */
  253. { 0x0000, 0x0000, 0x0000 }, /* R163 */
  254. { 0x0000, 0x0000, 0x0000 }, /* R164 */
  255. { 0x0000, 0x0000, 0x0000 }, /* R165 */
  256. { 0x0000, 0x0000, 0x0000 }, /* R166 */
  257. { 0x0000, 0x0000, 0x0000 }, /* R167 */
  258. { 0x0000, 0x0000, 0x0000 }, /* R168 */
  259. { 0x0000, 0x0000, 0x0000 }, /* R169 */
  260. { 0x0000, 0x0000, 0x0000 }, /* R170 */
  261. { 0x0000, 0x0000, 0x0000 }, /* R171 */
  262. { 0x0000, 0x0000, 0x0000 }, /* R172 */
  263. { 0x0000, 0x0000, 0x0000 }, /* R173 */
  264. { 0x0000, 0x0000, 0x0000 }, /* R174 */
  265. { 0x0000, 0x0000, 0x0000 }, /* R175 */
  266. { 0x0000, 0x0000, 0x0000 }, /* R176 */
  267. { 0x0000, 0x0000, 0x0000 }, /* R177 */
  268. { 0x0000, 0x0000, 0x0000 }, /* R178 */
  269. { 0x0000, 0x0000, 0x0000 }, /* R179 */
  270. { 0x0000, 0x0000, 0x0000 }, /* R180 */
  271. { 0x0000, 0x0000, 0x0000 }, /* R181 */
  272. { 0x0000, 0x0000, 0x0000 }, /* R182 */
  273. { 0x0000, 0x0000, 0x0000 }, /* R183 */
  274. { 0x0000, 0x0000, 0x0000 }, /* R184 */
  275. { 0x0000, 0x0000, 0x0000 }, /* R185 */
  276. { 0x0000, 0x0000, 0x0000 }, /* R186 */
  277. { 0x0000, 0x0000, 0x0000 }, /* R187 */
  278. { 0x0000, 0x0000, 0x0000 }, /* R188 */
  279. { 0x0000, 0x0000, 0x0000 }, /* R189 */
  280. { 0x0000, 0x0000, 0x0000 }, /* R190 */
  281. { 0x0000, 0x0000, 0x0000 }, /* R191 */
  282. { 0x0000, 0x0000, 0x0000 }, /* R192 */
  283. { 0x0000, 0x0000, 0x0000 }, /* R193 */
  284. { 0x0000, 0x0000, 0x0000 }, /* R194 */
  285. { 0x0000, 0x0000, 0x0000 }, /* R195 */
  286. { 0x0000, 0x0000, 0x0000 }, /* R196 */
  287. { 0x0000, 0x0000, 0x0000 }, /* R197 */
  288. { 0x0000, 0x0000, 0x0000 }, /* R198 */
  289. { 0x0000, 0x0000, 0x0000 }, /* R199 */
  290. { 0x0000, 0x0000, 0x0000 }, /* R200 */
  291. { 0x0000, 0x0000, 0x0000 }, /* R201 */
  292. { 0x0000, 0x0000, 0x0000 }, /* R202 */
  293. { 0x0000, 0x0000, 0x0000 }, /* R203 */
  294. { 0x0000, 0x0000, 0x0000 }, /* R204 */
  295. { 0x0000, 0x0000, 0x0000 }, /* R205 */
  296. { 0x0000, 0x0000, 0x0000 }, /* R206 */
  297. { 0x0000, 0x0000, 0x0000 }, /* R207 */
  298. { 0x0000, 0x0000, 0x0000 }, /* R208 */
  299. { 0x0000, 0x0000, 0x0000 }, /* R209 */
  300. { 0x0000, 0x0000, 0x0000 }, /* R210 */
  301. { 0x0000, 0x0000, 0x0000 }, /* R211 */
  302. { 0x0000, 0x0000, 0x0000 }, /* R212 */
  303. { 0x0000, 0x0000, 0x0000 }, /* R213 */
  304. { 0x0000, 0x0000, 0x0000 }, /* R214 */
  305. { 0x0000, 0x0000, 0x0000 }, /* R215 */
  306. { 0x0000, 0x0000, 0x0000 }, /* R216 */
  307. { 0x0000, 0x0000, 0x0000 }, /* R217 */
  308. { 0x0000, 0x0000, 0x0000 }, /* R218 */
  309. { 0x0000, 0x0000, 0x0000 }, /* R219 */
  310. { 0x0000, 0x0000, 0x0000 }, /* R220 */
  311. { 0x0000, 0x0000, 0x0000 }, /* R221 */
  312. { 0x0000, 0x0000, 0x0000 }, /* R222 */
  313. { 0x0000, 0x0000, 0x0000 }, /* R223 */
  314. { 0x0000, 0x0000, 0x0000 }, /* R224 */
  315. { 0x0000, 0x0000, 0x0000 }, /* R225 */
  316. { 0x0000, 0x0000, 0x0000 }, /* R226 */
  317. { 0x0000, 0x0000, 0x0000 }, /* R227 */
  318. { 0x0000, 0x0000, 0x0000 }, /* R228 */
  319. { 0x0000, 0x0000, 0x0000 }, /* R229 */
  320. { 0x0000, 0x0000, 0x0000 }, /* R230 */
  321. { 0x0000, 0x0000, 0x0000 }, /* R231 */
  322. { 0x0000, 0x0000, 0x0000 }, /* R232 */
  323. { 0x0000, 0x0000, 0x0000 }, /* R233 */
  324. { 0x0000, 0x0000, 0x0000 }, /* R234 */
  325. { 0x0000, 0x0000, 0x0000 }, /* R235 */
  326. { 0x0000, 0x0000, 0x0000 }, /* R236 */
  327. { 0x0000, 0x0000, 0x0000 }, /* R237 */
  328. { 0x0000, 0x0000, 0x0000 }, /* R238 */
  329. { 0x0000, 0x0000, 0x0000 }, /* R239 */
  330. { 0x0000, 0x0000, 0x0000 }, /* R240 */
  331. { 0x0000, 0x0000, 0x0000 }, /* R241 */
  332. { 0x0000, 0x0000, 0x0000 }, /* R242 */
  333. { 0x0000, 0x0000, 0x0000 }, /* R243 */
  334. { 0x0000, 0x0000, 0x0000 }, /* R244 */
  335. { 0x0000, 0x0000, 0x0000 }, /* R245 */
  336. { 0x0000, 0x0000, 0x0000 }, /* R246 */
  337. { 0x0000, 0x0000, 0x0000 }, /* R247 */
  338. { 0x0000, 0x0000, 0x0000 }, /* R248 */
  339. { 0x0000, 0x0000, 0x0000 }, /* R249 */
  340. { 0x0000, 0x0000, 0x0000 }, /* R250 */
  341. { 0x0000, 0x0000, 0x0000 }, /* R251 */
  342. { 0x0000, 0x0000, 0x0000 }, /* R252 */
  343. { 0x0000, 0x0000, 0x0000 }, /* R253 */
  344. { 0x0000, 0x0000, 0x0000 }, /* R254 */
  345. { 0x0000, 0x0000, 0x0000 }, /* R255 */
  346. { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */
  347. { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */
  348. { 0x0000, 0x0000, 0x0000 }, /* R258 */
  349. { 0x0000, 0x0000, 0x0000 }, /* R259 */
  350. { 0x0000, 0x0000, 0x0000 }, /* R260 */
  351. { 0x0000, 0x0000, 0x0000 }, /* R261 */
  352. { 0x0000, 0x0000, 0x0000 }, /* R262 */
  353. { 0x0000, 0x0000, 0x0000 }, /* R263 */
  354. { 0x0000, 0x0000, 0x0000 }, /* R264 */
  355. { 0x0000, 0x0000, 0x0000 }, /* R265 */
  356. { 0x0000, 0x0000, 0x0000 }, /* R266 */
  357. { 0x0000, 0x0000, 0x0000 }, /* R267 */
  358. { 0x0000, 0x0000, 0x0000 }, /* R268 */
  359. { 0x0000, 0x0000, 0x0000 }, /* R269 */
  360. { 0x0000, 0x0000, 0x0000 }, /* R270 */
  361. { 0x0000, 0x0000, 0x0000 }, /* R271 */
  362. { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
  363. { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
  364. { 0x0000, 0x0000, 0x0000 }, /* R274 */
  365. { 0x0000, 0x0000, 0x0000 }, /* R275 */
  366. { 0x0000, 0x0000, 0x0000 }, /* R276 */
  367. { 0x0000, 0x0000, 0x0000 }, /* R277 */
  368. { 0x0000, 0x0000, 0x0000 }, /* R278 */
  369. { 0x0000, 0x0000, 0x0000 }, /* R279 */
  370. { 0x0000, 0x0000, 0x0000 }, /* R280 */
  371. { 0x0000, 0x0000, 0x0000 }, /* R281 */
  372. { 0x0000, 0x0000, 0x0000 }, /* R282 */
  373. { 0x0000, 0x0000, 0x0000 }, /* R283 */
  374. { 0x0000, 0x0000, 0x0000 }, /* R284 */
  375. { 0x0000, 0x0000, 0x0000 }, /* R285 */
  376. { 0x0000, 0x0000, 0x0000 }, /* R286 */
  377. { 0x0000, 0x0000, 0x0000 }, /* R287 */
  378. { 0x0000, 0x0000, 0x0000 }, /* R288 */
  379. { 0x0000, 0x0000, 0x0000 }, /* R289 */
  380. { 0x0000, 0x0000, 0x0000 }, /* R290 */
  381. { 0x0000, 0x0000, 0x0000 }, /* R291 */
  382. { 0x0000, 0x0000, 0x0000 }, /* R292 */
  383. { 0x0000, 0x0000, 0x0000 }, /* R293 */
  384. { 0x0000, 0x0000, 0x0000 }, /* R294 */
  385. { 0x0000, 0x0000, 0x0000 }, /* R295 */
  386. { 0x0000, 0x0000, 0x0000 }, /* R296 */
  387. { 0x0000, 0x0000, 0x0000 }, /* R297 */
  388. { 0x0000, 0x0000, 0x0000 }, /* R298 */
  389. { 0x0000, 0x0000, 0x0000 }, /* R299 */
  390. { 0x0000, 0x0000, 0x0000 }, /* R300 */
  391. { 0x0000, 0x0000, 0x0000 }, /* R301 */
  392. { 0x0000, 0x0000, 0x0000 }, /* R302 */
  393. { 0x0000, 0x0000, 0x0000 }, /* R303 */
  394. { 0x0000, 0x0000, 0x0000 }, /* R304 */
  395. { 0x0000, 0x0000, 0x0000 }, /* R305 */
  396. { 0x0000, 0x0000, 0x0000 }, /* R306 */
  397. { 0x0000, 0x0000, 0x0000 }, /* R307 */
  398. { 0x0000, 0x0000, 0x0000 }, /* R308 */
  399. { 0x0000, 0x0000, 0x0000 }, /* R309 */
  400. { 0x0000, 0x0000, 0x0000 }, /* R310 */
  401. { 0x0000, 0x0000, 0x0000 }, /* R311 */
  402. { 0x0000, 0x0000, 0x0000 }, /* R312 */
  403. { 0x0000, 0x0000, 0x0000 }, /* R313 */
  404. { 0x0000, 0x0000, 0x0000 }, /* R314 */
  405. { 0x0000, 0x0000, 0x0000 }, /* R315 */
  406. { 0x0000, 0x0000, 0x0000 }, /* R316 */
  407. { 0x0000, 0x0000, 0x0000 }, /* R317 */
  408. { 0x0000, 0x0000, 0x0000 }, /* R318 */
  409. { 0x0000, 0x0000, 0x0000 }, /* R319 */
  410. { 0x0000, 0x0000, 0x0000 }, /* R320 */
  411. { 0x0000, 0x0000, 0x0000 }, /* R321 */
  412. { 0x0000, 0x0000, 0x0000 }, /* R322 */
  413. { 0x0000, 0x0000, 0x0000 }, /* R323 */
  414. { 0x0000, 0x0000, 0x0000 }, /* R324 */
  415. { 0x0000, 0x0000, 0x0000 }, /* R325 */
  416. { 0x0000, 0x0000, 0x0000 }, /* R326 */
  417. { 0x0000, 0x0000, 0x0000 }, /* R327 */
  418. { 0x0000, 0x0000, 0x0000 }, /* R328 */
  419. { 0x0000, 0x0000, 0x0000 }, /* R329 */
  420. { 0x0000, 0x0000, 0x0000 }, /* R330 */
  421. { 0x0000, 0x0000, 0x0000 }, /* R331 */
  422. { 0x0000, 0x0000, 0x0000 }, /* R332 */
  423. { 0x0000, 0x0000, 0x0000 }, /* R333 */
  424. { 0x0000, 0x0000, 0x0000 }, /* R334 */
  425. { 0x0000, 0x0000, 0x0000 }, /* R335 */
  426. { 0x0000, 0x0000, 0x0000 }, /* R336 */
  427. { 0x0000, 0x0000, 0x0000 }, /* R337 */
  428. { 0x0000, 0x0000, 0x0000 }, /* R338 */
  429. { 0x0000, 0x0000, 0x0000 }, /* R339 */
  430. { 0x0000, 0x0000, 0x0000 }, /* R340 */
  431. { 0x0000, 0x0000, 0x0000 }, /* R341 */
  432. { 0x0000, 0x0000, 0x0000 }, /* R342 */
  433. { 0x0000, 0x0000, 0x0000 }, /* R343 */
  434. { 0x0000, 0x0000, 0x0000 }, /* R344 */
  435. { 0x0000, 0x0000, 0x0000 }, /* R345 */
  436. { 0x0000, 0x0000, 0x0000 }, /* R346 */
  437. { 0x0000, 0x0000, 0x0000 }, /* R347 */
  438. { 0x0000, 0x0000, 0x0000 }, /* R348 */
  439. { 0x0000, 0x0000, 0x0000 }, /* R349 */
  440. { 0x0000, 0x0000, 0x0000 }, /* R350 */
  441. { 0x0000, 0x0000, 0x0000 }, /* R351 */
  442. { 0x0000, 0x0000, 0x0000 }, /* R352 */
  443. { 0x0000, 0x0000, 0x0000 }, /* R353 */
  444. { 0x0000, 0x0000, 0x0000 }, /* R354 */
  445. { 0x0000, 0x0000, 0x0000 }, /* R355 */
  446. { 0x0000, 0x0000, 0x0000 }, /* R356 */
  447. { 0x0000, 0x0000, 0x0000 }, /* R357 */
  448. { 0x0000, 0x0000, 0x0000 }, /* R358 */
  449. { 0x0000, 0x0000, 0x0000 }, /* R359 */
  450. { 0x0000, 0x0000, 0x0000 }, /* R360 */
  451. { 0x0000, 0x0000, 0x0000 }, /* R361 */
  452. { 0x0000, 0x0000, 0x0000 }, /* R362 */
  453. { 0x0000, 0x0000, 0x0000 }, /* R363 */
  454. { 0x0000, 0x0000, 0x0000 }, /* R364 */
  455. { 0x0000, 0x0000, 0x0000 }, /* R365 */
  456. { 0x0000, 0x0000, 0x0000 }, /* R366 */
  457. { 0x0000, 0x0000, 0x0000 }, /* R367 */
  458. { 0x0000, 0x0000, 0x0000 }, /* R368 */
  459. { 0x0000, 0x0000, 0x0000 }, /* R369 */
  460. { 0x0000, 0x0000, 0x0000 }, /* R370 */
  461. { 0x0000, 0x0000, 0x0000 }, /* R371 */
  462. { 0x0000, 0x0000, 0x0000 }, /* R372 */
  463. { 0x0000, 0x0000, 0x0000 }, /* R373 */
  464. { 0x0000, 0x0000, 0x0000 }, /* R374 */
  465. { 0x0000, 0x0000, 0x0000 }, /* R375 */
  466. { 0x0000, 0x0000, 0x0000 }, /* R376 */
  467. { 0x0000, 0x0000, 0x0000 }, /* R377 */
  468. { 0x0000, 0x0000, 0x0000 }, /* R378 */
  469. { 0x0000, 0x0000, 0x0000 }, /* R379 */
  470. { 0x0000, 0x0000, 0x0000 }, /* R380 */
  471. { 0x0000, 0x0000, 0x0000 }, /* R381 */
  472. { 0x0000, 0x0000, 0x0000 }, /* R382 */
  473. { 0x0000, 0x0000, 0x0000 }, /* R383 */
  474. { 0x0000, 0x0000, 0x0000 }, /* R384 */
  475. { 0x0000, 0x0000, 0x0000 }, /* R385 */
  476. { 0x0000, 0x0000, 0x0000 }, /* R386 */
  477. { 0x0000, 0x0000, 0x0000 }, /* R387 */
  478. { 0x0000, 0x0000, 0x0000 }, /* R388 */
  479. { 0x0000, 0x0000, 0x0000 }, /* R389 */
  480. { 0x0000, 0x0000, 0x0000 }, /* R390 */
  481. { 0x0000, 0x0000, 0x0000 }, /* R391 */
  482. { 0x0000, 0x0000, 0x0000 }, /* R392 */
  483. { 0x0000, 0x0000, 0x0000 }, /* R393 */
  484. { 0x0000, 0x0000, 0x0000 }, /* R394 */
  485. { 0x0000, 0x0000, 0x0000 }, /* R395 */
  486. { 0x0000, 0x0000, 0x0000 }, /* R396 */
  487. { 0x0000, 0x0000, 0x0000 }, /* R397 */
  488. { 0x0000, 0x0000, 0x0000 }, /* R398 */
  489. { 0x0000, 0x0000, 0x0000 }, /* R399 */
  490. { 0x0000, 0x0000, 0x0000 }, /* R400 */
  491. { 0x0000, 0x0000, 0x0000 }, /* R401 */
  492. { 0x0000, 0x0000, 0x0000 }, /* R402 */
  493. { 0x0000, 0x0000, 0x0000 }, /* R403 */
  494. { 0x0000, 0x0000, 0x0000 }, /* R404 */
  495. { 0x0000, 0x0000, 0x0000 }, /* R405 */
  496. { 0x0000, 0x0000, 0x0000 }, /* R406 */
  497. { 0x0000, 0x0000, 0x0000 }, /* R407 */
  498. { 0x0000, 0x0000, 0x0000 }, /* R408 */
  499. { 0x0000, 0x0000, 0x0000 }, /* R409 */
  500. { 0x0000, 0x0000, 0x0000 }, /* R410 */
  501. { 0x0000, 0x0000, 0x0000 }, /* R411 */
  502. { 0x0000, 0x0000, 0x0000 }, /* R412 */
  503. { 0x0000, 0x0000, 0x0000 }, /* R413 */
  504. { 0x0000, 0x0000, 0x0000 }, /* R414 */
  505. { 0x0000, 0x0000, 0x0000 }, /* R415 */
  506. { 0x0000, 0x0000, 0x0000 }, /* R416 */
  507. { 0x0000, 0x0000, 0x0000 }, /* R417 */
  508. { 0x0000, 0x0000, 0x0000 }, /* R418 */
  509. { 0x0000, 0x0000, 0x0000 }, /* R419 */
  510. { 0x0000, 0x0000, 0x0000 }, /* R420 */
  511. { 0x0000, 0x0000, 0x0000 }, /* R421 */
  512. { 0x0000, 0x0000, 0x0000 }, /* R422 */
  513. { 0x0000, 0x0000, 0x0000 }, /* R423 */
  514. { 0x0000, 0x0000, 0x0000 }, /* R424 */
  515. { 0x0000, 0x0000, 0x0000 }, /* R425 */
  516. { 0x0000, 0x0000, 0x0000 }, /* R426 */
  517. { 0x0000, 0x0000, 0x0000 }, /* R427 */
  518. { 0x0000, 0x0000, 0x0000 }, /* R428 */
  519. { 0x0000, 0x0000, 0x0000 }, /* R429 */
  520. { 0x0000, 0x0000, 0x0000 }, /* R430 */
  521. { 0x0000, 0x0000, 0x0000 }, /* R431 */
  522. { 0x0000, 0x0000, 0x0000 }, /* R432 */
  523. { 0x0000, 0x0000, 0x0000 }, /* R433 */
  524. { 0x0000, 0x0000, 0x0000 }, /* R434 */
  525. { 0x0000, 0x0000, 0x0000 }, /* R435 */
  526. { 0x0000, 0x0000, 0x0000 }, /* R436 */
  527. { 0x0000, 0x0000, 0x0000 }, /* R437 */
  528. { 0x0000, 0x0000, 0x0000 }, /* R438 */
  529. { 0x0000, 0x0000, 0x0000 }, /* R439 */
  530. { 0x0000, 0x0000, 0x0000 }, /* R440 */
  531. { 0x0000, 0x0000, 0x0000 }, /* R441 */
  532. { 0x0000, 0x0000, 0x0000 }, /* R442 */
  533. { 0x0000, 0x0000, 0x0000 }, /* R443 */
  534. { 0x0000, 0x0000, 0x0000 }, /* R444 */
  535. { 0x0000, 0x0000, 0x0000 }, /* R445 */
  536. { 0x0000, 0x0000, 0x0000 }, /* R446 */
  537. { 0x0000, 0x0000, 0x0000 }, /* R447 */
  538. { 0x0000, 0x0000, 0x0000 }, /* R448 */
  539. { 0x0000, 0x0000, 0x0000 }, /* R449 */
  540. { 0x0000, 0x0000, 0x0000 }, /* R450 */
  541. { 0x0000, 0x0000, 0x0000 }, /* R451 */
  542. { 0x0000, 0x0000, 0x0000 }, /* R452 */
  543. { 0x0000, 0x0000, 0x0000 }, /* R453 */
  544. { 0x0000, 0x0000, 0x0000 }, /* R454 */
  545. { 0x0000, 0x0000, 0x0000 }, /* R455 */
  546. { 0x0000, 0x0000, 0x0000 }, /* R456 */
  547. { 0x0000, 0x0000, 0x0000 }, /* R457 */
  548. { 0x0000, 0x0000, 0x0000 }, /* R458 */
  549. { 0x0000, 0x0000, 0x0000 }, /* R459 */
  550. { 0x0000, 0x0000, 0x0000 }, /* R460 */
  551. { 0x0000, 0x0000, 0x0000 }, /* R461 */
  552. { 0x0000, 0x0000, 0x0000 }, /* R462 */
  553. { 0x0000, 0x0000, 0x0000 }, /* R463 */
  554. { 0x0000, 0x0000, 0x0000 }, /* R464 */
  555. { 0x0000, 0x0000, 0x0000 }, /* R465 */
  556. { 0x0000, 0x0000, 0x0000 }, /* R466 */
  557. { 0x0000, 0x0000, 0x0000 }, /* R467 */
  558. { 0x0000, 0x0000, 0x0000 }, /* R468 */
  559. { 0x0000, 0x0000, 0x0000 }, /* R469 */
  560. { 0x0000, 0x0000, 0x0000 }, /* R470 */
  561. { 0x0000, 0x0000, 0x0000 }, /* R471 */
  562. { 0x0000, 0x0000, 0x0000 }, /* R472 */
  563. { 0x0000, 0x0000, 0x0000 }, /* R473 */
  564. { 0x0000, 0x0000, 0x0000 }, /* R474 */
  565. { 0x0000, 0x0000, 0x0000 }, /* R475 */
  566. { 0x0000, 0x0000, 0x0000 }, /* R476 */
  567. { 0x0000, 0x0000, 0x0000 }, /* R477 */
  568. { 0x0000, 0x0000, 0x0000 }, /* R478 */
  569. { 0x0000, 0x0000, 0x0000 }, /* R479 */
  570. { 0x0000, 0x0000, 0x0000 }, /* R480 */
  571. { 0x0000, 0x0000, 0x0000 }, /* R481 */
  572. { 0x0000, 0x0000, 0x0000 }, /* R482 */
  573. { 0x0000, 0x0000, 0x0000 }, /* R483 */
  574. { 0x0000, 0x0000, 0x0000 }, /* R484 */
  575. { 0x0000, 0x0000, 0x0000 }, /* R485 */
  576. { 0x0000, 0x0000, 0x0000 }, /* R486 */
  577. { 0x0000, 0x0000, 0x0000 }, /* R487 */
  578. { 0x0000, 0x0000, 0x0000 }, /* R488 */
  579. { 0x0000, 0x0000, 0x0000 }, /* R489 */
  580. { 0x0000, 0x0000, 0x0000 }, /* R490 */
  581. { 0x0000, 0x0000, 0x0000 }, /* R491 */
  582. { 0x0000, 0x0000, 0x0000 }, /* R492 */
  583. { 0x0000, 0x0000, 0x0000 }, /* R493 */
  584. { 0x0000, 0x0000, 0x0000 }, /* R494 */
  585. { 0x0000, 0x0000, 0x0000 }, /* R495 */
  586. { 0x0000, 0x0000, 0x0000 }, /* R496 */
  587. { 0x0000, 0x0000, 0x0000 }, /* R497 */
  588. { 0x0000, 0x0000, 0x0000 }, /* R498 */
  589. { 0x0000, 0x0000, 0x0000 }, /* R499 */
  590. { 0x0000, 0x0000, 0x0000 }, /* R500 */
  591. { 0x0000, 0x0000, 0x0000 }, /* R501 */
  592. { 0x0000, 0x0000, 0x0000 }, /* R502 */
  593. { 0x0000, 0x0000, 0x0000 }, /* R503 */
  594. { 0x0000, 0x0000, 0x0000 }, /* R504 */
  595. { 0x0000, 0x0000, 0x0000 }, /* R505 */
  596. { 0x0000, 0x0000, 0x0000 }, /* R506 */
  597. { 0x0000, 0x0000, 0x0000 }, /* R507 */
  598. { 0x0000, 0x0000, 0x0000 }, /* R508 */
  599. { 0x0000, 0x0000, 0x0000 }, /* R509 */
  600. { 0x0000, 0x0000, 0x0000 }, /* R510 */
  601. { 0x0000, 0x0000, 0x0000 }, /* R511 */
  602. { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */
  603. { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */
  604. { 0x0000, 0x0000, 0x0000 }, /* R514 */
  605. { 0x0000, 0x0000, 0x0000 }, /* R515 */
  606. { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */
  607. { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */
  608. { 0x0000, 0x0000, 0x0000 }, /* R518 */
  609. { 0x0000, 0x0000, 0x0000 }, /* R519 */
  610. { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */
  611. { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */
  612. { 0x0000, 0x0000, 0x0000 }, /* R522 */
  613. { 0x0000, 0x0000, 0x0000 }, /* R523 */
  614. { 0x0000, 0x0000, 0x0000 }, /* R524 */
  615. { 0x0000, 0x0000, 0x0000 }, /* R525 */
  616. { 0x0000, 0x0000, 0x0000 }, /* R526 */
  617. { 0x0000, 0x0000, 0x0000 }, /* R527 */
  618. { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */
  619. { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */
  620. { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */
  621. { 0x0000, 0x0000, 0x0000 }, /* R531 */
  622. { 0x0000, 0x0000, 0x0000 }, /* R532 */
  623. { 0x0000, 0x0000, 0x0000 }, /* R533 */
  624. { 0x0000, 0x0000, 0x0000 }, /* R534 */
  625. { 0x0000, 0x0000, 0x0000 }, /* R535 */
  626. { 0x0000, 0x0000, 0x0000 }, /* R536 */
  627. { 0x0000, 0x0000, 0x0000 }, /* R537 */
  628. { 0x0000, 0x0000, 0x0000 }, /* R538 */
  629. { 0x0000, 0x0000, 0x0000 }, /* R539 */
  630. { 0x0000, 0x0000, 0x0000 }, /* R540 */
  631. { 0x0000, 0x0000, 0x0000 }, /* R541 */
  632. { 0x0000, 0x0000, 0x0000 }, /* R542 */
  633. { 0x0000, 0x0000, 0x0000 }, /* R543 */
  634. { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */
  635. { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */
  636. { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */
  637. { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */
  638. { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */
  639. { 0x0000, 0x0000, 0x0000 }, /* R549 */
  640. { 0x0000, 0x0000, 0x0000 }, /* R550 */
  641. { 0x0000, 0x0000, 0x0000 }, /* R551 */
  642. { 0x0000, 0x0000, 0x0000 }, /* R552 */
  643. { 0x0000, 0x0000, 0x0000 }, /* R553 */
  644. { 0x0000, 0x0000, 0x0000 }, /* R554 */
  645. { 0x0000, 0x0000, 0x0000 }, /* R555 */
  646. { 0x0000, 0x0000, 0x0000 }, /* R556 */
  647. { 0x0000, 0x0000, 0x0000 }, /* R557 */
  648. { 0x0000, 0x0000, 0x0000 }, /* R558 */
  649. { 0x0000, 0x0000, 0x0000 }, /* R559 */
  650. { 0x0000, 0x0000, 0x0000 }, /* R560 */
  651. { 0x0000, 0x0000, 0x0000 }, /* R561 */
  652. { 0x0000, 0x0000, 0x0000 }, /* R562 */
  653. { 0x0000, 0x0000, 0x0000 }, /* R563 */
  654. { 0x0000, 0x0000, 0x0000 }, /* R564 */
  655. { 0x0000, 0x0000, 0x0000 }, /* R565 */
  656. { 0x0000, 0x0000, 0x0000 }, /* R566 */
  657. { 0x0000, 0x0000, 0x0000 }, /* R567 */
  658. { 0x0000, 0x0000, 0x0000 }, /* R568 */
  659. { 0x0000, 0x0000, 0x0000 }, /* R569 */
  660. { 0x0000, 0x0000, 0x0000 }, /* R570 */
  661. { 0x0000, 0x0000, 0x0000 }, /* R571 */
  662. { 0x0000, 0x0000, 0x0000 }, /* R572 */
  663. { 0x0000, 0x0000, 0x0000 }, /* R573 */
  664. { 0x0000, 0x0000, 0x0000 }, /* R574 */
  665. { 0x0000, 0x0000, 0x0000 }, /* R575 */
  666. { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */
  667. { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */
  668. { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */
  669. { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */
  670. { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */
  671. { 0x0000, 0x0000, 0x0000 }, /* R581 */
  672. { 0x0000, 0x0000, 0x0000 }, /* R582 */
  673. { 0x0000, 0x0000, 0x0000 }, /* R583 */
  674. { 0x0000, 0x0000, 0x0000 }, /* R584 */
  675. { 0x0000, 0x0000, 0x0000 }, /* R585 */
  676. { 0x0000, 0x0000, 0x0000 }, /* R586 */
  677. { 0x0000, 0x0000, 0x0000 }, /* R587 */
  678. { 0x0000, 0x0000, 0x0000 }, /* R588 */
  679. { 0x0000, 0x0000, 0x0000 }, /* R589 */
  680. { 0x0000, 0x0000, 0x0000 }, /* R590 */
  681. { 0x0000, 0x0000, 0x0000 }, /* R591 */
  682. { 0x0000, 0x0000, 0x0000 }, /* R592 */
  683. { 0x0000, 0x0000, 0x0000 }, /* R593 */
  684. { 0x0000, 0x0000, 0x0000 }, /* R594 */
  685. { 0x0000, 0x0000, 0x0000 }, /* R595 */
  686. { 0x0000, 0x0000, 0x0000 }, /* R596 */
  687. { 0x0000, 0x0000, 0x0000 }, /* R597 */
  688. { 0x0000, 0x0000, 0x0000 }, /* R598 */
  689. { 0x0000, 0x0000, 0x0000 }, /* R599 */
  690. { 0x0000, 0x0000, 0x0000 }, /* R600 */
  691. { 0x0000, 0x0000, 0x0000 }, /* R601 */
  692. { 0x0000, 0x0000, 0x0000 }, /* R602 */
  693. { 0x0000, 0x0000, 0x0000 }, /* R603 */
  694. { 0x0000, 0x0000, 0x0000 }, /* R604 */
  695. { 0x0000, 0x0000, 0x0000 }, /* R605 */
  696. { 0x0000, 0x0000, 0x0000 }, /* R606 */
  697. { 0x0000, 0x0000, 0x0000 }, /* R607 */
  698. { 0x0000, 0x0000, 0x0000 }, /* R608 */
  699. { 0x0000, 0x0000, 0x0000 }, /* R609 */
  700. { 0x0000, 0x0000, 0x0000 }, /* R610 */
  701. { 0x0000, 0x0000, 0x0000 }, /* R611 */
  702. { 0x0000, 0x0000, 0x0000 }, /* R612 */
  703. { 0x0000, 0x0000, 0x0000 }, /* R613 */
  704. { 0x0000, 0x0000, 0x0000 }, /* R614 */
  705. { 0x0000, 0x0000, 0x0000 }, /* R615 */
  706. { 0x0000, 0x0000, 0x0000 }, /* R616 */
  707. { 0x0000, 0x0000, 0x0000 }, /* R617 */
  708. { 0x0000, 0x0000, 0x0000 }, /* R618 */
  709. { 0x0000, 0x0000, 0x0000 }, /* R619 */
  710. { 0x0000, 0x0000, 0x0000 }, /* R620 */
  711. { 0x0000, 0x0000, 0x0000 }, /* R621 */
  712. { 0x0000, 0x0000, 0x0000 }, /* R622 */
  713. { 0x0000, 0x0000, 0x0000 }, /* R623 */
  714. { 0x0000, 0x0000, 0x0000 }, /* R624 */
  715. { 0x0000, 0x0000, 0x0000 }, /* R625 */
  716. { 0x0000, 0x0000, 0x0000 }, /* R626 */
  717. { 0x0000, 0x0000, 0x0000 }, /* R627 */
  718. { 0x0000, 0x0000, 0x0000 }, /* R628 */
  719. { 0x0000, 0x0000, 0x0000 }, /* R629 */
  720. { 0x0000, 0x0000, 0x0000 }, /* R630 */
  721. { 0x0000, 0x0000, 0x0000 }, /* R631 */
  722. { 0x0000, 0x0000, 0x0000 }, /* R632 */
  723. { 0x0000, 0x0000, 0x0000 }, /* R633 */
  724. { 0x0000, 0x0000, 0x0000 }, /* R634 */
  725. { 0x0000, 0x0000, 0x0000 }, /* R635 */
  726. { 0x0000, 0x0000, 0x0000 }, /* R636 */
  727. { 0x0000, 0x0000, 0x0000 }, /* R637 */
  728. { 0x0000, 0x0000, 0x0000 }, /* R638 */
  729. { 0x0000, 0x0000, 0x0000 }, /* R639 */
  730. { 0x0000, 0x0000, 0x0000 }, /* R640 */
  731. { 0x0000, 0x0000, 0x0000 }, /* R641 */
  732. { 0x0000, 0x0000, 0x0000 }, /* R642 */
  733. { 0x0000, 0x0000, 0x0000 }, /* R643 */
  734. { 0x0000, 0x0000, 0x0000 }, /* R644 */
  735. { 0x0000, 0x0000, 0x0000 }, /* R645 */
  736. { 0x0000, 0x0000, 0x0000 }, /* R646 */
  737. { 0x0000, 0x0000, 0x0000 }, /* R647 */
  738. { 0x0000, 0x0000, 0x0000 }, /* R648 */
  739. { 0x0000, 0x0000, 0x0000 }, /* R649 */
  740. { 0x0000, 0x0000, 0x0000 }, /* R650 */
  741. { 0x0000, 0x0000, 0x0000 }, /* R651 */
  742. { 0x0000, 0x0000, 0x0000 }, /* R652 */
  743. { 0x0000, 0x0000, 0x0000 }, /* R653 */
  744. { 0x0000, 0x0000, 0x0000 }, /* R654 */
  745. { 0x0000, 0x0000, 0x0000 }, /* R655 */
  746. { 0x0000, 0x0000, 0x0000 }, /* R656 */
  747. { 0x0000, 0x0000, 0x0000 }, /* R657 */
  748. { 0x0000, 0x0000, 0x0000 }, /* R658 */
  749. { 0x0000, 0x0000, 0x0000 }, /* R659 */
  750. { 0x0000, 0x0000, 0x0000 }, /* R660 */
  751. { 0x0000, 0x0000, 0x0000 }, /* R661 */
  752. { 0x0000, 0x0000, 0x0000 }, /* R662 */
  753. { 0x0000, 0x0000, 0x0000 }, /* R663 */
  754. { 0x0000, 0x0000, 0x0000 }, /* R664 */
  755. { 0x0000, 0x0000, 0x0000 }, /* R665 */
  756. { 0x0000, 0x0000, 0x0000 }, /* R666 */
  757. { 0x0000, 0x0000, 0x0000 }, /* R667 */
  758. { 0x0000, 0x0000, 0x0000 }, /* R668 */
  759. { 0x0000, 0x0000, 0x0000 }, /* R669 */
  760. { 0x0000, 0x0000, 0x0000 }, /* R670 */
  761. { 0x0000, 0x0000, 0x0000 }, /* R671 */
  762. { 0x0000, 0x0000, 0x0000 }, /* R672 */
  763. { 0x0000, 0x0000, 0x0000 }, /* R673 */
  764. { 0x0000, 0x0000, 0x0000 }, /* R674 */
  765. { 0x0000, 0x0000, 0x0000 }, /* R675 */
  766. { 0x0000, 0x0000, 0x0000 }, /* R676 */
  767. { 0x0000, 0x0000, 0x0000 }, /* R677 */
  768. { 0x0000, 0x0000, 0x0000 }, /* R678 */
  769. { 0x0000, 0x0000, 0x0000 }, /* R679 */
  770. { 0x0000, 0x0000, 0x0000 }, /* R680 */
  771. { 0x0000, 0x0000, 0x0000 }, /* R681 */
  772. { 0x0000, 0x0000, 0x0000 }, /* R682 */
  773. { 0x0000, 0x0000, 0x0000 }, /* R683 */
  774. { 0x0000, 0x0000, 0x0000 }, /* R684 */
  775. { 0x0000, 0x0000, 0x0000 }, /* R685 */
  776. { 0x0000, 0x0000, 0x0000 }, /* R686 */
  777. { 0x0000, 0x0000, 0x0000 }, /* R687 */
  778. { 0x0000, 0x0000, 0x0000 }, /* R688 */
  779. { 0x0000, 0x0000, 0x0000 }, /* R689 */
  780. { 0x0000, 0x0000, 0x0000 }, /* R690 */
  781. { 0x0000, 0x0000, 0x0000 }, /* R691 */
  782. { 0x0000, 0x0000, 0x0000 }, /* R692 */
  783. { 0x0000, 0x0000, 0x0000 }, /* R693 */
  784. { 0x0000, 0x0000, 0x0000 }, /* R694 */
  785. { 0x0000, 0x0000, 0x0000 }, /* R695 */
  786. { 0x0000, 0x0000, 0x0000 }, /* R696 */
  787. { 0x0000, 0x0000, 0x0000 }, /* R697 */
  788. { 0x0000, 0x0000, 0x0000 }, /* R698 */
  789. { 0x0000, 0x0000, 0x0000 }, /* R699 */
  790. { 0x0000, 0x0000, 0x0000 }, /* R700 */
  791. { 0x0000, 0x0000, 0x0000 }, /* R701 */
  792. { 0x0000, 0x0000, 0x0000 }, /* R702 */
  793. { 0x0000, 0x0000, 0x0000 }, /* R703 */
  794. { 0x0000, 0x0000, 0x0000 }, /* R704 */
  795. { 0x0000, 0x0000, 0x0000 }, /* R705 */
  796. { 0x0000, 0x0000, 0x0000 }, /* R706 */
  797. { 0x0000, 0x0000, 0x0000 }, /* R707 */
  798. { 0x0000, 0x0000, 0x0000 }, /* R708 */
  799. { 0x0000, 0x0000, 0x0000 }, /* R709 */
  800. { 0x0000, 0x0000, 0x0000 }, /* R710 */
  801. { 0x0000, 0x0000, 0x0000 }, /* R711 */
  802. { 0x0000, 0x0000, 0x0000 }, /* R712 */
  803. { 0x0000, 0x0000, 0x0000 }, /* R713 */
  804. { 0x0000, 0x0000, 0x0000 }, /* R714 */
  805. { 0x0000, 0x0000, 0x0000 }, /* R715 */
  806. { 0x0000, 0x0000, 0x0000 }, /* R716 */
  807. { 0x0000, 0x0000, 0x0000 }, /* R717 */
  808. { 0x0000, 0x0000, 0x0000 }, /* R718 */
  809. { 0x0000, 0x0000, 0x0000 }, /* R719 */
  810. { 0x0000, 0x0000, 0x0000 }, /* R720 */
  811. { 0x0000, 0x0000, 0x0000 }, /* R721 */
  812. { 0x0000, 0x0000, 0x0000 }, /* R722 */
  813. { 0x0000, 0x0000, 0x0000 }, /* R723 */
  814. { 0x0000, 0x0000, 0x0000 }, /* R724 */
  815. { 0x0000, 0x0000, 0x0000 }, /* R725 */
  816. { 0x0000, 0x0000, 0x0000 }, /* R726 */
  817. { 0x0000, 0x0000, 0x0000 }, /* R727 */
  818. { 0x0000, 0x0000, 0x0000 }, /* R728 */
  819. { 0x0000, 0x0000, 0x0000 }, /* R729 */
  820. { 0x0000, 0x0000, 0x0000 }, /* R730 */
  821. { 0x0000, 0x0000, 0x0000 }, /* R731 */
  822. { 0x0000, 0x0000, 0x0000 }, /* R732 */
  823. { 0x0000, 0x0000, 0x0000 }, /* R733 */
  824. { 0x0000, 0x0000, 0x0000 }, /* R734 */
  825. { 0x0000, 0x0000, 0x0000 }, /* R735 */
  826. { 0x0000, 0x0000, 0x0000 }, /* R736 */
  827. { 0x0000, 0x0000, 0x0000 }, /* R737 */
  828. { 0x0000, 0x0000, 0x0000 }, /* R738 */
  829. { 0x0000, 0x0000, 0x0000 }, /* R739 */
  830. { 0x0000, 0x0000, 0x0000 }, /* R740 */
  831. { 0x0000, 0x0000, 0x0000 }, /* R741 */
  832. { 0x0000, 0x0000, 0x0000 }, /* R742 */
  833. { 0x0000, 0x0000, 0x0000 }, /* R743 */
  834. { 0x0000, 0x0000, 0x0000 }, /* R744 */
  835. { 0x0000, 0x0000, 0x0000 }, /* R745 */
  836. { 0x0000, 0x0000, 0x0000 }, /* R746 */
  837. { 0x0000, 0x0000, 0x0000 }, /* R747 */
  838. { 0x0000, 0x0000, 0x0000 }, /* R748 */
  839. { 0x0000, 0x0000, 0x0000 }, /* R749 */
  840. { 0x0000, 0x0000, 0x0000 }, /* R750 */
  841. { 0x0000, 0x0000, 0x0000 }, /* R751 */
  842. { 0x0000, 0x0000, 0x0000 }, /* R752 */
  843. { 0x0000, 0x0000, 0x0000 }, /* R753 */
  844. { 0x0000, 0x0000, 0x0000 }, /* R754 */
  845. { 0x0000, 0x0000, 0x0000 }, /* R755 */
  846. { 0x0000, 0x0000, 0x0000 }, /* R756 */
  847. { 0x0000, 0x0000, 0x0000 }, /* R757 */
  848. { 0x0000, 0x0000, 0x0000 }, /* R758 */
  849. { 0x0000, 0x0000, 0x0000 }, /* R759 */
  850. { 0x0000, 0x0000, 0x0000 }, /* R760 */
  851. { 0x0000, 0x0000, 0x0000 }, /* R761 */
  852. { 0x0000, 0x0000, 0x0000 }, /* R762 */
  853. { 0x0000, 0x0000, 0x0000 }, /* R763 */
  854. { 0x0000, 0x0000, 0x0000 }, /* R764 */
  855. { 0x0000, 0x0000, 0x0000 }, /* R765 */
  856. { 0x0000, 0x0000, 0x0000 }, /* R766 */
  857. { 0x0000, 0x0000, 0x0000 }, /* R767 */
  858. { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */
  859. { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */
  860. { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */
  861. { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */
  862. { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */
  863. { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */
  864. { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */
  865. { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */
  866. { 0x0000, 0x0000, 0x0000 }, /* R776 */
  867. { 0x0000, 0x0000, 0x0000 }, /* R777 */
  868. { 0x0000, 0x0000, 0x0000 }, /* R778 */
  869. { 0x0000, 0x0000, 0x0000 }, /* R779 */
  870. { 0x0000, 0x0000, 0x0000 }, /* R780 */
  871. { 0x0000, 0x0000, 0x0000 }, /* R781 */
  872. { 0x0000, 0x0000, 0x0000 }, /* R782 */
  873. { 0x0000, 0x0000, 0x0000 }, /* R783 */
  874. { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */
  875. { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */
  876. { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */
  877. { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */
  878. { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */
  879. { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */
  880. { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */
  881. { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */
  882. { 0x0000, 0x0000, 0x0000 }, /* R792 */
  883. { 0x0000, 0x0000, 0x0000 }, /* R793 */
  884. { 0x0000, 0x0000, 0x0000 }, /* R794 */
  885. { 0x0000, 0x0000, 0x0000 }, /* R795 */
  886. { 0x0000, 0x0000, 0x0000 }, /* R796 */
  887. { 0x0000, 0x0000, 0x0000 }, /* R797 */
  888. { 0x0000, 0x0000, 0x0000 }, /* R798 */
  889. { 0x0000, 0x0000, 0x0000 }, /* R799 */
  890. { 0x0000, 0x0000, 0x0000 }, /* R800 */
  891. { 0x0000, 0x0000, 0x0000 }, /* R801 */
  892. { 0x0000, 0x0000, 0x0000 }, /* R802 */
  893. { 0x0000, 0x0000, 0x0000 }, /* R803 */
  894. { 0x0000, 0x0000, 0x0000 }, /* R804 */
  895. { 0x0000, 0x0000, 0x0000 }, /* R805 */
  896. { 0x0000, 0x0000, 0x0000 }, /* R806 */
  897. { 0x0000, 0x0000, 0x0000 }, /* R807 */
  898. { 0x0000, 0x0000, 0x0000 }, /* R808 */
  899. { 0x0000, 0x0000, 0x0000 }, /* R809 */
  900. { 0x0000, 0x0000, 0x0000 }, /* R810 */
  901. { 0x0000, 0x0000, 0x0000 }, /* R811 */
  902. { 0x0000, 0x0000, 0x0000 }, /* R812 */
  903. { 0x0000, 0x0000, 0x0000 }, /* R813 */
  904. { 0x0000, 0x0000, 0x0000 }, /* R814 */
  905. { 0x0000, 0x0000, 0x0000 }, /* R815 */
  906. { 0x0000, 0x0000, 0x0000 }, /* R816 */
  907. { 0x0000, 0x0000, 0x0000 }, /* R817 */
  908. { 0x0000, 0x0000, 0x0000 }, /* R818 */
  909. { 0x0000, 0x0000, 0x0000 }, /* R819 */
  910. { 0x0000, 0x0000, 0x0000 }, /* R820 */
  911. { 0x0000, 0x0000, 0x0000 }, /* R821 */
  912. { 0x0000, 0x0000, 0x0000 }, /* R822 */
  913. { 0x0000, 0x0000, 0x0000 }, /* R823 */
  914. { 0x0000, 0x0000, 0x0000 }, /* R824 */
  915. { 0x0000, 0x0000, 0x0000 }, /* R825 */
  916. { 0x0000, 0x0000, 0x0000 }, /* R826 */
  917. { 0x0000, 0x0000, 0x0000 }, /* R827 */
  918. { 0x0000, 0x0000, 0x0000 }, /* R828 */
  919. { 0x0000, 0x0000, 0x0000 }, /* R829 */
  920. { 0x0000, 0x0000, 0x0000 }, /* R830 */
  921. { 0x0000, 0x0000, 0x0000 }, /* R831 */
  922. { 0x0000, 0x0000, 0x0000 }, /* R832 */
  923. { 0x0000, 0x0000, 0x0000 }, /* R833 */
  924. { 0x0000, 0x0000, 0x0000 }, /* R834 */
  925. { 0x0000, 0x0000, 0x0000 }, /* R835 */
  926. { 0x0000, 0x0000, 0x0000 }, /* R836 */
  927. { 0x0000, 0x0000, 0x0000 }, /* R837 */
  928. { 0x0000, 0x0000, 0x0000 }, /* R838 */
  929. { 0x0000, 0x0000, 0x0000 }, /* R839 */
  930. { 0x0000, 0x0000, 0x0000 }, /* R840 */
  931. { 0x0000, 0x0000, 0x0000 }, /* R841 */
  932. { 0x0000, 0x0000, 0x0000 }, /* R842 */
  933. { 0x0000, 0x0000, 0x0000 }, /* R843 */
  934. { 0x0000, 0x0000, 0x0000 }, /* R844 */
  935. { 0x0000, 0x0000, 0x0000 }, /* R845 */
  936. { 0x0000, 0x0000, 0x0000 }, /* R846 */
  937. { 0x0000, 0x0000, 0x0000 }, /* R847 */
  938. { 0x0000, 0x0000, 0x0000 }, /* R848 */
  939. { 0x0000, 0x0000, 0x0000 }, /* R849 */
  940. { 0x0000, 0x0000, 0x0000 }, /* R850 */
  941. { 0x0000, 0x0000, 0x0000 }, /* R851 */
  942. { 0x0000, 0x0000, 0x0000 }, /* R852 */
  943. { 0x0000, 0x0000, 0x0000 }, /* R853 */
  944. { 0x0000, 0x0000, 0x0000 }, /* R854 */
  945. { 0x0000, 0x0000, 0x0000 }, /* R855 */
  946. { 0x0000, 0x0000, 0x0000 }, /* R856 */
  947. { 0x0000, 0x0000, 0x0000 }, /* R857 */
  948. { 0x0000, 0x0000, 0x0000 }, /* R858 */
  949. { 0x0000, 0x0000, 0x0000 }, /* R859 */
  950. { 0x0000, 0x0000, 0x0000 }, /* R860 */
  951. { 0x0000, 0x0000, 0x0000 }, /* R861 */
  952. { 0x0000, 0x0000, 0x0000 }, /* R862 */
  953. { 0x0000, 0x0000, 0x0000 }, /* R863 */
  954. { 0x0000, 0x0000, 0x0000 }, /* R864 */
  955. { 0x0000, 0x0000, 0x0000 }, /* R865 */
  956. { 0x0000, 0x0000, 0x0000 }, /* R866 */
  957. { 0x0000, 0x0000, 0x0000 }, /* R867 */
  958. { 0x0000, 0x0000, 0x0000 }, /* R868 */
  959. { 0x0000, 0x0000, 0x0000 }, /* R869 */
  960. { 0x0000, 0x0000, 0x0000 }, /* R870 */
  961. { 0x0000, 0x0000, 0x0000 }, /* R871 */
  962. { 0x0000, 0x0000, 0x0000 }, /* R872 */
  963. { 0x0000, 0x0000, 0x0000 }, /* R873 */
  964. { 0x0000, 0x0000, 0x0000 }, /* R874 */
  965. { 0x0000, 0x0000, 0x0000 }, /* R875 */
  966. { 0x0000, 0x0000, 0x0000 }, /* R876 */
  967. { 0x0000, 0x0000, 0x0000 }, /* R877 */
  968. { 0x0000, 0x0000, 0x0000 }, /* R878 */
  969. { 0x0000, 0x0000, 0x0000 }, /* R879 */
  970. { 0x0000, 0x0000, 0x0000 }, /* R880 */
  971. { 0x0000, 0x0000, 0x0000 }, /* R881 */
  972. { 0x0000, 0x0000, 0x0000 }, /* R882 */
  973. { 0x0000, 0x0000, 0x0000 }, /* R883 */
  974. { 0x0000, 0x0000, 0x0000 }, /* R884 */
  975. { 0x0000, 0x0000, 0x0000 }, /* R885 */
  976. { 0x0000, 0x0000, 0x0000 }, /* R886 */
  977. { 0x0000, 0x0000, 0x0000 }, /* R887 */
  978. { 0x0000, 0x0000, 0x0000 }, /* R888 */
  979. { 0x0000, 0x0000, 0x0000 }, /* R889 */
  980. { 0x0000, 0x0000, 0x0000 }, /* R890 */
  981. { 0x0000, 0x0000, 0x0000 }, /* R891 */
  982. { 0x0000, 0x0000, 0x0000 }, /* R892 */
  983. { 0x0000, 0x0000, 0x0000 }, /* R893 */
  984. { 0x0000, 0x0000, 0x0000 }, /* R894 */
  985. { 0x0000, 0x0000, 0x0000 }, /* R895 */
  986. { 0x0000, 0x0000, 0x0000 }, /* R896 */
  987. { 0x0000, 0x0000, 0x0000 }, /* R897 */
  988. { 0x0000, 0x0000, 0x0000 }, /* R898 */
  989. { 0x0000, 0x0000, 0x0000 }, /* R899 */
  990. { 0x0000, 0x0000, 0x0000 }, /* R900 */
  991. { 0x0000, 0x0000, 0x0000 }, /* R901 */
  992. { 0x0000, 0x0000, 0x0000 }, /* R902 */
  993. { 0x0000, 0x0000, 0x0000 }, /* R903 */
  994. { 0x0000, 0x0000, 0x0000 }, /* R904 */
  995. { 0x0000, 0x0000, 0x0000 }, /* R905 */
  996. { 0x0000, 0x0000, 0x0000 }, /* R906 */
  997. { 0x0000, 0x0000, 0x0000 }, /* R907 */
  998. { 0x0000, 0x0000, 0x0000 }, /* R908 */
  999. { 0x0000, 0x0000, 0x0000 }, /* R909 */
  1000. { 0x0000, 0x0000, 0x0000 }, /* R910 */
  1001. { 0x0000, 0x0000, 0x0000 }, /* R911 */
  1002. { 0x0000, 0x0000, 0x0000 }, /* R912 */
  1003. { 0x0000, 0x0000, 0x0000 }, /* R913 */
  1004. { 0x0000, 0x0000, 0x0000 }, /* R914 */
  1005. { 0x0000, 0x0000, 0x0000 }, /* R915 */
  1006. { 0x0000, 0x0000, 0x0000 }, /* R916 */
  1007. { 0x0000, 0x0000, 0x0000 }, /* R917 */
  1008. { 0x0000, 0x0000, 0x0000 }, /* R918 */
  1009. { 0x0000, 0x0000, 0x0000 }, /* R919 */
  1010. { 0x0000, 0x0000, 0x0000 }, /* R920 */
  1011. { 0x0000, 0x0000, 0x0000 }, /* R921 */
  1012. { 0x0000, 0x0000, 0x0000 }, /* R922 */
  1013. { 0x0000, 0x0000, 0x0000 }, /* R923 */
  1014. { 0x0000, 0x0000, 0x0000 }, /* R924 */
  1015. { 0x0000, 0x0000, 0x0000 }, /* R925 */
  1016. { 0x0000, 0x0000, 0x0000 }, /* R926 */
  1017. { 0x0000, 0x0000, 0x0000 }, /* R927 */
  1018. { 0x0000, 0x0000, 0x0000 }, /* R928 */
  1019. { 0x0000, 0x0000, 0x0000 }, /* R929 */
  1020. { 0x0000, 0x0000, 0x0000 }, /* R930 */
  1021. { 0x0000, 0x0000, 0x0000 }, /* R931 */
  1022. { 0x0000, 0x0000, 0x0000 }, /* R932 */
  1023. { 0x0000, 0x0000, 0x0000 }, /* R933 */
  1024. { 0x0000, 0x0000, 0x0000 }, /* R934 */
  1025. { 0x0000, 0x0000, 0x0000 }, /* R935 */
  1026. { 0x0000, 0x0000, 0x0000 }, /* R936 */
  1027. { 0x0000, 0x0000, 0x0000 }, /* R937 */
  1028. { 0x0000, 0x0000, 0x0000 }, /* R938 */
  1029. { 0x0000, 0x0000, 0x0000 }, /* R939 */
  1030. { 0x0000, 0x0000, 0x0000 }, /* R940 */
  1031. { 0x0000, 0x0000, 0x0000 }, /* R941 */
  1032. { 0x0000, 0x0000, 0x0000 }, /* R942 */
  1033. { 0x0000, 0x0000, 0x0000 }, /* R943 */
  1034. { 0x0000, 0x0000, 0x0000 }, /* R944 */
  1035. { 0x0000, 0x0000, 0x0000 }, /* R945 */
  1036. { 0x0000, 0x0000, 0x0000 }, /* R946 */
  1037. { 0x0000, 0x0000, 0x0000 }, /* R947 */
  1038. { 0x0000, 0x0000, 0x0000 }, /* R948 */
  1039. { 0x0000, 0x0000, 0x0000 }, /* R949 */
  1040. { 0x0000, 0x0000, 0x0000 }, /* R950 */
  1041. { 0x0000, 0x0000, 0x0000 }, /* R951 */
  1042. { 0x0000, 0x0000, 0x0000 }, /* R952 */
  1043. { 0x0000, 0x0000, 0x0000 }, /* R953 */
  1044. { 0x0000, 0x0000, 0x0000 }, /* R954 */
  1045. { 0x0000, 0x0000, 0x0000 }, /* R955 */
  1046. { 0x0000, 0x0000, 0x0000 }, /* R956 */
  1047. { 0x0000, 0x0000, 0x0000 }, /* R957 */
  1048. { 0x0000, 0x0000, 0x0000 }, /* R958 */
  1049. { 0x0000, 0x0000, 0x0000 }, /* R959 */
  1050. { 0x0000, 0x0000, 0x0000 }, /* R960 */
  1051. { 0x0000, 0x0000, 0x0000 }, /* R961 */
  1052. { 0x0000, 0x0000, 0x0000 }, /* R962 */
  1053. { 0x0000, 0x0000, 0x0000 }, /* R963 */
  1054. { 0x0000, 0x0000, 0x0000 }, /* R964 */
  1055. { 0x0000, 0x0000, 0x0000 }, /* R965 */
  1056. { 0x0000, 0x0000, 0x0000 }, /* R966 */
  1057. { 0x0000, 0x0000, 0x0000 }, /* R967 */
  1058. { 0x0000, 0x0000, 0x0000 }, /* R968 */
  1059. { 0x0000, 0x0000, 0x0000 }, /* R969 */
  1060. { 0x0000, 0x0000, 0x0000 }, /* R970 */
  1061. { 0x0000, 0x0000, 0x0000 }, /* R971 */
  1062. { 0x0000, 0x0000, 0x0000 }, /* R972 */
  1063. { 0x0000, 0x0000, 0x0000 }, /* R973 */
  1064. { 0x0000, 0x0000, 0x0000 }, /* R974 */
  1065. { 0x0000, 0x0000, 0x0000 }, /* R975 */
  1066. { 0x0000, 0x0000, 0x0000 }, /* R976 */
  1067. { 0x0000, 0x0000, 0x0000 }, /* R977 */
  1068. { 0x0000, 0x0000, 0x0000 }, /* R978 */
  1069. { 0x0000, 0x0000, 0x0000 }, /* R979 */
  1070. { 0x0000, 0x0000, 0x0000 }, /* R980 */
  1071. { 0x0000, 0x0000, 0x0000 }, /* R981 */
  1072. { 0x0000, 0x0000, 0x0000 }, /* R982 */
  1073. { 0x0000, 0x0000, 0x0000 }, /* R983 */
  1074. { 0x0000, 0x0000, 0x0000 }, /* R984 */
  1075. { 0x0000, 0x0000, 0x0000 }, /* R985 */
  1076. { 0x0000, 0x0000, 0x0000 }, /* R986 */
  1077. { 0x0000, 0x0000, 0x0000 }, /* R987 */
  1078. { 0x0000, 0x0000, 0x0000 }, /* R988 */
  1079. { 0x0000, 0x0000, 0x0000 }, /* R989 */
  1080. { 0x0000, 0x0000, 0x0000 }, /* R990 */
  1081. { 0x0000, 0x0000, 0x0000 }, /* R991 */
  1082. { 0x0000, 0x0000, 0x0000 }, /* R992 */
  1083. { 0x0000, 0x0000, 0x0000 }, /* R993 */
  1084. { 0x0000, 0x0000, 0x0000 }, /* R994 */
  1085. { 0x0000, 0x0000, 0x0000 }, /* R995 */
  1086. { 0x0000, 0x0000, 0x0000 }, /* R996 */
  1087. { 0x0000, 0x0000, 0x0000 }, /* R997 */
  1088. { 0x0000, 0x0000, 0x0000 }, /* R998 */
  1089. { 0x0000, 0x0000, 0x0000 }, /* R999 */
  1090. { 0x0000, 0x0000, 0x0000 }, /* R1000 */
  1091. { 0x0000, 0x0000, 0x0000 }, /* R1001 */
  1092. { 0x0000, 0x0000, 0x0000 }, /* R1002 */
  1093. { 0x0000, 0x0000, 0x0000 }, /* R1003 */
  1094. { 0x0000, 0x0000, 0x0000 }, /* R1004 */
  1095. { 0x0000, 0x0000, 0x0000 }, /* R1005 */
  1096. { 0x0000, 0x0000, 0x0000 }, /* R1006 */
  1097. { 0x0000, 0x0000, 0x0000 }, /* R1007 */
  1098. { 0x0000, 0x0000, 0x0000 }, /* R1008 */
  1099. { 0x0000, 0x0000, 0x0000 }, /* R1009 */
  1100. { 0x0000, 0x0000, 0x0000 }, /* R1010 */
  1101. { 0x0000, 0x0000, 0x0000 }, /* R1011 */
  1102. { 0x0000, 0x0000, 0x0000 }, /* R1012 */
  1103. { 0x0000, 0x0000, 0x0000 }, /* R1013 */
  1104. { 0x0000, 0x0000, 0x0000 }, /* R1014 */
  1105. { 0x0000, 0x0000, 0x0000 }, /* R1015 */
  1106. { 0x0000, 0x0000, 0x0000 }, /* R1016 */
  1107. { 0x0000, 0x0000, 0x0000 }, /* R1017 */
  1108. { 0x0000, 0x0000, 0x0000 }, /* R1018 */
  1109. { 0x0000, 0x0000, 0x0000 }, /* R1019 */
  1110. { 0x0000, 0x0000, 0x0000 }, /* R1020 */
  1111. { 0x0000, 0x0000, 0x0000 }, /* R1021 */
  1112. { 0x0000, 0x0000, 0x0000 }, /* R1022 */
  1113. { 0x0000, 0x0000, 0x0000 }, /* R1023 */
  1114. { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */
  1115. { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */
  1116. { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */
  1117. { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */
  1118. { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */
  1119. { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */
  1120. { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */
  1121. { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */
  1122. { 0x0000, 0x0000, 0x0000 }, /* R1032 */
  1123. { 0x0000, 0x0000, 0x0000 }, /* R1033 */
  1124. { 0x0000, 0x0000, 0x0000 }, /* R1034 */
  1125. { 0x0000, 0x0000, 0x0000 }, /* R1035 */
  1126. { 0x0000, 0x0000, 0x0000 }, /* R1036 */
  1127. { 0x0000, 0x0000, 0x0000 }, /* R1037 */
  1128. { 0x0000, 0x0000, 0x0000 }, /* R1038 */
  1129. { 0x0000, 0x0000, 0x0000 }, /* R1039 */
  1130. { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
  1131. { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
  1132. { 0x0000, 0x0000, 0x0000 }, /* R1042 */
  1133. { 0x0000, 0x0000, 0x0000 }, /* R1043 */
  1134. { 0x0000, 0x0000, 0x0000 }, /* R1044 */
  1135. { 0x0000, 0x0000, 0x0000 }, /* R1045 */
  1136. { 0x0000, 0x0000, 0x0000 }, /* R1046 */
  1137. { 0x0000, 0x0000, 0x0000 }, /* R1047 */
  1138. { 0x0000, 0x0000, 0x0000 }, /* R1048 */
  1139. { 0x0000, 0x0000, 0x0000 }, /* R1049 */
  1140. { 0x0000, 0x0000, 0x0000 }, /* R1050 */
  1141. { 0x0000, 0x0000, 0x0000 }, /* R1051 */
  1142. { 0x0000, 0x0000, 0x0000 }, /* R1052 */
  1143. { 0x0000, 0x0000, 0x0000 }, /* R1053 */
  1144. { 0x0000, 0x0000, 0x0000 }, /* R1054 */
  1145. { 0x0000, 0x0000, 0x0000 }, /* R1055 */
  1146. { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */
  1147. { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */
  1148. { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */
  1149. { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */
  1150. { 0x0000, 0x0000, 0x0000 }, /* R1060 */
  1151. { 0x0000, 0x0000, 0x0000 }, /* R1061 */
  1152. { 0x0000, 0x0000, 0x0000 }, /* R1062 */
  1153. { 0x0000, 0x0000, 0x0000 }, /* R1063 */
  1154. { 0x0000, 0x0000, 0x0000 }, /* R1064 */
  1155. { 0x0000, 0x0000, 0x0000 }, /* R1065 */
  1156. { 0x0000, 0x0000, 0x0000 }, /* R1066 */
  1157. { 0x0000, 0x0000, 0x0000 }, /* R1067 */
  1158. { 0x0000, 0x0000, 0x0000 }, /* R1068 */
  1159. { 0x0000, 0x0000, 0x0000 }, /* R1069 */
  1160. { 0x0000, 0x0000, 0x0000 }, /* R1070 */
  1161. { 0x0000, 0x0000, 0x0000 }, /* R1071 */
  1162. { 0x0000, 0x0000, 0x0000 }, /* R1072 */
  1163. { 0x0000, 0x0000, 0x0000 }, /* R1073 */
  1164. { 0x0000, 0x0000, 0x0000 }, /* R1074 */
  1165. { 0x0000, 0x0000, 0x0000 }, /* R1075 */
  1166. { 0x0000, 0x0000, 0x0000 }, /* R1076 */
  1167. { 0x0000, 0x0000, 0x0000 }, /* R1077 */
  1168. { 0x0000, 0x0000, 0x0000 }, /* R1078 */
  1169. { 0x0000, 0x0000, 0x0000 }, /* R1079 */
  1170. { 0x0000, 0x0000, 0x0000 }, /* R1080 */
  1171. { 0x0000, 0x0000, 0x0000 }, /* R1081 */
  1172. { 0x0000, 0x0000, 0x0000 }, /* R1082 */
  1173. { 0x0000, 0x0000, 0x0000 }, /* R1083 */
  1174. { 0x0000, 0x0000, 0x0000 }, /* R1084 */
  1175. { 0x0000, 0x0000, 0x0000 }, /* R1085 */
  1176. { 0x0000, 0x0000, 0x0000 }, /* R1086 */
  1177. { 0x0000, 0x0000, 0x0000 }, /* R1087 */
  1178. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */
  1179. { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */
  1180. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
  1181. { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
  1182. { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
  1183. { 0x0000, 0x0000, 0x0000 }, /* R1093 */
  1184. { 0x0000, 0x0000, 0x0000 }, /* R1094 */
  1185. { 0x0000, 0x0000, 0x0000 }, /* R1095 */
  1186. { 0x0000, 0x0000, 0x0000 }, /* R1096 */
  1187. { 0x0000, 0x0000, 0x0000 }, /* R1097 */
  1188. { 0x0000, 0x0000, 0x0000 }, /* R1098 */
  1189. { 0x0000, 0x0000, 0x0000 }, /* R1099 */
  1190. { 0x0000, 0x0000, 0x0000 }, /* R1100 */
  1191. { 0x0000, 0x0000, 0x0000 }, /* R1101 */
  1192. { 0x0000, 0x0000, 0x0000 }, /* R1102 */
  1193. { 0x0000, 0x0000, 0x0000 }, /* R1103 */
  1194. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */
  1195. { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */
  1196. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
  1197. { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
  1198. { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
  1199. { 0x0000, 0x0000, 0x0000 }, /* R1109 */
  1200. { 0x0000, 0x0000, 0x0000 }, /* R1110 */
  1201. { 0x0000, 0x0000, 0x0000 }, /* R1111 */
  1202. { 0x0000, 0x0000, 0x0000 }, /* R1112 */
  1203. { 0x0000, 0x0000, 0x0000 }, /* R1113 */
  1204. { 0x0000, 0x0000, 0x0000 }, /* R1114 */
  1205. { 0x0000, 0x0000, 0x0000 }, /* R1115 */
  1206. { 0x0000, 0x0000, 0x0000 }, /* R1116 */
  1207. { 0x0000, 0x0000, 0x0000 }, /* R1117 */
  1208. { 0x0000, 0x0000, 0x0000 }, /* R1118 */
  1209. { 0x0000, 0x0000, 0x0000 }, /* R1119 */
  1210. { 0x0000, 0x0000, 0x0000 }, /* R1120 */
  1211. { 0x0000, 0x0000, 0x0000 }, /* R1121 */
  1212. { 0x0000, 0x0000, 0x0000 }, /* R1122 */
  1213. { 0x0000, 0x0000, 0x0000 }, /* R1123 */
  1214. { 0x0000, 0x0000, 0x0000 }, /* R1124 */
  1215. { 0x0000, 0x0000, 0x0000 }, /* R1125 */
  1216. { 0x0000, 0x0000, 0x0000 }, /* R1126 */
  1217. { 0x0000, 0x0000, 0x0000 }, /* R1127 */
  1218. { 0x0000, 0x0000, 0x0000 }, /* R1128 */
  1219. { 0x0000, 0x0000, 0x0000 }, /* R1129 */
  1220. { 0x0000, 0x0000, 0x0000 }, /* R1130 */
  1221. { 0x0000, 0x0000, 0x0000 }, /* R1131 */
  1222. { 0x0000, 0x0000, 0x0000 }, /* R1132 */
  1223. { 0x0000, 0x0000, 0x0000 }, /* R1133 */
  1224. { 0x0000, 0x0000, 0x0000 }, /* R1134 */
  1225. { 0x0000, 0x0000, 0x0000 }, /* R1135 */
  1226. { 0x0000, 0x0000, 0x0000 }, /* R1136 */
  1227. { 0x0000, 0x0000, 0x0000 }, /* R1137 */
  1228. { 0x0000, 0x0000, 0x0000 }, /* R1138 */
  1229. { 0x0000, 0x0000, 0x0000 }, /* R1139 */
  1230. { 0x0000, 0x0000, 0x0000 }, /* R1140 */
  1231. { 0x0000, 0x0000, 0x0000 }, /* R1141 */
  1232. { 0x0000, 0x0000, 0x0000 }, /* R1142 */
  1233. { 0x0000, 0x0000, 0x0000 }, /* R1143 */
  1234. { 0x0000, 0x0000, 0x0000 }, /* R1144 */
  1235. { 0x0000, 0x0000, 0x0000 }, /* R1145 */
  1236. { 0x0000, 0x0000, 0x0000 }, /* R1146 */
  1237. { 0x0000, 0x0000, 0x0000 }, /* R1147 */
  1238. { 0x0000, 0x0000, 0x0000 }, /* R1148 */
  1239. { 0x0000, 0x0000, 0x0000 }, /* R1149 */
  1240. { 0x0000, 0x0000, 0x0000 }, /* R1150 */
  1241. { 0x0000, 0x0000, 0x0000 }, /* R1151 */
  1242. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
  1243. { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
  1244. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
  1245. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
  1246. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
  1247. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
  1248. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
  1249. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
  1250. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
  1251. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
  1252. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
  1253. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
  1254. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
  1255. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
  1256. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
  1257. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
  1258. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
  1259. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
  1260. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
  1261. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
  1262. { 0x0000, 0x0000, 0x0000 }, /* R1172 */
  1263. { 0x0000, 0x0000, 0x0000 }, /* R1173 */
  1264. { 0x0000, 0x0000, 0x0000 }, /* R1174 */
  1265. { 0x0000, 0x0000, 0x0000 }, /* R1175 */
  1266. { 0x0000, 0x0000, 0x0000 }, /* R1176 */
  1267. { 0x0000, 0x0000, 0x0000 }, /* R1177 */
  1268. { 0x0000, 0x0000, 0x0000 }, /* R1178 */
  1269. { 0x0000, 0x0000, 0x0000 }, /* R1179 */
  1270. { 0x0000, 0x0000, 0x0000 }, /* R1180 */
  1271. { 0x0000, 0x0000, 0x0000 }, /* R1181 */
  1272. { 0x0000, 0x0000, 0x0000 }, /* R1182 */
  1273. { 0x0000, 0x0000, 0x0000 }, /* R1183 */
  1274. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
  1275. { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
  1276. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
  1277. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
  1278. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
  1279. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
  1280. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
  1281. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
  1282. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
  1283. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
  1284. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
  1285. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
  1286. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
  1287. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
  1288. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
  1289. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
  1290. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
  1291. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
  1292. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
  1293. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
  1294. { 0x0000, 0x0000, 0x0000 }, /* R1204 */
  1295. { 0x0000, 0x0000, 0x0000 }, /* R1205 */
  1296. { 0x0000, 0x0000, 0x0000 }, /* R1206 */
  1297. { 0x0000, 0x0000, 0x0000 }, /* R1207 */
  1298. { 0x0000, 0x0000, 0x0000 }, /* R1208 */
  1299. { 0x0000, 0x0000, 0x0000 }, /* R1209 */
  1300. { 0x0000, 0x0000, 0x0000 }, /* R1210 */
  1301. { 0x0000, 0x0000, 0x0000 }, /* R1211 */
  1302. { 0x0000, 0x0000, 0x0000 }, /* R1212 */
  1303. { 0x0000, 0x0000, 0x0000 }, /* R1213 */
  1304. { 0x0000, 0x0000, 0x0000 }, /* R1214 */
  1305. { 0x0000, 0x0000, 0x0000 }, /* R1215 */
  1306. { 0x0000, 0x0000, 0x0000 }, /* R1216 */
  1307. { 0x0000, 0x0000, 0x0000 }, /* R1217 */
  1308. { 0x0000, 0x0000, 0x0000 }, /* R1218 */
  1309. { 0x0000, 0x0000, 0x0000 }, /* R1219 */
  1310. { 0x0000, 0x0000, 0x0000 }, /* R1220 */
  1311. { 0x0000, 0x0000, 0x0000 }, /* R1221 */
  1312. { 0x0000, 0x0000, 0x0000 }, /* R1222 */
  1313. { 0x0000, 0x0000, 0x0000 }, /* R1223 */
  1314. { 0x0000, 0x0000, 0x0000 }, /* R1224 */
  1315. { 0x0000, 0x0000, 0x0000 }, /* R1225 */
  1316. { 0x0000, 0x0000, 0x0000 }, /* R1226 */
  1317. { 0x0000, 0x0000, 0x0000 }, /* R1227 */
  1318. { 0x0000, 0x0000, 0x0000 }, /* R1228 */
  1319. { 0x0000, 0x0000, 0x0000 }, /* R1229 */
  1320. { 0x0000, 0x0000, 0x0000 }, /* R1230 */
  1321. { 0x0000, 0x0000, 0x0000 }, /* R1231 */
  1322. { 0x0000, 0x0000, 0x0000 }, /* R1232 */
  1323. { 0x0000, 0x0000, 0x0000 }, /* R1233 */
  1324. { 0x0000, 0x0000, 0x0000 }, /* R1234 */
  1325. { 0x0000, 0x0000, 0x0000 }, /* R1235 */
  1326. { 0x0000, 0x0000, 0x0000 }, /* R1236 */
  1327. { 0x0000, 0x0000, 0x0000 }, /* R1237 */
  1328. { 0x0000, 0x0000, 0x0000 }, /* R1238 */
  1329. { 0x0000, 0x0000, 0x0000 }, /* R1239 */
  1330. { 0x0000, 0x0000, 0x0000 }, /* R1240 */
  1331. { 0x0000, 0x0000, 0x0000 }, /* R1241 */
  1332. { 0x0000, 0x0000, 0x0000 }, /* R1242 */
  1333. { 0x0000, 0x0000, 0x0000 }, /* R1243 */
  1334. { 0x0000, 0x0000, 0x0000 }, /* R1244 */
  1335. { 0x0000, 0x0000, 0x0000 }, /* R1245 */
  1336. { 0x0000, 0x0000, 0x0000 }, /* R1246 */
  1337. { 0x0000, 0x0000, 0x0000 }, /* R1247 */
  1338. { 0x0000, 0x0000, 0x0000 }, /* R1248 */
  1339. { 0x0000, 0x0000, 0x0000 }, /* R1249 */
  1340. { 0x0000, 0x0000, 0x0000 }, /* R1250 */
  1341. { 0x0000, 0x0000, 0x0000 }, /* R1251 */
  1342. { 0x0000, 0x0000, 0x0000 }, /* R1252 */
  1343. { 0x0000, 0x0000, 0x0000 }, /* R1253 */
  1344. { 0x0000, 0x0000, 0x0000 }, /* R1254 */
  1345. { 0x0000, 0x0000, 0x0000 }, /* R1255 */
  1346. { 0x0000, 0x0000, 0x0000 }, /* R1256 */
  1347. { 0x0000, 0x0000, 0x0000 }, /* R1257 */
  1348. { 0x0000, 0x0000, 0x0000 }, /* R1258 */
  1349. { 0x0000, 0x0000, 0x0000 }, /* R1259 */
  1350. { 0x0000, 0x0000, 0x0000 }, /* R1260 */
  1351. { 0x0000, 0x0000, 0x0000 }, /* R1261 */
  1352. { 0x0000, 0x0000, 0x0000 }, /* R1262 */
  1353. { 0x0000, 0x0000, 0x0000 }, /* R1263 */
  1354. { 0x0000, 0x0000, 0x0000 }, /* R1264 */
  1355. { 0x0000, 0x0000, 0x0000 }, /* R1265 */
  1356. { 0x0000, 0x0000, 0x0000 }, /* R1266 */
  1357. { 0x0000, 0x0000, 0x0000 }, /* R1267 */
  1358. { 0x0000, 0x0000, 0x0000 }, /* R1268 */
  1359. { 0x0000, 0x0000, 0x0000 }, /* R1269 */
  1360. { 0x0000, 0x0000, 0x0000 }, /* R1270 */
  1361. { 0x0000, 0x0000, 0x0000 }, /* R1271 */
  1362. { 0x0000, 0x0000, 0x0000 }, /* R1272 */
  1363. { 0x0000, 0x0000, 0x0000 }, /* R1273 */
  1364. { 0x0000, 0x0000, 0x0000 }, /* R1274 */
  1365. { 0x0000, 0x0000, 0x0000 }, /* R1275 */
  1366. { 0x0000, 0x0000, 0x0000 }, /* R1276 */
  1367. { 0x0000, 0x0000, 0x0000 }, /* R1277 */
  1368. { 0x0000, 0x0000, 0x0000 }, /* R1278 */
  1369. { 0x0000, 0x0000, 0x0000 }, /* R1279 */
  1370. { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */
  1371. { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */
  1372. { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */
  1373. { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */
  1374. { 0x0000, 0x0000, 0x0000 }, /* R1284 */
  1375. { 0x0000, 0x0000, 0x0000 }, /* R1285 */
  1376. { 0x0000, 0x0000, 0x0000 }, /* R1286 */
  1377. { 0x0000, 0x0000, 0x0000 }, /* R1287 */
  1378. { 0x0000, 0x0000, 0x0000 }, /* R1288 */
  1379. { 0x0000, 0x0000, 0x0000 }, /* R1289 */
  1380. { 0x0000, 0x0000, 0x0000 }, /* R1290 */
  1381. { 0x0000, 0x0000, 0x0000 }, /* R1291 */
  1382. { 0x0000, 0x0000, 0x0000 }, /* R1292 */
  1383. { 0x0000, 0x0000, 0x0000 }, /* R1293 */
  1384. { 0x0000, 0x0000, 0x0000 }, /* R1294 */
  1385. { 0x0000, 0x0000, 0x0000 }, /* R1295 */
  1386. { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */
  1387. { 0x0000, 0x0000, 0x0000 }, /* R1297 */
  1388. { 0x0000, 0x0000, 0x0000 }, /* R1298 */
  1389. { 0x0000, 0x0000, 0x0000 }, /* R1299 */
  1390. { 0x0000, 0x0000, 0x0000 }, /* R1300 */
  1391. { 0x0000, 0x0000, 0x0000 }, /* R1301 */
  1392. { 0x0000, 0x0000, 0x0000 }, /* R1302 */
  1393. { 0x0000, 0x0000, 0x0000 }, /* R1303 */
  1394. { 0x0000, 0x0000, 0x0000 }, /* R1304 */
  1395. { 0x0000, 0x0000, 0x0000 }, /* R1305 */
  1396. { 0x0000, 0x0000, 0x0000 }, /* R1306 */
  1397. { 0x0000, 0x0000, 0x0000 }, /* R1307 */
  1398. { 0x0000, 0x0000, 0x0000 }, /* R1308 */
  1399. { 0x0000, 0x0000, 0x0000 }, /* R1309 */
  1400. { 0x0000, 0x0000, 0x0000 }, /* R1310 */
  1401. { 0x0000, 0x0000, 0x0000 }, /* R1311 */
  1402. { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */
  1403. { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */
  1404. { 0x0000, 0x0000, 0x0000 }, /* R1314 */
  1405. { 0x0000, 0x0000, 0x0000 }, /* R1315 */
  1406. { 0x0000, 0x0000, 0x0000 }, /* R1316 */
  1407. { 0x0000, 0x0000, 0x0000 }, /* R1317 */
  1408. { 0x0000, 0x0000, 0x0000 }, /* R1318 */
  1409. { 0x0000, 0x0000, 0x0000 }, /* R1319 */
  1410. { 0x0000, 0x0000, 0x0000 }, /* R1320 */
  1411. { 0x0000, 0x0000, 0x0000 }, /* R1321 */
  1412. { 0x0000, 0x0000, 0x0000 }, /* R1322 */
  1413. { 0x0000, 0x0000, 0x0000 }, /* R1323 */
  1414. { 0x0000, 0x0000, 0x0000 }, /* R1324 */
  1415. { 0x0000, 0x0000, 0x0000 }, /* R1325 */
  1416. { 0x0000, 0x0000, 0x0000 }, /* R1326 */
  1417. { 0x0000, 0x0000, 0x0000 }, /* R1327 */
  1418. { 0x0000, 0x0000, 0x0000 }, /* R1328 */
  1419. { 0x0000, 0x0000, 0x0000 }, /* R1329 */
  1420. { 0x0000, 0x0000, 0x0000 }, /* R1330 */
  1421. { 0x0000, 0x0000, 0x0000 }, /* R1331 */
  1422. { 0x0000, 0x0000, 0x0000 }, /* R1332 */
  1423. { 0x0000, 0x0000, 0x0000 }, /* R1333 */
  1424. { 0x0000, 0x0000, 0x0000 }, /* R1334 */
  1425. { 0x0000, 0x0000, 0x0000 }, /* R1335 */
  1426. { 0x0000, 0x0000, 0x0000 }, /* R1336 */
  1427. { 0x0000, 0x0000, 0x0000 }, /* R1337 */
  1428. { 0x0000, 0x0000, 0x0000 }, /* R1338 */
  1429. { 0x0000, 0x0000, 0x0000 }, /* R1339 */
  1430. { 0x0000, 0x0000, 0x0000 }, /* R1340 */
  1431. { 0x0000, 0x0000, 0x0000 }, /* R1341 */
  1432. { 0x0000, 0x0000, 0x0000 }, /* R1342 */
  1433. { 0x0000, 0x0000, 0x0000 }, /* R1343 */
  1434. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */
  1435. { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */
  1436. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */
  1437. { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */
  1438. { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */
  1439. { 0x0000, 0x0000, 0x0000 }, /* R1349 */
  1440. { 0x0000, 0x0000, 0x0000 }, /* R1350 */
  1441. { 0x0000, 0x0000, 0x0000 }, /* R1351 */
  1442. { 0x0000, 0x0000, 0x0000 }, /* R1352 */
  1443. { 0x0000, 0x0000, 0x0000 }, /* R1353 */
  1444. { 0x0000, 0x0000, 0x0000 }, /* R1354 */
  1445. { 0x0000, 0x0000, 0x0000 }, /* R1355 */
  1446. { 0x0000, 0x0000, 0x0000 }, /* R1356 */
  1447. { 0x0000, 0x0000, 0x0000 }, /* R1357 */
  1448. { 0x0000, 0x0000, 0x0000 }, /* R1358 */
  1449. { 0x0000, 0x0000, 0x0000 }, /* R1359 */
  1450. { 0x0000, 0x0000, 0x0000 }, /* R1360 */
  1451. { 0x0000, 0x0000, 0x0000 }, /* R1361 */
  1452. { 0x0000, 0x0000, 0x0000 }, /* R1362 */
  1453. { 0x0000, 0x0000, 0x0000 }, /* R1363 */
  1454. { 0x0000, 0x0000, 0x0000 }, /* R1364 */
  1455. { 0x0000, 0x0000, 0x0000 }, /* R1365 */
  1456. { 0x0000, 0x0000, 0x0000 }, /* R1366 */
  1457. { 0x0000, 0x0000, 0x0000 }, /* R1367 */
  1458. { 0x0000, 0x0000, 0x0000 }, /* R1368 */
  1459. { 0x0000, 0x0000, 0x0000 }, /* R1369 */
  1460. { 0x0000, 0x0000, 0x0000 }, /* R1370 */
  1461. { 0x0000, 0x0000, 0x0000 }, /* R1371 */
  1462. { 0x0000, 0x0000, 0x0000 }, /* R1372 */
  1463. { 0x0000, 0x0000, 0x0000 }, /* R1373 */
  1464. { 0x0000, 0x0000, 0x0000 }, /* R1374 */
  1465. { 0x0000, 0x0000, 0x0000 }, /* R1375 */
  1466. { 0x0000, 0x0000, 0x0000 }, /* R1376 */
  1467. { 0x0000, 0x0000, 0x0000 }, /* R1377 */
  1468. { 0x0000, 0x0000, 0x0000 }, /* R1378 */
  1469. { 0x0000, 0x0000, 0x0000 }, /* R1379 */
  1470. { 0x0000, 0x0000, 0x0000 }, /* R1380 */
  1471. { 0x0000, 0x0000, 0x0000 }, /* R1381 */
  1472. { 0x0000, 0x0000, 0x0000 }, /* R1382 */
  1473. { 0x0000, 0x0000, 0x0000 }, /* R1383 */
  1474. { 0x0000, 0x0000, 0x0000 }, /* R1384 */
  1475. { 0x0000, 0x0000, 0x0000 }, /* R1385 */
  1476. { 0x0000, 0x0000, 0x0000 }, /* R1386 */
  1477. { 0x0000, 0x0000, 0x0000 }, /* R1387 */
  1478. { 0x0000, 0x0000, 0x0000 }, /* R1388 */
  1479. { 0x0000, 0x0000, 0x0000 }, /* R1389 */
  1480. { 0x0000, 0x0000, 0x0000 }, /* R1390 */
  1481. { 0x0000, 0x0000, 0x0000 }, /* R1391 */
  1482. { 0x0000, 0x0000, 0x0000 }, /* R1392 */
  1483. { 0x0000, 0x0000, 0x0000 }, /* R1393 */
  1484. { 0x0000, 0x0000, 0x0000 }, /* R1394 */
  1485. { 0x0000, 0x0000, 0x0000 }, /* R1395 */
  1486. { 0x0000, 0x0000, 0x0000 }, /* R1396 */
  1487. { 0x0000, 0x0000, 0x0000 }, /* R1397 */
  1488. { 0x0000, 0x0000, 0x0000 }, /* R1398 */
  1489. { 0x0000, 0x0000, 0x0000 }, /* R1399 */
  1490. { 0x0000, 0x0000, 0x0000 }, /* R1400 */
  1491. { 0x0000, 0x0000, 0x0000 }, /* R1401 */
  1492. { 0x0000, 0x0000, 0x0000 }, /* R1402 */
  1493. { 0x0000, 0x0000, 0x0000 }, /* R1403 */
  1494. { 0x0000, 0x0000, 0x0000 }, /* R1404 */
  1495. { 0x0000, 0x0000, 0x0000 }, /* R1405 */
  1496. { 0x0000, 0x0000, 0x0000 }, /* R1406 */
  1497. { 0x0000, 0x0000, 0x0000 }, /* R1407 */
  1498. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */
  1499. { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */
  1500. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */
  1501. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */
  1502. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */
  1503. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */
  1504. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */
  1505. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */
  1506. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */
  1507. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */
  1508. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */
  1509. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */
  1510. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */
  1511. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */
  1512. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */
  1513. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */
  1514. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */
  1515. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */
  1516. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */
  1517. { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */
  1518. { 0x0000, 0x0000, 0x0000 }, /* R1428 */
  1519. { 0x0000, 0x0000, 0x0000 }, /* R1429 */
  1520. { 0x0000, 0x0000, 0x0000 }, /* R1430 */
  1521. { 0x0000, 0x0000, 0x0000 }, /* R1431 */
  1522. { 0x0000, 0x0000, 0x0000 }, /* R1432 */
  1523. { 0x0000, 0x0000, 0x0000 }, /* R1433 */
  1524. { 0x0000, 0x0000, 0x0000 }, /* R1434 */
  1525. { 0x0000, 0x0000, 0x0000 }, /* R1435 */
  1526. { 0x0000, 0x0000, 0x0000 }, /* R1436 */
  1527. { 0x0000, 0x0000, 0x0000 }, /* R1437 */
  1528. { 0x0000, 0x0000, 0x0000 }, /* R1438 */
  1529. { 0x0000, 0x0000, 0x0000 }, /* R1439 */
  1530. { 0x0000, 0x0000, 0x0000 }, /* R1440 */
  1531. { 0x0000, 0x0000, 0x0000 }, /* R1441 */
  1532. { 0x0000, 0x0000, 0x0000 }, /* R1442 */
  1533. { 0x0000, 0x0000, 0x0000 }, /* R1443 */
  1534. { 0x0000, 0x0000, 0x0000 }, /* R1444 */
  1535. { 0x0000, 0x0000, 0x0000 }, /* R1445 */
  1536. { 0x0000, 0x0000, 0x0000 }, /* R1446 */
  1537. { 0x0000, 0x0000, 0x0000 }, /* R1447 */
  1538. { 0x0000, 0x0000, 0x0000 }, /* R1448 */
  1539. { 0x0000, 0x0000, 0x0000 }, /* R1449 */
  1540. { 0x0000, 0x0000, 0x0000 }, /* R1450 */
  1541. { 0x0000, 0x0000, 0x0000 }, /* R1451 */
  1542. { 0x0000, 0x0000, 0x0000 }, /* R1452 */
  1543. { 0x0000, 0x0000, 0x0000 }, /* R1453 */
  1544. { 0x0000, 0x0000, 0x0000 }, /* R1454 */
  1545. { 0x0000, 0x0000, 0x0000 }, /* R1455 */
  1546. { 0x0000, 0x0000, 0x0000 }, /* R1456 */
  1547. { 0x0000, 0x0000, 0x0000 }, /* R1457 */
  1548. { 0x0000, 0x0000, 0x0000 }, /* R1458 */
  1549. { 0x0000, 0x0000, 0x0000 }, /* R1459 */
  1550. { 0x0000, 0x0000, 0x0000 }, /* R1460 */
  1551. { 0x0000, 0x0000, 0x0000 }, /* R1461 */
  1552. { 0x0000, 0x0000, 0x0000 }, /* R1462 */
  1553. { 0x0000, 0x0000, 0x0000 }, /* R1463 */
  1554. { 0x0000, 0x0000, 0x0000 }, /* R1464 */
  1555. { 0x0000, 0x0000, 0x0000 }, /* R1465 */
  1556. { 0x0000, 0x0000, 0x0000 }, /* R1466 */
  1557. { 0x0000, 0x0000, 0x0000 }, /* R1467 */
  1558. { 0x0000, 0x0000, 0x0000 }, /* R1468 */
  1559. { 0x0000, 0x0000, 0x0000 }, /* R1469 */
  1560. { 0x0000, 0x0000, 0x0000 }, /* R1470 */
  1561. { 0x0000, 0x0000, 0x0000 }, /* R1471 */
  1562. { 0x0000, 0x0000, 0x0000 }, /* R1472 */
  1563. { 0x0000, 0x0000, 0x0000 }, /* R1473 */
  1564. { 0x0000, 0x0000, 0x0000 }, /* R1474 */
  1565. { 0x0000, 0x0000, 0x0000 }, /* R1475 */
  1566. { 0x0000, 0x0000, 0x0000 }, /* R1476 */
  1567. { 0x0000, 0x0000, 0x0000 }, /* R1477 */
  1568. { 0x0000, 0x0000, 0x0000 }, /* R1478 */
  1569. { 0x0000, 0x0000, 0x0000 }, /* R1479 */
  1570. { 0x0000, 0x0000, 0x0000 }, /* R1480 */
  1571. { 0x0000, 0x0000, 0x0000 }, /* R1481 */
  1572. { 0x0000, 0x0000, 0x0000 }, /* R1482 */
  1573. { 0x0000, 0x0000, 0x0000 }, /* R1483 */
  1574. { 0x0000, 0x0000, 0x0000 }, /* R1484 */
  1575. { 0x0000, 0x0000, 0x0000 }, /* R1485 */
  1576. { 0x0000, 0x0000, 0x0000 }, /* R1486 */
  1577. { 0x0000, 0x0000, 0x0000 }, /* R1487 */
  1578. { 0x0000, 0x0000, 0x0000 }, /* R1488 */
  1579. { 0x0000, 0x0000, 0x0000 }, /* R1489 */
  1580. { 0x0000, 0x0000, 0x0000 }, /* R1490 */
  1581. { 0x0000, 0x0000, 0x0000 }, /* R1491 */
  1582. { 0x0000, 0x0000, 0x0000 }, /* R1492 */
  1583. { 0x0000, 0x0000, 0x0000 }, /* R1493 */
  1584. { 0x0000, 0x0000, 0x0000 }, /* R1494 */
  1585. { 0x0000, 0x0000, 0x0000 }, /* R1495 */
  1586. { 0x0000, 0x0000, 0x0000 }, /* R1496 */
  1587. { 0x0000, 0x0000, 0x0000 }, /* R1497 */
  1588. { 0x0000, 0x0000, 0x0000 }, /* R1498 */
  1589. { 0x0000, 0x0000, 0x0000 }, /* R1499 */
  1590. { 0x0000, 0x0000, 0x0000 }, /* R1500 */
  1591. { 0x0000, 0x0000, 0x0000 }, /* R1501 */
  1592. { 0x0000, 0x0000, 0x0000 }, /* R1502 */
  1593. { 0x0000, 0x0000, 0x0000 }, /* R1503 */
  1594. { 0x0000, 0x0000, 0x0000 }, /* R1504 */
  1595. { 0x0000, 0x0000, 0x0000 }, /* R1505 */
  1596. { 0x0000, 0x0000, 0x0000 }, /* R1506 */
  1597. { 0x0000, 0x0000, 0x0000 }, /* R1507 */
  1598. { 0x0000, 0x0000, 0x0000 }, /* R1508 */
  1599. { 0x0000, 0x0000, 0x0000 }, /* R1509 */
  1600. { 0x0000, 0x0000, 0x0000 }, /* R1510 */
  1601. { 0x0000, 0x0000, 0x0000 }, /* R1511 */
  1602. { 0x0000, 0x0000, 0x0000 }, /* R1512 */
  1603. { 0x0000, 0x0000, 0x0000 }, /* R1513 */
  1604. { 0x0000, 0x0000, 0x0000 }, /* R1514 */
  1605. { 0x0000, 0x0000, 0x0000 }, /* R1515 */
  1606. { 0x0000, 0x0000, 0x0000 }, /* R1516 */
  1607. { 0x0000, 0x0000, 0x0000 }, /* R1517 */
  1608. { 0x0000, 0x0000, 0x0000 }, /* R1518 */
  1609. { 0x0000, 0x0000, 0x0000 }, /* R1519 */
  1610. { 0x0000, 0x0000, 0x0000 }, /* R1520 */
  1611. { 0x0000, 0x0000, 0x0000 }, /* R1521 */
  1612. { 0x0000, 0x0000, 0x0000 }, /* R1522 */
  1613. { 0x0000, 0x0000, 0x0000 }, /* R1523 */
  1614. { 0x0000, 0x0000, 0x0000 }, /* R1524 */
  1615. { 0x0000, 0x0000, 0x0000 }, /* R1525 */
  1616. { 0x0000, 0x0000, 0x0000 }, /* R1526 */
  1617. { 0x0000, 0x0000, 0x0000 }, /* R1527 */
  1618. { 0x0000, 0x0000, 0x0000 }, /* R1528 */
  1619. { 0x0000, 0x0000, 0x0000 }, /* R1529 */
  1620. { 0x0000, 0x0000, 0x0000 }, /* R1530 */
  1621. { 0x0000, 0x0000, 0x0000 }, /* R1531 */
  1622. { 0x0000, 0x0000, 0x0000 }, /* R1532 */
  1623. { 0x0000, 0x0000, 0x0000 }, /* R1533 */
  1624. { 0x0000, 0x0000, 0x0000 }, /* R1534 */
  1625. { 0x0000, 0x0000, 0x0000 }, /* R1535 */
  1626. { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
  1627. { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
  1628. { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
  1629. { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
  1630. { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
  1631. { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
  1632. { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
  1633. { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
  1634. { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
  1635. { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
  1636. { 0x0000, 0x0000, 0x0000 }, /* R1546 */
  1637. { 0x0000, 0x0000, 0x0000 }, /* R1547 */
  1638. { 0x0000, 0x0000, 0x0000 }, /* R1548 */
  1639. { 0x0000, 0x0000, 0x0000 }, /* R1549 */
  1640. { 0x0000, 0x0000, 0x0000 }, /* R1550 */
  1641. { 0x0000, 0x0000, 0x0000 }, /* R1551 */
  1642. { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */
  1643. { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */
  1644. { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */
  1645. { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */
  1646. { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */
  1647. { 0x0000, 0x0000, 0x0000 }, /* R1557 */
  1648. { 0x0000, 0x0000, 0x0000 }, /* R1558 */
  1649. { 0x0000, 0x0000, 0x0000 }, /* R1559 */
  1650. { 0x0000, 0x0000, 0x0000 }, /* R1560 */
  1651. { 0x0000, 0x0000, 0x0000 }, /* R1561 */
  1652. { 0x0000, 0x0000, 0x0000 }, /* R1562 */
  1653. { 0x0000, 0x0000, 0x0000 }, /* R1563 */
  1654. { 0x0000, 0x0000, 0x0000 }, /* R1564 */
  1655. { 0x0000, 0x0000, 0x0000 }, /* R1565 */
  1656. { 0x0000, 0x0000, 0x0000 }, /* R1566 */
  1657. { 0x0000, 0x0000, 0x0000 }, /* R1567 */
  1658. { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */
  1659. { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */
  1660. };
  1661. static int wm8994_readable(unsigned int reg)
  1662. {
  1663. switch (reg) {
  1664. case WM8994_GPIO_1:
  1665. case WM8994_GPIO_2:
  1666. case WM8994_GPIO_3:
  1667. case WM8994_GPIO_4:
  1668. case WM8994_GPIO_5:
  1669. case WM8994_GPIO_6:
  1670. case WM8994_GPIO_7:
  1671. case WM8994_GPIO_8:
  1672. case WM8994_GPIO_9:
  1673. case WM8994_GPIO_10:
  1674. case WM8994_GPIO_11:
  1675. case WM8994_INTERRUPT_STATUS_1:
  1676. case WM8994_INTERRUPT_STATUS_2:
  1677. case WM8994_INTERRUPT_RAW_STATUS_2:
  1678. return 1;
  1679. default:
  1680. break;
  1681. }
  1682. if (reg >= ARRAY_SIZE(access_masks))
  1683. return 0;
  1684. return access_masks[reg].readable != 0;
  1685. }
  1686. static int wm8994_volatile(unsigned int reg)
  1687. {
  1688. if (reg >= WM8994_REG_CACHE_SIZE)
  1689. return 1;
  1690. switch (reg) {
  1691. case WM8994_SOFTWARE_RESET:
  1692. case WM8994_CHIP_REVISION:
  1693. case WM8994_DC_SERVO_1:
  1694. case WM8994_DC_SERVO_READBACK:
  1695. case WM8994_RATE_STATUS:
  1696. case WM8994_LDO_1:
  1697. case WM8994_LDO_2:
  1698. return 1;
  1699. default:
  1700. return 0;
  1701. }
  1702. }
  1703. static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
  1704. unsigned int value)
  1705. {
  1706. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1707. BUG_ON(reg > WM8994_MAX_REGISTER);
  1708. if (!wm8994_volatile(reg))
  1709. wm8994->reg_cache[reg] = value;
  1710. dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
  1711. return wm8994_reg_write(codec->control_data, reg, value);
  1712. }
  1713. static unsigned int wm8994_read(struct snd_soc_codec *codec,
  1714. unsigned int reg)
  1715. {
  1716. u16 *reg_cache = codec->reg_cache;
  1717. BUG_ON(reg > WM8994_MAX_REGISTER);
  1718. if (wm8994_volatile(reg))
  1719. return wm8994_reg_read(codec->control_data, reg);
  1720. else
  1721. return reg_cache[reg];
  1722. }
  1723. static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
  1724. {
  1725. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1726. int rate;
  1727. int reg1 = 0;
  1728. int offset;
  1729. if (aif)
  1730. offset = 4;
  1731. else
  1732. offset = 0;
  1733. switch (wm8994->sysclk[aif]) {
  1734. case WM8994_SYSCLK_MCLK1:
  1735. rate = wm8994->mclk[0];
  1736. break;
  1737. case WM8994_SYSCLK_MCLK2:
  1738. reg1 |= 0x8;
  1739. rate = wm8994->mclk[1];
  1740. break;
  1741. case WM8994_SYSCLK_FLL1:
  1742. reg1 |= 0x10;
  1743. rate = wm8994->fll[0].out;
  1744. break;
  1745. case WM8994_SYSCLK_FLL2:
  1746. reg1 |= 0x18;
  1747. rate = wm8994->fll[1].out;
  1748. break;
  1749. default:
  1750. return -EINVAL;
  1751. }
  1752. if (rate >= 13500000) {
  1753. rate /= 2;
  1754. reg1 |= WM8994_AIF1CLK_DIV;
  1755. dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
  1756. aif + 1, rate);
  1757. }
  1758. if (rate && rate < 3000000)
  1759. dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
  1760. aif + 1, rate);
  1761. wm8994->aifclk[aif] = rate;
  1762. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
  1763. WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
  1764. reg1);
  1765. return 0;
  1766. }
  1767. static int configure_clock(struct snd_soc_codec *codec)
  1768. {
  1769. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1770. int old, new;
  1771. /* Bring up the AIF clocks first */
  1772. configure_aif_clock(codec, 0);
  1773. configure_aif_clock(codec, 1);
  1774. /* Then switch CLK_SYS over to the higher of them; a change
  1775. * can only happen as a result of a clocking change which can
  1776. * only be made outside of DAPM so we can safely redo the
  1777. * clocking.
  1778. */
  1779. /* If they're equal it doesn't matter which is used */
  1780. if (wm8994->aifclk[0] == wm8994->aifclk[1])
  1781. return 0;
  1782. if (wm8994->aifclk[0] < wm8994->aifclk[1])
  1783. new = WM8994_SYSCLK_SRC;
  1784. else
  1785. new = 0;
  1786. old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
  1787. /* If there's no change then we're done. */
  1788. if (old == new)
  1789. return 0;
  1790. snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
  1791. snd_soc_dapm_sync(codec);
  1792. return 0;
  1793. }
  1794. static int check_clk_sys(struct snd_soc_dapm_widget *source,
  1795. struct snd_soc_dapm_widget *sink)
  1796. {
  1797. int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
  1798. const char *clk;
  1799. /* Check what we're currently using for CLK_SYS */
  1800. if (reg & WM8994_SYSCLK_SRC)
  1801. clk = "AIF2CLK";
  1802. else
  1803. clk = "AIF1CLK";
  1804. return strcmp(source->name, clk) == 0;
  1805. }
  1806. static const char *sidetone_hpf_text[] = {
  1807. "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
  1808. };
  1809. static const struct soc_enum sidetone_hpf =
  1810. SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
  1811. static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
  1812. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  1813. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  1814. static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
  1815. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  1816. #define WM8994_DRC_SWITCH(xname, reg, shift) \
  1817. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1818. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  1819. .put = wm8994_put_drc_sw, \
  1820. .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
  1821. static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
  1822. struct snd_ctl_elem_value *ucontrol)
  1823. {
  1824. struct soc_mixer_control *mc =
  1825. (struct soc_mixer_control *)kcontrol->private_value;
  1826. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1827. int mask, ret;
  1828. /* Can't enable both ADC and DAC paths simultaneously */
  1829. if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
  1830. mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
  1831. WM8994_AIF1ADC1R_DRC_ENA_MASK;
  1832. else
  1833. mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
  1834. ret = snd_soc_read(codec, mc->reg);
  1835. if (ret < 0)
  1836. return ret;
  1837. if (ret & mask)
  1838. return -EINVAL;
  1839. return snd_soc_put_volsw(kcontrol, ucontrol);
  1840. }
  1841. static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
  1842. {
  1843. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1844. struct wm8994_pdata *pdata = wm8994->pdata;
  1845. int base = wm8994_drc_base[drc];
  1846. int cfg = wm8994->drc_cfg[drc];
  1847. int save, i;
  1848. /* Save any enables; the configuration should clear them. */
  1849. save = snd_soc_read(codec, base);
  1850. save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  1851. WM8994_AIF1ADC1R_DRC_ENA;
  1852. for (i = 0; i < WM8994_DRC_REGS; i++)
  1853. snd_soc_update_bits(codec, base + i, 0xffff,
  1854. pdata->drc_cfgs[cfg].regs[i]);
  1855. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
  1856. WM8994_AIF1ADC1L_DRC_ENA |
  1857. WM8994_AIF1ADC1R_DRC_ENA, save);
  1858. }
  1859. /* Icky as hell but saves code duplication */
  1860. static int wm8994_get_drc(const char *name)
  1861. {
  1862. if (strcmp(name, "AIF1DRC1 Mode") == 0)
  1863. return 0;
  1864. if (strcmp(name, "AIF1DRC2 Mode") == 0)
  1865. return 1;
  1866. if (strcmp(name, "AIF2DRC Mode") == 0)
  1867. return 2;
  1868. return -EINVAL;
  1869. }
  1870. static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
  1871. struct snd_ctl_elem_value *ucontrol)
  1872. {
  1873. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1874. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1875. struct wm8994_pdata *pdata = wm8994->pdata;
  1876. int drc = wm8994_get_drc(kcontrol->id.name);
  1877. int value = ucontrol->value.integer.value[0];
  1878. if (drc < 0)
  1879. return drc;
  1880. if (value >= pdata->num_drc_cfgs)
  1881. return -EINVAL;
  1882. wm8994->drc_cfg[drc] = value;
  1883. wm8994_set_drc(codec, drc);
  1884. return 0;
  1885. }
  1886. static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
  1887. struct snd_ctl_elem_value *ucontrol)
  1888. {
  1889. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1890. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1891. int drc = wm8994_get_drc(kcontrol->id.name);
  1892. ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
  1893. return 0;
  1894. }
  1895. static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
  1896. {
  1897. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1898. struct wm8994_pdata *pdata = wm8994->pdata;
  1899. int base = wm8994_retune_mobile_base[block];
  1900. int iface, best, best_val, save, i, cfg;
  1901. if (!pdata || !wm8994->num_retune_mobile_texts)
  1902. return;
  1903. switch (block) {
  1904. case 0:
  1905. case 1:
  1906. iface = 0;
  1907. break;
  1908. case 2:
  1909. iface = 1;
  1910. break;
  1911. default:
  1912. return;
  1913. }
  1914. /* Find the version of the currently selected configuration
  1915. * with the nearest sample rate. */
  1916. cfg = wm8994->retune_mobile_cfg[block];
  1917. best = 0;
  1918. best_val = INT_MAX;
  1919. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  1920. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  1921. wm8994->retune_mobile_texts[cfg]) == 0 &&
  1922. abs(pdata->retune_mobile_cfgs[i].rate
  1923. - wm8994->dac_rates[iface]) < best_val) {
  1924. best = i;
  1925. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  1926. - wm8994->dac_rates[iface]);
  1927. }
  1928. }
  1929. dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
  1930. block,
  1931. pdata->retune_mobile_cfgs[best].name,
  1932. pdata->retune_mobile_cfgs[best].rate,
  1933. wm8994->dac_rates[iface]);
  1934. /* The EQ will be disabled while reconfiguring it, remember the
  1935. * current configuration.
  1936. */
  1937. save = snd_soc_read(codec, base);
  1938. save &= WM8994_AIF1DAC1_EQ_ENA;
  1939. for (i = 0; i < WM8994_EQ_REGS; i++)
  1940. snd_soc_update_bits(codec, base + i, 0xffff,
  1941. pdata->retune_mobile_cfgs[best].regs[i]);
  1942. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
  1943. }
  1944. /* Icky as hell but saves code duplication */
  1945. static int wm8994_get_retune_mobile_block(const char *name)
  1946. {
  1947. if (strcmp(name, "AIF1.1 EQ Mode") == 0)
  1948. return 0;
  1949. if (strcmp(name, "AIF1.2 EQ Mode") == 0)
  1950. return 1;
  1951. if (strcmp(name, "AIF2 EQ Mode") == 0)
  1952. return 2;
  1953. return -EINVAL;
  1954. }
  1955. static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  1956. struct snd_ctl_elem_value *ucontrol)
  1957. {
  1958. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1959. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1960. struct wm8994_pdata *pdata = wm8994->pdata;
  1961. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  1962. int value = ucontrol->value.integer.value[0];
  1963. if (block < 0)
  1964. return block;
  1965. if (value >= pdata->num_retune_mobile_cfgs)
  1966. return -EINVAL;
  1967. wm8994->retune_mobile_cfg[block] = value;
  1968. wm8994_set_retune_mobile(codec, block);
  1969. return 0;
  1970. }
  1971. static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  1972. struct snd_ctl_elem_value *ucontrol)
  1973. {
  1974. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1975. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1976. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  1977. ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
  1978. return 0;
  1979. }
  1980. static const struct snd_kcontrol_new wm8994_snd_controls[] = {
  1981. SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
  1982. WM8994_AIF1_ADC1_RIGHT_VOLUME,
  1983. 1, 119, 0, digital_tlv),
  1984. SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
  1985. WM8994_AIF1_ADC2_RIGHT_VOLUME,
  1986. 1, 119, 0, digital_tlv),
  1987. SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
  1988. WM8994_AIF2_ADC_RIGHT_VOLUME,
  1989. 1, 119, 0, digital_tlv),
  1990. SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
  1991. WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  1992. SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
  1993. WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  1994. SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
  1995. WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  1996. SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
  1997. SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
  1998. SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
  1999. SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
  2000. SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
  2001. WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
  2002. WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
  2003. WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
  2004. WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
  2005. WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
  2006. WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
  2007. WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
  2008. WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
  2009. WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
  2010. SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  2011. 5, 12, 0, st_tlv),
  2012. SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  2013. 0, 12, 0, st_tlv),
  2014. SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  2015. 5, 12, 0, st_tlv),
  2016. SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  2017. 0, 12, 0, st_tlv),
  2018. SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
  2019. SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
  2020. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
  2021. WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  2022. SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
  2023. WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
  2024. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
  2025. WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  2026. SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
  2027. WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
  2028. SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
  2029. 6, 1, 1, wm_hubs_spkmix_tlv),
  2030. SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
  2031. 2, 1, 1, wm_hubs_spkmix_tlv),
  2032. SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
  2033. 6, 1, 1, wm_hubs_spkmix_tlv),
  2034. SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
  2035. 2, 1, 1, wm_hubs_spkmix_tlv),
  2036. SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
  2037. 10, 15, 0, wm8994_3d_tlv),
  2038. SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  2039. 8, 1, 0),
  2040. SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
  2041. 10, 15, 0, wm8994_3d_tlv),
  2042. SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  2043. 8, 1, 0),
  2044. SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
  2045. 10, 15, 0, wm8994_3d_tlv),
  2046. SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  2047. 8, 1, 0),
  2048. };
  2049. static const struct snd_kcontrol_new wm8994_eq_controls[] = {
  2050. SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
  2051. eq_tlv),
  2052. SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
  2053. eq_tlv),
  2054. SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
  2055. eq_tlv),
  2056. SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
  2057. eq_tlv),
  2058. SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
  2059. eq_tlv),
  2060. SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
  2061. eq_tlv),
  2062. SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
  2063. eq_tlv),
  2064. SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
  2065. eq_tlv),
  2066. SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
  2067. eq_tlv),
  2068. SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
  2069. eq_tlv),
  2070. SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
  2071. eq_tlv),
  2072. SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
  2073. eq_tlv),
  2074. SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
  2075. eq_tlv),
  2076. SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
  2077. eq_tlv),
  2078. SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
  2079. eq_tlv),
  2080. };
  2081. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  2082. struct snd_kcontrol *kcontrol, int event)
  2083. {
  2084. struct snd_soc_codec *codec = w->codec;
  2085. switch (event) {
  2086. case SND_SOC_DAPM_PRE_PMU:
  2087. return configure_clock(codec);
  2088. case SND_SOC_DAPM_POST_PMD:
  2089. configure_clock(codec);
  2090. break;
  2091. }
  2092. return 0;
  2093. }
  2094. static void wm8994_update_class_w(struct snd_soc_codec *codec)
  2095. {
  2096. int enable = 1;
  2097. int source = 0; /* GCC flow analysis can't track enable */
  2098. int reg, reg_r;
  2099. /* Only support direct DAC->headphone paths */
  2100. reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
  2101. if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
  2102. dev_vdbg(codec->dev, "HPL connected to output mixer\n");
  2103. enable = 0;
  2104. }
  2105. reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
  2106. if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
  2107. dev_vdbg(codec->dev, "HPR connected to output mixer\n");
  2108. enable = 0;
  2109. }
  2110. /* We also need the same setting for L/R and only one path */
  2111. reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
  2112. switch (reg) {
  2113. case WM8994_AIF2DACL_TO_DAC1L:
  2114. dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
  2115. source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  2116. break;
  2117. case WM8994_AIF1DAC2L_TO_DAC1L:
  2118. dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
  2119. source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  2120. break;
  2121. case WM8994_AIF1DAC1L_TO_DAC1L:
  2122. dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
  2123. source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  2124. break;
  2125. default:
  2126. dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
  2127. enable = 0;
  2128. break;
  2129. }
  2130. reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
  2131. if (reg_r != reg) {
  2132. dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
  2133. enable = 0;
  2134. }
  2135. if (enable) {
  2136. dev_dbg(codec->dev, "Class W enabled\n");
  2137. snd_soc_update_bits(codec, WM8994_CLASS_W_1,
  2138. WM8994_CP_DYN_PWR |
  2139. WM8994_CP_DYN_SRC_SEL_MASK,
  2140. source | WM8994_CP_DYN_PWR);
  2141. } else {
  2142. dev_dbg(codec->dev, "Class W disabled\n");
  2143. snd_soc_update_bits(codec, WM8994_CLASS_W_1,
  2144. WM8994_CP_DYN_PWR, 0);
  2145. }
  2146. }
  2147. static const char *hp_mux_text[] = {
  2148. "Mixer",
  2149. "DAC",
  2150. };
  2151. #define WM8994_HP_ENUM(xname, xenum) \
  2152. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  2153. .info = snd_soc_info_enum_double, \
  2154. .get = snd_soc_dapm_get_enum_double, \
  2155. .put = wm8994_put_hp_enum, \
  2156. .private_value = (unsigned long)&xenum }
  2157. static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
  2158. struct snd_ctl_elem_value *ucontrol)
  2159. {
  2160. struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
  2161. struct snd_soc_codec *codec = w->codec;
  2162. int ret;
  2163. ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  2164. wm8994_update_class_w(codec);
  2165. return ret;
  2166. }
  2167. static const struct soc_enum hpl_enum =
  2168. SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
  2169. static const struct snd_kcontrol_new hpl_mux =
  2170. WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
  2171. static const struct soc_enum hpr_enum =
  2172. SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
  2173. static const struct snd_kcontrol_new hpr_mux =
  2174. WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
  2175. static const char *adc_mux_text[] = {
  2176. "ADC",
  2177. "DMIC",
  2178. };
  2179. static const struct soc_enum adc_enum =
  2180. SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
  2181. static const struct snd_kcontrol_new adcl_mux =
  2182. SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
  2183. static const struct snd_kcontrol_new adcr_mux =
  2184. SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
  2185. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  2186. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
  2187. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
  2188. SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
  2189. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
  2190. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
  2191. };
  2192. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  2193. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
  2194. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
  2195. SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
  2196. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
  2197. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
  2198. };
  2199. /* Debugging; dump chip status after DAPM transitions */
  2200. static int post_ev(struct snd_soc_dapm_widget *w,
  2201. struct snd_kcontrol *kcontrol, int event)
  2202. {
  2203. struct snd_soc_codec *codec = w->codec;
  2204. dev_dbg(codec->dev, "SRC status: %x\n",
  2205. snd_soc_read(codec,
  2206. WM8994_RATE_STATUS));
  2207. return 0;
  2208. }
  2209. static const struct snd_kcontrol_new aif1adc1l_mix[] = {
  2210. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  2211. 1, 1, 0),
  2212. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  2213. 0, 1, 0),
  2214. };
  2215. static const struct snd_kcontrol_new aif1adc1r_mix[] = {
  2216. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  2217. 1, 1, 0),
  2218. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  2219. 0, 1, 0),
  2220. };
  2221. static const struct snd_kcontrol_new aif1adc2l_mix[] = {
  2222. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  2223. 1, 1, 0),
  2224. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  2225. 0, 1, 0),
  2226. };
  2227. static const struct snd_kcontrol_new aif1adc2r_mix[] = {
  2228. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  2229. 1, 1, 0),
  2230. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  2231. 0, 1, 0),
  2232. };
  2233. static const struct snd_kcontrol_new aif2dac2l_mix[] = {
  2234. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  2235. 5, 1, 0),
  2236. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  2237. 4, 1, 0),
  2238. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  2239. 2, 1, 0),
  2240. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  2241. 1, 1, 0),
  2242. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  2243. 0, 1, 0),
  2244. };
  2245. static const struct snd_kcontrol_new aif2dac2r_mix[] = {
  2246. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  2247. 5, 1, 0),
  2248. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  2249. 4, 1, 0),
  2250. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  2251. 2, 1, 0),
  2252. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  2253. 1, 1, 0),
  2254. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  2255. 0, 1, 0),
  2256. };
  2257. #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
  2258. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  2259. .info = snd_soc_info_volsw, \
  2260. .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
  2261. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
  2262. static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
  2263. struct snd_ctl_elem_value *ucontrol)
  2264. {
  2265. struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
  2266. struct snd_soc_codec *codec = w->codec;
  2267. int ret;
  2268. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  2269. wm8994_update_class_w(codec);
  2270. return ret;
  2271. }
  2272. static const struct snd_kcontrol_new dac1l_mix[] = {
  2273. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  2274. 5, 1, 0),
  2275. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  2276. 4, 1, 0),
  2277. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  2278. 2, 1, 0),
  2279. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  2280. 1, 1, 0),
  2281. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  2282. 0, 1, 0),
  2283. };
  2284. static const struct snd_kcontrol_new dac1r_mix[] = {
  2285. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  2286. 5, 1, 0),
  2287. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  2288. 4, 1, 0),
  2289. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  2290. 2, 1, 0),
  2291. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  2292. 1, 1, 0),
  2293. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  2294. 0, 1, 0),
  2295. };
  2296. static const char *sidetone_text[] = {
  2297. "ADC/DMIC1", "DMIC2",
  2298. };
  2299. static const struct soc_enum sidetone1_enum =
  2300. SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
  2301. static const struct snd_kcontrol_new sidetone1_mux =
  2302. SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
  2303. static const struct soc_enum sidetone2_enum =
  2304. SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
  2305. static const struct snd_kcontrol_new sidetone2_mux =
  2306. SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
  2307. static const char *aif1dac_text[] = {
  2308. "AIF1DACDAT", "AIF3DACDAT",
  2309. };
  2310. static const struct soc_enum aif1dac_enum =
  2311. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
  2312. static const struct snd_kcontrol_new aif1dac_mux =
  2313. SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
  2314. static const char *aif2dac_text[] = {
  2315. "AIF2DACDAT", "AIF3DACDAT",
  2316. };
  2317. static const struct soc_enum aif2dac_enum =
  2318. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
  2319. static const struct snd_kcontrol_new aif2dac_mux =
  2320. SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
  2321. static const char *aif2adc_text[] = {
  2322. "AIF2ADCDAT", "AIF3DACDAT",
  2323. };
  2324. static const struct soc_enum aif2adc_enum =
  2325. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
  2326. static const struct snd_kcontrol_new aif2adc_mux =
  2327. SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
  2328. static const char *aif3adc_text[] = {
  2329. "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
  2330. };
  2331. static const struct soc_enum aif3adc_enum =
  2332. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
  2333. static const struct snd_kcontrol_new aif3adc_mux =
  2334. SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
  2335. static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
  2336. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  2337. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  2338. SND_SOC_DAPM_INPUT("Clock"),
  2339. SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
  2340. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  2341. SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
  2342. SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
  2343. SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
  2344. SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
  2345. SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
  2346. SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
  2347. 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
  2348. SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
  2349. 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
  2350. SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
  2351. WM8994_POWER_MANAGEMENT_5, 9, 0),
  2352. SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
  2353. WM8994_POWER_MANAGEMENT_5, 8, 0),
  2354. SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
  2355. 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
  2356. SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
  2357. 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
  2358. SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
  2359. WM8994_POWER_MANAGEMENT_5, 11, 0),
  2360. SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
  2361. WM8994_POWER_MANAGEMENT_5, 10, 0),
  2362. SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
  2363. aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
  2364. SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
  2365. aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
  2366. SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
  2367. aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
  2368. SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
  2369. aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
  2370. SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  2371. aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
  2372. SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  2373. aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
  2374. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
  2375. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
  2376. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
  2377. dac1l_mix, ARRAY_SIZE(dac1l_mix)),
  2378. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
  2379. dac1r_mix, ARRAY_SIZE(dac1r_mix)),
  2380. SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
  2381. WM8994_POWER_MANAGEMENT_4, 13, 0),
  2382. SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
  2383. WM8994_POWER_MANAGEMENT_4, 12, 0),
  2384. SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
  2385. WM8994_POWER_MANAGEMENT_5, 13, 0),
  2386. SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
  2387. WM8994_POWER_MANAGEMENT_5, 12, 0),
  2388. SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  2389. SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  2390. SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  2391. SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
  2392. SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
  2393. SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
  2394. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
  2395. SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
  2396. SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
  2397. SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
  2398. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
  2399. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
  2400. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
  2401. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
  2402. /* Power is done with the muxes since the ADC power also controls the
  2403. * downsampling chain, the chip will automatically manage the analogue
  2404. * specific portions.
  2405. */
  2406. SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
  2407. SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
  2408. SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
  2409. SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
  2410. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
  2411. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
  2412. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
  2413. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
  2414. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  2415. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  2416. SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  2417. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  2418. SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  2419. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  2420. SND_SOC_DAPM_POST("Debug log", post_ev),
  2421. };
  2422. static const struct snd_soc_dapm_route intercon[] = {
  2423. { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
  2424. { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
  2425. { "DSP1CLK", NULL, "CLK_SYS" },
  2426. { "DSP2CLK", NULL, "CLK_SYS" },
  2427. { "DSPINTCLK", NULL, "CLK_SYS" },
  2428. { "AIF1ADC1L", NULL, "AIF1CLK" },
  2429. { "AIF1ADC1L", NULL, "DSP1CLK" },
  2430. { "AIF1ADC1R", NULL, "AIF1CLK" },
  2431. { "AIF1ADC1R", NULL, "DSP1CLK" },
  2432. { "AIF1ADC1R", NULL, "DSPINTCLK" },
  2433. { "AIF1DAC1L", NULL, "AIF1CLK" },
  2434. { "AIF1DAC1L", NULL, "DSP1CLK" },
  2435. { "AIF1DAC1R", NULL, "AIF1CLK" },
  2436. { "AIF1DAC1R", NULL, "DSP1CLK" },
  2437. { "AIF1DAC1R", NULL, "DSPINTCLK" },
  2438. { "AIF1ADC2L", NULL, "AIF1CLK" },
  2439. { "AIF1ADC2L", NULL, "DSP1CLK" },
  2440. { "AIF1ADC2R", NULL, "AIF1CLK" },
  2441. { "AIF1ADC2R", NULL, "DSP1CLK" },
  2442. { "AIF1ADC2R", NULL, "DSPINTCLK" },
  2443. { "AIF1DAC2L", NULL, "AIF1CLK" },
  2444. { "AIF1DAC2L", NULL, "DSP1CLK" },
  2445. { "AIF1DAC2R", NULL, "AIF1CLK" },
  2446. { "AIF1DAC2R", NULL, "DSP1CLK" },
  2447. { "AIF1DAC2R", NULL, "DSPINTCLK" },
  2448. { "AIF2ADCL", NULL, "AIF2CLK" },
  2449. { "AIF2ADCL", NULL, "DSP2CLK" },
  2450. { "AIF2ADCR", NULL, "AIF2CLK" },
  2451. { "AIF2ADCR", NULL, "DSP2CLK" },
  2452. { "AIF2ADCR", NULL, "DSPINTCLK" },
  2453. { "AIF2DACL", NULL, "AIF2CLK" },
  2454. { "AIF2DACL", NULL, "DSP2CLK" },
  2455. { "AIF2DACR", NULL, "AIF2CLK" },
  2456. { "AIF2DACR", NULL, "DSP2CLK" },
  2457. { "AIF2DACR", NULL, "DSPINTCLK" },
  2458. { "DMIC1L", NULL, "DMIC1DAT" },
  2459. { "DMIC1L", NULL, "CLK_SYS" },
  2460. { "DMIC1R", NULL, "DMIC1DAT" },
  2461. { "DMIC1R", NULL, "CLK_SYS" },
  2462. { "DMIC2L", NULL, "DMIC2DAT" },
  2463. { "DMIC2L", NULL, "CLK_SYS" },
  2464. { "DMIC2R", NULL, "DMIC2DAT" },
  2465. { "DMIC2R", NULL, "CLK_SYS" },
  2466. { "ADCL", NULL, "AIF1CLK" },
  2467. { "ADCL", NULL, "DSP1CLK" },
  2468. { "ADCL", NULL, "DSPINTCLK" },
  2469. { "ADCR", NULL, "AIF1CLK" },
  2470. { "ADCR", NULL, "DSP1CLK" },
  2471. { "ADCR", NULL, "DSPINTCLK" },
  2472. { "ADCL Mux", "ADC", "ADCL" },
  2473. { "ADCL Mux", "DMIC", "DMIC1L" },
  2474. { "ADCR Mux", "ADC", "ADCR" },
  2475. { "ADCR Mux", "DMIC", "DMIC1R" },
  2476. { "DAC1L", NULL, "AIF1CLK" },
  2477. { "DAC1L", NULL, "DSP1CLK" },
  2478. { "DAC1L", NULL, "DSPINTCLK" },
  2479. { "DAC1R", NULL, "AIF1CLK" },
  2480. { "DAC1R", NULL, "DSP1CLK" },
  2481. { "DAC1R", NULL, "DSPINTCLK" },
  2482. { "DAC2L", NULL, "AIF2CLK" },
  2483. { "DAC2L", NULL, "DSP2CLK" },
  2484. { "DAC2L", NULL, "DSPINTCLK" },
  2485. { "DAC2R", NULL, "AIF2DACR" },
  2486. { "DAC2R", NULL, "AIF2CLK" },
  2487. { "DAC2R", NULL, "DSP2CLK" },
  2488. { "DAC2R", NULL, "DSPINTCLK" },
  2489. { "TOCLK", NULL, "CLK_SYS" },
  2490. /* AIF1 outputs */
  2491. { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
  2492. { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
  2493. { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  2494. { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
  2495. { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
  2496. { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  2497. { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
  2498. { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
  2499. { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  2500. { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
  2501. { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
  2502. { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  2503. /* Pin level routing for AIF3 */
  2504. { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
  2505. { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
  2506. { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
  2507. { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
  2508. { "AIF2DACL", NULL, "AIF2DAC Mux" },
  2509. { "AIF2DACR", NULL, "AIF2DAC Mux" },
  2510. { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
  2511. { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  2512. { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
  2513. { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  2514. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
  2515. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
  2516. { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
  2517. /* DAC1 inputs */
  2518. { "DAC1L", NULL, "DAC1L Mixer" },
  2519. { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  2520. { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  2521. { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  2522. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  2523. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  2524. { "DAC1R", NULL, "DAC1R Mixer" },
  2525. { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  2526. { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  2527. { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  2528. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  2529. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  2530. /* DAC2/AIF2 outputs */
  2531. { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
  2532. { "DAC2L", NULL, "AIF2DAC2L Mixer" },
  2533. { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  2534. { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  2535. { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  2536. { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  2537. { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  2538. { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
  2539. { "DAC2R", NULL, "AIF2DAC2R Mixer" },
  2540. { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  2541. { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  2542. { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  2543. { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  2544. { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  2545. { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
  2546. /* AIF3 output */
  2547. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
  2548. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
  2549. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
  2550. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
  2551. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
  2552. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
  2553. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
  2554. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
  2555. /* Sidetone */
  2556. { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
  2557. { "Left Sidetone", "DMIC2", "DMIC2L" },
  2558. { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
  2559. { "Right Sidetone", "DMIC2", "DMIC2R" },
  2560. /* Output stages */
  2561. { "Left Output Mixer", "DAC Switch", "DAC1L" },
  2562. { "Right Output Mixer", "DAC Switch", "DAC1R" },
  2563. { "SPKL", "DAC1 Switch", "DAC1L" },
  2564. { "SPKL", "DAC2 Switch", "DAC2L" },
  2565. { "SPKR", "DAC1 Switch", "DAC1R" },
  2566. { "SPKR", "DAC2 Switch", "DAC2R" },
  2567. { "Left Headphone Mux", "DAC", "DAC1L" },
  2568. { "Right Headphone Mux", "DAC", "DAC1R" },
  2569. };
  2570. /* The size in bits of the FLL divide multiplied by 10
  2571. * to allow rounding later */
  2572. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  2573. struct fll_div {
  2574. u16 outdiv;
  2575. u16 n;
  2576. u16 k;
  2577. u16 clk_ref_div;
  2578. u16 fll_fratio;
  2579. };
  2580. static int wm8994_get_fll_config(struct fll_div *fll,
  2581. int freq_in, int freq_out)
  2582. {
  2583. u64 Kpart;
  2584. unsigned int K, Ndiv, Nmod;
  2585. pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
  2586. /* Scale the input frequency down to <= 13.5MHz */
  2587. fll->clk_ref_div = 0;
  2588. while (freq_in > 13500000) {
  2589. fll->clk_ref_div++;
  2590. freq_in /= 2;
  2591. if (fll->clk_ref_div > 3)
  2592. return -EINVAL;
  2593. }
  2594. pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
  2595. /* Scale the output to give 90MHz<=Fvco<=100MHz */
  2596. fll->outdiv = 3;
  2597. while (freq_out * (fll->outdiv + 1) < 90000000) {
  2598. fll->outdiv++;
  2599. if (fll->outdiv > 63)
  2600. return -EINVAL;
  2601. }
  2602. freq_out *= fll->outdiv + 1;
  2603. pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
  2604. if (freq_in > 1000000) {
  2605. fll->fll_fratio = 0;
  2606. } else if (freq_in > 256000) {
  2607. fll->fll_fratio = 1;
  2608. freq_in *= 2;
  2609. } else if (freq_in > 128000) {
  2610. fll->fll_fratio = 2;
  2611. freq_in *= 4;
  2612. } else if (freq_in > 64000) {
  2613. fll->fll_fratio = 3;
  2614. freq_in *= 8;
  2615. } else {
  2616. fll->fll_fratio = 4;
  2617. freq_in *= 16;
  2618. }
  2619. pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
  2620. /* Now, calculate N.K */
  2621. Ndiv = freq_out / freq_in;
  2622. fll->n = Ndiv;
  2623. Nmod = freq_out % freq_in;
  2624. pr_debug("Nmod=%d\n", Nmod);
  2625. /* Calculate fractional part - scale up so we can round. */
  2626. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  2627. do_div(Kpart, freq_in);
  2628. K = Kpart & 0xFFFFFFFF;
  2629. if ((K % 10) >= 5)
  2630. K += 5;
  2631. /* Move down to proper range now rounding is done */
  2632. fll->k = K / 10;
  2633. pr_debug("N=%x K=%x\n", fll->n, fll->k);
  2634. return 0;
  2635. }
  2636. static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
  2637. unsigned int freq_in, unsigned int freq_out)
  2638. {
  2639. struct snd_soc_codec *codec = dai->codec;
  2640. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2641. int reg_offset, ret;
  2642. struct fll_div fll;
  2643. u16 reg, aif1, aif2;
  2644. aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  2645. & WM8994_AIF1CLK_ENA;
  2646. aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  2647. & WM8994_AIF2CLK_ENA;
  2648. switch (id) {
  2649. case WM8994_FLL1:
  2650. reg_offset = 0;
  2651. id = 0;
  2652. break;
  2653. case WM8994_FLL2:
  2654. reg_offset = 0x20;
  2655. id = 1;
  2656. break;
  2657. default:
  2658. return -EINVAL;
  2659. }
  2660. switch (src) {
  2661. case 0:
  2662. /* Allow no source specification when stopping */
  2663. if (freq_out)
  2664. return -EINVAL;
  2665. break;
  2666. case WM8994_FLL_SRC_MCLK1:
  2667. case WM8994_FLL_SRC_MCLK2:
  2668. case WM8994_FLL_SRC_LRCLK:
  2669. case WM8994_FLL_SRC_BCLK:
  2670. break;
  2671. default:
  2672. return -EINVAL;
  2673. }
  2674. /* Are we changing anything? */
  2675. if (wm8994->fll[id].src == src &&
  2676. wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
  2677. return 0;
  2678. /* If we're stopping the FLL redo the old config - no
  2679. * registers will actually be written but we avoid GCC flow
  2680. * analysis bugs spewing warnings.
  2681. */
  2682. if (freq_out)
  2683. ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
  2684. else
  2685. ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
  2686. wm8994->fll[id].out);
  2687. if (ret < 0)
  2688. return ret;
  2689. /* Gate the AIF clocks while we reclock */
  2690. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  2691. WM8994_AIF1CLK_ENA, 0);
  2692. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  2693. WM8994_AIF2CLK_ENA, 0);
  2694. /* We always need to disable the FLL while reconfiguring */
  2695. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  2696. WM8994_FLL1_ENA, 0);
  2697. reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
  2698. (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
  2699. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
  2700. WM8994_FLL1_OUTDIV_MASK |
  2701. WM8994_FLL1_FRATIO_MASK, reg);
  2702. snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
  2703. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
  2704. WM8994_FLL1_N_MASK,
  2705. fll.n << WM8994_FLL1_N_SHIFT);
  2706. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
  2707. WM8994_FLL1_REFCLK_DIV_MASK |
  2708. WM8994_FLL1_REFCLK_SRC_MASK,
  2709. (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
  2710. (src - 1));
  2711. /* Enable (with fractional mode if required) */
  2712. if (freq_out) {
  2713. if (fll.k)
  2714. reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
  2715. else
  2716. reg = WM8994_FLL1_ENA;
  2717. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  2718. WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
  2719. reg);
  2720. }
  2721. wm8994->fll[id].in = freq_in;
  2722. wm8994->fll[id].out = freq_out;
  2723. wm8994->fll[id].src = src;
  2724. /* Enable any gated AIF clocks */
  2725. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  2726. WM8994_AIF1CLK_ENA, aif1);
  2727. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  2728. WM8994_AIF2CLK_ENA, aif2);
  2729. configure_clock(codec);
  2730. return 0;
  2731. }
  2732. static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  2733. static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
  2734. int clk_id, unsigned int freq, int dir)
  2735. {
  2736. struct snd_soc_codec *codec = dai->codec;
  2737. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2738. int i;
  2739. switch (dai->id) {
  2740. case 1:
  2741. case 2:
  2742. break;
  2743. default:
  2744. /* AIF3 shares clocking with AIF1/2 */
  2745. return -EINVAL;
  2746. }
  2747. switch (clk_id) {
  2748. case WM8994_SYSCLK_MCLK1:
  2749. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
  2750. wm8994->mclk[0] = freq;
  2751. dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
  2752. dai->id, freq);
  2753. break;
  2754. case WM8994_SYSCLK_MCLK2:
  2755. /* TODO: Set GPIO AF */
  2756. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
  2757. wm8994->mclk[1] = freq;
  2758. dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
  2759. dai->id, freq);
  2760. break;
  2761. case WM8994_SYSCLK_FLL1:
  2762. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
  2763. dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
  2764. break;
  2765. case WM8994_SYSCLK_FLL2:
  2766. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
  2767. dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
  2768. break;
  2769. case WM8994_SYSCLK_OPCLK:
  2770. /* Special case - a division (times 10) is given and
  2771. * no effect on main clocking.
  2772. */
  2773. if (freq) {
  2774. for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
  2775. if (opclk_divs[i] == freq)
  2776. break;
  2777. if (i == ARRAY_SIZE(opclk_divs))
  2778. return -EINVAL;
  2779. snd_soc_update_bits(codec, WM8994_CLOCKING_2,
  2780. WM8994_OPCLK_DIV_MASK, i);
  2781. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  2782. WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
  2783. } else {
  2784. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  2785. WM8994_OPCLK_ENA, 0);
  2786. }
  2787. default:
  2788. return -EINVAL;
  2789. }
  2790. configure_clock(codec);
  2791. return 0;
  2792. }
  2793. static int wm8994_set_bias_level(struct snd_soc_codec *codec,
  2794. enum snd_soc_bias_level level)
  2795. {
  2796. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2797. switch (level) {
  2798. case SND_SOC_BIAS_ON:
  2799. break;
  2800. case SND_SOC_BIAS_PREPARE:
  2801. /* VMID=2x40k */
  2802. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  2803. WM8994_VMID_SEL_MASK, 0x2);
  2804. break;
  2805. case SND_SOC_BIAS_STANDBY:
  2806. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  2807. /* Tweak DC servo and DSP configuration for
  2808. * improved performance. */
  2809. if (wm8994->revision < 4) {
  2810. /* Tweak DC servo and DSP configuration for
  2811. * improved performance. */
  2812. snd_soc_write(codec, 0x102, 0x3);
  2813. snd_soc_write(codec, 0x56, 0x3);
  2814. snd_soc_write(codec, 0x817, 0);
  2815. snd_soc_write(codec, 0x102, 0);
  2816. }
  2817. /* Discharge LINEOUT1 & 2 */
  2818. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  2819. WM8994_LINEOUT1_DISCH |
  2820. WM8994_LINEOUT2_DISCH,
  2821. WM8994_LINEOUT1_DISCH |
  2822. WM8994_LINEOUT2_DISCH);
  2823. /* Startup bias, VMID ramp & buffer */
  2824. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  2825. WM8994_STARTUP_BIAS_ENA |
  2826. WM8994_VMID_BUF_ENA |
  2827. WM8994_VMID_RAMP_MASK,
  2828. WM8994_STARTUP_BIAS_ENA |
  2829. WM8994_VMID_BUF_ENA |
  2830. (0x11 << WM8994_VMID_RAMP_SHIFT));
  2831. /* Main bias enable, VMID=2x40k */
  2832. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  2833. WM8994_BIAS_ENA |
  2834. WM8994_VMID_SEL_MASK,
  2835. WM8994_BIAS_ENA | 0x2);
  2836. msleep(20);
  2837. }
  2838. /* VMID=2x500k */
  2839. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  2840. WM8994_VMID_SEL_MASK, 0x4);
  2841. break;
  2842. case SND_SOC_BIAS_OFF:
  2843. if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
  2844. /* Switch over to startup biases */
  2845. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  2846. WM8994_BIAS_SRC |
  2847. WM8994_STARTUP_BIAS_ENA |
  2848. WM8994_VMID_BUF_ENA |
  2849. WM8994_VMID_RAMP_MASK,
  2850. WM8994_BIAS_SRC |
  2851. WM8994_STARTUP_BIAS_ENA |
  2852. WM8994_VMID_BUF_ENA |
  2853. (1 << WM8994_VMID_RAMP_SHIFT));
  2854. /* Disable main biases */
  2855. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  2856. WM8994_BIAS_ENA |
  2857. WM8994_VMID_SEL_MASK, 0);
  2858. /* Discharge line */
  2859. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  2860. WM8994_LINEOUT1_DISCH |
  2861. WM8994_LINEOUT2_DISCH,
  2862. WM8994_LINEOUT1_DISCH |
  2863. WM8994_LINEOUT2_DISCH);
  2864. msleep(5);
  2865. /* Switch off startup biases */
  2866. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  2867. WM8994_BIAS_SRC |
  2868. WM8994_STARTUP_BIAS_ENA |
  2869. WM8994_VMID_BUF_ENA |
  2870. WM8994_VMID_RAMP_MASK, 0);
  2871. }
  2872. break;
  2873. }
  2874. codec->bias_level = level;
  2875. return 0;
  2876. }
  2877. static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2878. {
  2879. struct snd_soc_codec *codec = dai->codec;
  2880. int ms_reg;
  2881. int aif1_reg;
  2882. int ms = 0;
  2883. int aif1 = 0;
  2884. switch (dai->id) {
  2885. case 1:
  2886. ms_reg = WM8994_AIF1_MASTER_SLAVE;
  2887. aif1_reg = WM8994_AIF1_CONTROL_1;
  2888. break;
  2889. case 2:
  2890. ms_reg = WM8994_AIF2_MASTER_SLAVE;
  2891. aif1_reg = WM8994_AIF2_CONTROL_1;
  2892. break;
  2893. default:
  2894. return -EINVAL;
  2895. }
  2896. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2897. case SND_SOC_DAIFMT_CBS_CFS:
  2898. break;
  2899. case SND_SOC_DAIFMT_CBM_CFM:
  2900. ms = WM8994_AIF1_MSTR;
  2901. break;
  2902. default:
  2903. return -EINVAL;
  2904. }
  2905. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2906. case SND_SOC_DAIFMT_DSP_B:
  2907. aif1 |= WM8994_AIF1_LRCLK_INV;
  2908. case SND_SOC_DAIFMT_DSP_A:
  2909. aif1 |= 0x18;
  2910. break;
  2911. case SND_SOC_DAIFMT_I2S:
  2912. aif1 |= 0x10;
  2913. break;
  2914. case SND_SOC_DAIFMT_RIGHT_J:
  2915. break;
  2916. case SND_SOC_DAIFMT_LEFT_J:
  2917. aif1 |= 0x8;
  2918. break;
  2919. default:
  2920. return -EINVAL;
  2921. }
  2922. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2923. case SND_SOC_DAIFMT_DSP_A:
  2924. case SND_SOC_DAIFMT_DSP_B:
  2925. /* frame inversion not valid for DSP modes */
  2926. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2927. case SND_SOC_DAIFMT_NB_NF:
  2928. break;
  2929. case SND_SOC_DAIFMT_IB_NF:
  2930. aif1 |= WM8994_AIF1_BCLK_INV;
  2931. break;
  2932. default:
  2933. return -EINVAL;
  2934. }
  2935. break;
  2936. case SND_SOC_DAIFMT_I2S:
  2937. case SND_SOC_DAIFMT_RIGHT_J:
  2938. case SND_SOC_DAIFMT_LEFT_J:
  2939. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2940. case SND_SOC_DAIFMT_NB_NF:
  2941. break;
  2942. case SND_SOC_DAIFMT_IB_IF:
  2943. aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
  2944. break;
  2945. case SND_SOC_DAIFMT_IB_NF:
  2946. aif1 |= WM8994_AIF1_BCLK_INV;
  2947. break;
  2948. case SND_SOC_DAIFMT_NB_IF:
  2949. aif1 |= WM8994_AIF1_LRCLK_INV;
  2950. break;
  2951. default:
  2952. return -EINVAL;
  2953. }
  2954. break;
  2955. default:
  2956. return -EINVAL;
  2957. }
  2958. snd_soc_update_bits(codec, aif1_reg,
  2959. WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
  2960. WM8994_AIF1_FMT_MASK,
  2961. aif1);
  2962. snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
  2963. ms);
  2964. return 0;
  2965. }
  2966. static struct {
  2967. int val, rate;
  2968. } srs[] = {
  2969. { 0, 8000 },
  2970. { 1, 11025 },
  2971. { 2, 12000 },
  2972. { 3, 16000 },
  2973. { 4, 22050 },
  2974. { 5, 24000 },
  2975. { 6, 32000 },
  2976. { 7, 44100 },
  2977. { 8, 48000 },
  2978. { 9, 88200 },
  2979. { 10, 96000 },
  2980. };
  2981. static int fs_ratios[] = {
  2982. 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  2983. };
  2984. static int bclk_divs[] = {
  2985. 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  2986. 640, 880, 960, 1280, 1760, 1920
  2987. };
  2988. static int wm8994_hw_params(struct snd_pcm_substream *substream,
  2989. struct snd_pcm_hw_params *params,
  2990. struct snd_soc_dai *dai)
  2991. {
  2992. struct snd_soc_codec *codec = dai->codec;
  2993. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2994. int aif1_reg;
  2995. int bclk_reg;
  2996. int lrclk_reg;
  2997. int rate_reg;
  2998. int aif1 = 0;
  2999. int bclk = 0;
  3000. int lrclk = 0;
  3001. int rate_val = 0;
  3002. int id = dai->id - 1;
  3003. int i, cur_val, best_val, bclk_rate, best;
  3004. switch (dai->id) {
  3005. case 1:
  3006. aif1_reg = WM8994_AIF1_CONTROL_1;
  3007. bclk_reg = WM8994_AIF1_BCLK;
  3008. rate_reg = WM8994_AIF1_RATE;
  3009. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  3010. wm8994->lrclk_shared[0])
  3011. lrclk_reg = WM8994_AIF1DAC_LRCLK;
  3012. else
  3013. lrclk_reg = WM8994_AIF1ADC_LRCLK;
  3014. break;
  3015. case 2:
  3016. aif1_reg = WM8994_AIF2_CONTROL_1;
  3017. bclk_reg = WM8994_AIF2_BCLK;
  3018. rate_reg = WM8994_AIF2_RATE;
  3019. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  3020. wm8994->lrclk_shared[1])
  3021. lrclk_reg = WM8994_AIF2DAC_LRCLK;
  3022. else
  3023. lrclk_reg = WM8994_AIF2ADC_LRCLK;
  3024. break;
  3025. default:
  3026. return -EINVAL;
  3027. }
  3028. bclk_rate = params_rate(params) * 2;
  3029. switch (params_format(params)) {
  3030. case SNDRV_PCM_FORMAT_S16_LE:
  3031. bclk_rate *= 16;
  3032. break;
  3033. case SNDRV_PCM_FORMAT_S20_3LE:
  3034. bclk_rate *= 20;
  3035. aif1 |= 0x20;
  3036. break;
  3037. case SNDRV_PCM_FORMAT_S24_LE:
  3038. bclk_rate *= 24;
  3039. aif1 |= 0x40;
  3040. break;
  3041. case SNDRV_PCM_FORMAT_S32_LE:
  3042. bclk_rate *= 32;
  3043. aif1 |= 0x60;
  3044. break;
  3045. default:
  3046. return -EINVAL;
  3047. }
  3048. /* Try to find an appropriate sample rate; look for an exact match. */
  3049. for (i = 0; i < ARRAY_SIZE(srs); i++)
  3050. if (srs[i].rate == params_rate(params))
  3051. break;
  3052. if (i == ARRAY_SIZE(srs))
  3053. return -EINVAL;
  3054. rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
  3055. dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
  3056. dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
  3057. dai->id, wm8994->aifclk[id], bclk_rate);
  3058. if (wm8994->aifclk[id] == 0) {
  3059. dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
  3060. return -EINVAL;
  3061. }
  3062. /* AIFCLK/fs ratio; look for a close match in either direction */
  3063. best = 0;
  3064. best_val = abs((fs_ratios[0] * params_rate(params))
  3065. - wm8994->aifclk[id]);
  3066. for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
  3067. cur_val = abs((fs_ratios[i] * params_rate(params))
  3068. - wm8994->aifclk[id]);
  3069. if (cur_val >= best_val)
  3070. continue;
  3071. best = i;
  3072. best_val = cur_val;
  3073. }
  3074. dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
  3075. dai->id, fs_ratios[best]);
  3076. rate_val |= best;
  3077. /* We may not get quite the right frequency if using
  3078. * approximate clocks so look for the closest match that is
  3079. * higher than the target (we need to ensure that there enough
  3080. * BCLKs to clock out the samples).
  3081. */
  3082. best = 0;
  3083. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  3084. cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
  3085. if (cur_val < 0) /* BCLK table is sorted */
  3086. break;
  3087. best = i;
  3088. }
  3089. bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
  3090. dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  3091. bclk_divs[best], bclk_rate);
  3092. bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
  3093. lrclk = bclk_rate / params_rate(params);
  3094. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  3095. lrclk, bclk_rate / lrclk);
  3096. snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  3097. snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
  3098. snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
  3099. lrclk);
  3100. snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
  3101. WM8994_AIF1CLK_RATE_MASK, rate_val);
  3102. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3103. switch (dai->id) {
  3104. case 1:
  3105. wm8994->dac_rates[0] = params_rate(params);
  3106. wm8994_set_retune_mobile(codec, 0);
  3107. wm8994_set_retune_mobile(codec, 1);
  3108. break;
  3109. case 2:
  3110. wm8994->dac_rates[1] = params_rate(params);
  3111. wm8994_set_retune_mobile(codec, 2);
  3112. break;
  3113. }
  3114. }
  3115. return 0;
  3116. }
  3117. static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
  3118. {
  3119. struct snd_soc_codec *codec = codec_dai->codec;
  3120. int mute_reg;
  3121. int reg;
  3122. switch (codec_dai->id) {
  3123. case 1:
  3124. mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
  3125. break;
  3126. case 2:
  3127. mute_reg = WM8994_AIF2_DAC_FILTERS_1;
  3128. break;
  3129. default:
  3130. return -EINVAL;
  3131. }
  3132. if (mute)
  3133. reg = WM8994_AIF1DAC1_MUTE;
  3134. else
  3135. reg = 0;
  3136. snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
  3137. return 0;
  3138. }
  3139. static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
  3140. {
  3141. struct snd_soc_codec *codec = codec_dai->codec;
  3142. int reg, val, mask;
  3143. switch (codec_dai->id) {
  3144. case 1:
  3145. reg = WM8994_AIF1_MASTER_SLAVE;
  3146. mask = WM8994_AIF1_TRI;
  3147. break;
  3148. case 2:
  3149. reg = WM8994_AIF2_MASTER_SLAVE;
  3150. mask = WM8994_AIF2_TRI;
  3151. break;
  3152. case 3:
  3153. reg = WM8994_POWER_MANAGEMENT_6;
  3154. mask = WM8994_AIF3_TRI;
  3155. break;
  3156. default:
  3157. return -EINVAL;
  3158. }
  3159. if (tristate)
  3160. val = mask;
  3161. else
  3162. val = 0;
  3163. return snd_soc_update_bits(codec, reg, mask, reg);
  3164. }
  3165. #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
  3166. #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  3167. SNDRV_PCM_FMTBIT_S24_LE)
  3168. static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
  3169. .set_sysclk = wm8994_set_dai_sysclk,
  3170. .set_fmt = wm8994_set_dai_fmt,
  3171. .hw_params = wm8994_hw_params,
  3172. .digital_mute = wm8994_aif_mute,
  3173. .set_pll = wm8994_set_fll,
  3174. .set_tristate = wm8994_set_tristate,
  3175. };
  3176. static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
  3177. .set_sysclk = wm8994_set_dai_sysclk,
  3178. .set_fmt = wm8994_set_dai_fmt,
  3179. .hw_params = wm8994_hw_params,
  3180. .digital_mute = wm8994_aif_mute,
  3181. .set_pll = wm8994_set_fll,
  3182. .set_tristate = wm8994_set_tristate,
  3183. };
  3184. static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
  3185. .set_tristate = wm8994_set_tristate,
  3186. };
  3187. struct snd_soc_dai wm8994_dai[] = {
  3188. {
  3189. .name = "WM8994 AIF1",
  3190. .id = 1,
  3191. .playback = {
  3192. .stream_name = "AIF1 Playback",
  3193. .channels_min = 2,
  3194. .channels_max = 2,
  3195. .rates = WM8994_RATES,
  3196. .formats = WM8994_FORMATS,
  3197. },
  3198. .capture = {
  3199. .stream_name = "AIF1 Capture",
  3200. .channels_min = 2,
  3201. .channels_max = 2,
  3202. .rates = WM8994_RATES,
  3203. .formats = WM8994_FORMATS,
  3204. },
  3205. .ops = &wm8994_aif1_dai_ops,
  3206. },
  3207. {
  3208. .name = "WM8994 AIF2",
  3209. .id = 2,
  3210. .playback = {
  3211. .stream_name = "AIF2 Playback",
  3212. .channels_min = 2,
  3213. .channels_max = 2,
  3214. .rates = WM8994_RATES,
  3215. .formats = WM8994_FORMATS,
  3216. },
  3217. .capture = {
  3218. .stream_name = "AIF2 Capture",
  3219. .channels_min = 2,
  3220. .channels_max = 2,
  3221. .rates = WM8994_RATES,
  3222. .formats = WM8994_FORMATS,
  3223. },
  3224. .ops = &wm8994_aif2_dai_ops,
  3225. },
  3226. {
  3227. .name = "WM8994 AIF3",
  3228. .id = 3,
  3229. .playback = {
  3230. .stream_name = "AIF3 Playback",
  3231. .channels_min = 2,
  3232. .channels_max = 2,
  3233. .rates = WM8994_RATES,
  3234. .formats = WM8994_FORMATS,
  3235. },
  3236. .capture = {
  3237. .stream_name = "AIF3 Capture",
  3238. .channels_min = 2,
  3239. .channels_max = 2,
  3240. .rates = WM8994_RATES,
  3241. .formats = WM8994_FORMATS,
  3242. },
  3243. .ops = &wm8994_aif3_dai_ops,
  3244. }
  3245. };
  3246. EXPORT_SYMBOL_GPL(wm8994_dai);
  3247. #ifdef CONFIG_PM
  3248. static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
  3249. {
  3250. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  3251. struct snd_soc_codec *codec = socdev->card->codec;
  3252. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3253. int i, ret;
  3254. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  3255. memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
  3256. sizeof(struct fll_config));
  3257. ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0);
  3258. if (ret < 0)
  3259. dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
  3260. i + 1, ret);
  3261. }
  3262. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  3263. return 0;
  3264. }
  3265. static int wm8994_resume(struct platform_device *pdev)
  3266. {
  3267. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  3268. struct snd_soc_codec *codec = socdev->card->codec;
  3269. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3270. u16 *reg_cache = codec->reg_cache;
  3271. int i, ret;
  3272. /* Restore the registers */
  3273. for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
  3274. switch (i) {
  3275. case WM8994_LDO_1:
  3276. case WM8994_LDO_2:
  3277. case WM8994_SOFTWARE_RESET:
  3278. /* Handled by other MFD drivers */
  3279. continue;
  3280. default:
  3281. break;
  3282. }
  3283. if (!access_masks[i].writable)
  3284. continue;
  3285. wm8994_reg_write(codec->control_data, i, reg_cache[i]);
  3286. }
  3287. wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  3288. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  3289. if (!wm8994->fll_suspend[i].out)
  3290. continue;
  3291. ret = wm8994_set_fll(&codec->dai[0], i + 1,
  3292. wm8994->fll_suspend[i].src,
  3293. wm8994->fll_suspend[i].in,
  3294. wm8994->fll_suspend[i].out);
  3295. if (ret < 0)
  3296. dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
  3297. i + 1, ret);
  3298. }
  3299. return 0;
  3300. }
  3301. #else
  3302. #define wm8994_suspend NULL
  3303. #define wm8994_resume NULL
  3304. #endif
  3305. static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
  3306. {
  3307. struct snd_soc_codec *codec = &wm8994->codec;
  3308. struct wm8994_pdata *pdata = wm8994->pdata;
  3309. struct snd_kcontrol_new controls[] = {
  3310. SOC_ENUM_EXT("AIF1.1 EQ Mode",
  3311. wm8994->retune_mobile_enum,
  3312. wm8994_get_retune_mobile_enum,
  3313. wm8994_put_retune_mobile_enum),
  3314. SOC_ENUM_EXT("AIF1.2 EQ Mode",
  3315. wm8994->retune_mobile_enum,
  3316. wm8994_get_retune_mobile_enum,
  3317. wm8994_put_retune_mobile_enum),
  3318. SOC_ENUM_EXT("AIF2 EQ Mode",
  3319. wm8994->retune_mobile_enum,
  3320. wm8994_get_retune_mobile_enum,
  3321. wm8994_put_retune_mobile_enum),
  3322. };
  3323. int ret, i, j;
  3324. const char **t;
  3325. /* We need an array of texts for the enum API but the number
  3326. * of texts is likely to be less than the number of
  3327. * configurations due to the sample rate dependency of the
  3328. * configurations. */
  3329. wm8994->num_retune_mobile_texts = 0;
  3330. wm8994->retune_mobile_texts = NULL;
  3331. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  3332. for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
  3333. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  3334. wm8994->retune_mobile_texts[j]) == 0)
  3335. break;
  3336. }
  3337. if (j != wm8994->num_retune_mobile_texts)
  3338. continue;
  3339. /* Expand the array... */
  3340. t = krealloc(wm8994->retune_mobile_texts,
  3341. sizeof(char *) *
  3342. (wm8994->num_retune_mobile_texts + 1),
  3343. GFP_KERNEL);
  3344. if (t == NULL)
  3345. continue;
  3346. /* ...store the new entry... */
  3347. t[wm8994->num_retune_mobile_texts] =
  3348. pdata->retune_mobile_cfgs[i].name;
  3349. /* ...and remember the new version. */
  3350. wm8994->num_retune_mobile_texts++;
  3351. wm8994->retune_mobile_texts = t;
  3352. }
  3353. dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
  3354. wm8994->num_retune_mobile_texts);
  3355. wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
  3356. wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
  3357. ret = snd_soc_add_controls(&wm8994->codec, controls,
  3358. ARRAY_SIZE(controls));
  3359. if (ret != 0)
  3360. dev_err(wm8994->codec.dev,
  3361. "Failed to add ReTune Mobile controls: %d\n", ret);
  3362. }
  3363. static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
  3364. {
  3365. struct snd_soc_codec *codec = &wm8994->codec;
  3366. struct wm8994_pdata *pdata = wm8994->pdata;
  3367. int ret, i;
  3368. if (!pdata)
  3369. return;
  3370. wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
  3371. pdata->lineout2_diff,
  3372. pdata->lineout1fb,
  3373. pdata->lineout2fb,
  3374. pdata->jd_scthr,
  3375. pdata->jd_thr,
  3376. pdata->micbias1_lvl,
  3377. pdata->micbias2_lvl);
  3378. dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  3379. if (pdata->num_drc_cfgs) {
  3380. struct snd_kcontrol_new controls[] = {
  3381. SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
  3382. wm8994_get_drc_enum, wm8994_put_drc_enum),
  3383. SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
  3384. wm8994_get_drc_enum, wm8994_put_drc_enum),
  3385. SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
  3386. wm8994_get_drc_enum, wm8994_put_drc_enum),
  3387. };
  3388. /* We need an array of texts for the enum API */
  3389. wm8994->drc_texts = kmalloc(sizeof(char *)
  3390. * pdata->num_drc_cfgs, GFP_KERNEL);
  3391. if (!wm8994->drc_texts) {
  3392. dev_err(wm8994->codec.dev,
  3393. "Failed to allocate %d DRC config texts\n",
  3394. pdata->num_drc_cfgs);
  3395. return;
  3396. }
  3397. for (i = 0; i < pdata->num_drc_cfgs; i++)
  3398. wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
  3399. wm8994->drc_enum.max = pdata->num_drc_cfgs;
  3400. wm8994->drc_enum.texts = wm8994->drc_texts;
  3401. ret = snd_soc_add_controls(&wm8994->codec, controls,
  3402. ARRAY_SIZE(controls));
  3403. if (ret != 0)
  3404. dev_err(wm8994->codec.dev,
  3405. "Failed to add DRC mode controls: %d\n", ret);
  3406. for (i = 0; i < WM8994_NUM_DRC; i++)
  3407. wm8994_set_drc(codec, i);
  3408. }
  3409. dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
  3410. pdata->num_retune_mobile_cfgs);
  3411. if (pdata->num_retune_mobile_cfgs)
  3412. wm8994_handle_retune_mobile_pdata(wm8994);
  3413. else
  3414. snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls,
  3415. ARRAY_SIZE(wm8994_eq_controls));
  3416. }
  3417. static int wm8994_probe(struct platform_device *pdev)
  3418. {
  3419. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  3420. struct snd_soc_codec *codec;
  3421. int ret = 0;
  3422. if (wm8994_codec == NULL) {
  3423. dev_err(&pdev->dev, "Codec device not registered\n");
  3424. return -ENODEV;
  3425. }
  3426. socdev->card->codec = wm8994_codec;
  3427. codec = wm8994_codec;
  3428. /* register pcms */
  3429. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  3430. if (ret < 0) {
  3431. dev_err(codec->dev, "failed to create pcms: %d\n", ret);
  3432. return ret;
  3433. }
  3434. wm8994_handle_pdata(snd_soc_codec_get_drvdata(codec));
  3435. wm_hubs_add_analogue_controls(codec);
  3436. snd_soc_add_controls(codec, wm8994_snd_controls,
  3437. ARRAY_SIZE(wm8994_snd_controls));
  3438. snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
  3439. ARRAY_SIZE(wm8994_dapm_widgets));
  3440. wm_hubs_add_analogue_routes(codec, 0, 0);
  3441. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  3442. return 0;
  3443. }
  3444. static int wm8994_remove(struct platform_device *pdev)
  3445. {
  3446. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  3447. snd_soc_free_pcms(socdev);
  3448. snd_soc_dapm_free(socdev);
  3449. return 0;
  3450. }
  3451. struct snd_soc_codec_device soc_codec_dev_wm8994 = {
  3452. .probe = wm8994_probe,
  3453. .remove = wm8994_remove,
  3454. .suspend = wm8994_suspend,
  3455. .resume = wm8994_resume,
  3456. };
  3457. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
  3458. /**
  3459. * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
  3460. *
  3461. * @codec: WM8994 codec
  3462. * @jack: jack to report detection events on
  3463. * @micbias: microphone bias to detect on
  3464. * @det: value to report for presence detection
  3465. * @shrt: value to report for short detection
  3466. *
  3467. * Enable microphone detection via IRQ on the WM8994. If GPIOs are
  3468. * being used to bring out signals to the processor then only platform
  3469. * data configuration is needed for WM8903 and processor GPIOs should
  3470. * be configured using snd_soc_jack_add_gpios() instead.
  3471. *
  3472. * Configuration of detection levels is available via the micbias1_lvl
  3473. * and micbias2_lvl platform data members.
  3474. */
  3475. int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  3476. int micbias, int det, int shrt)
  3477. {
  3478. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3479. struct wm8994_micdet *micdet;
  3480. int reg;
  3481. switch (micbias) {
  3482. case 1:
  3483. micdet = &wm8994->micdet[0];
  3484. break;
  3485. case 2:
  3486. micdet = &wm8994->micdet[1];
  3487. break;
  3488. default:
  3489. return -EINVAL;
  3490. }
  3491. dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
  3492. micbias, det, shrt);
  3493. /* Store the configuration */
  3494. micdet->jack = jack;
  3495. micdet->det = det;
  3496. micdet->shrt = shrt;
  3497. /* If either of the jacks is set up then enable detection */
  3498. if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
  3499. reg = WM8994_MICD_ENA;
  3500. else
  3501. reg = 0;
  3502. snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
  3503. return 0;
  3504. }
  3505. EXPORT_SYMBOL_GPL(wm8994_mic_detect);
  3506. static irqreturn_t wm8994_mic_irq(int irq, void *data)
  3507. {
  3508. struct wm8994_priv *priv = data;
  3509. struct snd_soc_codec *codec = &priv->codec;
  3510. int reg;
  3511. int report;
  3512. reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
  3513. if (reg < 0) {
  3514. dev_err(codec->dev, "Failed to read microphone status: %d\n",
  3515. reg);
  3516. return IRQ_HANDLED;
  3517. }
  3518. dev_dbg(codec->dev, "Microphone status: %x\n", reg);
  3519. report = 0;
  3520. if (reg & WM8994_MIC1_DET_STS)
  3521. report |= priv->micdet[0].det;
  3522. if (reg & WM8994_MIC1_SHRT_STS)
  3523. report |= priv->micdet[0].shrt;
  3524. snd_soc_jack_report(priv->micdet[0].jack, report,
  3525. priv->micdet[0].det | priv->micdet[0].shrt);
  3526. report = 0;
  3527. if (reg & WM8994_MIC2_DET_STS)
  3528. report |= priv->micdet[1].det;
  3529. if (reg & WM8994_MIC2_SHRT_STS)
  3530. report |= priv->micdet[1].shrt;
  3531. snd_soc_jack_report(priv->micdet[1].jack, report,
  3532. priv->micdet[1].det | priv->micdet[1].shrt);
  3533. return IRQ_HANDLED;
  3534. }
  3535. static int wm8994_codec_probe(struct platform_device *pdev)
  3536. {
  3537. int ret;
  3538. struct wm8994_priv *wm8994;
  3539. struct snd_soc_codec *codec;
  3540. int i;
  3541. if (wm8994_codec) {
  3542. dev_err(&pdev->dev, "Another WM8994 is registered\n");
  3543. return -EINVAL;
  3544. }
  3545. wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
  3546. if (!wm8994) {
  3547. dev_err(&pdev->dev, "Failed to allocate private data\n");
  3548. return -ENOMEM;
  3549. }
  3550. codec = &wm8994->codec;
  3551. mutex_init(&codec->mutex);
  3552. INIT_LIST_HEAD(&codec->dapm_widgets);
  3553. INIT_LIST_HEAD(&codec->dapm_paths);
  3554. snd_soc_codec_set_drvdata(codec, wm8994);
  3555. codec->control_data = dev_get_drvdata(pdev->dev.parent);
  3556. codec->name = "WM8994";
  3557. codec->owner = THIS_MODULE;
  3558. codec->read = wm8994_read;
  3559. codec->write = wm8994_write;
  3560. codec->readable_register = wm8994_readable;
  3561. codec->bias_level = SND_SOC_BIAS_OFF;
  3562. codec->set_bias_level = wm8994_set_bias_level;
  3563. codec->dai = &wm8994_dai[0];
  3564. codec->num_dai = 3;
  3565. codec->reg_cache_size = WM8994_MAX_REGISTER;
  3566. codec->reg_cache = &wm8994->reg_cache;
  3567. codec->dev = &pdev->dev;
  3568. wm8994->pdata = pdev->dev.parent->platform_data;
  3569. /* Fill the cache with physical values we inherited; don't reset */
  3570. ret = wm8994_bulk_read(codec->control_data, 0,
  3571. ARRAY_SIZE(wm8994->reg_cache) - 1,
  3572. codec->reg_cache);
  3573. if (ret < 0) {
  3574. dev_err(codec->dev, "Failed to fill register cache: %d\n",
  3575. ret);
  3576. goto err;
  3577. }
  3578. /* Clear the cached values for unreadable/volatile registers to
  3579. * avoid potential confusion.
  3580. */
  3581. for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
  3582. if (wm8994_volatile(i) || !wm8994_readable(i))
  3583. wm8994->reg_cache[i] = 0;
  3584. /* Set revision-specific configuration */
  3585. wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
  3586. switch (wm8994->revision) {
  3587. case 2:
  3588. case 3:
  3589. wm8994->hubs.dcs_codes = -5;
  3590. wm8994->hubs.hp_startup_mode = 1;
  3591. wm8994->hubs.dcs_readback_mode = 1;
  3592. break;
  3593. default:
  3594. wm8994->hubs.dcs_readback_mode = 1;
  3595. break;
  3596. }
  3597. ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
  3598. wm8994_mic_irq, "Mic 1 detect", wm8994);
  3599. if (ret != 0)
  3600. dev_warn(&pdev->dev,
  3601. "Failed to request Mic1 detect IRQ: %d\n", ret);
  3602. ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
  3603. wm8994_mic_irq, "Mic 1 short", wm8994);
  3604. if (ret != 0)
  3605. dev_warn(&pdev->dev,
  3606. "Failed to request Mic1 short IRQ: %d\n", ret);
  3607. ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
  3608. wm8994_mic_irq, "Mic 2 detect", wm8994);
  3609. if (ret != 0)
  3610. dev_warn(&pdev->dev,
  3611. "Failed to request Mic2 detect IRQ: %d\n", ret);
  3612. ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
  3613. wm8994_mic_irq, "Mic 2 short", wm8994);
  3614. if (ret != 0)
  3615. dev_warn(&pdev->dev,
  3616. "Failed to request Mic2 short IRQ: %d\n", ret);
  3617. /* Remember if AIFnLRCLK is configured as a GPIO. This should be
  3618. * configured on init - if a system wants to do this dynamically
  3619. * at runtime we can deal with that then.
  3620. */
  3621. ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
  3622. if (ret < 0) {
  3623. dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
  3624. goto err_irq;
  3625. }
  3626. if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3627. wm8994->lrclk_shared[0] = 1;
  3628. wm8994_dai[0].symmetric_rates = 1;
  3629. } else {
  3630. wm8994->lrclk_shared[0] = 0;
  3631. }
  3632. ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
  3633. if (ret < 0) {
  3634. dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
  3635. goto err_irq;
  3636. }
  3637. if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3638. wm8994->lrclk_shared[1] = 1;
  3639. wm8994_dai[1].symmetric_rates = 1;
  3640. } else {
  3641. wm8994->lrclk_shared[1] = 0;
  3642. }
  3643. for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
  3644. wm8994_dai[i].dev = codec->dev;
  3645. wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  3646. wm8994_codec = codec;
  3647. /* Latch volume updates (right only; we always do left then right). */
  3648. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
  3649. WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
  3650. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
  3651. WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
  3652. snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
  3653. WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
  3654. snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
  3655. WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
  3656. snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
  3657. WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
  3658. snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
  3659. WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
  3660. snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
  3661. WM8994_DAC1_VU, WM8994_DAC1_VU);
  3662. snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
  3663. WM8994_DAC2_VU, WM8994_DAC2_VU);
  3664. /* Set the low bit of the 3D stereo depth so TLV matches */
  3665. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
  3666. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
  3667. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
  3668. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
  3669. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
  3670. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
  3671. snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
  3672. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
  3673. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
  3674. /* Unconditionally enable AIF1 ADC TDM mode; it only affects
  3675. * behaviour on idle TDM clock cycles. */
  3676. snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
  3677. WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
  3678. wm8994_update_class_w(codec);
  3679. ret = snd_soc_register_codec(codec);
  3680. if (ret != 0) {
  3681. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  3682. goto err_irq;
  3683. }
  3684. ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
  3685. if (ret != 0) {
  3686. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  3687. goto err_codec;
  3688. }
  3689. platform_set_drvdata(pdev, wm8994);
  3690. return 0;
  3691. err_codec:
  3692. snd_soc_unregister_codec(codec);
  3693. err_irq:
  3694. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
  3695. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
  3696. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
  3697. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
  3698. err:
  3699. kfree(wm8994);
  3700. return ret;
  3701. }
  3702. static int __devexit wm8994_codec_remove(struct platform_device *pdev)
  3703. {
  3704. struct wm8994_priv *wm8994 = platform_get_drvdata(pdev);
  3705. struct snd_soc_codec *codec = &wm8994->codec;
  3706. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  3707. snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
  3708. snd_soc_unregister_codec(&wm8994->codec);
  3709. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
  3710. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
  3711. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
  3712. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
  3713. kfree(wm8994);
  3714. wm8994_codec = NULL;
  3715. return 0;
  3716. }
  3717. static struct platform_driver wm8994_codec_driver = {
  3718. .driver = {
  3719. .name = "wm8994-codec",
  3720. .owner = THIS_MODULE,
  3721. },
  3722. .probe = wm8994_codec_probe,
  3723. .remove = __devexit_p(wm8994_codec_remove),
  3724. };
  3725. static __init int wm8994_init(void)
  3726. {
  3727. return platform_driver_register(&wm8994_codec_driver);
  3728. }
  3729. module_init(wm8994_init);
  3730. static __exit void wm8994_exit(void)
  3731. {
  3732. platform_driver_unregister(&wm8994_codec_driver);
  3733. }
  3734. module_exit(wm8994_exit);
  3735. MODULE_DESCRIPTION("ASoC WM8994 driver");
  3736. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  3737. MODULE_LICENSE("GPL");
  3738. MODULE_ALIAS("platform:wm8994-codec");