wm8904.c 74 KB

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  1. /*
  2. * wm8904.c -- WM8904 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <sound/wm8904.h>
  30. #include "wm8904.h"
  31. static struct snd_soc_codec *wm8904_codec;
  32. struct snd_soc_codec_device soc_codec_dev_wm8904;
  33. enum wm8904_type {
  34. WM8904,
  35. WM8912,
  36. };
  37. #define WM8904_NUM_DCS_CHANNELS 4
  38. #define WM8904_NUM_SUPPLIES 5
  39. static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
  40. "DCVDD",
  41. "DBVDD",
  42. "AVDD",
  43. "CPVDD",
  44. "MICVDD",
  45. };
  46. /* codec private data */
  47. struct wm8904_priv {
  48. struct snd_soc_codec codec;
  49. u16 reg_cache[WM8904_MAX_REGISTER + 1];
  50. enum wm8904_type devtype;
  51. struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
  52. struct wm8904_pdata *pdata;
  53. int deemph;
  54. /* Platform provided DRC configuration */
  55. const char **drc_texts;
  56. int drc_cfg;
  57. struct soc_enum drc_enum;
  58. /* Platform provided ReTune mobile configuration */
  59. int num_retune_mobile_texts;
  60. const char **retune_mobile_texts;
  61. int retune_mobile_cfg;
  62. struct soc_enum retune_mobile_enum;
  63. /* FLL setup */
  64. int fll_src;
  65. int fll_fref;
  66. int fll_fout;
  67. /* Clocking configuration */
  68. unsigned int mclk_rate;
  69. int sysclk_src;
  70. unsigned int sysclk_rate;
  71. int tdm_width;
  72. int tdm_slots;
  73. int bclk;
  74. int fs;
  75. /* DC servo configuration - cached offset values */
  76. int dcs_state[WM8904_NUM_DCS_CHANNELS];
  77. };
  78. static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = {
  79. 0x8904, /* R0 - SW Reset and ID */
  80. 0x0000, /* R1 - Revision */
  81. 0x0000, /* R2 */
  82. 0x0000, /* R3 */
  83. 0x0018, /* R4 - Bias Control 0 */
  84. 0x0000, /* R5 - VMID Control 0 */
  85. 0x0000, /* R6 - Mic Bias Control 0 */
  86. 0x0000, /* R7 - Mic Bias Control 1 */
  87. 0x0001, /* R8 - Analogue DAC 0 */
  88. 0x9696, /* R9 - mic Filter Control */
  89. 0x0001, /* R10 - Analogue ADC 0 */
  90. 0x0000, /* R11 */
  91. 0x0000, /* R12 - Power Management 0 */
  92. 0x0000, /* R13 */
  93. 0x0000, /* R14 - Power Management 2 */
  94. 0x0000, /* R15 - Power Management 3 */
  95. 0x0000, /* R16 */
  96. 0x0000, /* R17 */
  97. 0x0000, /* R18 - Power Management 6 */
  98. 0x0000, /* R19 */
  99. 0x945E, /* R20 - Clock Rates 0 */
  100. 0x0C05, /* R21 - Clock Rates 1 */
  101. 0x0006, /* R22 - Clock Rates 2 */
  102. 0x0000, /* R23 */
  103. 0x0050, /* R24 - Audio Interface 0 */
  104. 0x000A, /* R25 - Audio Interface 1 */
  105. 0x00E4, /* R26 - Audio Interface 2 */
  106. 0x0040, /* R27 - Audio Interface 3 */
  107. 0x0000, /* R28 */
  108. 0x0000, /* R29 */
  109. 0x00C0, /* R30 - DAC Digital Volume Left */
  110. 0x00C0, /* R31 - DAC Digital Volume Right */
  111. 0x0000, /* R32 - DAC Digital 0 */
  112. 0x0008, /* R33 - DAC Digital 1 */
  113. 0x0000, /* R34 */
  114. 0x0000, /* R35 */
  115. 0x00C0, /* R36 - ADC Digital Volume Left */
  116. 0x00C0, /* R37 - ADC Digital Volume Right */
  117. 0x0010, /* R38 - ADC Digital 0 */
  118. 0x0000, /* R39 - Digital Microphone 0 */
  119. 0x01AF, /* R40 - DRC 0 */
  120. 0x3248, /* R41 - DRC 1 */
  121. 0x0000, /* R42 - DRC 2 */
  122. 0x0000, /* R43 - DRC 3 */
  123. 0x0085, /* R44 - Analogue Left Input 0 */
  124. 0x0085, /* R45 - Analogue Right Input 0 */
  125. 0x0044, /* R46 - Analogue Left Input 1 */
  126. 0x0044, /* R47 - Analogue Right Input 1 */
  127. 0x0000, /* R48 */
  128. 0x0000, /* R49 */
  129. 0x0000, /* R50 */
  130. 0x0000, /* R51 */
  131. 0x0000, /* R52 */
  132. 0x0000, /* R53 */
  133. 0x0000, /* R54 */
  134. 0x0000, /* R55 */
  135. 0x0000, /* R56 */
  136. 0x002D, /* R57 - Analogue OUT1 Left */
  137. 0x002D, /* R58 - Analogue OUT1 Right */
  138. 0x0039, /* R59 - Analogue OUT2 Left */
  139. 0x0039, /* R60 - Analogue OUT2 Right */
  140. 0x0000, /* R61 - Analogue OUT12 ZC */
  141. 0x0000, /* R62 */
  142. 0x0000, /* R63 */
  143. 0x0000, /* R64 */
  144. 0x0000, /* R65 */
  145. 0x0000, /* R66 */
  146. 0x0000, /* R67 - DC Servo 0 */
  147. 0x0000, /* R68 - DC Servo 1 */
  148. 0xAAAA, /* R69 - DC Servo 2 */
  149. 0x0000, /* R70 */
  150. 0xAAAA, /* R71 - DC Servo 4 */
  151. 0xAAAA, /* R72 - DC Servo 5 */
  152. 0x0000, /* R73 - DC Servo 6 */
  153. 0x0000, /* R74 - DC Servo 7 */
  154. 0x0000, /* R75 - DC Servo 8 */
  155. 0x0000, /* R76 - DC Servo 9 */
  156. 0x0000, /* R77 - DC Servo Readback 0 */
  157. 0x0000, /* R78 */
  158. 0x0000, /* R79 */
  159. 0x0000, /* R80 */
  160. 0x0000, /* R81 */
  161. 0x0000, /* R82 */
  162. 0x0000, /* R83 */
  163. 0x0000, /* R84 */
  164. 0x0000, /* R85 */
  165. 0x0000, /* R86 */
  166. 0x0000, /* R87 */
  167. 0x0000, /* R88 */
  168. 0x0000, /* R89 */
  169. 0x0000, /* R90 - Analogue HP 0 */
  170. 0x0000, /* R91 */
  171. 0x0000, /* R92 */
  172. 0x0000, /* R93 */
  173. 0x0000, /* R94 - Analogue Lineout 0 */
  174. 0x0000, /* R95 */
  175. 0x0000, /* R96 */
  176. 0x0000, /* R97 */
  177. 0x0000, /* R98 - Charge Pump 0 */
  178. 0x0000, /* R99 */
  179. 0x0000, /* R100 */
  180. 0x0000, /* R101 */
  181. 0x0000, /* R102 */
  182. 0x0000, /* R103 */
  183. 0x0004, /* R104 - Class W 0 */
  184. 0x0000, /* R105 */
  185. 0x0000, /* R106 */
  186. 0x0000, /* R107 */
  187. 0x0000, /* R108 - Write Sequencer 0 */
  188. 0x0000, /* R109 - Write Sequencer 1 */
  189. 0x0000, /* R110 - Write Sequencer 2 */
  190. 0x0000, /* R111 - Write Sequencer 3 */
  191. 0x0000, /* R112 - Write Sequencer 4 */
  192. 0x0000, /* R113 */
  193. 0x0000, /* R114 */
  194. 0x0000, /* R115 */
  195. 0x0000, /* R116 - FLL Control 1 */
  196. 0x0007, /* R117 - FLL Control 2 */
  197. 0x0000, /* R118 - FLL Control 3 */
  198. 0x2EE0, /* R119 - FLL Control 4 */
  199. 0x0004, /* R120 - FLL Control 5 */
  200. 0x0014, /* R121 - GPIO Control 1 */
  201. 0x0010, /* R122 - GPIO Control 2 */
  202. 0x0010, /* R123 - GPIO Control 3 */
  203. 0x0000, /* R124 - GPIO Control 4 */
  204. 0x0000, /* R125 */
  205. 0x0000, /* R126 - Digital Pulls */
  206. 0x0000, /* R127 - Interrupt Status */
  207. 0xFFFF, /* R128 - Interrupt Status Mask */
  208. 0x0000, /* R129 - Interrupt Polarity */
  209. 0x0000, /* R130 - Interrupt Debounce */
  210. 0x0000, /* R131 */
  211. 0x0000, /* R132 */
  212. 0x0000, /* R133 */
  213. 0x0000, /* R134 - EQ1 */
  214. 0x000C, /* R135 - EQ2 */
  215. 0x000C, /* R136 - EQ3 */
  216. 0x000C, /* R137 - EQ4 */
  217. 0x000C, /* R138 - EQ5 */
  218. 0x000C, /* R139 - EQ6 */
  219. 0x0FCA, /* R140 - EQ7 */
  220. 0x0400, /* R141 - EQ8 */
  221. 0x00D8, /* R142 - EQ9 */
  222. 0x1EB5, /* R143 - EQ10 */
  223. 0xF145, /* R144 - EQ11 */
  224. 0x0B75, /* R145 - EQ12 */
  225. 0x01C5, /* R146 - EQ13 */
  226. 0x1C58, /* R147 - EQ14 */
  227. 0xF373, /* R148 - EQ15 */
  228. 0x0A54, /* R149 - EQ16 */
  229. 0x0558, /* R150 - EQ17 */
  230. 0x168E, /* R151 - EQ18 */
  231. 0xF829, /* R152 - EQ19 */
  232. 0x07AD, /* R153 - EQ20 */
  233. 0x1103, /* R154 - EQ21 */
  234. 0x0564, /* R155 - EQ22 */
  235. 0x0559, /* R156 - EQ23 */
  236. 0x4000, /* R157 - EQ24 */
  237. 0x0000, /* R158 */
  238. 0x0000, /* R159 */
  239. 0x0000, /* R160 */
  240. 0x0000, /* R161 - Control Interface Test 1 */
  241. 0x0000, /* R162 */
  242. 0x0000, /* R163 */
  243. 0x0000, /* R164 */
  244. 0x0000, /* R165 */
  245. 0x0000, /* R166 */
  246. 0x0000, /* R167 */
  247. 0x0000, /* R168 */
  248. 0x0000, /* R169 */
  249. 0x0000, /* R170 */
  250. 0x0000, /* R171 */
  251. 0x0000, /* R172 */
  252. 0x0000, /* R173 */
  253. 0x0000, /* R174 */
  254. 0x0000, /* R175 */
  255. 0x0000, /* R176 */
  256. 0x0000, /* R177 */
  257. 0x0000, /* R178 */
  258. 0x0000, /* R179 */
  259. 0x0000, /* R180 */
  260. 0x0000, /* R181 */
  261. 0x0000, /* R182 */
  262. 0x0000, /* R183 */
  263. 0x0000, /* R184 */
  264. 0x0000, /* R185 */
  265. 0x0000, /* R186 */
  266. 0x0000, /* R187 */
  267. 0x0000, /* R188 */
  268. 0x0000, /* R189 */
  269. 0x0000, /* R190 */
  270. 0x0000, /* R191 */
  271. 0x0000, /* R192 */
  272. 0x0000, /* R193 */
  273. 0x0000, /* R194 */
  274. 0x0000, /* R195 */
  275. 0x0000, /* R196 */
  276. 0x0000, /* R197 */
  277. 0x0000, /* R198 */
  278. 0x0000, /* R199 */
  279. 0x0000, /* R200 */
  280. 0x0000, /* R201 */
  281. 0x0000, /* R202 */
  282. 0x0000, /* R203 */
  283. 0x0000, /* R204 - Analogue Output Bias 0 */
  284. 0x0000, /* R205 */
  285. 0x0000, /* R206 */
  286. 0x0000, /* R207 */
  287. 0x0000, /* R208 */
  288. 0x0000, /* R209 */
  289. 0x0000, /* R210 */
  290. 0x0000, /* R211 */
  291. 0x0000, /* R212 */
  292. 0x0000, /* R213 */
  293. 0x0000, /* R214 */
  294. 0x0000, /* R215 */
  295. 0x0000, /* R216 */
  296. 0x0000, /* R217 */
  297. 0x0000, /* R218 */
  298. 0x0000, /* R219 */
  299. 0x0000, /* R220 */
  300. 0x0000, /* R221 */
  301. 0x0000, /* R222 */
  302. 0x0000, /* R223 */
  303. 0x0000, /* R224 */
  304. 0x0000, /* R225 */
  305. 0x0000, /* R226 */
  306. 0x0000, /* R227 */
  307. 0x0000, /* R228 */
  308. 0x0000, /* R229 */
  309. 0x0000, /* R230 */
  310. 0x0000, /* R231 */
  311. 0x0000, /* R232 */
  312. 0x0000, /* R233 */
  313. 0x0000, /* R234 */
  314. 0x0000, /* R235 */
  315. 0x0000, /* R236 */
  316. 0x0000, /* R237 */
  317. 0x0000, /* R238 */
  318. 0x0000, /* R239 */
  319. 0x0000, /* R240 */
  320. 0x0000, /* R241 */
  321. 0x0000, /* R242 */
  322. 0x0000, /* R243 */
  323. 0x0000, /* R244 */
  324. 0x0000, /* R245 */
  325. 0x0000, /* R246 */
  326. 0x0000, /* R247 - FLL NCO Test 0 */
  327. 0x0019, /* R248 - FLL NCO Test 1 */
  328. };
  329. static struct {
  330. int readable;
  331. int writable;
  332. int vol;
  333. } wm8904_access[] = {
  334. { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */
  335. { 0x0000, 0x0000, 0 }, /* R1 - Revision */
  336. { 0x0000, 0x0000, 0 }, /* R2 */
  337. { 0x0000, 0x0000, 0 }, /* R3 */
  338. { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */
  339. { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */
  340. { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */
  341. { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */
  342. { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */
  343. { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */
  344. { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */
  345. { 0x0000, 0x0000, 0 }, /* R11 */
  346. { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */
  347. { 0x0000, 0x0000, 0 }, /* R13 */
  348. { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */
  349. { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */
  350. { 0x0000, 0x0000, 0 }, /* R16 */
  351. { 0x0000, 0x0000, 0 }, /* R17 */
  352. { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */
  353. { 0x0000, 0x0000, 0 }, /* R19 */
  354. { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */
  355. { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */
  356. { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */
  357. { 0x0000, 0x0000, 0 }, /* R23 */
  358. { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */
  359. { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */
  360. { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */
  361. { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */
  362. { 0x0000, 0x0000, 0 }, /* R28 */
  363. { 0x0000, 0x0000, 0 }, /* R29 */
  364. { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */
  365. { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */
  366. { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */
  367. { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */
  368. { 0x0000, 0x0000, 0 }, /* R34 */
  369. { 0x0000, 0x0000, 0 }, /* R35 */
  370. { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */
  371. { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */
  372. { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */
  373. { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */
  374. { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */
  375. { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */
  376. { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */
  377. { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */
  378. { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */
  379. { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */
  380. { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */
  381. { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */
  382. { 0x0000, 0x0000, 0 }, /* R48 */
  383. { 0x0000, 0x0000, 0 }, /* R49 */
  384. { 0x0000, 0x0000, 0 }, /* R50 */
  385. { 0x0000, 0x0000, 0 }, /* R51 */
  386. { 0x0000, 0x0000, 0 }, /* R52 */
  387. { 0x0000, 0x0000, 0 }, /* R53 */
  388. { 0x0000, 0x0000, 0 }, /* R54 */
  389. { 0x0000, 0x0000, 0 }, /* R55 */
  390. { 0x0000, 0x0000, 0 }, /* R56 */
  391. { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */
  392. { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */
  393. { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */
  394. { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */
  395. { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */
  396. { 0x0000, 0x0000, 0 }, /* R62 */
  397. { 0x0000, 0x0000, 0 }, /* R63 */
  398. { 0x0000, 0x0000, 0 }, /* R64 */
  399. { 0x0000, 0x0000, 0 }, /* R65 */
  400. { 0x0000, 0x0000, 0 }, /* R66 */
  401. { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */
  402. { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */
  403. { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */
  404. { 0x0000, 0x0000, 0 }, /* R70 */
  405. { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */
  406. { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */
  407. { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */
  408. { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */
  409. { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */
  410. { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */
  411. { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */
  412. { 0x0000, 0x0000, 0 }, /* R78 */
  413. { 0x0000, 0x0000, 0 }, /* R79 */
  414. { 0x0000, 0x0000, 0 }, /* R80 */
  415. { 0x0000, 0x0000, 0 }, /* R81 */
  416. { 0x0000, 0x0000, 0 }, /* R82 */
  417. { 0x0000, 0x0000, 0 }, /* R83 */
  418. { 0x0000, 0x0000, 0 }, /* R84 */
  419. { 0x0000, 0x0000, 0 }, /* R85 */
  420. { 0x0000, 0x0000, 0 }, /* R86 */
  421. { 0x0000, 0x0000, 0 }, /* R87 */
  422. { 0x0000, 0x0000, 0 }, /* R88 */
  423. { 0x0000, 0x0000, 0 }, /* R89 */
  424. { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */
  425. { 0x0000, 0x0000, 0 }, /* R91 */
  426. { 0x0000, 0x0000, 0 }, /* R92 */
  427. { 0x0000, 0x0000, 0 }, /* R93 */
  428. { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */
  429. { 0x0000, 0x0000, 0 }, /* R95 */
  430. { 0x0000, 0x0000, 0 }, /* R96 */
  431. { 0x0000, 0x0000, 0 }, /* R97 */
  432. { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */
  433. { 0x0000, 0x0000, 0 }, /* R99 */
  434. { 0x0000, 0x0000, 0 }, /* R100 */
  435. { 0x0000, 0x0000, 0 }, /* R101 */
  436. { 0x0000, 0x0000, 0 }, /* R102 */
  437. { 0x0000, 0x0000, 0 }, /* R103 */
  438. { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */
  439. { 0x0000, 0x0000, 0 }, /* R105 */
  440. { 0x0000, 0x0000, 0 }, /* R106 */
  441. { 0x0000, 0x0000, 0 }, /* R107 */
  442. { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */
  443. { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */
  444. { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */
  445. { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */
  446. { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */
  447. { 0x0000, 0x0000, 0 }, /* R113 */
  448. { 0x0000, 0x0000, 0 }, /* R114 */
  449. { 0x0000, 0x0000, 0 }, /* R115 */
  450. { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */
  451. { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */
  452. { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */
  453. { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */
  454. { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */
  455. { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */
  456. { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */
  457. { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */
  458. { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */
  459. { 0x0000, 0x0000, 0 }, /* R125 */
  460. { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */
  461. { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */
  462. { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */
  463. { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */
  464. { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */
  465. { 0x0000, 0x0000, 0 }, /* R131 */
  466. { 0x0000, 0x0000, 0 }, /* R132 */
  467. { 0x0000, 0x0000, 0 }, /* R133 */
  468. { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */
  469. { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */
  470. { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */
  471. { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */
  472. { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */
  473. { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */
  474. { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */
  475. { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */
  476. { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */
  477. { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */
  478. { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */
  479. { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */
  480. { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */
  481. { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */
  482. { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */
  483. { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */
  484. { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */
  485. { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */
  486. { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */
  487. { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */
  488. { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */
  489. { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */
  490. { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */
  491. { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */
  492. { 0x0000, 0x0000, 0 }, /* R158 */
  493. { 0x0000, 0x0000, 0 }, /* R159 */
  494. { 0x0000, 0x0000, 0 }, /* R160 */
  495. { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */
  496. { 0x0000, 0x0000, 0 }, /* R162 */
  497. { 0x0000, 0x0000, 0 }, /* R163 */
  498. { 0x0000, 0x0000, 0 }, /* R164 */
  499. { 0x0000, 0x0000, 0 }, /* R165 */
  500. { 0x0000, 0x0000, 0 }, /* R166 */
  501. { 0x0000, 0x0000, 0 }, /* R167 */
  502. { 0x0000, 0x0000, 0 }, /* R168 */
  503. { 0x0000, 0x0000, 0 }, /* R169 */
  504. { 0x0000, 0x0000, 0 }, /* R170 */
  505. { 0x0000, 0x0000, 0 }, /* R171 */
  506. { 0x0000, 0x0000, 0 }, /* R172 */
  507. { 0x0000, 0x0000, 0 }, /* R173 */
  508. { 0x0000, 0x0000, 0 }, /* R174 */
  509. { 0x0000, 0x0000, 0 }, /* R175 */
  510. { 0x0000, 0x0000, 0 }, /* R176 */
  511. { 0x0000, 0x0000, 0 }, /* R177 */
  512. { 0x0000, 0x0000, 0 }, /* R178 */
  513. { 0x0000, 0x0000, 0 }, /* R179 */
  514. { 0x0000, 0x0000, 0 }, /* R180 */
  515. { 0x0000, 0x0000, 0 }, /* R181 */
  516. { 0x0000, 0x0000, 0 }, /* R182 */
  517. { 0x0000, 0x0000, 0 }, /* R183 */
  518. { 0x0000, 0x0000, 0 }, /* R184 */
  519. { 0x0000, 0x0000, 0 }, /* R185 */
  520. { 0x0000, 0x0000, 0 }, /* R186 */
  521. { 0x0000, 0x0000, 0 }, /* R187 */
  522. { 0x0000, 0x0000, 0 }, /* R188 */
  523. { 0x0000, 0x0000, 0 }, /* R189 */
  524. { 0x0000, 0x0000, 0 }, /* R190 */
  525. { 0x0000, 0x0000, 0 }, /* R191 */
  526. { 0x0000, 0x0000, 0 }, /* R192 */
  527. { 0x0000, 0x0000, 0 }, /* R193 */
  528. { 0x0000, 0x0000, 0 }, /* R194 */
  529. { 0x0000, 0x0000, 0 }, /* R195 */
  530. { 0x0000, 0x0000, 0 }, /* R196 */
  531. { 0x0000, 0x0000, 0 }, /* R197 */
  532. { 0x0000, 0x0000, 0 }, /* R198 */
  533. { 0x0000, 0x0000, 0 }, /* R199 */
  534. { 0x0000, 0x0000, 0 }, /* R200 */
  535. { 0x0000, 0x0000, 0 }, /* R201 */
  536. { 0x0000, 0x0000, 0 }, /* R202 */
  537. { 0x0000, 0x0000, 0 }, /* R203 */
  538. { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */
  539. { 0x0000, 0x0000, 0 }, /* R205 */
  540. { 0x0000, 0x0000, 0 }, /* R206 */
  541. { 0x0000, 0x0000, 0 }, /* R207 */
  542. { 0x0000, 0x0000, 0 }, /* R208 */
  543. { 0x0000, 0x0000, 0 }, /* R209 */
  544. { 0x0000, 0x0000, 0 }, /* R210 */
  545. { 0x0000, 0x0000, 0 }, /* R211 */
  546. { 0x0000, 0x0000, 0 }, /* R212 */
  547. { 0x0000, 0x0000, 0 }, /* R213 */
  548. { 0x0000, 0x0000, 0 }, /* R214 */
  549. { 0x0000, 0x0000, 0 }, /* R215 */
  550. { 0x0000, 0x0000, 0 }, /* R216 */
  551. { 0x0000, 0x0000, 0 }, /* R217 */
  552. { 0x0000, 0x0000, 0 }, /* R218 */
  553. { 0x0000, 0x0000, 0 }, /* R219 */
  554. { 0x0000, 0x0000, 0 }, /* R220 */
  555. { 0x0000, 0x0000, 0 }, /* R221 */
  556. { 0x0000, 0x0000, 0 }, /* R222 */
  557. { 0x0000, 0x0000, 0 }, /* R223 */
  558. { 0x0000, 0x0000, 0 }, /* R224 */
  559. { 0x0000, 0x0000, 0 }, /* R225 */
  560. { 0x0000, 0x0000, 0 }, /* R226 */
  561. { 0x0000, 0x0000, 0 }, /* R227 */
  562. { 0x0000, 0x0000, 0 }, /* R228 */
  563. { 0x0000, 0x0000, 0 }, /* R229 */
  564. { 0x0000, 0x0000, 0 }, /* R230 */
  565. { 0x0000, 0x0000, 0 }, /* R231 */
  566. { 0x0000, 0x0000, 0 }, /* R232 */
  567. { 0x0000, 0x0000, 0 }, /* R233 */
  568. { 0x0000, 0x0000, 0 }, /* R234 */
  569. { 0x0000, 0x0000, 0 }, /* R235 */
  570. { 0x0000, 0x0000, 0 }, /* R236 */
  571. { 0x0000, 0x0000, 0 }, /* R237 */
  572. { 0x0000, 0x0000, 0 }, /* R238 */
  573. { 0x0000, 0x0000, 0 }, /* R239 */
  574. { 0x0000, 0x0000, 0 }, /* R240 */
  575. { 0x0000, 0x0000, 0 }, /* R241 */
  576. { 0x0000, 0x0000, 0 }, /* R242 */
  577. { 0x0000, 0x0000, 0 }, /* R243 */
  578. { 0x0000, 0x0000, 0 }, /* R244 */
  579. { 0x0000, 0x0000, 0 }, /* R245 */
  580. { 0x0000, 0x0000, 0 }, /* R246 */
  581. { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */
  582. { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
  583. };
  584. static int wm8904_volatile_register(unsigned int reg)
  585. {
  586. return wm8904_access[reg].vol;
  587. }
  588. static int wm8904_reset(struct snd_soc_codec *codec)
  589. {
  590. return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0);
  591. }
  592. static int wm8904_configure_clocking(struct snd_soc_codec *codec)
  593. {
  594. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  595. unsigned int clock0, clock2, rate;
  596. /* Gate the clock while we're updating to avoid misclocking */
  597. clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
  598. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  599. WM8904_SYSCLK_SRC, 0);
  600. /* This should be done on init() for bypass paths */
  601. switch (wm8904->sysclk_src) {
  602. case WM8904_CLK_MCLK:
  603. dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
  604. clock2 &= ~WM8904_SYSCLK_SRC;
  605. rate = wm8904->mclk_rate;
  606. /* Ensure the FLL is stopped */
  607. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  608. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  609. break;
  610. case WM8904_CLK_FLL:
  611. dev_dbg(codec->dev, "Using %dHz FLL clock\n",
  612. wm8904->fll_fout);
  613. clock2 |= WM8904_SYSCLK_SRC;
  614. rate = wm8904->fll_fout;
  615. break;
  616. default:
  617. dev_err(codec->dev, "System clock not configured\n");
  618. return -EINVAL;
  619. }
  620. /* SYSCLK shouldn't be over 13.5MHz */
  621. if (rate > 13500000) {
  622. clock0 = WM8904_MCLK_DIV;
  623. wm8904->sysclk_rate = rate / 2;
  624. } else {
  625. clock0 = 0;
  626. wm8904->sysclk_rate = rate;
  627. }
  628. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
  629. clock0);
  630. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  631. WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
  632. dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
  633. return 0;
  634. }
  635. static void wm8904_set_drc(struct snd_soc_codec *codec)
  636. {
  637. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  638. struct wm8904_pdata *pdata = wm8904->pdata;
  639. int save, i;
  640. /* Save any enables; the configuration should clear them. */
  641. save = snd_soc_read(codec, WM8904_DRC_0);
  642. for (i = 0; i < WM8904_DRC_REGS; i++)
  643. snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
  644. pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
  645. /* Reenable the DRC */
  646. snd_soc_update_bits(codec, WM8904_DRC_0,
  647. WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
  648. }
  649. static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
  650. struct snd_ctl_elem_value *ucontrol)
  651. {
  652. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  653. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  654. struct wm8904_pdata *pdata = wm8904->pdata;
  655. int value = ucontrol->value.integer.value[0];
  656. if (value >= pdata->num_drc_cfgs)
  657. return -EINVAL;
  658. wm8904->drc_cfg = value;
  659. wm8904_set_drc(codec);
  660. return 0;
  661. }
  662. static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
  663. struct snd_ctl_elem_value *ucontrol)
  664. {
  665. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  666. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  667. ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
  668. return 0;
  669. }
  670. static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
  671. {
  672. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  673. struct wm8904_pdata *pdata = wm8904->pdata;
  674. int best, best_val, save, i, cfg;
  675. if (!pdata || !wm8904->num_retune_mobile_texts)
  676. return;
  677. /* Find the version of the currently selected configuration
  678. * with the nearest sample rate. */
  679. cfg = wm8904->retune_mobile_cfg;
  680. best = 0;
  681. best_val = INT_MAX;
  682. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  683. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  684. wm8904->retune_mobile_texts[cfg]) == 0 &&
  685. abs(pdata->retune_mobile_cfgs[i].rate
  686. - wm8904->fs) < best_val) {
  687. best = i;
  688. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  689. - wm8904->fs);
  690. }
  691. }
  692. dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
  693. pdata->retune_mobile_cfgs[best].name,
  694. pdata->retune_mobile_cfgs[best].rate,
  695. wm8904->fs);
  696. /* The EQ will be disabled while reconfiguring it, remember the
  697. * current configuration.
  698. */
  699. save = snd_soc_read(codec, WM8904_EQ1);
  700. for (i = 0; i < WM8904_EQ_REGS; i++)
  701. snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
  702. pdata->retune_mobile_cfgs[best].regs[i]);
  703. snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
  704. }
  705. static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  706. struct snd_ctl_elem_value *ucontrol)
  707. {
  708. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  709. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  710. struct wm8904_pdata *pdata = wm8904->pdata;
  711. int value = ucontrol->value.integer.value[0];
  712. if (value >= pdata->num_retune_mobile_cfgs)
  713. return -EINVAL;
  714. wm8904->retune_mobile_cfg = value;
  715. wm8904_set_retune_mobile(codec);
  716. return 0;
  717. }
  718. static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  719. struct snd_ctl_elem_value *ucontrol)
  720. {
  721. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  722. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  723. ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
  724. return 0;
  725. }
  726. static int deemph_settings[] = { 0, 32000, 44100, 48000 };
  727. static int wm8904_set_deemph(struct snd_soc_codec *codec)
  728. {
  729. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  730. int val, i, best;
  731. /* If we're using deemphasis select the nearest available sample
  732. * rate.
  733. */
  734. if (wm8904->deemph) {
  735. best = 1;
  736. for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
  737. if (abs(deemph_settings[i] - wm8904->fs) <
  738. abs(deemph_settings[best] - wm8904->fs))
  739. best = i;
  740. }
  741. val = best << WM8904_DEEMPH_SHIFT;
  742. } else {
  743. val = 0;
  744. }
  745. dev_dbg(codec->dev, "Set deemphasis %d\n", val);
  746. return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
  747. WM8904_DEEMPH_MASK, val);
  748. }
  749. static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
  750. struct snd_ctl_elem_value *ucontrol)
  751. {
  752. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  753. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  754. return wm8904->deemph;
  755. }
  756. static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
  757. struct snd_ctl_elem_value *ucontrol)
  758. {
  759. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  760. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  761. int deemph = ucontrol->value.enumerated.item[0];
  762. if (deemph > 1)
  763. return -EINVAL;
  764. wm8904->deemph = deemph;
  765. return wm8904_set_deemph(codec);
  766. }
  767. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  768. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  769. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  770. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  771. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  772. static const char *input_mode_text[] = {
  773. "Single-Ended", "Differential Line", "Differential Mic"
  774. };
  775. static const struct soc_enum lin_mode =
  776. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
  777. static const struct soc_enum rin_mode =
  778. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
  779. static const char *hpf_mode_text[] = {
  780. "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
  781. };
  782. static const struct soc_enum hpf_mode =
  783. SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
  784. static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
  785. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
  786. WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
  787. SOC_ENUM("Left Caputure Mode", lin_mode),
  788. SOC_ENUM("Right Capture Mode", rin_mode),
  789. /* No TLV since it depends on mode */
  790. SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
  791. WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
  792. SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
  793. WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0),
  794. SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
  795. SOC_ENUM("High Pass Filter Mode", hpf_mode),
  796. SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0),
  797. };
  798. static const char *drc_path_text[] = {
  799. "ADC", "DAC"
  800. };
  801. static const struct soc_enum drc_path =
  802. SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
  803. static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
  804. SOC_SINGLE_TLV("Digital Playback Boost Volume",
  805. WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
  806. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
  807. WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
  808. SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
  809. WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
  810. SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
  811. WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
  812. SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
  813. WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
  814. SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
  815. WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
  816. SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
  817. WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
  818. SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
  819. WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
  820. SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
  821. SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
  822. SOC_ENUM("DRC Path", drc_path),
  823. SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
  824. SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
  825. wm8904_get_deemph, wm8904_put_deemph),
  826. };
  827. static const struct snd_kcontrol_new wm8904_snd_controls[] = {
  828. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
  829. sidetone_tlv),
  830. };
  831. static const struct snd_kcontrol_new wm8904_eq_controls[] = {
  832. SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
  833. SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
  834. SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
  835. SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
  836. SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
  837. };
  838. static int cp_event(struct snd_soc_dapm_widget *w,
  839. struct snd_kcontrol *kcontrol, int event)
  840. {
  841. BUG_ON(event != SND_SOC_DAPM_POST_PMU);
  842. /* Maximum startup time */
  843. udelay(500);
  844. return 0;
  845. }
  846. static int sysclk_event(struct snd_soc_dapm_widget *w,
  847. struct snd_kcontrol *kcontrol, int event)
  848. {
  849. struct snd_soc_codec *codec = w->codec;
  850. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  851. switch (event) {
  852. case SND_SOC_DAPM_PRE_PMU:
  853. /* If we're using the FLL then we only start it when
  854. * required; we assume that the configuration has been
  855. * done previously and all we need to do is kick it
  856. * off.
  857. */
  858. switch (wm8904->sysclk_src) {
  859. case WM8904_CLK_FLL:
  860. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  861. WM8904_FLL_OSC_ENA,
  862. WM8904_FLL_OSC_ENA);
  863. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  864. WM8904_FLL_ENA,
  865. WM8904_FLL_ENA);
  866. break;
  867. default:
  868. break;
  869. }
  870. break;
  871. case SND_SOC_DAPM_POST_PMD:
  872. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  873. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  874. break;
  875. }
  876. return 0;
  877. }
  878. static int out_pga_event(struct snd_soc_dapm_widget *w,
  879. struct snd_kcontrol *kcontrol, int event)
  880. {
  881. struct snd_soc_codec *codec = w->codec;
  882. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  883. int reg, val;
  884. int dcs_mask;
  885. int dcs_l, dcs_r;
  886. int dcs_l_reg, dcs_r_reg;
  887. int timeout;
  888. int pwr_reg;
  889. /* This code is shared between HP and LINEOUT; we do all our
  890. * power management in stereo pairs to avoid latency issues so
  891. * we reuse shift to identify which rather than strcmp() the
  892. * name. */
  893. reg = w->shift;
  894. switch (reg) {
  895. case WM8904_ANALOGUE_HP_0:
  896. pwr_reg = WM8904_POWER_MANAGEMENT_2;
  897. dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
  898. dcs_r_reg = WM8904_DC_SERVO_8;
  899. dcs_l_reg = WM8904_DC_SERVO_9;
  900. dcs_l = 0;
  901. dcs_r = 1;
  902. break;
  903. case WM8904_ANALOGUE_LINEOUT_0:
  904. pwr_reg = WM8904_POWER_MANAGEMENT_3;
  905. dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
  906. dcs_r_reg = WM8904_DC_SERVO_6;
  907. dcs_l_reg = WM8904_DC_SERVO_7;
  908. dcs_l = 2;
  909. dcs_r = 3;
  910. break;
  911. default:
  912. BUG();
  913. return -EINVAL;
  914. }
  915. switch (event) {
  916. case SND_SOC_DAPM_PRE_PMU:
  917. /* Power on the PGAs */
  918. snd_soc_update_bits(codec, pwr_reg,
  919. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  920. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
  921. /* Power on the amplifier */
  922. snd_soc_update_bits(codec, reg,
  923. WM8904_HPL_ENA | WM8904_HPR_ENA,
  924. WM8904_HPL_ENA | WM8904_HPR_ENA);
  925. /* Enable the first stage */
  926. snd_soc_update_bits(codec, reg,
  927. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
  928. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
  929. /* Power up the DC servo */
  930. snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
  931. dcs_mask, dcs_mask);
  932. /* Either calibrate the DC servo or restore cached state
  933. * if we have that.
  934. */
  935. if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
  936. dev_dbg(codec->dev, "Restoring DC servo state\n");
  937. snd_soc_write(codec, dcs_l_reg,
  938. wm8904->dcs_state[dcs_l]);
  939. snd_soc_write(codec, dcs_r_reg,
  940. wm8904->dcs_state[dcs_r]);
  941. snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
  942. timeout = 20;
  943. } else {
  944. dev_dbg(codec->dev, "Calibrating DC servo\n");
  945. snd_soc_write(codec, WM8904_DC_SERVO_1,
  946. dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
  947. timeout = 500;
  948. }
  949. /* Wait for DC servo to complete */
  950. dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
  951. do {
  952. val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
  953. if ((val & dcs_mask) == dcs_mask)
  954. break;
  955. msleep(1);
  956. } while (--timeout);
  957. if ((val & dcs_mask) != dcs_mask)
  958. dev_warn(codec->dev, "DC servo timed out\n");
  959. else
  960. dev_dbg(codec->dev, "DC servo ready\n");
  961. /* Enable the output stage */
  962. snd_soc_update_bits(codec, reg,
  963. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  964. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
  965. break;
  966. case SND_SOC_DAPM_POST_PMU:
  967. /* Unshort the output itself */
  968. snd_soc_update_bits(codec, reg,
  969. WM8904_HPL_RMV_SHORT |
  970. WM8904_HPR_RMV_SHORT,
  971. WM8904_HPL_RMV_SHORT |
  972. WM8904_HPR_RMV_SHORT);
  973. break;
  974. case SND_SOC_DAPM_PRE_PMD:
  975. /* Short the output */
  976. snd_soc_update_bits(codec, reg,
  977. WM8904_HPL_RMV_SHORT |
  978. WM8904_HPR_RMV_SHORT, 0);
  979. break;
  980. case SND_SOC_DAPM_POST_PMD:
  981. /* Cache the DC servo configuration; this will be
  982. * invalidated if we change the configuration. */
  983. wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
  984. wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
  985. snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
  986. dcs_mask, 0);
  987. /* Disable the amplifier input and output stages */
  988. snd_soc_update_bits(codec, reg,
  989. WM8904_HPL_ENA | WM8904_HPR_ENA |
  990. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
  991. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  992. 0);
  993. /* PGAs too */
  994. snd_soc_update_bits(codec, pwr_reg,
  995. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  996. 0);
  997. break;
  998. }
  999. return 0;
  1000. }
  1001. static const char *lin_text[] = {
  1002. "IN1L", "IN2L", "IN3L"
  1003. };
  1004. static const struct soc_enum lin_enum =
  1005. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
  1006. static const struct snd_kcontrol_new lin_mux =
  1007. SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
  1008. static const struct soc_enum lin_inv_enum =
  1009. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
  1010. static const struct snd_kcontrol_new lin_inv_mux =
  1011. SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
  1012. static const char *rin_text[] = {
  1013. "IN1R", "IN2R", "IN3R"
  1014. };
  1015. static const struct soc_enum rin_enum =
  1016. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
  1017. static const struct snd_kcontrol_new rin_mux =
  1018. SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
  1019. static const struct soc_enum rin_inv_enum =
  1020. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
  1021. static const struct snd_kcontrol_new rin_inv_mux =
  1022. SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
  1023. static const char *aif_text[] = {
  1024. "Left", "Right"
  1025. };
  1026. static const struct soc_enum aifoutl_enum =
  1027. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
  1028. static const struct snd_kcontrol_new aifoutl_mux =
  1029. SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
  1030. static const struct soc_enum aifoutr_enum =
  1031. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
  1032. static const struct snd_kcontrol_new aifoutr_mux =
  1033. SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
  1034. static const struct soc_enum aifinl_enum =
  1035. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
  1036. static const struct snd_kcontrol_new aifinl_mux =
  1037. SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
  1038. static const struct soc_enum aifinr_enum =
  1039. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
  1040. static const struct snd_kcontrol_new aifinr_mux =
  1041. SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
  1042. static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
  1043. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
  1044. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1045. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
  1046. SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
  1047. };
  1048. static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
  1049. SND_SOC_DAPM_INPUT("IN1L"),
  1050. SND_SOC_DAPM_INPUT("IN1R"),
  1051. SND_SOC_DAPM_INPUT("IN2L"),
  1052. SND_SOC_DAPM_INPUT("IN2R"),
  1053. SND_SOC_DAPM_INPUT("IN3L"),
  1054. SND_SOC_DAPM_INPUT("IN3R"),
  1055. SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0),
  1056. SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
  1057. SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  1058. &lin_inv_mux),
  1059. SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
  1060. SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  1061. &rin_inv_mux),
  1062. SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
  1063. NULL, 0),
  1064. SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
  1065. NULL, 0),
  1066. SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
  1067. SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
  1068. SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
  1069. SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
  1070. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  1071. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  1072. };
  1073. static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
  1074. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  1075. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  1076. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
  1077. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
  1078. SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
  1079. SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
  1080. SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
  1081. SND_SOC_DAPM_POST_PMU),
  1082. SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  1083. SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  1084. SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  1085. SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  1086. SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
  1087. 0, NULL, 0, out_pga_event,
  1088. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1089. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1090. SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
  1091. 0, NULL, 0, out_pga_event,
  1092. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1093. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1094. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  1095. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  1096. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  1097. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  1098. };
  1099. static const char *out_mux_text[] = {
  1100. "DAC", "Bypass"
  1101. };
  1102. static const struct soc_enum hpl_enum =
  1103. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
  1104. static const struct snd_kcontrol_new hpl_mux =
  1105. SOC_DAPM_ENUM("HPL Mux", hpl_enum);
  1106. static const struct soc_enum hpr_enum =
  1107. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
  1108. static const struct snd_kcontrol_new hpr_mux =
  1109. SOC_DAPM_ENUM("HPR Mux", hpr_enum);
  1110. static const struct soc_enum linel_enum =
  1111. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
  1112. static const struct snd_kcontrol_new linel_mux =
  1113. SOC_DAPM_ENUM("LINEL Mux", linel_enum);
  1114. static const struct soc_enum liner_enum =
  1115. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
  1116. static const struct snd_kcontrol_new liner_mux =
  1117. SOC_DAPM_ENUM("LINEL Mux", liner_enum);
  1118. static const char *sidetone_text[] = {
  1119. "None", "Left", "Right"
  1120. };
  1121. static const struct soc_enum dacl_sidetone_enum =
  1122. SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
  1123. static const struct snd_kcontrol_new dacl_sidetone_mux =
  1124. SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
  1125. static const struct soc_enum dacr_sidetone_enum =
  1126. SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
  1127. static const struct snd_kcontrol_new dacr_sidetone_mux =
  1128. SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
  1129. static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
  1130. SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
  1131. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  1132. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  1133. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
  1134. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
  1135. SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  1136. SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  1137. SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
  1138. SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
  1139. };
  1140. static const struct snd_soc_dapm_route core_intercon[] = {
  1141. { "CLK_DSP", NULL, "SYSCLK" },
  1142. { "TOCLK", NULL, "SYSCLK" },
  1143. };
  1144. static const struct snd_soc_dapm_route adc_intercon[] = {
  1145. { "Left Capture Mux", "IN1L", "IN1L" },
  1146. { "Left Capture Mux", "IN2L", "IN2L" },
  1147. { "Left Capture Mux", "IN3L", "IN3L" },
  1148. { "Left Capture Inverting Mux", "IN1L", "IN1L" },
  1149. { "Left Capture Inverting Mux", "IN2L", "IN2L" },
  1150. { "Left Capture Inverting Mux", "IN3L", "IN3L" },
  1151. { "Right Capture Mux", "IN1R", "IN1R" },
  1152. { "Right Capture Mux", "IN2R", "IN2R" },
  1153. { "Right Capture Mux", "IN3R", "IN3R" },
  1154. { "Right Capture Inverting Mux", "IN1R", "IN1R" },
  1155. { "Right Capture Inverting Mux", "IN2R", "IN2R" },
  1156. { "Right Capture Inverting Mux", "IN3R", "IN3R" },
  1157. { "Left Capture PGA", NULL, "Left Capture Mux" },
  1158. { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
  1159. { "Right Capture PGA", NULL, "Right Capture Mux" },
  1160. { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
  1161. { "AIFOUTL", "Left", "ADCL" },
  1162. { "AIFOUTL", "Right", "ADCR" },
  1163. { "AIFOUTR", "Left", "ADCL" },
  1164. { "AIFOUTR", "Right", "ADCR" },
  1165. { "ADCL", NULL, "CLK_DSP" },
  1166. { "ADCL", NULL, "Left Capture PGA" },
  1167. { "ADCR", NULL, "CLK_DSP" },
  1168. { "ADCR", NULL, "Right Capture PGA" },
  1169. };
  1170. static const struct snd_soc_dapm_route dac_intercon[] = {
  1171. { "DACL", "Right", "AIFINR" },
  1172. { "DACL", "Left", "AIFINL" },
  1173. { "DACL", NULL, "CLK_DSP" },
  1174. { "DACR", "Right", "AIFINR" },
  1175. { "DACR", "Left", "AIFINL" },
  1176. { "DACR", NULL, "CLK_DSP" },
  1177. { "Charge pump", NULL, "SYSCLK" },
  1178. { "Headphone Output", NULL, "HPL PGA" },
  1179. { "Headphone Output", NULL, "HPR PGA" },
  1180. { "Headphone Output", NULL, "Charge pump" },
  1181. { "Headphone Output", NULL, "TOCLK" },
  1182. { "Line Output", NULL, "LINEL PGA" },
  1183. { "Line Output", NULL, "LINER PGA" },
  1184. { "Line Output", NULL, "Charge pump" },
  1185. { "Line Output", NULL, "TOCLK" },
  1186. { "HPOUTL", NULL, "Headphone Output" },
  1187. { "HPOUTR", NULL, "Headphone Output" },
  1188. { "LINEOUTL", NULL, "Line Output" },
  1189. { "LINEOUTR", NULL, "Line Output" },
  1190. };
  1191. static const struct snd_soc_dapm_route wm8904_intercon[] = {
  1192. { "Left Sidetone", "Left", "ADCL" },
  1193. { "Left Sidetone", "Right", "ADCR" },
  1194. { "DACL", NULL, "Left Sidetone" },
  1195. { "Right Sidetone", "Left", "ADCL" },
  1196. { "Right Sidetone", "Right", "ADCR" },
  1197. { "DACR", NULL, "Right Sidetone" },
  1198. { "Left Bypass", NULL, "Class G" },
  1199. { "Left Bypass", NULL, "Left Capture PGA" },
  1200. { "Right Bypass", NULL, "Class G" },
  1201. { "Right Bypass", NULL, "Right Capture PGA" },
  1202. { "HPL Mux", "DAC", "DACL" },
  1203. { "HPL Mux", "Bypass", "Left Bypass" },
  1204. { "HPR Mux", "DAC", "DACR" },
  1205. { "HPR Mux", "Bypass", "Right Bypass" },
  1206. { "LINEL Mux", "DAC", "DACL" },
  1207. { "LINEL Mux", "Bypass", "Left Bypass" },
  1208. { "LINER Mux", "DAC", "DACR" },
  1209. { "LINER Mux", "Bypass", "Right Bypass" },
  1210. { "HPL PGA", NULL, "HPL Mux" },
  1211. { "HPR PGA", NULL, "HPR Mux" },
  1212. { "LINEL PGA", NULL, "LINEL Mux" },
  1213. { "LINER PGA", NULL, "LINER Mux" },
  1214. };
  1215. static const struct snd_soc_dapm_route wm8912_intercon[] = {
  1216. { "HPL PGA", NULL, "DACL" },
  1217. { "HPR PGA", NULL, "DACR" },
  1218. { "LINEL PGA", NULL, "DACL" },
  1219. { "LINER PGA", NULL, "DACR" },
  1220. };
  1221. static int wm8904_add_widgets(struct snd_soc_codec *codec)
  1222. {
  1223. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1224. snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets,
  1225. ARRAY_SIZE(wm8904_core_dapm_widgets));
  1226. snd_soc_dapm_add_routes(codec, core_intercon,
  1227. ARRAY_SIZE(core_intercon));
  1228. switch (wm8904->devtype) {
  1229. case WM8904:
  1230. snd_soc_add_controls(codec, wm8904_adc_snd_controls,
  1231. ARRAY_SIZE(wm8904_adc_snd_controls));
  1232. snd_soc_add_controls(codec, wm8904_dac_snd_controls,
  1233. ARRAY_SIZE(wm8904_dac_snd_controls));
  1234. snd_soc_add_controls(codec, wm8904_snd_controls,
  1235. ARRAY_SIZE(wm8904_snd_controls));
  1236. snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets,
  1237. ARRAY_SIZE(wm8904_adc_dapm_widgets));
  1238. snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
  1239. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  1240. snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets,
  1241. ARRAY_SIZE(wm8904_dapm_widgets));
  1242. snd_soc_dapm_add_routes(codec, core_intercon,
  1243. ARRAY_SIZE(core_intercon));
  1244. snd_soc_dapm_add_routes(codec, adc_intercon,
  1245. ARRAY_SIZE(adc_intercon));
  1246. snd_soc_dapm_add_routes(codec, dac_intercon,
  1247. ARRAY_SIZE(dac_intercon));
  1248. snd_soc_dapm_add_routes(codec, wm8904_intercon,
  1249. ARRAY_SIZE(wm8904_intercon));
  1250. break;
  1251. case WM8912:
  1252. snd_soc_add_controls(codec, wm8904_dac_snd_controls,
  1253. ARRAY_SIZE(wm8904_dac_snd_controls));
  1254. snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
  1255. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  1256. snd_soc_dapm_add_routes(codec, dac_intercon,
  1257. ARRAY_SIZE(dac_intercon));
  1258. snd_soc_dapm_add_routes(codec, wm8912_intercon,
  1259. ARRAY_SIZE(wm8912_intercon));
  1260. break;
  1261. }
  1262. snd_soc_dapm_new_widgets(codec);
  1263. return 0;
  1264. }
  1265. static struct {
  1266. int ratio;
  1267. unsigned int clk_sys_rate;
  1268. } clk_sys_rates[] = {
  1269. { 64, 0 },
  1270. { 128, 1 },
  1271. { 192, 2 },
  1272. { 256, 3 },
  1273. { 384, 4 },
  1274. { 512, 5 },
  1275. { 786, 6 },
  1276. { 1024, 7 },
  1277. { 1408, 8 },
  1278. { 1536, 9 },
  1279. };
  1280. static struct {
  1281. int rate;
  1282. int sample_rate;
  1283. } sample_rates[] = {
  1284. { 8000, 0 },
  1285. { 11025, 1 },
  1286. { 12000, 1 },
  1287. { 16000, 2 },
  1288. { 22050, 3 },
  1289. { 24000, 3 },
  1290. { 32000, 4 },
  1291. { 44100, 5 },
  1292. { 48000, 5 },
  1293. };
  1294. static struct {
  1295. int div; /* *10 due to .5s */
  1296. int bclk_div;
  1297. } bclk_divs[] = {
  1298. { 10, 0 },
  1299. { 15, 1 },
  1300. { 20, 2 },
  1301. { 30, 3 },
  1302. { 40, 4 },
  1303. { 50, 5 },
  1304. { 55, 6 },
  1305. { 60, 7 },
  1306. { 80, 8 },
  1307. { 100, 9 },
  1308. { 110, 10 },
  1309. { 120, 11 },
  1310. { 160, 12 },
  1311. { 200, 13 },
  1312. { 220, 14 },
  1313. { 240, 16 },
  1314. { 200, 17 },
  1315. { 320, 18 },
  1316. { 440, 19 },
  1317. { 480, 20 },
  1318. };
  1319. static int wm8904_hw_params(struct snd_pcm_substream *substream,
  1320. struct snd_pcm_hw_params *params,
  1321. struct snd_soc_dai *dai)
  1322. {
  1323. struct snd_soc_codec *codec = dai->codec;
  1324. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1325. int ret, i, best, best_val, cur_val;
  1326. unsigned int aif1 = 0;
  1327. unsigned int aif2 = 0;
  1328. unsigned int aif3 = 0;
  1329. unsigned int clock1 = 0;
  1330. unsigned int dac_digital1 = 0;
  1331. /* What BCLK do we need? */
  1332. wm8904->fs = params_rate(params);
  1333. if (wm8904->tdm_slots) {
  1334. dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
  1335. wm8904->tdm_slots, wm8904->tdm_width);
  1336. wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
  1337. wm8904->tdm_width, 2,
  1338. wm8904->tdm_slots);
  1339. } else {
  1340. wm8904->bclk = snd_soc_params_to_bclk(params);
  1341. }
  1342. switch (params_format(params)) {
  1343. case SNDRV_PCM_FORMAT_S16_LE:
  1344. break;
  1345. case SNDRV_PCM_FORMAT_S20_3LE:
  1346. aif1 |= 0x40;
  1347. break;
  1348. case SNDRV_PCM_FORMAT_S24_LE:
  1349. aif1 |= 0x80;
  1350. break;
  1351. case SNDRV_PCM_FORMAT_S32_LE:
  1352. aif1 |= 0xc0;
  1353. break;
  1354. default:
  1355. return -EINVAL;
  1356. }
  1357. dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
  1358. ret = wm8904_configure_clocking(codec);
  1359. if (ret != 0)
  1360. return ret;
  1361. /* Select nearest CLK_SYS_RATE */
  1362. best = 0;
  1363. best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
  1364. - wm8904->fs);
  1365. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  1366. cur_val = abs((wm8904->sysclk_rate /
  1367. clk_sys_rates[i].ratio) - wm8904->fs);;
  1368. if (cur_val < best_val) {
  1369. best = i;
  1370. best_val = cur_val;
  1371. }
  1372. }
  1373. dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
  1374. clk_sys_rates[best].ratio);
  1375. clock1 |= (clk_sys_rates[best].clk_sys_rate
  1376. << WM8904_CLK_SYS_RATE_SHIFT);
  1377. /* SAMPLE_RATE */
  1378. best = 0;
  1379. best_val = abs(wm8904->fs - sample_rates[0].rate);
  1380. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1381. /* Closest match */
  1382. cur_val = abs(wm8904->fs - sample_rates[i].rate);
  1383. if (cur_val < best_val) {
  1384. best = i;
  1385. best_val = cur_val;
  1386. }
  1387. }
  1388. dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
  1389. sample_rates[best].rate);
  1390. clock1 |= (sample_rates[best].sample_rate
  1391. << WM8904_SAMPLE_RATE_SHIFT);
  1392. /* Enable sloping stopband filter for low sample rates */
  1393. if (wm8904->fs <= 24000)
  1394. dac_digital1 |= WM8904_DAC_SB_FILT;
  1395. /* BCLK_DIV */
  1396. best = 0;
  1397. best_val = INT_MAX;
  1398. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1399. cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
  1400. - wm8904->bclk;
  1401. if (cur_val < 0) /* Table is sorted */
  1402. break;
  1403. if (cur_val < best_val) {
  1404. best = i;
  1405. best_val = cur_val;
  1406. }
  1407. }
  1408. wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
  1409. dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  1410. bclk_divs[best].div, wm8904->bclk);
  1411. aif2 |= bclk_divs[best].bclk_div;
  1412. /* LRCLK is a simple fraction of BCLK */
  1413. dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
  1414. aif3 |= wm8904->bclk / wm8904->fs;
  1415. /* Apply the settings */
  1416. snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
  1417. WM8904_DAC_SB_FILT, dac_digital1);
  1418. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1419. WM8904_AIF_WL_MASK, aif1);
  1420. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
  1421. WM8904_BCLK_DIV_MASK, aif2);
  1422. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
  1423. WM8904_LRCLK_RATE_MASK, aif3);
  1424. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
  1425. WM8904_SAMPLE_RATE_MASK |
  1426. WM8904_CLK_SYS_RATE_MASK, clock1);
  1427. /* Update filters for the new settings */
  1428. wm8904_set_retune_mobile(codec);
  1429. wm8904_set_deemph(codec);
  1430. return 0;
  1431. }
  1432. static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  1433. unsigned int freq, int dir)
  1434. {
  1435. struct snd_soc_codec *codec = dai->codec;
  1436. struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
  1437. switch (clk_id) {
  1438. case WM8904_CLK_MCLK:
  1439. priv->sysclk_src = clk_id;
  1440. priv->mclk_rate = freq;
  1441. break;
  1442. case WM8904_CLK_FLL:
  1443. priv->sysclk_src = clk_id;
  1444. break;
  1445. default:
  1446. return -EINVAL;
  1447. }
  1448. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  1449. wm8904_configure_clocking(codec);
  1450. return 0;
  1451. }
  1452. static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1453. {
  1454. struct snd_soc_codec *codec = dai->codec;
  1455. unsigned int aif1 = 0;
  1456. unsigned int aif3 = 0;
  1457. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1458. case SND_SOC_DAIFMT_CBS_CFS:
  1459. break;
  1460. case SND_SOC_DAIFMT_CBS_CFM:
  1461. aif3 |= WM8904_LRCLK_DIR;
  1462. break;
  1463. case SND_SOC_DAIFMT_CBM_CFS:
  1464. aif1 |= WM8904_BCLK_DIR;
  1465. break;
  1466. case SND_SOC_DAIFMT_CBM_CFM:
  1467. aif1 |= WM8904_BCLK_DIR;
  1468. aif3 |= WM8904_LRCLK_DIR;
  1469. break;
  1470. default:
  1471. return -EINVAL;
  1472. }
  1473. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1474. case SND_SOC_DAIFMT_DSP_B:
  1475. aif1 |= WM8904_AIF_LRCLK_INV;
  1476. case SND_SOC_DAIFMT_DSP_A:
  1477. aif1 |= 0x3;
  1478. break;
  1479. case SND_SOC_DAIFMT_I2S:
  1480. aif1 |= 0x2;
  1481. break;
  1482. case SND_SOC_DAIFMT_RIGHT_J:
  1483. break;
  1484. case SND_SOC_DAIFMT_LEFT_J:
  1485. aif1 |= 0x1;
  1486. break;
  1487. default:
  1488. return -EINVAL;
  1489. }
  1490. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1491. case SND_SOC_DAIFMT_DSP_A:
  1492. case SND_SOC_DAIFMT_DSP_B:
  1493. /* frame inversion not valid for DSP modes */
  1494. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1495. case SND_SOC_DAIFMT_NB_NF:
  1496. break;
  1497. case SND_SOC_DAIFMT_IB_NF:
  1498. aif1 |= WM8904_AIF_BCLK_INV;
  1499. break;
  1500. default:
  1501. return -EINVAL;
  1502. }
  1503. break;
  1504. case SND_SOC_DAIFMT_I2S:
  1505. case SND_SOC_DAIFMT_RIGHT_J:
  1506. case SND_SOC_DAIFMT_LEFT_J:
  1507. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1508. case SND_SOC_DAIFMT_NB_NF:
  1509. break;
  1510. case SND_SOC_DAIFMT_IB_IF:
  1511. aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
  1512. break;
  1513. case SND_SOC_DAIFMT_IB_NF:
  1514. aif1 |= WM8904_AIF_BCLK_INV;
  1515. break;
  1516. case SND_SOC_DAIFMT_NB_IF:
  1517. aif1 |= WM8904_AIF_LRCLK_INV;
  1518. break;
  1519. default:
  1520. return -EINVAL;
  1521. }
  1522. break;
  1523. default:
  1524. return -EINVAL;
  1525. }
  1526. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1527. WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
  1528. WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
  1529. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
  1530. WM8904_LRCLK_DIR, aif3);
  1531. return 0;
  1532. }
  1533. static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1534. unsigned int rx_mask, int slots, int slot_width)
  1535. {
  1536. struct snd_soc_codec *codec = dai->codec;
  1537. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1538. int aif1 = 0;
  1539. /* Don't need to validate anything if we're turning off TDM */
  1540. if (slots == 0)
  1541. goto out;
  1542. /* Note that we allow configurations we can't handle ourselves -
  1543. * for example, we can generate clocks for slots 2 and up even if
  1544. * we can't use those slots ourselves.
  1545. */
  1546. aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
  1547. switch (rx_mask) {
  1548. case 3:
  1549. break;
  1550. case 0xc:
  1551. aif1 |= WM8904_AIFADC_TDM_CHAN;
  1552. break;
  1553. default:
  1554. return -EINVAL;
  1555. }
  1556. switch (tx_mask) {
  1557. case 3:
  1558. break;
  1559. case 0xc:
  1560. aif1 |= WM8904_AIFDAC_TDM_CHAN;
  1561. break;
  1562. default:
  1563. return -EINVAL;
  1564. }
  1565. out:
  1566. wm8904->tdm_width = slot_width;
  1567. wm8904->tdm_slots = slots / 2;
  1568. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1569. WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
  1570. WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
  1571. return 0;
  1572. }
  1573. struct _fll_div {
  1574. u16 fll_fratio;
  1575. u16 fll_outdiv;
  1576. u16 fll_clk_ref_div;
  1577. u16 n;
  1578. u16 k;
  1579. };
  1580. /* The size in bits of the FLL divide multiplied by 10
  1581. * to allow rounding later */
  1582. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1583. static struct {
  1584. unsigned int min;
  1585. unsigned int max;
  1586. u16 fll_fratio;
  1587. int ratio;
  1588. } fll_fratios[] = {
  1589. { 0, 64000, 4, 16 },
  1590. { 64000, 128000, 3, 8 },
  1591. { 128000, 256000, 2, 4 },
  1592. { 256000, 1000000, 1, 2 },
  1593. { 1000000, 13500000, 0, 1 },
  1594. };
  1595. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1596. unsigned int Fout)
  1597. {
  1598. u64 Kpart;
  1599. unsigned int K, Ndiv, Nmod, target;
  1600. unsigned int div;
  1601. int i;
  1602. /* Fref must be <=13.5MHz */
  1603. div = 1;
  1604. fll_div->fll_clk_ref_div = 0;
  1605. while ((Fref / div) > 13500000) {
  1606. div *= 2;
  1607. fll_div->fll_clk_ref_div++;
  1608. if (div > 8) {
  1609. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1610. Fref);
  1611. return -EINVAL;
  1612. }
  1613. }
  1614. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  1615. /* Apply the division for our remaining calculations */
  1616. Fref /= div;
  1617. /* Fvco should be 90-100MHz; don't check the upper bound */
  1618. div = 4;
  1619. while (Fout * div < 90000000) {
  1620. div++;
  1621. if (div > 64) {
  1622. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1623. Fout);
  1624. return -EINVAL;
  1625. }
  1626. }
  1627. target = Fout * div;
  1628. fll_div->fll_outdiv = div - 1;
  1629. pr_debug("Fvco=%dHz\n", target);
  1630. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  1631. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1632. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1633. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1634. target /= fll_fratios[i].ratio;
  1635. break;
  1636. }
  1637. }
  1638. if (i == ARRAY_SIZE(fll_fratios)) {
  1639. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1640. return -EINVAL;
  1641. }
  1642. /* Now, calculate N.K */
  1643. Ndiv = target / Fref;
  1644. fll_div->n = Ndiv;
  1645. Nmod = target % Fref;
  1646. pr_debug("Nmod=%d\n", Nmod);
  1647. /* Calculate fractional part - scale up so we can round. */
  1648. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1649. do_div(Kpart, Fref);
  1650. K = Kpart & 0xFFFFFFFF;
  1651. if ((K % 10) >= 5)
  1652. K += 5;
  1653. /* Move down to proper range now rounding is done */
  1654. fll_div->k = K / 10;
  1655. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  1656. fll_div->n, fll_div->k,
  1657. fll_div->fll_fratio, fll_div->fll_outdiv,
  1658. fll_div->fll_clk_ref_div);
  1659. return 0;
  1660. }
  1661. static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1662. unsigned int Fref, unsigned int Fout)
  1663. {
  1664. struct snd_soc_codec *codec = dai->codec;
  1665. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1666. struct _fll_div fll_div;
  1667. int ret, val;
  1668. int clock2, fll1;
  1669. /* Any change? */
  1670. if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
  1671. Fout == wm8904->fll_fout)
  1672. return 0;
  1673. clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
  1674. if (Fout == 0) {
  1675. dev_dbg(codec->dev, "FLL disabled\n");
  1676. wm8904->fll_fref = 0;
  1677. wm8904->fll_fout = 0;
  1678. /* Gate SYSCLK to avoid glitches */
  1679. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1680. WM8904_CLK_SYS_ENA, 0);
  1681. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1682. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1683. goto out;
  1684. }
  1685. /* Validate the FLL ID */
  1686. switch (source) {
  1687. case WM8904_FLL_MCLK:
  1688. case WM8904_FLL_LRCLK:
  1689. case WM8904_FLL_BCLK:
  1690. ret = fll_factors(&fll_div, Fref, Fout);
  1691. if (ret != 0)
  1692. return ret;
  1693. break;
  1694. case WM8904_FLL_FREE_RUNNING:
  1695. dev_dbg(codec->dev, "Using free running FLL\n");
  1696. /* Force 12MHz and output/4 for now */
  1697. Fout = 12000000;
  1698. Fref = 12000000;
  1699. memset(&fll_div, 0, sizeof(fll_div));
  1700. fll_div.fll_outdiv = 3;
  1701. break;
  1702. default:
  1703. dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
  1704. return -EINVAL;
  1705. }
  1706. /* Save current state then disable the FLL and SYSCLK to avoid
  1707. * misclocking */
  1708. fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
  1709. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1710. WM8904_CLK_SYS_ENA, 0);
  1711. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1712. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1713. /* Unlock forced oscilator control to switch it on/off */
  1714. snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
  1715. WM8904_USER_KEY, WM8904_USER_KEY);
  1716. if (fll_id == WM8904_FLL_FREE_RUNNING) {
  1717. val = WM8904_FLL_FRC_NCO;
  1718. } else {
  1719. val = 0;
  1720. }
  1721. snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
  1722. val);
  1723. snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
  1724. WM8904_USER_KEY, 0);
  1725. switch (fll_id) {
  1726. case WM8904_FLL_MCLK:
  1727. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1728. WM8904_FLL_CLK_REF_SRC_MASK, 0);
  1729. break;
  1730. case WM8904_FLL_LRCLK:
  1731. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1732. WM8904_FLL_CLK_REF_SRC_MASK, 1);
  1733. break;
  1734. case WM8904_FLL_BCLK:
  1735. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1736. WM8904_FLL_CLK_REF_SRC_MASK, 2);
  1737. break;
  1738. }
  1739. if (fll_div.k)
  1740. val = WM8904_FLL_FRACN_ENA;
  1741. else
  1742. val = 0;
  1743. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1744. WM8904_FLL_FRACN_ENA, val);
  1745. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
  1746. WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
  1747. (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
  1748. (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
  1749. snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
  1750. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
  1751. fll_div.n << WM8904_FLL_N_SHIFT);
  1752. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1753. WM8904_FLL_CLK_REF_DIV_MASK,
  1754. fll_div.fll_clk_ref_div
  1755. << WM8904_FLL_CLK_REF_DIV_SHIFT);
  1756. dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1757. wm8904->fll_fref = Fref;
  1758. wm8904->fll_fout = Fout;
  1759. wm8904->fll_src = source;
  1760. /* Enable the FLL if it was previously active */
  1761. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1762. WM8904_FLL_OSC_ENA, fll1);
  1763. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1764. WM8904_FLL_ENA, fll1);
  1765. out:
  1766. /* Reenable SYSCLK if it was previously active */
  1767. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1768. WM8904_CLK_SYS_ENA, clock2);
  1769. return 0;
  1770. }
  1771. static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  1772. {
  1773. struct snd_soc_codec *codec = codec_dai->codec;
  1774. int val;
  1775. if (mute)
  1776. val = WM8904_DAC_MUTE;
  1777. else
  1778. val = 0;
  1779. snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
  1780. return 0;
  1781. }
  1782. static void wm8904_sync_cache(struct snd_soc_codec *codec)
  1783. {
  1784. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1785. int i;
  1786. if (!codec->cache_sync)
  1787. return;
  1788. codec->cache_only = 0;
  1789. /* Sync back cached values if they're different from the
  1790. * hardware default.
  1791. */
  1792. for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) {
  1793. if (!wm8904_access[i].writable)
  1794. continue;
  1795. if (wm8904->reg_cache[i] == wm8904_reg[i])
  1796. continue;
  1797. snd_soc_write(codec, i, wm8904->reg_cache[i]);
  1798. }
  1799. codec->cache_sync = 0;
  1800. }
  1801. static int wm8904_set_bias_level(struct snd_soc_codec *codec,
  1802. enum snd_soc_bias_level level)
  1803. {
  1804. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1805. int ret;
  1806. switch (level) {
  1807. case SND_SOC_BIAS_ON:
  1808. break;
  1809. case SND_SOC_BIAS_PREPARE:
  1810. /* VMID resistance 2*50k */
  1811. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1812. WM8904_VMID_RES_MASK,
  1813. 0x1 << WM8904_VMID_RES_SHIFT);
  1814. /* Normal bias current */
  1815. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1816. WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
  1817. break;
  1818. case SND_SOC_BIAS_STANDBY:
  1819. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  1820. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  1821. wm8904->supplies);
  1822. if (ret != 0) {
  1823. dev_err(codec->dev,
  1824. "Failed to enable supplies: %d\n",
  1825. ret);
  1826. return ret;
  1827. }
  1828. wm8904_sync_cache(codec);
  1829. /* Enable bias */
  1830. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1831. WM8904_BIAS_ENA, WM8904_BIAS_ENA);
  1832. /* Enable VMID, VMID buffering, 2*5k resistance */
  1833. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1834. WM8904_VMID_ENA |
  1835. WM8904_VMID_RES_MASK,
  1836. WM8904_VMID_ENA |
  1837. 0x3 << WM8904_VMID_RES_SHIFT);
  1838. /* Let VMID ramp */
  1839. msleep(1);
  1840. }
  1841. /* Maintain VMID with 2*250k */
  1842. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1843. WM8904_VMID_RES_MASK,
  1844. 0x2 << WM8904_VMID_RES_SHIFT);
  1845. /* Bias current *0.5 */
  1846. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1847. WM8904_ISEL_MASK, 0);
  1848. break;
  1849. case SND_SOC_BIAS_OFF:
  1850. /* Turn off VMID */
  1851. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1852. WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
  1853. /* Stop bias generation */
  1854. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1855. WM8904_BIAS_ENA, 0);
  1856. #ifdef CONFIG_REGULATOR
  1857. /* Post 2.6.34 we will be able to get a callback when
  1858. * the regulators are disabled which we can use but
  1859. * for now just assume that the power will be cut if
  1860. * the regulator API is in use.
  1861. */
  1862. codec->cache_sync = 1;
  1863. #endif
  1864. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
  1865. wm8904->supplies);
  1866. break;
  1867. }
  1868. codec->bias_level = level;
  1869. return 0;
  1870. }
  1871. #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
  1872. #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1873. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1874. static struct snd_soc_dai_ops wm8904_dai_ops = {
  1875. .set_sysclk = wm8904_set_sysclk,
  1876. .set_fmt = wm8904_set_fmt,
  1877. .set_tdm_slot = wm8904_set_tdm_slot,
  1878. .set_pll = wm8904_set_fll,
  1879. .hw_params = wm8904_hw_params,
  1880. .digital_mute = wm8904_digital_mute,
  1881. };
  1882. struct snd_soc_dai wm8904_dai = {
  1883. .name = "WM8904",
  1884. .playback = {
  1885. .stream_name = "Playback",
  1886. .channels_min = 2,
  1887. .channels_max = 2,
  1888. .rates = WM8904_RATES,
  1889. .formats = WM8904_FORMATS,
  1890. },
  1891. .capture = {
  1892. .stream_name = "Capture",
  1893. .channels_min = 2,
  1894. .channels_max = 2,
  1895. .rates = WM8904_RATES,
  1896. .formats = WM8904_FORMATS,
  1897. },
  1898. .ops = &wm8904_dai_ops,
  1899. .symmetric_rates = 1,
  1900. };
  1901. EXPORT_SYMBOL_GPL(wm8904_dai);
  1902. #ifdef CONFIG_PM
  1903. static int wm8904_suspend(struct platform_device *pdev, pm_message_t state)
  1904. {
  1905. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1906. struct snd_soc_codec *codec = socdev->card->codec;
  1907. wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1908. return 0;
  1909. }
  1910. static int wm8904_resume(struct platform_device *pdev)
  1911. {
  1912. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1913. struct snd_soc_codec *codec = socdev->card->codec;
  1914. wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1915. return 0;
  1916. }
  1917. #else
  1918. #define wm8904_suspend NULL
  1919. #define wm8904_resume NULL
  1920. #endif
  1921. static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904)
  1922. {
  1923. struct snd_soc_codec *codec = &wm8904->codec;
  1924. struct wm8904_pdata *pdata = wm8904->pdata;
  1925. struct snd_kcontrol_new control =
  1926. SOC_ENUM_EXT("EQ Mode",
  1927. wm8904->retune_mobile_enum,
  1928. wm8904_get_retune_mobile_enum,
  1929. wm8904_put_retune_mobile_enum);
  1930. int ret, i, j;
  1931. const char **t;
  1932. /* We need an array of texts for the enum API but the number
  1933. * of texts is likely to be less than the number of
  1934. * configurations due to the sample rate dependency of the
  1935. * configurations. */
  1936. wm8904->num_retune_mobile_texts = 0;
  1937. wm8904->retune_mobile_texts = NULL;
  1938. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  1939. for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
  1940. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  1941. wm8904->retune_mobile_texts[j]) == 0)
  1942. break;
  1943. }
  1944. if (j != wm8904->num_retune_mobile_texts)
  1945. continue;
  1946. /* Expand the array... */
  1947. t = krealloc(wm8904->retune_mobile_texts,
  1948. sizeof(char *) *
  1949. (wm8904->num_retune_mobile_texts + 1),
  1950. GFP_KERNEL);
  1951. if (t == NULL)
  1952. continue;
  1953. /* ...store the new entry... */
  1954. t[wm8904->num_retune_mobile_texts] =
  1955. pdata->retune_mobile_cfgs[i].name;
  1956. /* ...and remember the new version. */
  1957. wm8904->num_retune_mobile_texts++;
  1958. wm8904->retune_mobile_texts = t;
  1959. }
  1960. dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
  1961. wm8904->num_retune_mobile_texts);
  1962. wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
  1963. wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
  1964. ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
  1965. if (ret != 0)
  1966. dev_err(wm8904->codec.dev,
  1967. "Failed to add ReTune Mobile control: %d\n", ret);
  1968. }
  1969. static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
  1970. {
  1971. struct snd_soc_codec *codec = &wm8904->codec;
  1972. struct wm8904_pdata *pdata = wm8904->pdata;
  1973. int ret, i;
  1974. if (!pdata) {
  1975. snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
  1976. ARRAY_SIZE(wm8904_eq_controls));
  1977. return;
  1978. }
  1979. dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  1980. if (pdata->num_drc_cfgs) {
  1981. struct snd_kcontrol_new control =
  1982. SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
  1983. wm8904_get_drc_enum, wm8904_put_drc_enum);
  1984. /* We need an array of texts for the enum API */
  1985. wm8904->drc_texts = kmalloc(sizeof(char *)
  1986. * pdata->num_drc_cfgs, GFP_KERNEL);
  1987. if (!wm8904->drc_texts) {
  1988. dev_err(wm8904->codec.dev,
  1989. "Failed to allocate %d DRC config texts\n",
  1990. pdata->num_drc_cfgs);
  1991. return;
  1992. }
  1993. for (i = 0; i < pdata->num_drc_cfgs; i++)
  1994. wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
  1995. wm8904->drc_enum.max = pdata->num_drc_cfgs;
  1996. wm8904->drc_enum.texts = wm8904->drc_texts;
  1997. ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
  1998. if (ret != 0)
  1999. dev_err(wm8904->codec.dev,
  2000. "Failed to add DRC mode control: %d\n", ret);
  2001. wm8904_set_drc(codec);
  2002. }
  2003. dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
  2004. pdata->num_retune_mobile_cfgs);
  2005. if (pdata->num_retune_mobile_cfgs)
  2006. wm8904_handle_retune_mobile_pdata(wm8904);
  2007. else
  2008. snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
  2009. ARRAY_SIZE(wm8904_eq_controls));
  2010. }
  2011. static int wm8904_probe(struct platform_device *pdev)
  2012. {
  2013. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  2014. struct snd_soc_codec *codec;
  2015. int ret = 0;
  2016. if (wm8904_codec == NULL) {
  2017. dev_err(&pdev->dev, "Codec device not registered\n");
  2018. return -ENODEV;
  2019. }
  2020. socdev->card->codec = wm8904_codec;
  2021. codec = wm8904_codec;
  2022. /* register pcms */
  2023. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  2024. if (ret < 0) {
  2025. dev_err(codec->dev, "failed to create pcms: %d\n", ret);
  2026. goto pcm_err;
  2027. }
  2028. wm8904_handle_pdata(snd_soc_codec_get_drvdata(codec));
  2029. wm8904_add_widgets(codec);
  2030. return ret;
  2031. pcm_err:
  2032. return ret;
  2033. }
  2034. static int wm8904_remove(struct platform_device *pdev)
  2035. {
  2036. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  2037. snd_soc_free_pcms(socdev);
  2038. snd_soc_dapm_free(socdev);
  2039. return 0;
  2040. }
  2041. struct snd_soc_codec_device soc_codec_dev_wm8904 = {
  2042. .probe = wm8904_probe,
  2043. .remove = wm8904_remove,
  2044. .suspend = wm8904_suspend,
  2045. .resume = wm8904_resume,
  2046. };
  2047. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
  2048. static int wm8904_register(struct wm8904_priv *wm8904,
  2049. enum snd_soc_control_type control)
  2050. {
  2051. struct wm8904_pdata *pdata = wm8904->pdata;
  2052. int ret;
  2053. struct snd_soc_codec *codec = &wm8904->codec;
  2054. int i;
  2055. if (wm8904_codec) {
  2056. dev_err(codec->dev, "Another WM8904 is registered\n");
  2057. ret = -EINVAL;
  2058. goto err;
  2059. }
  2060. mutex_init(&codec->mutex);
  2061. INIT_LIST_HEAD(&codec->dapm_widgets);
  2062. INIT_LIST_HEAD(&codec->dapm_paths);
  2063. snd_soc_codec_set_drvdata(codec, wm8904);
  2064. codec->name = "WM8904";
  2065. codec->owner = THIS_MODULE;
  2066. codec->bias_level = SND_SOC_BIAS_OFF;
  2067. codec->set_bias_level = wm8904_set_bias_level;
  2068. codec->dai = &wm8904_dai;
  2069. codec->num_dai = 1;
  2070. codec->reg_cache_size = WM8904_MAX_REGISTER;
  2071. codec->reg_cache = &wm8904->reg_cache;
  2072. codec->volatile_register = wm8904_volatile_register;
  2073. codec->cache_sync = 1;
  2074. codec->idle_bias_off = 1;
  2075. switch (wm8904->devtype) {
  2076. case WM8904:
  2077. break;
  2078. case WM8912:
  2079. memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
  2080. break;
  2081. default:
  2082. dev_err(codec->dev, "Unknown device type %d\n",
  2083. wm8904->devtype);
  2084. ret = -EINVAL;
  2085. goto err;
  2086. }
  2087. memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg));
  2088. ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
  2089. if (ret != 0) {
  2090. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  2091. goto err;
  2092. }
  2093. for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
  2094. wm8904->supplies[i].supply = wm8904_supply_names[i];
  2095. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies),
  2096. wm8904->supplies);
  2097. if (ret != 0) {
  2098. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  2099. goto err;
  2100. }
  2101. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  2102. wm8904->supplies);
  2103. if (ret != 0) {
  2104. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  2105. goto err_get;
  2106. }
  2107. ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID);
  2108. if (ret < 0) {
  2109. dev_err(codec->dev, "Failed to read ID register\n");
  2110. goto err_enable;
  2111. }
  2112. if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) {
  2113. dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret);
  2114. ret = -EINVAL;
  2115. goto err_enable;
  2116. }
  2117. ret = snd_soc_read(codec, WM8904_REVISION);
  2118. if (ret < 0) {
  2119. dev_err(codec->dev, "Failed to read device revision: %d\n",
  2120. ret);
  2121. goto err_enable;
  2122. }
  2123. dev_info(codec->dev, "revision %c\n", ret + 'A');
  2124. ret = wm8904_reset(codec);
  2125. if (ret < 0) {
  2126. dev_err(codec->dev, "Failed to issue reset\n");
  2127. goto err_enable;
  2128. }
  2129. wm8904_dai.dev = codec->dev;
  2130. /* Change some default settings - latch VU and enable ZC */
  2131. wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
  2132. wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
  2133. wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
  2134. wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
  2135. wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
  2136. WM8904_HPOUTLZC;
  2137. wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
  2138. WM8904_HPOUTRZC;
  2139. wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
  2140. WM8904_LINEOUTLZC;
  2141. wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
  2142. WM8904_LINEOUTRZC;
  2143. wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
  2144. /* Apply configuration from the platform data. */
  2145. if (wm8904->pdata) {
  2146. for (i = 0; i < WM8904_GPIO_REGS; i++) {
  2147. if (!pdata->gpio_cfg[i])
  2148. continue;
  2149. wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i]
  2150. = pdata->gpio_cfg[i] & 0xffff;
  2151. }
  2152. /* Zero is the default value for these anyway */
  2153. for (i = 0; i < WM8904_MIC_REGS; i++)
  2154. wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i]
  2155. = pdata->mic_cfg[i];
  2156. }
  2157. /* Set Class W by default - this will be managed by the Class
  2158. * G widget at runtime where bypass paths are available.
  2159. */
  2160. wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
  2161. /* Use normal bias source */
  2162. wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
  2163. wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  2164. /* Bias level configuration will have done an extra enable */
  2165. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  2166. wm8904_codec = codec;
  2167. ret = snd_soc_register_codec(codec);
  2168. if (ret != 0) {
  2169. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2170. goto err_enable;
  2171. }
  2172. ret = snd_soc_register_dai(&wm8904_dai);
  2173. if (ret != 0) {
  2174. dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
  2175. goto err_codec;
  2176. }
  2177. return 0;
  2178. err_codec:
  2179. snd_soc_unregister_codec(codec);
  2180. err_enable:
  2181. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  2182. err_get:
  2183. regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  2184. err:
  2185. kfree(wm8904);
  2186. return ret;
  2187. }
  2188. static void wm8904_unregister(struct wm8904_priv *wm8904)
  2189. {
  2190. wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF);
  2191. regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  2192. snd_soc_unregister_dai(&wm8904_dai);
  2193. snd_soc_unregister_codec(&wm8904->codec);
  2194. kfree(wm8904);
  2195. wm8904_codec = NULL;
  2196. }
  2197. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  2198. static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
  2199. const struct i2c_device_id *id)
  2200. {
  2201. struct wm8904_priv *wm8904;
  2202. struct snd_soc_codec *codec;
  2203. wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL);
  2204. if (wm8904 == NULL)
  2205. return -ENOMEM;
  2206. codec = &wm8904->codec;
  2207. codec->hw_write = (hw_write_t)i2c_master_send;
  2208. wm8904->devtype = id->driver_data;
  2209. i2c_set_clientdata(i2c, wm8904);
  2210. codec->control_data = i2c;
  2211. wm8904->pdata = i2c->dev.platform_data;
  2212. codec->dev = &i2c->dev;
  2213. return wm8904_register(wm8904, SND_SOC_I2C);
  2214. }
  2215. static __devexit int wm8904_i2c_remove(struct i2c_client *client)
  2216. {
  2217. struct wm8904_priv *wm8904 = i2c_get_clientdata(client);
  2218. wm8904_unregister(wm8904);
  2219. return 0;
  2220. }
  2221. static const struct i2c_device_id wm8904_i2c_id[] = {
  2222. { "wm8904", WM8904 },
  2223. { "wm8912", WM8912 },
  2224. { }
  2225. };
  2226. MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
  2227. static struct i2c_driver wm8904_i2c_driver = {
  2228. .driver = {
  2229. .name = "WM8904",
  2230. .owner = THIS_MODULE,
  2231. },
  2232. .probe = wm8904_i2c_probe,
  2233. .remove = __devexit_p(wm8904_i2c_remove),
  2234. .id_table = wm8904_i2c_id,
  2235. };
  2236. #endif
  2237. static int __init wm8904_modinit(void)
  2238. {
  2239. int ret;
  2240. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  2241. ret = i2c_add_driver(&wm8904_i2c_driver);
  2242. if (ret != 0) {
  2243. printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n",
  2244. ret);
  2245. }
  2246. #endif
  2247. return 0;
  2248. }
  2249. module_init(wm8904_modinit);
  2250. static void __exit wm8904_exit(void)
  2251. {
  2252. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  2253. i2c_del_driver(&wm8904_i2c_driver);
  2254. #endif
  2255. }
  2256. module_exit(wm8904_exit);
  2257. MODULE_DESCRIPTION("ASoC WM8904 driver");
  2258. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  2259. MODULE_LICENSE("GPL");