wm8903.c 54 KB

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  1. /*
  2. * wm8903.c -- WM8903 ALSA SoC Audio driver
  3. *
  4. * Copyright 2008 Wolfson Microelectronics
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * TODO:
  13. * - TDM mode configuration.
  14. * - Digital microphone support.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/init.h>
  19. #include <linux/completion.h>
  20. #include <linux/delay.h>
  21. #include <linux/pm.h>
  22. #include <linux/i2c.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/slab.h>
  25. #include <sound/core.h>
  26. #include <sound/jack.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/tlv.h>
  30. #include <sound/soc.h>
  31. #include <sound/soc-dapm.h>
  32. #include <sound/initval.h>
  33. #include <sound/wm8903.h>
  34. #include "wm8903.h"
  35. /* Register defaults at reset */
  36. static u16 wm8903_reg_defaults[] = {
  37. 0x8903, /* R0 - SW Reset and ID */
  38. 0x0000, /* R1 - Revision Number */
  39. 0x0000, /* R2 */
  40. 0x0000, /* R3 */
  41. 0x0018, /* R4 - Bias Control 0 */
  42. 0x0000, /* R5 - VMID Control 0 */
  43. 0x0000, /* R6 - Mic Bias Control 0 */
  44. 0x0000, /* R7 */
  45. 0x0001, /* R8 - Analogue DAC 0 */
  46. 0x0000, /* R9 */
  47. 0x0001, /* R10 - Analogue ADC 0 */
  48. 0x0000, /* R11 */
  49. 0x0000, /* R12 - Power Management 0 */
  50. 0x0000, /* R13 - Power Management 1 */
  51. 0x0000, /* R14 - Power Management 2 */
  52. 0x0000, /* R15 - Power Management 3 */
  53. 0x0000, /* R16 - Power Management 4 */
  54. 0x0000, /* R17 - Power Management 5 */
  55. 0x0000, /* R18 - Power Management 6 */
  56. 0x0000, /* R19 */
  57. 0x0400, /* R20 - Clock Rates 0 */
  58. 0x0D07, /* R21 - Clock Rates 1 */
  59. 0x0000, /* R22 - Clock Rates 2 */
  60. 0x0000, /* R23 */
  61. 0x0050, /* R24 - Audio Interface 0 */
  62. 0x0242, /* R25 - Audio Interface 1 */
  63. 0x0008, /* R26 - Audio Interface 2 */
  64. 0x0022, /* R27 - Audio Interface 3 */
  65. 0x0000, /* R28 */
  66. 0x0000, /* R29 */
  67. 0x00C0, /* R30 - DAC Digital Volume Left */
  68. 0x00C0, /* R31 - DAC Digital Volume Right */
  69. 0x0000, /* R32 - DAC Digital 0 */
  70. 0x0000, /* R33 - DAC Digital 1 */
  71. 0x0000, /* R34 */
  72. 0x0000, /* R35 */
  73. 0x00C0, /* R36 - ADC Digital Volume Left */
  74. 0x00C0, /* R37 - ADC Digital Volume Right */
  75. 0x0000, /* R38 - ADC Digital 0 */
  76. 0x0073, /* R39 - Digital Microphone 0 */
  77. 0x09BF, /* R40 - DRC 0 */
  78. 0x3241, /* R41 - DRC 1 */
  79. 0x0020, /* R42 - DRC 2 */
  80. 0x0000, /* R43 - DRC 3 */
  81. 0x0085, /* R44 - Analogue Left Input 0 */
  82. 0x0085, /* R45 - Analogue Right Input 0 */
  83. 0x0044, /* R46 - Analogue Left Input 1 */
  84. 0x0044, /* R47 - Analogue Right Input 1 */
  85. 0x0000, /* R48 */
  86. 0x0000, /* R49 */
  87. 0x0008, /* R50 - Analogue Left Mix 0 */
  88. 0x0004, /* R51 - Analogue Right Mix 0 */
  89. 0x0000, /* R52 - Analogue Spk Mix Left 0 */
  90. 0x0000, /* R53 - Analogue Spk Mix Left 1 */
  91. 0x0000, /* R54 - Analogue Spk Mix Right 0 */
  92. 0x0000, /* R55 - Analogue Spk Mix Right 1 */
  93. 0x0000, /* R56 */
  94. 0x002D, /* R57 - Analogue OUT1 Left */
  95. 0x002D, /* R58 - Analogue OUT1 Right */
  96. 0x0039, /* R59 - Analogue OUT2 Left */
  97. 0x0039, /* R60 - Analogue OUT2 Right */
  98. 0x0100, /* R61 */
  99. 0x0139, /* R62 - Analogue OUT3 Left */
  100. 0x0139, /* R63 - Analogue OUT3 Right */
  101. 0x0000, /* R64 */
  102. 0x0000, /* R65 - Analogue SPK Output Control 0 */
  103. 0x0000, /* R66 */
  104. 0x0010, /* R67 - DC Servo 0 */
  105. 0x0100, /* R68 */
  106. 0x00A4, /* R69 - DC Servo 2 */
  107. 0x0807, /* R70 */
  108. 0x0000, /* R71 */
  109. 0x0000, /* R72 */
  110. 0x0000, /* R73 */
  111. 0x0000, /* R74 */
  112. 0x0000, /* R75 */
  113. 0x0000, /* R76 */
  114. 0x0000, /* R77 */
  115. 0x0000, /* R78 */
  116. 0x000E, /* R79 */
  117. 0x0000, /* R80 */
  118. 0x0000, /* R81 */
  119. 0x0000, /* R82 */
  120. 0x0000, /* R83 */
  121. 0x0000, /* R84 */
  122. 0x0000, /* R85 */
  123. 0x0000, /* R86 */
  124. 0x0006, /* R87 */
  125. 0x0000, /* R88 */
  126. 0x0000, /* R89 */
  127. 0x0000, /* R90 - Analogue HP 0 */
  128. 0x0060, /* R91 */
  129. 0x0000, /* R92 */
  130. 0x0000, /* R93 */
  131. 0x0000, /* R94 - Analogue Lineout 0 */
  132. 0x0060, /* R95 */
  133. 0x0000, /* R96 */
  134. 0x0000, /* R97 */
  135. 0x0000, /* R98 - Charge Pump 0 */
  136. 0x1F25, /* R99 */
  137. 0x2B19, /* R100 */
  138. 0x01C0, /* R101 */
  139. 0x01EF, /* R102 */
  140. 0x2B00, /* R103 */
  141. 0x0000, /* R104 - Class W 0 */
  142. 0x01C0, /* R105 */
  143. 0x1C10, /* R106 */
  144. 0x0000, /* R107 */
  145. 0x0000, /* R108 - Write Sequencer 0 */
  146. 0x0000, /* R109 - Write Sequencer 1 */
  147. 0x0000, /* R110 - Write Sequencer 2 */
  148. 0x0000, /* R111 - Write Sequencer 3 */
  149. 0x0000, /* R112 - Write Sequencer 4 */
  150. 0x0000, /* R113 */
  151. 0x0000, /* R114 - Control Interface */
  152. 0x0000, /* R115 */
  153. 0x00A8, /* R116 - GPIO Control 1 */
  154. 0x00A8, /* R117 - GPIO Control 2 */
  155. 0x00A8, /* R118 - GPIO Control 3 */
  156. 0x0220, /* R119 - GPIO Control 4 */
  157. 0x01A0, /* R120 - GPIO Control 5 */
  158. 0x0000, /* R121 - Interrupt Status 1 */
  159. 0xFFFF, /* R122 - Interrupt Status 1 Mask */
  160. 0x0000, /* R123 - Interrupt Polarity 1 */
  161. 0x0000, /* R124 */
  162. 0x0003, /* R125 */
  163. 0x0000, /* R126 - Interrupt Control */
  164. 0x0000, /* R127 */
  165. 0x0005, /* R128 */
  166. 0x0000, /* R129 - Control Interface Test 1 */
  167. 0x0000, /* R130 */
  168. 0x0000, /* R131 */
  169. 0x0000, /* R132 */
  170. 0x0000, /* R133 */
  171. 0x0000, /* R134 */
  172. 0x03FF, /* R135 */
  173. 0x0007, /* R136 */
  174. 0x0040, /* R137 */
  175. 0x0000, /* R138 */
  176. 0x0000, /* R139 */
  177. 0x0000, /* R140 */
  178. 0x0000, /* R141 */
  179. 0x0000, /* R142 */
  180. 0x0000, /* R143 */
  181. 0x0000, /* R144 */
  182. 0x0000, /* R145 */
  183. 0x0000, /* R146 */
  184. 0x0000, /* R147 */
  185. 0x4000, /* R148 */
  186. 0x6810, /* R149 - Charge Pump Test 1 */
  187. 0x0004, /* R150 */
  188. 0x0000, /* R151 */
  189. 0x0000, /* R152 */
  190. 0x0000, /* R153 */
  191. 0x0000, /* R154 */
  192. 0x0000, /* R155 */
  193. 0x0000, /* R156 */
  194. 0x0000, /* R157 */
  195. 0x0000, /* R158 */
  196. 0x0000, /* R159 */
  197. 0x0000, /* R160 */
  198. 0x0000, /* R161 */
  199. 0x0000, /* R162 */
  200. 0x0000, /* R163 */
  201. 0x0028, /* R164 - Clock Rate Test 4 */
  202. 0x0004, /* R165 */
  203. 0x0000, /* R166 */
  204. 0x0060, /* R167 */
  205. 0x0000, /* R168 */
  206. 0x0000, /* R169 */
  207. 0x0000, /* R170 */
  208. 0x0000, /* R171 */
  209. 0x0000, /* R172 - Analogue Output Bias 0 */
  210. };
  211. struct wm8903_priv {
  212. struct snd_soc_codec codec;
  213. u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
  214. int sysclk;
  215. /* Reference counts */
  216. int class_w_users;
  217. int playback_active;
  218. int capture_active;
  219. struct completion wseq;
  220. struct snd_soc_jack *mic_jack;
  221. int mic_det;
  222. int mic_short;
  223. int mic_last_report;
  224. int mic_delay;
  225. struct snd_pcm_substream *master_substream;
  226. struct snd_pcm_substream *slave_substream;
  227. };
  228. static int wm8903_volatile_register(unsigned int reg)
  229. {
  230. switch (reg) {
  231. case WM8903_SW_RESET_AND_ID:
  232. case WM8903_REVISION_NUMBER:
  233. case WM8903_INTERRUPT_STATUS_1:
  234. case WM8903_WRITE_SEQUENCER_4:
  235. return 1;
  236. default:
  237. return 0;
  238. }
  239. }
  240. static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
  241. {
  242. u16 reg[5];
  243. struct i2c_client *i2c = codec->control_data;
  244. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  245. BUG_ON(start > 48);
  246. /* Enable the sequencer if it's not already on */
  247. reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
  248. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
  249. reg[0] | WM8903_WSEQ_ENA);
  250. dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
  251. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
  252. start | WM8903_WSEQ_START);
  253. /* Wait for it to complete. If we have the interrupt wired up then
  254. * that will break us out of the poll early.
  255. */
  256. do {
  257. wait_for_completion_timeout(&wm8903->wseq,
  258. msecs_to_jiffies(10));
  259. reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
  260. } while (reg[4] & WM8903_WSEQ_BUSY);
  261. dev_dbg(&i2c->dev, "Sequence complete\n");
  262. /* Disable the sequencer again if we enabled it */
  263. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
  264. return 0;
  265. }
  266. static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
  267. {
  268. int i;
  269. /* There really ought to be something better we can do here :/ */
  270. for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
  271. cache[i] = codec->hw_read(codec, i);
  272. }
  273. static void wm8903_reset(struct snd_soc_codec *codec)
  274. {
  275. snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
  276. memcpy(codec->reg_cache, wm8903_reg_defaults,
  277. sizeof(wm8903_reg_defaults));
  278. }
  279. #define WM8903_OUTPUT_SHORT 0x8
  280. #define WM8903_OUTPUT_OUT 0x4
  281. #define WM8903_OUTPUT_INT 0x2
  282. #define WM8903_OUTPUT_IN 0x1
  283. static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
  284. struct snd_kcontrol *kcontrol, int event)
  285. {
  286. WARN_ON(event != SND_SOC_DAPM_POST_PMU);
  287. mdelay(4);
  288. return 0;
  289. }
  290. /*
  291. * Event for headphone and line out amplifier power changes. Special
  292. * power up/down sequences are required in order to maximise pop/click
  293. * performance.
  294. */
  295. static int wm8903_output_event(struct snd_soc_dapm_widget *w,
  296. struct snd_kcontrol *kcontrol, int event)
  297. {
  298. struct snd_soc_codec *codec = w->codec;
  299. u16 val;
  300. u16 reg;
  301. u16 dcs_reg;
  302. u16 dcs_bit;
  303. int shift;
  304. switch (w->reg) {
  305. case WM8903_POWER_MANAGEMENT_2:
  306. reg = WM8903_ANALOGUE_HP_0;
  307. dcs_bit = 0 + w->shift;
  308. break;
  309. case WM8903_POWER_MANAGEMENT_3:
  310. reg = WM8903_ANALOGUE_LINEOUT_0;
  311. dcs_bit = 2 + w->shift;
  312. break;
  313. default:
  314. BUG();
  315. return -EINVAL; /* Spurious warning from some compilers */
  316. }
  317. switch (w->shift) {
  318. case 0:
  319. shift = 0;
  320. break;
  321. case 1:
  322. shift = 4;
  323. break;
  324. default:
  325. BUG();
  326. return -EINVAL; /* Spurious warning from some compilers */
  327. }
  328. if (event & SND_SOC_DAPM_PRE_PMU) {
  329. val = snd_soc_read(codec, reg);
  330. /* Short the output */
  331. val &= ~(WM8903_OUTPUT_SHORT << shift);
  332. snd_soc_write(codec, reg, val);
  333. }
  334. if (event & SND_SOC_DAPM_POST_PMU) {
  335. val = snd_soc_read(codec, reg);
  336. val |= (WM8903_OUTPUT_IN << shift);
  337. snd_soc_write(codec, reg, val);
  338. val |= (WM8903_OUTPUT_INT << shift);
  339. snd_soc_write(codec, reg, val);
  340. /* Turn on the output ENA_OUTP */
  341. val |= (WM8903_OUTPUT_OUT << shift);
  342. snd_soc_write(codec, reg, val);
  343. /* Enable the DC servo */
  344. dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
  345. dcs_reg |= dcs_bit;
  346. snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
  347. /* Remove the short */
  348. val |= (WM8903_OUTPUT_SHORT << shift);
  349. snd_soc_write(codec, reg, val);
  350. }
  351. if (event & SND_SOC_DAPM_PRE_PMD) {
  352. val = snd_soc_read(codec, reg);
  353. /* Short the output */
  354. val &= ~(WM8903_OUTPUT_SHORT << shift);
  355. snd_soc_write(codec, reg, val);
  356. /* Disable the DC servo */
  357. dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
  358. dcs_reg &= ~dcs_bit;
  359. snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
  360. /* Then disable the intermediate and output stages */
  361. val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
  362. WM8903_OUTPUT_IN) << shift);
  363. snd_soc_write(codec, reg, val);
  364. }
  365. return 0;
  366. }
  367. /*
  368. * When used with DAC outputs only the WM8903 charge pump supports
  369. * operation in class W mode, providing very low power consumption
  370. * when used with digital sources. Enable and disable this mode
  371. * automatically depending on the mixer configuration.
  372. *
  373. * All the relevant controls are simple switches.
  374. */
  375. static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
  376. struct snd_ctl_elem_value *ucontrol)
  377. {
  378. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  379. struct snd_soc_codec *codec = widget->codec;
  380. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  381. struct i2c_client *i2c = codec->control_data;
  382. u16 reg;
  383. int ret;
  384. reg = snd_soc_read(codec, WM8903_CLASS_W_0);
  385. /* Turn it off if we're about to enable bypass */
  386. if (ucontrol->value.integer.value[0]) {
  387. if (wm8903->class_w_users == 0) {
  388. dev_dbg(&i2c->dev, "Disabling Class W\n");
  389. snd_soc_write(codec, WM8903_CLASS_W_0, reg &
  390. ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
  391. }
  392. wm8903->class_w_users++;
  393. }
  394. /* Implement the change */
  395. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  396. /* If we've just disabled the last bypass path turn Class W on */
  397. if (!ucontrol->value.integer.value[0]) {
  398. if (wm8903->class_w_users == 1) {
  399. dev_dbg(&i2c->dev, "Enabling Class W\n");
  400. snd_soc_write(codec, WM8903_CLASS_W_0, reg |
  401. WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
  402. }
  403. wm8903->class_w_users--;
  404. }
  405. dev_dbg(&i2c->dev, "Bypass use count now %d\n",
  406. wm8903->class_w_users);
  407. return ret;
  408. }
  409. #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
  410. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  411. .info = snd_soc_info_volsw, \
  412. .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
  413. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
  414. /* ALSA can only do steps of .01dB */
  415. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  416. static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
  417. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  418. static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
  419. static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
  420. static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
  421. static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
  422. static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
  423. static const char *drc_slope_text[] = {
  424. "1", "1/2", "1/4", "1/8", "1/16", "0"
  425. };
  426. static const struct soc_enum drc_slope_r0 =
  427. SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
  428. static const struct soc_enum drc_slope_r1 =
  429. SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
  430. static const char *drc_attack_text[] = {
  431. "instantaneous",
  432. "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
  433. "46.4ms", "92.8ms", "185.6ms"
  434. };
  435. static const struct soc_enum drc_attack =
  436. SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
  437. static const char *drc_decay_text[] = {
  438. "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
  439. "23.87s", "47.56s"
  440. };
  441. static const struct soc_enum drc_decay =
  442. SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
  443. static const char *drc_ff_delay_text[] = {
  444. "5 samples", "9 samples"
  445. };
  446. static const struct soc_enum drc_ff_delay =
  447. SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
  448. static const char *drc_qr_decay_text[] = {
  449. "0.725ms", "1.45ms", "5.8ms"
  450. };
  451. static const struct soc_enum drc_qr_decay =
  452. SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
  453. static const char *drc_smoothing_text[] = {
  454. "Low", "Medium", "High"
  455. };
  456. static const struct soc_enum drc_smoothing =
  457. SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
  458. static const char *soft_mute_text[] = {
  459. "Fast (fs/2)", "Slow (fs/32)"
  460. };
  461. static const struct soc_enum soft_mute =
  462. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
  463. static const char *mute_mode_text[] = {
  464. "Hard", "Soft"
  465. };
  466. static const struct soc_enum mute_mode =
  467. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
  468. static const char *dac_deemphasis_text[] = {
  469. "Disabled", "32kHz", "44.1kHz", "48kHz"
  470. };
  471. static const struct soc_enum dac_deemphasis =
  472. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
  473. static const char *companding_text[] = {
  474. "ulaw", "alaw"
  475. };
  476. static const struct soc_enum dac_companding =
  477. SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
  478. static const struct soc_enum adc_companding =
  479. SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
  480. static const char *input_mode_text[] = {
  481. "Single-Ended", "Differential Line", "Differential Mic"
  482. };
  483. static const struct soc_enum linput_mode_enum =
  484. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
  485. static const struct soc_enum rinput_mode_enum =
  486. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
  487. static const char *linput_mux_text[] = {
  488. "IN1L", "IN2L", "IN3L"
  489. };
  490. static const struct soc_enum linput_enum =
  491. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
  492. static const struct soc_enum linput_inv_enum =
  493. SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
  494. static const char *rinput_mux_text[] = {
  495. "IN1R", "IN2R", "IN3R"
  496. };
  497. static const struct soc_enum rinput_enum =
  498. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
  499. static const struct soc_enum rinput_inv_enum =
  500. SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
  501. static const char *sidetone_text[] = {
  502. "None", "Left", "Right"
  503. };
  504. static const struct soc_enum lsidetone_enum =
  505. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
  506. static const struct soc_enum rsidetone_enum =
  507. SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
  508. static const struct snd_kcontrol_new wm8903_snd_controls[] = {
  509. /* Input PGAs - No TLV since the scale depends on PGA mode */
  510. SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
  511. 7, 1, 1),
  512. SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
  513. 0, 31, 0),
  514. SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
  515. 6, 1, 0),
  516. SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
  517. 7, 1, 1),
  518. SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
  519. 0, 31, 0),
  520. SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
  521. 6, 1, 0),
  522. /* ADCs */
  523. SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
  524. SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
  525. SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
  526. SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
  527. drc_tlv_thresh),
  528. SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
  529. SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
  530. SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
  531. SOC_ENUM("DRC Attack Rate", drc_attack),
  532. SOC_ENUM("DRC Decay Rate", drc_decay),
  533. SOC_ENUM("DRC FF Delay", drc_ff_delay),
  534. SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
  535. SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
  536. SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
  537. SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
  538. SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
  539. SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
  540. SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
  541. SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
  542. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
  543. WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
  544. SOC_ENUM("ADC Companding Mode", adc_companding),
  545. SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
  546. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
  547. 12, 0, digital_sidetone_tlv),
  548. /* DAC */
  549. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
  550. WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
  551. SOC_ENUM("DAC Soft Mute Rate", soft_mute),
  552. SOC_ENUM("DAC Mute Mode", mute_mode),
  553. SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
  554. SOC_ENUM("DAC De-emphasis", dac_deemphasis),
  555. SOC_ENUM("DAC Companding Mode", dac_companding),
  556. SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
  557. /* Headphones */
  558. SOC_DOUBLE_R("Headphone Switch",
  559. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  560. 8, 1, 1),
  561. SOC_DOUBLE_R("Headphone ZC Switch",
  562. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  563. 6, 1, 0),
  564. SOC_DOUBLE_R_TLV("Headphone Volume",
  565. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  566. 0, 63, 0, out_tlv),
  567. /* Line out */
  568. SOC_DOUBLE_R("Line Out Switch",
  569. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  570. 8, 1, 1),
  571. SOC_DOUBLE_R("Line Out ZC Switch",
  572. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  573. 6, 1, 0),
  574. SOC_DOUBLE_R_TLV("Line Out Volume",
  575. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  576. 0, 63, 0, out_tlv),
  577. /* Speaker */
  578. SOC_DOUBLE_R("Speaker Switch",
  579. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
  580. SOC_DOUBLE_R("Speaker ZC Switch",
  581. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
  582. SOC_DOUBLE_R_TLV("Speaker Volume",
  583. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
  584. 0, 63, 0, out_tlv),
  585. };
  586. static const struct snd_kcontrol_new linput_mode_mux =
  587. SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
  588. static const struct snd_kcontrol_new rinput_mode_mux =
  589. SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
  590. static const struct snd_kcontrol_new linput_mux =
  591. SOC_DAPM_ENUM("Left Input Mux", linput_enum);
  592. static const struct snd_kcontrol_new linput_inv_mux =
  593. SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
  594. static const struct snd_kcontrol_new rinput_mux =
  595. SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
  596. static const struct snd_kcontrol_new rinput_inv_mux =
  597. SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
  598. static const struct snd_kcontrol_new lsidetone_mux =
  599. SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
  600. static const struct snd_kcontrol_new rsidetone_mux =
  601. SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
  602. static const struct snd_kcontrol_new left_output_mixer[] = {
  603. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
  604. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
  605. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
  606. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
  607. };
  608. static const struct snd_kcontrol_new right_output_mixer[] = {
  609. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
  610. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
  611. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
  612. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
  613. };
  614. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  615. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
  616. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
  617. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
  618. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
  619. 0, 1, 0),
  620. };
  621. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  622. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
  623. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
  624. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  625. 1, 1, 0),
  626. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  627. 0, 1, 0),
  628. };
  629. static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
  630. SND_SOC_DAPM_INPUT("IN1L"),
  631. SND_SOC_DAPM_INPUT("IN1R"),
  632. SND_SOC_DAPM_INPUT("IN2L"),
  633. SND_SOC_DAPM_INPUT("IN2R"),
  634. SND_SOC_DAPM_INPUT("IN3L"),
  635. SND_SOC_DAPM_INPUT("IN3R"),
  636. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  637. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  638. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  639. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  640. SND_SOC_DAPM_OUTPUT("LOP"),
  641. SND_SOC_DAPM_OUTPUT("LON"),
  642. SND_SOC_DAPM_OUTPUT("ROP"),
  643. SND_SOC_DAPM_OUTPUT("RON"),
  644. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
  645. SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
  646. SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  647. &linput_inv_mux),
  648. SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
  649. SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
  650. SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  651. &rinput_inv_mux),
  652. SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
  653. SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
  654. SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
  655. SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
  656. SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
  657. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
  658. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
  659. SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
  660. SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
  661. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
  662. left_output_mixer, ARRAY_SIZE(left_output_mixer)),
  663. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
  664. right_output_mixer, ARRAY_SIZE(right_output_mixer)),
  665. SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
  666. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  667. SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
  668. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  669. SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
  670. 1, 0, NULL, 0, wm8903_output_event,
  671. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  672. SND_SOC_DAPM_PRE_PMD),
  673. SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
  674. 0, 0, NULL, 0, wm8903_output_event,
  675. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  676. SND_SOC_DAPM_PRE_PMD),
  677. SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
  678. NULL, 0, wm8903_output_event,
  679. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  680. SND_SOC_DAPM_PRE_PMD),
  681. SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
  682. NULL, 0, wm8903_output_event,
  683. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  684. SND_SOC_DAPM_PRE_PMD),
  685. SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
  686. NULL, 0),
  687. SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
  688. NULL, 0),
  689. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
  690. wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
  691. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
  692. };
  693. static const struct snd_soc_dapm_route intercon[] = {
  694. { "Left Input Mux", "IN1L", "IN1L" },
  695. { "Left Input Mux", "IN2L", "IN2L" },
  696. { "Left Input Mux", "IN3L", "IN3L" },
  697. { "Left Input Inverting Mux", "IN1L", "IN1L" },
  698. { "Left Input Inverting Mux", "IN2L", "IN2L" },
  699. { "Left Input Inverting Mux", "IN3L", "IN3L" },
  700. { "Right Input Mux", "IN1R", "IN1R" },
  701. { "Right Input Mux", "IN2R", "IN2R" },
  702. { "Right Input Mux", "IN3R", "IN3R" },
  703. { "Right Input Inverting Mux", "IN1R", "IN1R" },
  704. { "Right Input Inverting Mux", "IN2R", "IN2R" },
  705. { "Right Input Inverting Mux", "IN3R", "IN3R" },
  706. { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
  707. { "Left Input Mode Mux", "Differential Line",
  708. "Left Input Mux" },
  709. { "Left Input Mode Mux", "Differential Line",
  710. "Left Input Inverting Mux" },
  711. { "Left Input Mode Mux", "Differential Mic",
  712. "Left Input Mux" },
  713. { "Left Input Mode Mux", "Differential Mic",
  714. "Left Input Inverting Mux" },
  715. { "Right Input Mode Mux", "Single-Ended",
  716. "Right Input Inverting Mux" },
  717. { "Right Input Mode Mux", "Differential Line",
  718. "Right Input Mux" },
  719. { "Right Input Mode Mux", "Differential Line",
  720. "Right Input Inverting Mux" },
  721. { "Right Input Mode Mux", "Differential Mic",
  722. "Right Input Mux" },
  723. { "Right Input Mode Mux", "Differential Mic",
  724. "Right Input Inverting Mux" },
  725. { "Left Input PGA", NULL, "Left Input Mode Mux" },
  726. { "Right Input PGA", NULL, "Right Input Mode Mux" },
  727. { "ADCL", NULL, "Left Input PGA" },
  728. { "ADCL", NULL, "CLK_DSP" },
  729. { "ADCR", NULL, "Right Input PGA" },
  730. { "ADCR", NULL, "CLK_DSP" },
  731. { "DACL Sidetone", "Left", "ADCL" },
  732. { "DACL Sidetone", "Right", "ADCR" },
  733. { "DACR Sidetone", "Left", "ADCL" },
  734. { "DACR Sidetone", "Right", "ADCR" },
  735. { "DACL", NULL, "DACL Sidetone" },
  736. { "DACL", NULL, "CLK_DSP" },
  737. { "DACR", NULL, "DACR Sidetone" },
  738. { "DACR", NULL, "CLK_DSP" },
  739. { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  740. { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  741. { "Left Output Mixer", "DACL Switch", "DACL" },
  742. { "Left Output Mixer", "DACR Switch", "DACR" },
  743. { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  744. { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  745. { "Right Output Mixer", "DACL Switch", "DACL" },
  746. { "Right Output Mixer", "DACR Switch", "DACR" },
  747. { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  748. { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  749. { "Left Speaker Mixer", "DACL Switch", "DACL" },
  750. { "Left Speaker Mixer", "DACR Switch", "DACR" },
  751. { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  752. { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  753. { "Right Speaker Mixer", "DACL Switch", "DACL" },
  754. { "Right Speaker Mixer", "DACR Switch", "DACR" },
  755. { "Left Line Output PGA", NULL, "Left Output Mixer" },
  756. { "Right Line Output PGA", NULL, "Right Output Mixer" },
  757. { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
  758. { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
  759. { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
  760. { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
  761. { "HPOUTL", NULL, "Left Headphone Output PGA" },
  762. { "HPOUTR", NULL, "Right Headphone Output PGA" },
  763. { "LINEOUTL", NULL, "Left Line Output PGA" },
  764. { "LINEOUTR", NULL, "Right Line Output PGA" },
  765. { "LOP", NULL, "Left Speaker PGA" },
  766. { "LON", NULL, "Left Speaker PGA" },
  767. { "ROP", NULL, "Right Speaker PGA" },
  768. { "RON", NULL, "Right Speaker PGA" },
  769. { "Left Headphone Output PGA", NULL, "Charge Pump" },
  770. { "Right Headphone Output PGA", NULL, "Charge Pump" },
  771. { "Left Line Output PGA", NULL, "Charge Pump" },
  772. { "Right Line Output PGA", NULL, "Charge Pump" },
  773. };
  774. static int wm8903_add_widgets(struct snd_soc_codec *codec)
  775. {
  776. snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
  777. ARRAY_SIZE(wm8903_dapm_widgets));
  778. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  779. return 0;
  780. }
  781. static int wm8903_set_bias_level(struct snd_soc_codec *codec,
  782. enum snd_soc_bias_level level)
  783. {
  784. struct i2c_client *i2c = codec->control_data;
  785. u16 reg, reg2;
  786. switch (level) {
  787. case SND_SOC_BIAS_ON:
  788. case SND_SOC_BIAS_PREPARE:
  789. reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
  790. reg &= ~(WM8903_VMID_RES_MASK);
  791. reg |= WM8903_VMID_RES_50K;
  792. snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
  793. break;
  794. case SND_SOC_BIAS_STANDBY:
  795. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  796. snd_soc_write(codec, WM8903_CLOCK_RATES_2,
  797. WM8903_CLK_SYS_ENA);
  798. /* Change DC servo dither level in startup sequence */
  799. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
  800. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
  801. snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
  802. wm8903_run_sequence(codec, 0);
  803. wm8903_sync_reg_cache(codec, codec->reg_cache);
  804. /* Enable low impedence charge pump output */
  805. reg = snd_soc_read(codec,
  806. WM8903_CONTROL_INTERFACE_TEST_1);
  807. snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
  808. reg | WM8903_TEST_KEY);
  809. reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
  810. snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
  811. reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
  812. snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
  813. reg);
  814. /* By default no bypass paths are enabled so
  815. * enable Class W support.
  816. */
  817. dev_dbg(&i2c->dev, "Enabling Class W\n");
  818. snd_soc_write(codec, WM8903_CLASS_W_0, reg |
  819. WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
  820. }
  821. reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
  822. reg &= ~(WM8903_VMID_RES_MASK);
  823. reg |= WM8903_VMID_RES_250K;
  824. snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
  825. break;
  826. case SND_SOC_BIAS_OFF:
  827. wm8903_run_sequence(codec, 32);
  828. reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
  829. reg &= ~WM8903_CLK_SYS_ENA;
  830. snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
  831. break;
  832. }
  833. codec->bias_level = level;
  834. return 0;
  835. }
  836. static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  837. int clk_id, unsigned int freq, int dir)
  838. {
  839. struct snd_soc_codec *codec = codec_dai->codec;
  840. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  841. wm8903->sysclk = freq;
  842. return 0;
  843. }
  844. static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
  845. unsigned int fmt)
  846. {
  847. struct snd_soc_codec *codec = codec_dai->codec;
  848. u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
  849. aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
  850. WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
  851. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  852. case SND_SOC_DAIFMT_CBS_CFS:
  853. break;
  854. case SND_SOC_DAIFMT_CBS_CFM:
  855. aif1 |= WM8903_LRCLK_DIR;
  856. break;
  857. case SND_SOC_DAIFMT_CBM_CFM:
  858. aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
  859. break;
  860. case SND_SOC_DAIFMT_CBM_CFS:
  861. aif1 |= WM8903_BCLK_DIR;
  862. break;
  863. default:
  864. return -EINVAL;
  865. }
  866. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  867. case SND_SOC_DAIFMT_DSP_A:
  868. aif1 |= 0x3;
  869. break;
  870. case SND_SOC_DAIFMT_DSP_B:
  871. aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
  872. break;
  873. case SND_SOC_DAIFMT_I2S:
  874. aif1 |= 0x2;
  875. break;
  876. case SND_SOC_DAIFMT_RIGHT_J:
  877. aif1 |= 0x1;
  878. break;
  879. case SND_SOC_DAIFMT_LEFT_J:
  880. break;
  881. default:
  882. return -EINVAL;
  883. }
  884. /* Clock inversion */
  885. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  886. case SND_SOC_DAIFMT_DSP_A:
  887. case SND_SOC_DAIFMT_DSP_B:
  888. /* frame inversion not valid for DSP modes */
  889. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  890. case SND_SOC_DAIFMT_NB_NF:
  891. break;
  892. case SND_SOC_DAIFMT_IB_NF:
  893. aif1 |= WM8903_AIF_BCLK_INV;
  894. break;
  895. default:
  896. return -EINVAL;
  897. }
  898. break;
  899. case SND_SOC_DAIFMT_I2S:
  900. case SND_SOC_DAIFMT_RIGHT_J:
  901. case SND_SOC_DAIFMT_LEFT_J:
  902. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  903. case SND_SOC_DAIFMT_NB_NF:
  904. break;
  905. case SND_SOC_DAIFMT_IB_IF:
  906. aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
  907. break;
  908. case SND_SOC_DAIFMT_IB_NF:
  909. aif1 |= WM8903_AIF_BCLK_INV;
  910. break;
  911. case SND_SOC_DAIFMT_NB_IF:
  912. aif1 |= WM8903_AIF_LRCLK_INV;
  913. break;
  914. default:
  915. return -EINVAL;
  916. }
  917. break;
  918. default:
  919. return -EINVAL;
  920. }
  921. snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
  922. return 0;
  923. }
  924. static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  925. {
  926. struct snd_soc_codec *codec = codec_dai->codec;
  927. u16 reg;
  928. reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
  929. if (mute)
  930. reg |= WM8903_DAC_MUTE;
  931. else
  932. reg &= ~WM8903_DAC_MUTE;
  933. snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
  934. return 0;
  935. }
  936. /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
  937. * for optimal performance so we list the lower rates first and match
  938. * on the last match we find. */
  939. static struct {
  940. int div;
  941. int rate;
  942. int mode;
  943. int mclk_div;
  944. } clk_sys_ratios[] = {
  945. { 64, 0x0, 0x0, 1 },
  946. { 68, 0x0, 0x1, 1 },
  947. { 125, 0x0, 0x2, 1 },
  948. { 128, 0x1, 0x0, 1 },
  949. { 136, 0x1, 0x1, 1 },
  950. { 192, 0x2, 0x0, 1 },
  951. { 204, 0x2, 0x1, 1 },
  952. { 64, 0x0, 0x0, 2 },
  953. { 68, 0x0, 0x1, 2 },
  954. { 125, 0x0, 0x2, 2 },
  955. { 128, 0x1, 0x0, 2 },
  956. { 136, 0x1, 0x1, 2 },
  957. { 192, 0x2, 0x0, 2 },
  958. { 204, 0x2, 0x1, 2 },
  959. { 250, 0x2, 0x2, 1 },
  960. { 256, 0x3, 0x0, 1 },
  961. { 272, 0x3, 0x1, 1 },
  962. { 384, 0x4, 0x0, 1 },
  963. { 408, 0x4, 0x1, 1 },
  964. { 375, 0x4, 0x2, 1 },
  965. { 512, 0x5, 0x0, 1 },
  966. { 544, 0x5, 0x1, 1 },
  967. { 500, 0x5, 0x2, 1 },
  968. { 768, 0x6, 0x0, 1 },
  969. { 816, 0x6, 0x1, 1 },
  970. { 750, 0x6, 0x2, 1 },
  971. { 1024, 0x7, 0x0, 1 },
  972. { 1088, 0x7, 0x1, 1 },
  973. { 1000, 0x7, 0x2, 1 },
  974. { 1408, 0x8, 0x0, 1 },
  975. { 1496, 0x8, 0x1, 1 },
  976. { 1536, 0x9, 0x0, 1 },
  977. { 1632, 0x9, 0x1, 1 },
  978. { 1500, 0x9, 0x2, 1 },
  979. { 250, 0x2, 0x2, 2 },
  980. { 256, 0x3, 0x0, 2 },
  981. { 272, 0x3, 0x1, 2 },
  982. { 384, 0x4, 0x0, 2 },
  983. { 408, 0x4, 0x1, 2 },
  984. { 375, 0x4, 0x2, 2 },
  985. { 512, 0x5, 0x0, 2 },
  986. { 544, 0x5, 0x1, 2 },
  987. { 500, 0x5, 0x2, 2 },
  988. { 768, 0x6, 0x0, 2 },
  989. { 816, 0x6, 0x1, 2 },
  990. { 750, 0x6, 0x2, 2 },
  991. { 1024, 0x7, 0x0, 2 },
  992. { 1088, 0x7, 0x1, 2 },
  993. { 1000, 0x7, 0x2, 2 },
  994. { 1408, 0x8, 0x0, 2 },
  995. { 1496, 0x8, 0x1, 2 },
  996. { 1536, 0x9, 0x0, 2 },
  997. { 1632, 0x9, 0x1, 2 },
  998. { 1500, 0x9, 0x2, 2 },
  999. };
  1000. /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
  1001. static struct {
  1002. int ratio;
  1003. int div;
  1004. } bclk_divs[] = {
  1005. { 10, 0 },
  1006. { 20, 2 },
  1007. { 30, 3 },
  1008. { 40, 4 },
  1009. { 50, 5 },
  1010. { 60, 7 },
  1011. { 80, 8 },
  1012. { 100, 9 },
  1013. { 120, 11 },
  1014. { 160, 12 },
  1015. { 200, 13 },
  1016. { 220, 14 },
  1017. { 240, 15 },
  1018. { 300, 17 },
  1019. { 320, 18 },
  1020. { 440, 19 },
  1021. { 480, 20 },
  1022. };
  1023. /* Sample rates for DSP */
  1024. static struct {
  1025. int rate;
  1026. int value;
  1027. } sample_rates[] = {
  1028. { 8000, 0 },
  1029. { 11025, 1 },
  1030. { 12000, 2 },
  1031. { 16000, 3 },
  1032. { 22050, 4 },
  1033. { 24000, 5 },
  1034. { 32000, 6 },
  1035. { 44100, 7 },
  1036. { 48000, 8 },
  1037. { 88200, 9 },
  1038. { 96000, 10 },
  1039. { 0, 0 },
  1040. };
  1041. static int wm8903_startup(struct snd_pcm_substream *substream,
  1042. struct snd_soc_dai *dai)
  1043. {
  1044. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1045. struct snd_soc_device *socdev = rtd->socdev;
  1046. struct snd_soc_codec *codec = socdev->card->codec;
  1047. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  1048. struct i2c_client *i2c = codec->control_data;
  1049. struct snd_pcm_runtime *master_runtime;
  1050. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1051. wm8903->playback_active++;
  1052. else
  1053. wm8903->capture_active++;
  1054. /* The DAI has shared clocks so if we already have a playback or
  1055. * capture going then constrain this substream to match it.
  1056. */
  1057. if (wm8903->master_substream) {
  1058. master_runtime = wm8903->master_substream->runtime;
  1059. dev_dbg(&i2c->dev, "Constraining to %d bits\n",
  1060. master_runtime->sample_bits);
  1061. snd_pcm_hw_constraint_minmax(substream->runtime,
  1062. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1063. master_runtime->sample_bits,
  1064. master_runtime->sample_bits);
  1065. wm8903->slave_substream = substream;
  1066. } else
  1067. wm8903->master_substream = substream;
  1068. return 0;
  1069. }
  1070. static void wm8903_shutdown(struct snd_pcm_substream *substream,
  1071. struct snd_soc_dai *dai)
  1072. {
  1073. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1074. struct snd_soc_device *socdev = rtd->socdev;
  1075. struct snd_soc_codec *codec = socdev->card->codec;
  1076. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  1077. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1078. wm8903->playback_active--;
  1079. else
  1080. wm8903->capture_active--;
  1081. if (wm8903->master_substream == substream)
  1082. wm8903->master_substream = wm8903->slave_substream;
  1083. wm8903->slave_substream = NULL;
  1084. }
  1085. static int wm8903_hw_params(struct snd_pcm_substream *substream,
  1086. struct snd_pcm_hw_params *params,
  1087. struct snd_soc_dai *dai)
  1088. {
  1089. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1090. struct snd_soc_device *socdev = rtd->socdev;
  1091. struct snd_soc_codec *codec = socdev->card->codec;
  1092. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  1093. struct i2c_client *i2c = codec->control_data;
  1094. int fs = params_rate(params);
  1095. int bclk;
  1096. int bclk_div;
  1097. int i;
  1098. int dsp_config;
  1099. int clk_config;
  1100. int best_val;
  1101. int cur_val;
  1102. int clk_sys;
  1103. u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
  1104. u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
  1105. u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
  1106. u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
  1107. u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
  1108. u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
  1109. if (substream == wm8903->slave_substream) {
  1110. dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
  1111. return 0;
  1112. }
  1113. /* Enable sloping stopband filter for low sample rates */
  1114. if (fs <= 24000)
  1115. dac_digital1 |= WM8903_DAC_SB_FILT;
  1116. else
  1117. dac_digital1 &= ~WM8903_DAC_SB_FILT;
  1118. /* Configure sample rate logic for DSP - choose nearest rate */
  1119. dsp_config = 0;
  1120. best_val = abs(sample_rates[dsp_config].rate - fs);
  1121. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1122. cur_val = abs(sample_rates[i].rate - fs);
  1123. if (cur_val <= best_val) {
  1124. dsp_config = i;
  1125. best_val = cur_val;
  1126. }
  1127. }
  1128. /* Constraints should stop us hitting this but let's make sure */
  1129. if (wm8903->capture_active)
  1130. switch (sample_rates[dsp_config].rate) {
  1131. case 88200:
  1132. case 96000:
  1133. dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
  1134. fs);
  1135. return -EINVAL;
  1136. default:
  1137. break;
  1138. }
  1139. dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
  1140. clock1 &= ~WM8903_SAMPLE_RATE_MASK;
  1141. clock1 |= sample_rates[dsp_config].value;
  1142. aif1 &= ~WM8903_AIF_WL_MASK;
  1143. bclk = 2 * fs;
  1144. switch (params_format(params)) {
  1145. case SNDRV_PCM_FORMAT_S16_LE:
  1146. bclk *= 16;
  1147. break;
  1148. case SNDRV_PCM_FORMAT_S20_3LE:
  1149. bclk *= 20;
  1150. aif1 |= 0x4;
  1151. break;
  1152. case SNDRV_PCM_FORMAT_S24_LE:
  1153. bclk *= 24;
  1154. aif1 |= 0x8;
  1155. break;
  1156. case SNDRV_PCM_FORMAT_S32_LE:
  1157. bclk *= 32;
  1158. aif1 |= 0xc;
  1159. break;
  1160. default:
  1161. return -EINVAL;
  1162. }
  1163. dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
  1164. wm8903->sysclk, fs);
  1165. /* We may not have an MCLK which allows us to generate exactly
  1166. * the clock we want, particularly with USB derived inputs, so
  1167. * approximate.
  1168. */
  1169. clk_config = 0;
  1170. best_val = abs((wm8903->sysclk /
  1171. (clk_sys_ratios[0].mclk_div *
  1172. clk_sys_ratios[0].div)) - fs);
  1173. for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
  1174. cur_val = abs((wm8903->sysclk /
  1175. (clk_sys_ratios[i].mclk_div *
  1176. clk_sys_ratios[i].div)) - fs);
  1177. if (cur_val <= best_val) {
  1178. clk_config = i;
  1179. best_val = cur_val;
  1180. }
  1181. }
  1182. if (clk_sys_ratios[clk_config].mclk_div == 2) {
  1183. clock0 |= WM8903_MCLKDIV2;
  1184. clk_sys = wm8903->sysclk / 2;
  1185. } else {
  1186. clock0 &= ~WM8903_MCLKDIV2;
  1187. clk_sys = wm8903->sysclk;
  1188. }
  1189. clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
  1190. WM8903_CLK_SYS_MODE_MASK);
  1191. clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
  1192. clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
  1193. dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
  1194. clk_sys_ratios[clk_config].rate,
  1195. clk_sys_ratios[clk_config].mode,
  1196. clk_sys_ratios[clk_config].div);
  1197. dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
  1198. /* We may not get quite the right frequency if using
  1199. * approximate clocks so look for the closest match that is
  1200. * higher than the target (we need to ensure that there enough
  1201. * BCLKs to clock out the samples).
  1202. */
  1203. bclk_div = 0;
  1204. best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
  1205. i = 1;
  1206. while (i < ARRAY_SIZE(bclk_divs)) {
  1207. cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
  1208. if (cur_val < 0) /* BCLK table is sorted */
  1209. break;
  1210. bclk_div = i;
  1211. best_val = cur_val;
  1212. i++;
  1213. }
  1214. aif2 &= ~WM8903_BCLK_DIV_MASK;
  1215. aif3 &= ~WM8903_LRCLK_RATE_MASK;
  1216. dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
  1217. bclk_divs[bclk_div].ratio / 10, bclk,
  1218. (clk_sys * 10) / bclk_divs[bclk_div].ratio);
  1219. aif2 |= bclk_divs[bclk_div].div;
  1220. aif3 |= bclk / fs;
  1221. snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
  1222. snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
  1223. snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
  1224. snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
  1225. snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
  1226. snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
  1227. return 0;
  1228. }
  1229. /**
  1230. * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
  1231. *
  1232. * @codec: WM8903 codec
  1233. * @jack: jack to report detection events on
  1234. * @det: value to report for presence detection
  1235. * @shrt: value to report for short detection
  1236. *
  1237. * Enable microphone detection via IRQ on the WM8903. If GPIOs are
  1238. * being used to bring out signals to the processor then only platform
  1239. * data configuration is needed for WM8903 and processor GPIOs should
  1240. * be configured using snd_soc_jack_add_gpios() instead.
  1241. *
  1242. * The current threasholds for detection should be configured using
  1243. * micdet_cfg in the platform data. Using this function will force on
  1244. * the microphone bias for the device.
  1245. */
  1246. int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  1247. int det, int shrt)
  1248. {
  1249. struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
  1250. int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
  1251. dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
  1252. det, shrt);
  1253. /* Store the configuration */
  1254. wm8903->mic_jack = jack;
  1255. wm8903->mic_det = det;
  1256. wm8903->mic_short = shrt;
  1257. /* Enable interrupts we've got a report configured for */
  1258. if (det)
  1259. irq_mask &= ~WM8903_MICDET_EINT;
  1260. if (shrt)
  1261. irq_mask &= ~WM8903_MICSHRT_EINT;
  1262. snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
  1263. WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
  1264. irq_mask);
  1265. if (det && shrt) {
  1266. /* Enable mic detection, this may not have been set through
  1267. * platform data (eg, if the defaults are OK). */
  1268. snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
  1269. WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
  1270. snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
  1271. WM8903_MICDET_ENA, WM8903_MICDET_ENA);
  1272. } else {
  1273. snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
  1274. WM8903_MICDET_ENA, 0);
  1275. }
  1276. return 0;
  1277. }
  1278. EXPORT_SYMBOL_GPL(wm8903_mic_detect);
  1279. static irqreturn_t wm8903_irq(int irq, void *data)
  1280. {
  1281. struct wm8903_priv *wm8903 = data;
  1282. struct snd_soc_codec *codec = &wm8903->codec;
  1283. int mic_report;
  1284. int int_pol;
  1285. int int_val = 0;
  1286. int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
  1287. int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
  1288. if (int_val & WM8903_WSEQ_BUSY_EINT) {
  1289. dev_dbg(codec->dev, "Write sequencer done\n");
  1290. complete(&wm8903->wseq);
  1291. }
  1292. /*
  1293. * The rest is microphone jack detection. We need to manually
  1294. * invert the polarity of the interrupt after each event - to
  1295. * simplify the code keep track of the last state we reported
  1296. * and just invert the relevant bits in both the report and
  1297. * the polarity register.
  1298. */
  1299. mic_report = wm8903->mic_last_report;
  1300. int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
  1301. if (int_val & WM8903_MICSHRT_EINT) {
  1302. dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
  1303. mic_report ^= wm8903->mic_short;
  1304. int_pol ^= WM8903_MICSHRT_INV;
  1305. }
  1306. if (int_val & WM8903_MICDET_EINT) {
  1307. dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
  1308. mic_report ^= wm8903->mic_det;
  1309. int_pol ^= WM8903_MICDET_INV;
  1310. msleep(wm8903->mic_delay);
  1311. }
  1312. snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
  1313. WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
  1314. snd_soc_jack_report(wm8903->mic_jack, mic_report,
  1315. wm8903->mic_short | wm8903->mic_det);
  1316. wm8903->mic_last_report = mic_report;
  1317. return IRQ_HANDLED;
  1318. }
  1319. #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
  1320. SNDRV_PCM_RATE_11025 | \
  1321. SNDRV_PCM_RATE_16000 | \
  1322. SNDRV_PCM_RATE_22050 | \
  1323. SNDRV_PCM_RATE_32000 | \
  1324. SNDRV_PCM_RATE_44100 | \
  1325. SNDRV_PCM_RATE_48000 | \
  1326. SNDRV_PCM_RATE_88200 | \
  1327. SNDRV_PCM_RATE_96000)
  1328. #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
  1329. SNDRV_PCM_RATE_11025 | \
  1330. SNDRV_PCM_RATE_16000 | \
  1331. SNDRV_PCM_RATE_22050 | \
  1332. SNDRV_PCM_RATE_32000 | \
  1333. SNDRV_PCM_RATE_44100 | \
  1334. SNDRV_PCM_RATE_48000)
  1335. #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1336. SNDRV_PCM_FMTBIT_S20_3LE |\
  1337. SNDRV_PCM_FMTBIT_S24_LE)
  1338. static struct snd_soc_dai_ops wm8903_dai_ops = {
  1339. .startup = wm8903_startup,
  1340. .shutdown = wm8903_shutdown,
  1341. .hw_params = wm8903_hw_params,
  1342. .digital_mute = wm8903_digital_mute,
  1343. .set_fmt = wm8903_set_dai_fmt,
  1344. .set_sysclk = wm8903_set_dai_sysclk,
  1345. };
  1346. struct snd_soc_dai wm8903_dai = {
  1347. .name = "WM8903",
  1348. .playback = {
  1349. .stream_name = "Playback",
  1350. .channels_min = 2,
  1351. .channels_max = 2,
  1352. .rates = WM8903_PLAYBACK_RATES,
  1353. .formats = WM8903_FORMATS,
  1354. },
  1355. .capture = {
  1356. .stream_name = "Capture",
  1357. .channels_min = 2,
  1358. .channels_max = 2,
  1359. .rates = WM8903_CAPTURE_RATES,
  1360. .formats = WM8903_FORMATS,
  1361. },
  1362. .ops = &wm8903_dai_ops,
  1363. .symmetric_rates = 1,
  1364. };
  1365. EXPORT_SYMBOL_GPL(wm8903_dai);
  1366. static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
  1367. {
  1368. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1369. struct snd_soc_codec *codec = socdev->card->codec;
  1370. wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1371. return 0;
  1372. }
  1373. static int wm8903_resume(struct platform_device *pdev)
  1374. {
  1375. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1376. struct snd_soc_codec *codec = socdev->card->codec;
  1377. struct i2c_client *i2c = codec->control_data;
  1378. int i;
  1379. u16 *reg_cache = codec->reg_cache;
  1380. u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
  1381. GFP_KERNEL);
  1382. /* Bring the codec back up to standby first to minimise pop/clicks */
  1383. wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1384. /* Sync back everything else */
  1385. if (tmp_cache) {
  1386. for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
  1387. if (tmp_cache[i] != reg_cache[i])
  1388. snd_soc_write(codec, i, tmp_cache[i]);
  1389. kfree(tmp_cache);
  1390. } else {
  1391. dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
  1392. }
  1393. return 0;
  1394. }
  1395. static struct snd_soc_codec *wm8903_codec;
  1396. static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
  1397. const struct i2c_device_id *id)
  1398. {
  1399. struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1400. struct wm8903_priv *wm8903;
  1401. struct snd_soc_codec *codec;
  1402. int ret, i;
  1403. int trigger, irq_pol;
  1404. u16 val;
  1405. wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
  1406. if (wm8903 == NULL)
  1407. return -ENOMEM;
  1408. codec = &wm8903->codec;
  1409. mutex_init(&codec->mutex);
  1410. INIT_LIST_HEAD(&codec->dapm_widgets);
  1411. INIT_LIST_HEAD(&codec->dapm_paths);
  1412. codec->dev = &i2c->dev;
  1413. codec->name = "WM8903";
  1414. codec->owner = THIS_MODULE;
  1415. codec->bias_level = SND_SOC_BIAS_OFF;
  1416. codec->set_bias_level = wm8903_set_bias_level;
  1417. codec->dai = &wm8903_dai;
  1418. codec->num_dai = 1;
  1419. codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
  1420. codec->reg_cache = &wm8903->reg_cache[0];
  1421. snd_soc_codec_set_drvdata(codec, wm8903);
  1422. codec->volatile_register = wm8903_volatile_register;
  1423. init_completion(&wm8903->wseq);
  1424. i2c_set_clientdata(i2c, codec);
  1425. codec->control_data = i2c;
  1426. ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
  1427. if (ret != 0) {
  1428. dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
  1429. goto err;
  1430. }
  1431. val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
  1432. if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
  1433. dev_err(&i2c->dev,
  1434. "Device with ID register %x is not a WM8903\n", val);
  1435. return -ENODEV;
  1436. }
  1437. val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
  1438. dev_info(&i2c->dev, "WM8903 revision %d\n",
  1439. val & WM8903_CHIP_REV_MASK);
  1440. wm8903_reset(codec);
  1441. /* Set up GPIOs and microphone detection */
  1442. if (pdata) {
  1443. for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
  1444. if (!pdata->gpio_cfg[i])
  1445. continue;
  1446. snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
  1447. pdata->gpio_cfg[i] & 0xffff);
  1448. }
  1449. snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
  1450. pdata->micdet_cfg);
  1451. /* Microphone detection needs the WSEQ clock */
  1452. if (pdata->micdet_cfg)
  1453. snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
  1454. WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
  1455. wm8903->mic_delay = pdata->micdet_delay;
  1456. }
  1457. if (i2c->irq) {
  1458. if (pdata && pdata->irq_active_low) {
  1459. trigger = IRQF_TRIGGER_LOW;
  1460. irq_pol = WM8903_IRQ_POL;
  1461. } else {
  1462. trigger = IRQF_TRIGGER_HIGH;
  1463. irq_pol = 0;
  1464. }
  1465. snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
  1466. WM8903_IRQ_POL, irq_pol);
  1467. ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
  1468. trigger | IRQF_ONESHOT,
  1469. "wm8903", wm8903);
  1470. if (ret != 0) {
  1471. dev_err(&i2c->dev, "Failed to request IRQ: %d\n",
  1472. ret);
  1473. goto err;
  1474. }
  1475. /* Enable write sequencer interrupts */
  1476. snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
  1477. WM8903_IM_WSEQ_BUSY_EINT, 0);
  1478. }
  1479. /* power on device */
  1480. wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1481. /* Latch volume update bits */
  1482. val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
  1483. val |= WM8903_ADCVU;
  1484. snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
  1485. snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
  1486. val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
  1487. val |= WM8903_DACVU;
  1488. snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
  1489. snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
  1490. val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
  1491. val |= WM8903_HPOUTVU;
  1492. snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
  1493. snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
  1494. val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
  1495. val |= WM8903_LINEOUTVU;
  1496. snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
  1497. snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
  1498. val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
  1499. val |= WM8903_SPKVU;
  1500. snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
  1501. snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
  1502. /* Enable DAC soft mute by default */
  1503. val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
  1504. val |= WM8903_DAC_MUTEMODE;
  1505. snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
  1506. wm8903_dai.dev = &i2c->dev;
  1507. wm8903_codec = codec;
  1508. ret = snd_soc_register_codec(codec);
  1509. if (ret != 0) {
  1510. dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
  1511. goto err_irq;
  1512. }
  1513. ret = snd_soc_register_dai(&wm8903_dai);
  1514. if (ret != 0) {
  1515. dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
  1516. goto err_codec;
  1517. }
  1518. return ret;
  1519. err_codec:
  1520. snd_soc_unregister_codec(codec);
  1521. err_irq:
  1522. if (i2c->irq)
  1523. free_irq(i2c->irq, wm8903);
  1524. err:
  1525. wm8903_codec = NULL;
  1526. kfree(wm8903);
  1527. return ret;
  1528. }
  1529. static __devexit int wm8903_i2c_remove(struct i2c_client *client)
  1530. {
  1531. struct snd_soc_codec *codec = i2c_get_clientdata(client);
  1532. struct wm8903_priv *priv = snd_soc_codec_get_drvdata(codec);
  1533. snd_soc_unregister_dai(&wm8903_dai);
  1534. snd_soc_unregister_codec(codec);
  1535. wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1536. if (client->irq)
  1537. free_irq(client->irq, priv);
  1538. kfree(priv);
  1539. wm8903_codec = NULL;
  1540. wm8903_dai.dev = NULL;
  1541. return 0;
  1542. }
  1543. /* i2c codec control layer */
  1544. static const struct i2c_device_id wm8903_i2c_id[] = {
  1545. { "wm8903", 0 },
  1546. { }
  1547. };
  1548. MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
  1549. static struct i2c_driver wm8903_i2c_driver = {
  1550. .driver = {
  1551. .name = "WM8903",
  1552. .owner = THIS_MODULE,
  1553. },
  1554. .probe = wm8903_i2c_probe,
  1555. .remove = __devexit_p(wm8903_i2c_remove),
  1556. .id_table = wm8903_i2c_id,
  1557. };
  1558. static int wm8903_probe(struct platform_device *pdev)
  1559. {
  1560. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1561. int ret = 0;
  1562. if (!wm8903_codec) {
  1563. dev_err(&pdev->dev, "I2C device not yet probed\n");
  1564. goto err;
  1565. }
  1566. socdev->card->codec = wm8903_codec;
  1567. /* register pcms */
  1568. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1569. if (ret < 0) {
  1570. dev_err(&pdev->dev, "failed to create pcms\n");
  1571. goto err;
  1572. }
  1573. snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
  1574. ARRAY_SIZE(wm8903_snd_controls));
  1575. wm8903_add_widgets(socdev->card->codec);
  1576. return ret;
  1577. err:
  1578. return ret;
  1579. }
  1580. /* power down chip */
  1581. static int wm8903_remove(struct platform_device *pdev)
  1582. {
  1583. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1584. struct snd_soc_codec *codec = socdev->card->codec;
  1585. if (codec->control_data)
  1586. wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1587. snd_soc_free_pcms(socdev);
  1588. snd_soc_dapm_free(socdev);
  1589. return 0;
  1590. }
  1591. struct snd_soc_codec_device soc_codec_dev_wm8903 = {
  1592. .probe = wm8903_probe,
  1593. .remove = wm8903_remove,
  1594. .suspend = wm8903_suspend,
  1595. .resume = wm8903_resume,
  1596. };
  1597. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
  1598. static int __init wm8903_modinit(void)
  1599. {
  1600. return i2c_add_driver(&wm8903_i2c_driver);
  1601. }
  1602. module_init(wm8903_modinit);
  1603. static void __exit wm8903_exit(void)
  1604. {
  1605. i2c_del_driver(&wm8903_i2c_driver);
  1606. }
  1607. module_exit(wm8903_exit);
  1608. MODULE_DESCRIPTION("ASoC WM8903 driver");
  1609. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
  1610. MODULE_LICENSE("GPL");