uda134x.c 18 KB

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  1. /*
  2. * uda134x.c -- UDA134X ALSA SoC Codec driver
  3. *
  4. * Modifications by Christian Pellegrin <chripell@evolware.org>
  5. *
  6. * Copyright 2007 Dension Audio Systems Ltd.
  7. * Author: Zoltan Devai
  8. *
  9. * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/delay.h>
  17. #include <linux/slab.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include <sound/soc-dapm.h>
  22. #include <sound/initval.h>
  23. #include <sound/uda134x.h>
  24. #include <sound/l3.h>
  25. #include "uda134x.h"
  26. #define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
  27. #define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  28. SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
  29. struct uda134x_priv {
  30. int sysclk;
  31. int dai_fmt;
  32. struct snd_pcm_substream *master_substream;
  33. struct snd_pcm_substream *slave_substream;
  34. };
  35. /* In-data addresses are hard-coded into the reg-cache values */
  36. static const char uda134x_reg[UDA134X_REGS_NUM] = {
  37. /* Extended address registers */
  38. 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  39. /* Status, data regs */
  40. 0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
  41. };
  42. /*
  43. * The codec has no support for reading its registers except for peak level...
  44. */
  45. static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
  46. unsigned int reg)
  47. {
  48. u8 *cache = codec->reg_cache;
  49. if (reg >= UDA134X_REGS_NUM)
  50. return -1;
  51. return cache[reg];
  52. }
  53. /*
  54. * Write the register cache
  55. */
  56. static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
  57. u8 reg, unsigned int value)
  58. {
  59. u8 *cache = codec->reg_cache;
  60. if (reg >= UDA134X_REGS_NUM)
  61. return;
  62. cache[reg] = value;
  63. }
  64. /*
  65. * Write to the uda134x registers
  66. *
  67. */
  68. static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
  69. unsigned int value)
  70. {
  71. int ret;
  72. u8 addr;
  73. u8 data = value;
  74. struct uda134x_platform_data *pd = codec->control_data;
  75. pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
  76. if (reg >= UDA134X_REGS_NUM) {
  77. printk(KERN_ERR "%s unknown register: reg: %u",
  78. __func__, reg);
  79. return -EINVAL;
  80. }
  81. uda134x_write_reg_cache(codec, reg, value);
  82. switch (reg) {
  83. case UDA134X_STATUS0:
  84. case UDA134X_STATUS1:
  85. addr = UDA134X_STATUS_ADDR;
  86. break;
  87. case UDA134X_DATA000:
  88. case UDA134X_DATA001:
  89. case UDA134X_DATA010:
  90. case UDA134X_DATA011:
  91. addr = UDA134X_DATA0_ADDR;
  92. break;
  93. case UDA134X_DATA1:
  94. addr = UDA134X_DATA1_ADDR;
  95. break;
  96. default:
  97. /* It's an extended address register */
  98. addr = (reg | UDA134X_EXTADDR_PREFIX);
  99. ret = l3_write(&pd->l3,
  100. UDA134X_DATA0_ADDR, &addr, 1);
  101. if (ret != 1)
  102. return -EIO;
  103. addr = UDA134X_DATA0_ADDR;
  104. data = (value | UDA134X_EXTDATA_PREFIX);
  105. break;
  106. }
  107. ret = l3_write(&pd->l3,
  108. addr, &data, 1);
  109. if (ret != 1)
  110. return -EIO;
  111. return 0;
  112. }
  113. static inline void uda134x_reset(struct snd_soc_codec *codec)
  114. {
  115. u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
  116. uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
  117. msleep(1);
  118. uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
  119. }
  120. static int uda134x_mute(struct snd_soc_dai *dai, int mute)
  121. {
  122. struct snd_soc_codec *codec = dai->codec;
  123. u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
  124. pr_debug("%s mute: %d\n", __func__, mute);
  125. if (mute)
  126. mute_reg |= (1<<2);
  127. else
  128. mute_reg &= ~(1<<2);
  129. uda134x_write(codec, UDA134X_DATA010, mute_reg);
  130. return 0;
  131. }
  132. static int uda134x_startup(struct snd_pcm_substream *substream,
  133. struct snd_soc_dai *dai)
  134. {
  135. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  136. struct snd_soc_device *socdev = rtd->socdev;
  137. struct snd_soc_codec *codec = socdev->card->codec;
  138. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  139. struct snd_pcm_runtime *master_runtime;
  140. if (uda134x->master_substream) {
  141. master_runtime = uda134x->master_substream->runtime;
  142. pr_debug("%s constraining to %d bits at %d\n", __func__,
  143. master_runtime->sample_bits,
  144. master_runtime->rate);
  145. snd_pcm_hw_constraint_minmax(substream->runtime,
  146. SNDRV_PCM_HW_PARAM_RATE,
  147. master_runtime->rate,
  148. master_runtime->rate);
  149. snd_pcm_hw_constraint_minmax(substream->runtime,
  150. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  151. master_runtime->sample_bits,
  152. master_runtime->sample_bits);
  153. uda134x->slave_substream = substream;
  154. } else
  155. uda134x->master_substream = substream;
  156. return 0;
  157. }
  158. static void uda134x_shutdown(struct snd_pcm_substream *substream,
  159. struct snd_soc_dai *dai)
  160. {
  161. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  162. struct snd_soc_device *socdev = rtd->socdev;
  163. struct snd_soc_codec *codec = socdev->card->codec;
  164. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  165. if (uda134x->master_substream == substream)
  166. uda134x->master_substream = uda134x->slave_substream;
  167. uda134x->slave_substream = NULL;
  168. }
  169. static int uda134x_hw_params(struct snd_pcm_substream *substream,
  170. struct snd_pcm_hw_params *params,
  171. struct snd_soc_dai *dai)
  172. {
  173. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  174. struct snd_soc_device *socdev = rtd->socdev;
  175. struct snd_soc_codec *codec = socdev->card->codec;
  176. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  177. u8 hw_params;
  178. if (substream == uda134x->slave_substream) {
  179. pr_debug("%s ignoring hw_params for slave substream\n",
  180. __func__);
  181. return 0;
  182. }
  183. hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
  184. hw_params &= STATUS0_SYSCLK_MASK;
  185. hw_params &= STATUS0_DAIFMT_MASK;
  186. pr_debug("%s sysclk: %d, rate:%d\n", __func__,
  187. uda134x->sysclk, params_rate(params));
  188. /* set SYSCLK / fs ratio */
  189. switch (uda134x->sysclk / params_rate(params)) {
  190. case 512:
  191. break;
  192. case 384:
  193. hw_params |= (1<<4);
  194. break;
  195. case 256:
  196. hw_params |= (1<<5);
  197. break;
  198. default:
  199. printk(KERN_ERR "%s unsupported fs\n", __func__);
  200. return -EINVAL;
  201. }
  202. pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
  203. uda134x->dai_fmt, params_format(params));
  204. /* set DAI format and word length */
  205. switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  206. case SND_SOC_DAIFMT_I2S:
  207. break;
  208. case SND_SOC_DAIFMT_RIGHT_J:
  209. switch (params_format(params)) {
  210. case SNDRV_PCM_FORMAT_S16_LE:
  211. hw_params |= (1<<1);
  212. break;
  213. case SNDRV_PCM_FORMAT_S18_3LE:
  214. hw_params |= (1<<2);
  215. break;
  216. case SNDRV_PCM_FORMAT_S20_3LE:
  217. hw_params |= ((1<<2) | (1<<1));
  218. break;
  219. default:
  220. printk(KERN_ERR "%s unsupported format (right)\n",
  221. __func__);
  222. return -EINVAL;
  223. }
  224. break;
  225. case SND_SOC_DAIFMT_LEFT_J:
  226. hw_params |= (1<<3);
  227. break;
  228. default:
  229. printk(KERN_ERR "%s unsupported format\n", __func__);
  230. return -EINVAL;
  231. }
  232. uda134x_write(codec, UDA134X_STATUS0, hw_params);
  233. return 0;
  234. }
  235. static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  236. int clk_id, unsigned int freq, int dir)
  237. {
  238. struct snd_soc_codec *codec = codec_dai->codec;
  239. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  240. pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
  241. clk_id, freq, dir);
  242. /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
  243. because the codec is slave. Of course limitations of the clock
  244. master (the IIS controller) apply.
  245. We'll error out on set_hw_params if it's not OK */
  246. if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
  247. uda134x->sysclk = freq;
  248. return 0;
  249. }
  250. printk(KERN_ERR "%s unsupported sysclk\n", __func__);
  251. return -EINVAL;
  252. }
  253. static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
  254. unsigned int fmt)
  255. {
  256. struct snd_soc_codec *codec = codec_dai->codec;
  257. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  258. pr_debug("%s fmt: %08X\n", __func__, fmt);
  259. /* codec supports only full slave mode */
  260. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
  261. printk(KERN_ERR "%s unsupported slave mode\n", __func__);
  262. return -EINVAL;
  263. }
  264. /* no support for clock inversion */
  265. if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
  266. printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
  267. return -EINVAL;
  268. }
  269. /* We can't setup DAI format here as it depends on the word bit num */
  270. /* so let's just store the value for later */
  271. uda134x->dai_fmt = fmt;
  272. return 0;
  273. }
  274. static int uda134x_set_bias_level(struct snd_soc_codec *codec,
  275. enum snd_soc_bias_level level)
  276. {
  277. u8 reg;
  278. struct uda134x_platform_data *pd = codec->control_data;
  279. int i;
  280. u8 *cache = codec->reg_cache;
  281. pr_debug("%s bias level %d\n", __func__, level);
  282. switch (level) {
  283. case SND_SOC_BIAS_ON:
  284. /* ADC, DAC on */
  285. switch (pd->model) {
  286. case UDA134X_UDA1340:
  287. case UDA134X_UDA1344:
  288. case UDA134X_UDA1345:
  289. reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
  290. uda134x_write(codec, UDA134X_DATA011, reg | 0x03);
  291. break;
  292. case UDA134X_UDA1341:
  293. reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
  294. uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
  295. break;
  296. default:
  297. printk(KERN_ERR "UDA134X SoC codec: "
  298. "unsupported model %d\n", pd->model);
  299. return -EINVAL;
  300. }
  301. break;
  302. case SND_SOC_BIAS_PREPARE:
  303. /* power on */
  304. if (pd->power) {
  305. pd->power(1);
  306. /* Sync reg_cache with the hardware */
  307. for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
  308. codec->write(codec, i, *cache++);
  309. }
  310. break;
  311. case SND_SOC_BIAS_STANDBY:
  312. /* ADC, DAC power off */
  313. switch (pd->model) {
  314. case UDA134X_UDA1340:
  315. case UDA134X_UDA1344:
  316. case UDA134X_UDA1345:
  317. reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
  318. uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
  319. break;
  320. case UDA134X_UDA1341:
  321. reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
  322. uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
  323. break;
  324. default:
  325. printk(KERN_ERR "UDA134X SoC codec: "
  326. "unsupported model %d\n", pd->model);
  327. return -EINVAL;
  328. }
  329. break;
  330. case SND_SOC_BIAS_OFF:
  331. /* power off */
  332. if (pd->power)
  333. pd->power(0);
  334. break;
  335. }
  336. codec->bias_level = level;
  337. return 0;
  338. }
  339. static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
  340. "Minimum2", "Maximum"};
  341. static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
  342. static const char *uda134x_mixmode[] = {"Differential", "Analog1",
  343. "Analog2", "Both"};
  344. static const struct soc_enum uda134x_mixer_enum[] = {
  345. SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
  346. SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
  347. SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
  348. };
  349. static const struct snd_kcontrol_new uda1341_snd_controls[] = {
  350. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  351. SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
  352. SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
  353. SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
  354. SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
  355. SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
  356. SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
  357. SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
  358. SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
  359. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  360. SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
  361. SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
  362. SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
  363. SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
  364. SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
  365. SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
  366. SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
  367. SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
  368. SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
  369. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  370. };
  371. static const struct snd_kcontrol_new uda1340_snd_controls[] = {
  372. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  373. SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
  374. SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
  375. SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
  376. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  377. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  378. };
  379. static const struct snd_kcontrol_new uda1345_snd_controls[] = {
  380. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  381. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  382. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  383. };
  384. static struct snd_soc_dai_ops uda134x_dai_ops = {
  385. .startup = uda134x_startup,
  386. .shutdown = uda134x_shutdown,
  387. .hw_params = uda134x_hw_params,
  388. .digital_mute = uda134x_mute,
  389. .set_sysclk = uda134x_set_dai_sysclk,
  390. .set_fmt = uda134x_set_dai_fmt,
  391. };
  392. struct snd_soc_dai uda134x_dai = {
  393. .name = "UDA134X",
  394. /* playback capabilities */
  395. .playback = {
  396. .stream_name = "Playback",
  397. .channels_min = 1,
  398. .channels_max = 2,
  399. .rates = UDA134X_RATES,
  400. .formats = UDA134X_FORMATS,
  401. },
  402. /* capture capabilities */
  403. .capture = {
  404. .stream_name = "Capture",
  405. .channels_min = 1,
  406. .channels_max = 2,
  407. .rates = UDA134X_RATES,
  408. .formats = UDA134X_FORMATS,
  409. },
  410. /* pcm operations */
  411. .ops = &uda134x_dai_ops,
  412. };
  413. EXPORT_SYMBOL(uda134x_dai);
  414. static int uda134x_soc_probe(struct platform_device *pdev)
  415. {
  416. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  417. struct snd_soc_codec *codec;
  418. struct uda134x_priv *uda134x;
  419. void *codec_setup_data = socdev->codec_data;
  420. int ret = -ENOMEM;
  421. struct uda134x_platform_data *pd;
  422. printk(KERN_INFO "UDA134X SoC Audio Codec\n");
  423. if (!codec_setup_data) {
  424. printk(KERN_ERR "UDA134X SoC codec: "
  425. "missing L3 bitbang function\n");
  426. return -ENODEV;
  427. }
  428. pd = codec_setup_data;
  429. switch (pd->model) {
  430. case UDA134X_UDA1340:
  431. case UDA134X_UDA1341:
  432. case UDA134X_UDA1344:
  433. case UDA134X_UDA1345:
  434. break;
  435. default:
  436. printk(KERN_ERR "UDA134X SoC codec: "
  437. "unsupported model %d\n",
  438. pd->model);
  439. return -EINVAL;
  440. }
  441. socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  442. if (socdev->card->codec == NULL)
  443. return ret;
  444. codec = socdev->card->codec;
  445. uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
  446. if (uda134x == NULL)
  447. goto priv_err;
  448. snd_soc_codec_set_drvdata(codec, uda134x);
  449. codec->reg_cache = kmemdup(uda134x_reg, sizeof(uda134x_reg),
  450. GFP_KERNEL);
  451. if (codec->reg_cache == NULL)
  452. goto reg_err;
  453. mutex_init(&codec->mutex);
  454. codec->reg_cache_size = sizeof(uda134x_reg);
  455. codec->reg_cache_step = 1;
  456. codec->name = "UDA134X";
  457. codec->owner = THIS_MODULE;
  458. codec->dai = &uda134x_dai;
  459. codec->num_dai = 1;
  460. codec->read = uda134x_read_reg_cache;
  461. codec->write = uda134x_write;
  462. INIT_LIST_HEAD(&codec->dapm_widgets);
  463. INIT_LIST_HEAD(&codec->dapm_paths);
  464. codec->control_data = codec_setup_data;
  465. if (pd->power)
  466. pd->power(1);
  467. uda134x_reset(codec);
  468. if (pd->is_powered_on_standby) {
  469. codec->set_bias_level = NULL;
  470. uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
  471. } else {
  472. codec->set_bias_level = uda134x_set_bias_level;
  473. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  474. }
  475. /* register pcms */
  476. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  477. if (ret < 0) {
  478. printk(KERN_ERR "UDA134X: failed to register pcms\n");
  479. goto pcm_err;
  480. }
  481. switch (pd->model) {
  482. case UDA134X_UDA1340:
  483. case UDA134X_UDA1344:
  484. ret = snd_soc_add_controls(codec, uda1340_snd_controls,
  485. ARRAY_SIZE(uda1340_snd_controls));
  486. break;
  487. case UDA134X_UDA1341:
  488. ret = snd_soc_add_controls(codec, uda1341_snd_controls,
  489. ARRAY_SIZE(uda1341_snd_controls));
  490. break;
  491. case UDA134X_UDA1345:
  492. ret = snd_soc_add_controls(codec, uda1345_snd_controls,
  493. ARRAY_SIZE(uda1345_snd_controls));
  494. break;
  495. default:
  496. printk(KERN_ERR "%s unknown codec type: %d",
  497. __func__, pd->model);
  498. return -EINVAL;
  499. }
  500. if (ret < 0) {
  501. printk(KERN_ERR "UDA134X: failed to register controls\n");
  502. goto pcm_err;
  503. }
  504. return 0;
  505. pcm_err:
  506. kfree(codec->reg_cache);
  507. reg_err:
  508. kfree(snd_soc_codec_get_drvdata(codec));
  509. priv_err:
  510. kfree(codec);
  511. return ret;
  512. }
  513. /* power down chip */
  514. static int uda134x_soc_remove(struct platform_device *pdev)
  515. {
  516. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  517. struct snd_soc_codec *codec = socdev->card->codec;
  518. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  519. uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  520. snd_soc_free_pcms(socdev);
  521. snd_soc_dapm_free(socdev);
  522. kfree(snd_soc_codec_get_drvdata(codec));
  523. kfree(codec->reg_cache);
  524. kfree(codec);
  525. return 0;
  526. }
  527. #if defined(CONFIG_PM)
  528. static int uda134x_soc_suspend(struct platform_device *pdev,
  529. pm_message_t state)
  530. {
  531. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  532. struct snd_soc_codec *codec = socdev->card->codec;
  533. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  534. uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  535. return 0;
  536. }
  537. static int uda134x_soc_resume(struct platform_device *pdev)
  538. {
  539. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  540. struct snd_soc_codec *codec = socdev->card->codec;
  541. uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
  542. uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
  543. return 0;
  544. }
  545. #else
  546. #define uda134x_soc_suspend NULL
  547. #define uda134x_soc_resume NULL
  548. #endif /* CONFIG_PM */
  549. struct snd_soc_codec_device soc_codec_dev_uda134x = {
  550. .probe = uda134x_soc_probe,
  551. .remove = uda134x_soc_remove,
  552. .suspend = uda134x_soc_suspend,
  553. .resume = uda134x_soc_resume,
  554. };
  555. EXPORT_SYMBOL_GPL(soc_codec_dev_uda134x);
  556. static int __init uda134x_init(void)
  557. {
  558. return snd_soc_register_dai(&uda134x_dai);
  559. }
  560. module_init(uda134x_init);
  561. static void __exit uda134x_exit(void)
  562. {
  563. snd_soc_unregister_dai(&uda134x_dai);
  564. }
  565. module_exit(uda134x_exit);
  566. MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
  567. MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
  568. MODULE_LICENSE("GPL");