twl4030.c 73 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. #include "twl4030.h"
  38. /*
  39. * twl4030 register cache & default register settings
  40. */
  41. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  42. 0x00, /* this register not used */
  43. 0x00, /* REG_CODEC_MODE (0x1) */
  44. 0x00, /* REG_OPTION (0x2) */
  45. 0x00, /* REG_UNKNOWN (0x3) */
  46. 0x00, /* REG_MICBIAS_CTL (0x4) */
  47. 0x00, /* REG_ANAMICL (0x5) */
  48. 0x00, /* REG_ANAMICR (0x6) */
  49. 0x00, /* REG_AVADC_CTL (0x7) */
  50. 0x00, /* REG_ADCMICSEL (0x8) */
  51. 0x00, /* REG_DIGMIXING (0x9) */
  52. 0x0f, /* REG_ATXL1PGA (0xA) */
  53. 0x0f, /* REG_ATXR1PGA (0xB) */
  54. 0x0f, /* REG_AVTXL2PGA (0xC) */
  55. 0x0f, /* REG_AVTXR2PGA (0xD) */
  56. 0x00, /* REG_AUDIO_IF (0xE) */
  57. 0x00, /* REG_VOICE_IF (0xF) */
  58. 0x3f, /* REG_ARXR1PGA (0x10) */
  59. 0x3f, /* REG_ARXL1PGA (0x11) */
  60. 0x3f, /* REG_ARXR2PGA (0x12) */
  61. 0x3f, /* REG_ARXL2PGA (0x13) */
  62. 0x25, /* REG_VRXPGA (0x14) */
  63. 0x00, /* REG_VSTPGA (0x15) */
  64. 0x00, /* REG_VRX2ARXPGA (0x16) */
  65. 0x00, /* REG_AVDAC_CTL (0x17) */
  66. 0x00, /* REG_ARX2VTXPGA (0x18) */
  67. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  68. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  69. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  70. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  71. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  72. 0x00, /* REG_BT_IF (0x1E) */
  73. 0x55, /* REG_BTPGA (0x1F) */
  74. 0x00, /* REG_BTSTPGA (0x20) */
  75. 0x00, /* REG_EAR_CTL (0x21) */
  76. 0x00, /* REG_HS_SEL (0x22) */
  77. 0x00, /* REG_HS_GAIN_SET (0x23) */
  78. 0x00, /* REG_HS_POPN_SET (0x24) */
  79. 0x00, /* REG_PREDL_CTL (0x25) */
  80. 0x00, /* REG_PREDR_CTL (0x26) */
  81. 0x00, /* REG_PRECKL_CTL (0x27) */
  82. 0x00, /* REG_PRECKR_CTL (0x28) */
  83. 0x00, /* REG_HFL_CTL (0x29) */
  84. 0x00, /* REG_HFR_CTL (0x2A) */
  85. 0x05, /* REG_ALC_CTL (0x2B) */
  86. 0x00, /* REG_ALC_SET1 (0x2C) */
  87. 0x00, /* REG_ALC_SET2 (0x2D) */
  88. 0x00, /* REG_BOOST_CTL (0x2E) */
  89. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  90. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  91. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  92. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  93. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  94. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  95. 0x79, /* REG_DTMF_TONOFF (0x35) */
  96. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  99. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  100. 0x06, /* REG_APLL_CTL (0x3A) */
  101. 0x00, /* REG_DTMF_CTL (0x3B) */
  102. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  103. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  104. 0x00, /* REG_MISC_SET_1 (0x3E) */
  105. 0x00, /* REG_PCMBTMUX (0x3F) */
  106. 0x00, /* not used (0x40) */
  107. 0x00, /* not used (0x41) */
  108. 0x00, /* not used (0x42) */
  109. 0x00, /* REG_RX_PATH_SEL (0x43) */
  110. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  111. 0x00, /* REG_VIBRA_CTL (0x45) */
  112. 0x00, /* REG_VIBRA_SET (0x46) */
  113. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  114. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  115. 0x00, /* REG_MISC_SET_2 (0x49) */
  116. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  117. };
  118. /* codec private data */
  119. struct twl4030_priv {
  120. struct snd_soc_codec codec;
  121. unsigned int codec_powered;
  122. /* reference counts of AIF/APLL users */
  123. unsigned int apll_enabled;
  124. struct snd_pcm_substream *master_substream;
  125. struct snd_pcm_substream *slave_substream;
  126. unsigned int configured;
  127. unsigned int rate;
  128. unsigned int sample_bits;
  129. unsigned int channels;
  130. unsigned int sysclk;
  131. /* Output (with associated amp) states */
  132. u8 hsl_enabled, hsr_enabled;
  133. u8 earpiece_enabled;
  134. u8 predrivel_enabled, predriver_enabled;
  135. u8 carkitl_enabled, carkitr_enabled;
  136. /* Delay needed after enabling the digimic interface */
  137. unsigned int digimic_delay;
  138. };
  139. /*
  140. * read twl4030 register cache
  141. */
  142. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  143. unsigned int reg)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return -EIO;
  148. return cache[reg];
  149. }
  150. /*
  151. * write twl4030 register cache
  152. */
  153. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  154. u8 reg, u8 value)
  155. {
  156. u8 *cache = codec->reg_cache;
  157. if (reg >= TWL4030_CACHEREGNUM)
  158. return;
  159. cache[reg] = value;
  160. }
  161. /*
  162. * write to the twl4030 register space
  163. */
  164. static int twl4030_write(struct snd_soc_codec *codec,
  165. unsigned int reg, unsigned int value)
  166. {
  167. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  168. int write_to_reg = 0;
  169. twl4030_write_reg_cache(codec, reg, value);
  170. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  171. /* Decide if the given register can be written */
  172. switch (reg) {
  173. case TWL4030_REG_EAR_CTL:
  174. if (twl4030->earpiece_enabled)
  175. write_to_reg = 1;
  176. break;
  177. case TWL4030_REG_PREDL_CTL:
  178. if (twl4030->predrivel_enabled)
  179. write_to_reg = 1;
  180. break;
  181. case TWL4030_REG_PREDR_CTL:
  182. if (twl4030->predriver_enabled)
  183. write_to_reg = 1;
  184. break;
  185. case TWL4030_REG_PRECKL_CTL:
  186. if (twl4030->carkitl_enabled)
  187. write_to_reg = 1;
  188. break;
  189. case TWL4030_REG_PRECKR_CTL:
  190. if (twl4030->carkitr_enabled)
  191. write_to_reg = 1;
  192. break;
  193. case TWL4030_REG_HS_GAIN_SET:
  194. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  195. write_to_reg = 1;
  196. break;
  197. default:
  198. /* All other register can be written */
  199. write_to_reg = 1;
  200. break;
  201. }
  202. if (write_to_reg)
  203. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  204. value, reg);
  205. }
  206. return 0;
  207. }
  208. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  209. {
  210. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  211. int mode;
  212. if (enable == twl4030->codec_powered)
  213. return;
  214. if (enable)
  215. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  216. else
  217. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  218. if (mode >= 0) {
  219. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  220. twl4030->codec_powered = enable;
  221. }
  222. /* REVISIT: this delay is present in TI sample drivers */
  223. /* but there seems to be no TRM requirement for it */
  224. udelay(10);
  225. }
  226. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  227. {
  228. int i, difference = 0;
  229. u8 val;
  230. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  231. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  232. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  233. if (val != twl4030_reg[i]) {
  234. difference++;
  235. dev_dbg(codec->dev,
  236. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  237. i, val, twl4030_reg[i]);
  238. }
  239. }
  240. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  241. difference, difference ? "Not OK" : "OK");
  242. }
  243. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  244. {
  245. int i;
  246. /* set all audio section registers to reasonable defaults */
  247. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  248. if (i != TWL4030_REG_APLL_CTL)
  249. twl4030_write(codec, i, twl4030_reg[i]);
  250. }
  251. static void twl4030_init_chip(struct platform_device *pdev)
  252. {
  253. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  254. struct twl4030_setup_data *setup = socdev->codec_data;
  255. struct snd_soc_codec *codec = socdev->card->codec;
  256. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  257. u8 reg, byte;
  258. int i = 0;
  259. /* Check defaults, if instructed before anything else */
  260. if (setup && setup->check_defaults)
  261. twl4030_check_defaults(codec);
  262. /* Reset registers, if no setup data or if instructed to do so */
  263. if (!setup || (setup && setup->reset_registers))
  264. twl4030_reset_registers(codec);
  265. /* Refresh APLL_CTL register from HW */
  266. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  267. TWL4030_REG_APLL_CTL);
  268. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  269. /* anti-pop when changing analog gain */
  270. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  271. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  272. reg | TWL4030_SMOOTH_ANAVOL_EN);
  273. twl4030_write(codec, TWL4030_REG_OPTION,
  274. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  275. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  276. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  277. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  278. /* Machine dependent setup */
  279. if (!setup)
  280. return;
  281. twl4030->digimic_delay = setup->digimic_delay;
  282. /* Configuration for headset ramp delay from setup data */
  283. if (setup->sysclk != twl4030->sysclk)
  284. dev_warn(codec->dev,
  285. "Mismatch in APLL mclk: %u (configured: %u)\n",
  286. setup->sysclk, twl4030->sysclk);
  287. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  288. reg &= ~TWL4030_RAMP_DELAY;
  289. reg |= (setup->ramp_delay_value << 2);
  290. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  291. /* initiate offset cancellation */
  292. twl4030_codec_enable(codec, 1);
  293. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  294. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  295. reg |= setup->offset_cncl_path;
  296. twl4030_write(codec, TWL4030_REG_ANAMICL,
  297. reg | TWL4030_CNCL_OFFSET_START);
  298. /* wait for offset cancellation to complete */
  299. do {
  300. /* this takes a little while, so don't slam i2c */
  301. udelay(2000);
  302. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  303. TWL4030_REG_ANAMICL);
  304. } while ((i++ < 100) &&
  305. ((byte & TWL4030_CNCL_OFFSET_START) ==
  306. TWL4030_CNCL_OFFSET_START));
  307. /* Make sure that the reg_cache has the same value as the HW */
  308. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  309. twl4030_codec_enable(codec, 0);
  310. }
  311. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  312. {
  313. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  314. int status = -1;
  315. if (enable) {
  316. twl4030->apll_enabled++;
  317. if (twl4030->apll_enabled == 1)
  318. status = twl4030_codec_enable_resource(
  319. TWL4030_CODEC_RES_APLL);
  320. } else {
  321. twl4030->apll_enabled--;
  322. if (!twl4030->apll_enabled)
  323. status = twl4030_codec_disable_resource(
  324. TWL4030_CODEC_RES_APLL);
  325. }
  326. if (status >= 0)
  327. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  328. }
  329. /* Earpiece */
  330. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  331. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  332. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  333. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  334. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  335. };
  336. /* PreDrive Left */
  337. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  338. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  339. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  340. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  341. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  342. };
  343. /* PreDrive Right */
  344. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  345. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  346. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  347. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  348. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  349. };
  350. /* Headset Left */
  351. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  352. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  353. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  354. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  355. };
  356. /* Headset Right */
  357. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  358. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  359. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  360. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  361. };
  362. /* Carkit Left */
  363. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  364. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  365. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  366. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  367. };
  368. /* Carkit Right */
  369. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  370. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  371. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  372. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  373. };
  374. /* Handsfree Left */
  375. static const char *twl4030_handsfreel_texts[] =
  376. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  377. static const struct soc_enum twl4030_handsfreel_enum =
  378. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  379. ARRAY_SIZE(twl4030_handsfreel_texts),
  380. twl4030_handsfreel_texts);
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  382. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  383. /* Handsfree Left virtual mute */
  384. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  385. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  386. /* Handsfree Right */
  387. static const char *twl4030_handsfreer_texts[] =
  388. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  389. static const struct soc_enum twl4030_handsfreer_enum =
  390. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  391. ARRAY_SIZE(twl4030_handsfreer_texts),
  392. twl4030_handsfreer_texts);
  393. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  394. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  395. /* Handsfree Right virtual mute */
  396. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  397. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  398. /* Vibra */
  399. /* Vibra audio path selection */
  400. static const char *twl4030_vibra_texts[] =
  401. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  402. static const struct soc_enum twl4030_vibra_enum =
  403. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  404. ARRAY_SIZE(twl4030_vibra_texts),
  405. twl4030_vibra_texts);
  406. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  407. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  408. /* Vibra path selection: local vibrator (PWM) or audio driven */
  409. static const char *twl4030_vibrapath_texts[] =
  410. {"Local vibrator", "Audio"};
  411. static const struct soc_enum twl4030_vibrapath_enum =
  412. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  413. ARRAY_SIZE(twl4030_vibrapath_texts),
  414. twl4030_vibrapath_texts);
  415. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  416. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  417. /* Left analog microphone selection */
  418. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  419. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  420. TWL4030_REG_ANAMICL, 0, 1, 0),
  421. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  422. TWL4030_REG_ANAMICL, 1, 1, 0),
  423. SOC_DAPM_SINGLE("AUXL Capture Switch",
  424. TWL4030_REG_ANAMICL, 2, 1, 0),
  425. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  426. TWL4030_REG_ANAMICL, 3, 1, 0),
  427. };
  428. /* Right analog microphone selection */
  429. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  430. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  431. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  432. };
  433. /* TX1 L/R Analog/Digital microphone selection */
  434. static const char *twl4030_micpathtx1_texts[] =
  435. {"Analog", "Digimic0"};
  436. static const struct soc_enum twl4030_micpathtx1_enum =
  437. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  438. ARRAY_SIZE(twl4030_micpathtx1_texts),
  439. twl4030_micpathtx1_texts);
  440. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  441. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  442. /* TX2 L/R Analog/Digital microphone selection */
  443. static const char *twl4030_micpathtx2_texts[] =
  444. {"Analog", "Digimic1"};
  445. static const struct soc_enum twl4030_micpathtx2_enum =
  446. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  447. ARRAY_SIZE(twl4030_micpathtx2_texts),
  448. twl4030_micpathtx2_texts);
  449. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  450. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  451. /* Analog bypass for AudioR1 */
  452. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  453. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  454. /* Analog bypass for AudioL1 */
  455. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  456. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  457. /* Analog bypass for AudioR2 */
  458. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  459. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  460. /* Analog bypass for AudioL2 */
  461. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  462. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  463. /* Analog bypass for Voice */
  464. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  465. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  466. /* Digital bypass gain, mute instead of -30dB */
  467. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  468. TLV_DB_RANGE_HEAD(3),
  469. 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
  470. 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
  471. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  472. };
  473. /* Digital bypass left (TX1L -> RX2L) */
  474. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  475. SOC_DAPM_SINGLE_TLV("Volume",
  476. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  477. twl4030_dapm_dbypass_tlv);
  478. /* Digital bypass right (TX1R -> RX2R) */
  479. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  480. SOC_DAPM_SINGLE_TLV("Volume",
  481. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  482. twl4030_dapm_dbypass_tlv);
  483. /*
  484. * Voice Sidetone GAIN volume control:
  485. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  486. */
  487. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  488. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  489. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  490. SOC_DAPM_SINGLE_TLV("Volume",
  491. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  492. twl4030_dapm_dbypassv_tlv);
  493. /*
  494. * Output PGA builder:
  495. * Handle the muting and unmuting of the given output (turning off the
  496. * amplifier associated with the output pin)
  497. * On mute bypass the reg_cache and write 0 to the register
  498. * On unmute: restore the register content from the reg_cache
  499. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  500. */
  501. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  502. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  503. struct snd_kcontrol *kcontrol, int event) \
  504. { \
  505. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  506. \
  507. switch (event) { \
  508. case SND_SOC_DAPM_POST_PMU: \
  509. twl4030->pin_name##_enabled = 1; \
  510. twl4030_write(w->codec, reg, \
  511. twl4030_read_reg_cache(w->codec, reg)); \
  512. break; \
  513. case SND_SOC_DAPM_POST_PMD: \
  514. twl4030->pin_name##_enabled = 0; \
  515. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  516. 0, reg); \
  517. break; \
  518. } \
  519. return 0; \
  520. }
  521. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  522. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  523. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  524. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  525. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  526. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  527. {
  528. unsigned char hs_ctl;
  529. hs_ctl = twl4030_read_reg_cache(codec, reg);
  530. if (ramp) {
  531. /* HF ramp-up */
  532. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  533. twl4030_write(codec, reg, hs_ctl);
  534. udelay(10);
  535. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  536. twl4030_write(codec, reg, hs_ctl);
  537. udelay(40);
  538. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  539. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  540. twl4030_write(codec, reg, hs_ctl);
  541. } else {
  542. /* HF ramp-down */
  543. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  544. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  545. twl4030_write(codec, reg, hs_ctl);
  546. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  547. twl4030_write(codec, reg, hs_ctl);
  548. udelay(40);
  549. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  550. twl4030_write(codec, reg, hs_ctl);
  551. }
  552. }
  553. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  554. struct snd_kcontrol *kcontrol, int event)
  555. {
  556. switch (event) {
  557. case SND_SOC_DAPM_POST_PMU:
  558. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  559. break;
  560. case SND_SOC_DAPM_POST_PMD:
  561. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  562. break;
  563. }
  564. return 0;
  565. }
  566. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  567. struct snd_kcontrol *kcontrol, int event)
  568. {
  569. switch (event) {
  570. case SND_SOC_DAPM_POST_PMU:
  571. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  572. break;
  573. case SND_SOC_DAPM_POST_PMD:
  574. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  575. break;
  576. }
  577. return 0;
  578. }
  579. static int vibramux_event(struct snd_soc_dapm_widget *w,
  580. struct snd_kcontrol *kcontrol, int event)
  581. {
  582. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  583. return 0;
  584. }
  585. static int apll_event(struct snd_soc_dapm_widget *w,
  586. struct snd_kcontrol *kcontrol, int event)
  587. {
  588. switch (event) {
  589. case SND_SOC_DAPM_PRE_PMU:
  590. twl4030_apll_enable(w->codec, 1);
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. twl4030_apll_enable(w->codec, 0);
  594. break;
  595. }
  596. return 0;
  597. }
  598. static int aif_event(struct snd_soc_dapm_widget *w,
  599. struct snd_kcontrol *kcontrol, int event)
  600. {
  601. u8 audio_if;
  602. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  603. switch (event) {
  604. case SND_SOC_DAPM_PRE_PMU:
  605. /* Enable AIF */
  606. /* enable the PLL before we use it to clock the DAI */
  607. twl4030_apll_enable(w->codec, 1);
  608. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  609. audio_if | TWL4030_AIF_EN);
  610. break;
  611. case SND_SOC_DAPM_POST_PMD:
  612. /* disable the DAI before we stop it's source PLL */
  613. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  614. audio_if & ~TWL4030_AIF_EN);
  615. twl4030_apll_enable(w->codec, 0);
  616. break;
  617. }
  618. return 0;
  619. }
  620. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  621. {
  622. struct snd_soc_device *socdev = codec->socdev;
  623. struct twl4030_setup_data *setup = socdev->codec_data;
  624. unsigned char hs_gain, hs_pop;
  625. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  626. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  627. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  628. 8388608, 16777216, 33554432, 67108864};
  629. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  630. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  631. /* Enable external mute control, this dramatically reduces
  632. * the pop-noise */
  633. if (setup && setup->hs_extmute) {
  634. if (setup->set_hs_extmute) {
  635. setup->set_hs_extmute(1);
  636. } else {
  637. hs_pop |= TWL4030_EXTMUTE;
  638. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  639. }
  640. }
  641. if (ramp) {
  642. /* Headset ramp-up according to the TRM */
  643. hs_pop |= TWL4030_VMID_EN;
  644. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  645. /* Actually write to the register */
  646. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  647. hs_gain,
  648. TWL4030_REG_HS_GAIN_SET);
  649. hs_pop |= TWL4030_RAMP_EN;
  650. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  651. /* Wait ramp delay time + 1, so the VMID can settle */
  652. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  653. twl4030->sysclk) + 1);
  654. } else {
  655. /* Headset ramp-down _not_ according to
  656. * the TRM, but in a way that it is working */
  657. hs_pop &= ~TWL4030_RAMP_EN;
  658. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  659. /* Wait ramp delay time + 1, so the VMID can settle */
  660. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  661. twl4030->sysclk) + 1);
  662. /* Bypass the reg_cache to mute the headset */
  663. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  664. hs_gain & (~0x0f),
  665. TWL4030_REG_HS_GAIN_SET);
  666. hs_pop &= ~TWL4030_VMID_EN;
  667. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  668. }
  669. /* Disable external mute */
  670. if (setup && setup->hs_extmute) {
  671. if (setup->set_hs_extmute) {
  672. setup->set_hs_extmute(0);
  673. } else {
  674. hs_pop &= ~TWL4030_EXTMUTE;
  675. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  676. }
  677. }
  678. }
  679. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  680. struct snd_kcontrol *kcontrol, int event)
  681. {
  682. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  683. switch (event) {
  684. case SND_SOC_DAPM_POST_PMU:
  685. /* Do the ramp-up only once */
  686. if (!twl4030->hsr_enabled)
  687. headset_ramp(w->codec, 1);
  688. twl4030->hsl_enabled = 1;
  689. break;
  690. case SND_SOC_DAPM_POST_PMD:
  691. /* Do the ramp-down only if both headsetL/R is disabled */
  692. if (!twl4030->hsr_enabled)
  693. headset_ramp(w->codec, 0);
  694. twl4030->hsl_enabled = 0;
  695. break;
  696. }
  697. return 0;
  698. }
  699. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  700. struct snd_kcontrol *kcontrol, int event)
  701. {
  702. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  703. switch (event) {
  704. case SND_SOC_DAPM_POST_PMU:
  705. /* Do the ramp-up only once */
  706. if (!twl4030->hsl_enabled)
  707. headset_ramp(w->codec, 1);
  708. twl4030->hsr_enabled = 1;
  709. break;
  710. case SND_SOC_DAPM_POST_PMD:
  711. /* Do the ramp-down only if both headsetL/R is disabled */
  712. if (!twl4030->hsl_enabled)
  713. headset_ramp(w->codec, 0);
  714. twl4030->hsr_enabled = 0;
  715. break;
  716. }
  717. return 0;
  718. }
  719. static int digimic_event(struct snd_soc_dapm_widget *w,
  720. struct snd_kcontrol *kcontrol, int event)
  721. {
  722. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  723. if (twl4030->digimic_delay)
  724. mdelay(twl4030->digimic_delay);
  725. return 0;
  726. }
  727. /*
  728. * Some of the gain controls in TWL (mostly those which are associated with
  729. * the outputs) are implemented in an interesting way:
  730. * 0x0 : Power down (mute)
  731. * 0x1 : 6dB
  732. * 0x2 : 0 dB
  733. * 0x3 : -6 dB
  734. * Inverting not going to help with these.
  735. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  736. */
  737. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  738. xinvert, tlv_array) \
  739. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  740. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  741. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  742. .tlv.p = (tlv_array), \
  743. .info = snd_soc_info_volsw, \
  744. .get = snd_soc_get_volsw_twl4030, \
  745. .put = snd_soc_put_volsw_twl4030, \
  746. .private_value = (unsigned long)&(struct soc_mixer_control) \
  747. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  748. .max = xmax, .invert = xinvert} }
  749. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  750. xinvert, tlv_array) \
  751. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  752. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  753. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  754. .tlv.p = (tlv_array), \
  755. .info = snd_soc_info_volsw_2r, \
  756. .get = snd_soc_get_volsw_r2_twl4030,\
  757. .put = snd_soc_put_volsw_r2_twl4030, \
  758. .private_value = (unsigned long)&(struct soc_mixer_control) \
  759. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  760. .rshift = xshift, .max = xmax, .invert = xinvert} }
  761. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  762. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  763. xinvert, tlv_array)
  764. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  765. struct snd_ctl_elem_value *ucontrol)
  766. {
  767. struct soc_mixer_control *mc =
  768. (struct soc_mixer_control *)kcontrol->private_value;
  769. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  770. unsigned int reg = mc->reg;
  771. unsigned int shift = mc->shift;
  772. unsigned int rshift = mc->rshift;
  773. int max = mc->max;
  774. int mask = (1 << fls(max)) - 1;
  775. ucontrol->value.integer.value[0] =
  776. (snd_soc_read(codec, reg) >> shift) & mask;
  777. if (ucontrol->value.integer.value[0])
  778. ucontrol->value.integer.value[0] =
  779. max + 1 - ucontrol->value.integer.value[0];
  780. if (shift != rshift) {
  781. ucontrol->value.integer.value[1] =
  782. (snd_soc_read(codec, reg) >> rshift) & mask;
  783. if (ucontrol->value.integer.value[1])
  784. ucontrol->value.integer.value[1] =
  785. max + 1 - ucontrol->value.integer.value[1];
  786. }
  787. return 0;
  788. }
  789. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  790. struct snd_ctl_elem_value *ucontrol)
  791. {
  792. struct soc_mixer_control *mc =
  793. (struct soc_mixer_control *)kcontrol->private_value;
  794. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  795. unsigned int reg = mc->reg;
  796. unsigned int shift = mc->shift;
  797. unsigned int rshift = mc->rshift;
  798. int max = mc->max;
  799. int mask = (1 << fls(max)) - 1;
  800. unsigned short val, val2, val_mask;
  801. val = (ucontrol->value.integer.value[0] & mask);
  802. val_mask = mask << shift;
  803. if (val)
  804. val = max + 1 - val;
  805. val = val << shift;
  806. if (shift != rshift) {
  807. val2 = (ucontrol->value.integer.value[1] & mask);
  808. val_mask |= mask << rshift;
  809. if (val2)
  810. val2 = max + 1 - val2;
  811. val |= val2 << rshift;
  812. }
  813. return snd_soc_update_bits(codec, reg, val_mask, val);
  814. }
  815. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  816. struct snd_ctl_elem_value *ucontrol)
  817. {
  818. struct soc_mixer_control *mc =
  819. (struct soc_mixer_control *)kcontrol->private_value;
  820. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  821. unsigned int reg = mc->reg;
  822. unsigned int reg2 = mc->rreg;
  823. unsigned int shift = mc->shift;
  824. int max = mc->max;
  825. int mask = (1<<fls(max))-1;
  826. ucontrol->value.integer.value[0] =
  827. (snd_soc_read(codec, reg) >> shift) & mask;
  828. ucontrol->value.integer.value[1] =
  829. (snd_soc_read(codec, reg2) >> shift) & mask;
  830. if (ucontrol->value.integer.value[0])
  831. ucontrol->value.integer.value[0] =
  832. max + 1 - ucontrol->value.integer.value[0];
  833. if (ucontrol->value.integer.value[1])
  834. ucontrol->value.integer.value[1] =
  835. max + 1 - ucontrol->value.integer.value[1];
  836. return 0;
  837. }
  838. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  839. struct snd_ctl_elem_value *ucontrol)
  840. {
  841. struct soc_mixer_control *mc =
  842. (struct soc_mixer_control *)kcontrol->private_value;
  843. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  844. unsigned int reg = mc->reg;
  845. unsigned int reg2 = mc->rreg;
  846. unsigned int shift = mc->shift;
  847. int max = mc->max;
  848. int mask = (1 << fls(max)) - 1;
  849. int err;
  850. unsigned short val, val2, val_mask;
  851. val_mask = mask << shift;
  852. val = (ucontrol->value.integer.value[0] & mask);
  853. val2 = (ucontrol->value.integer.value[1] & mask);
  854. if (val)
  855. val = max + 1 - val;
  856. if (val2)
  857. val2 = max + 1 - val2;
  858. val = val << shift;
  859. val2 = val2 << shift;
  860. err = snd_soc_update_bits(codec, reg, val_mask, val);
  861. if (err < 0)
  862. return err;
  863. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  864. return err;
  865. }
  866. /* Codec operation modes */
  867. static const char *twl4030_op_modes_texts[] = {
  868. "Option 2 (voice/audio)", "Option 1 (audio)"
  869. };
  870. static const struct soc_enum twl4030_op_modes_enum =
  871. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  872. ARRAY_SIZE(twl4030_op_modes_texts),
  873. twl4030_op_modes_texts);
  874. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  875. struct snd_ctl_elem_value *ucontrol)
  876. {
  877. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  878. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  879. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  880. unsigned short val;
  881. unsigned short mask, bitmask;
  882. if (twl4030->configured) {
  883. printk(KERN_ERR "twl4030 operation mode cannot be "
  884. "changed on-the-fly\n");
  885. return -EBUSY;
  886. }
  887. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  888. ;
  889. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  890. return -EINVAL;
  891. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  892. mask = (bitmask - 1) << e->shift_l;
  893. if (e->shift_l != e->shift_r) {
  894. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  895. return -EINVAL;
  896. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  897. mask |= (bitmask - 1) << e->shift_r;
  898. }
  899. return snd_soc_update_bits(codec, e->reg, mask, val);
  900. }
  901. /*
  902. * FGAIN volume control:
  903. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  904. */
  905. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  906. /*
  907. * CGAIN volume control:
  908. * 0 dB to 12 dB in 6 dB steps
  909. * value 2 and 3 means 12 dB
  910. */
  911. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  912. /*
  913. * Voice Downlink GAIN volume control:
  914. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  915. */
  916. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  917. /*
  918. * Analog playback gain
  919. * -24 dB to 12 dB in 2 dB steps
  920. */
  921. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  922. /*
  923. * Gain controls tied to outputs
  924. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  925. */
  926. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  927. /*
  928. * Gain control for earpiece amplifier
  929. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  930. */
  931. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  932. /*
  933. * Capture gain after the ADCs
  934. * from 0 dB to 31 dB in 1 dB steps
  935. */
  936. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  937. /*
  938. * Gain control for input amplifiers
  939. * 0 dB to 30 dB in 6 dB steps
  940. */
  941. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  942. /* AVADC clock priority */
  943. static const char *twl4030_avadc_clk_priority_texts[] = {
  944. "Voice high priority", "HiFi high priority"
  945. };
  946. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  947. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  948. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  949. twl4030_avadc_clk_priority_texts);
  950. static const char *twl4030_rampdelay_texts[] = {
  951. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  952. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  953. "3495/2581/1748 ms"
  954. };
  955. static const struct soc_enum twl4030_rampdelay_enum =
  956. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  957. ARRAY_SIZE(twl4030_rampdelay_texts),
  958. twl4030_rampdelay_texts);
  959. /* Vibra H-bridge direction mode */
  960. static const char *twl4030_vibradirmode_texts[] = {
  961. "Vibra H-bridge direction", "Audio data MSB",
  962. };
  963. static const struct soc_enum twl4030_vibradirmode_enum =
  964. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  965. ARRAY_SIZE(twl4030_vibradirmode_texts),
  966. twl4030_vibradirmode_texts);
  967. /* Vibra H-bridge direction */
  968. static const char *twl4030_vibradir_texts[] = {
  969. "Positive polarity", "Negative polarity",
  970. };
  971. static const struct soc_enum twl4030_vibradir_enum =
  972. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  973. ARRAY_SIZE(twl4030_vibradir_texts),
  974. twl4030_vibradir_texts);
  975. /* Digimic Left and right swapping */
  976. static const char *twl4030_digimicswap_texts[] = {
  977. "Not swapped", "Swapped",
  978. };
  979. static const struct soc_enum twl4030_digimicswap_enum =
  980. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  981. ARRAY_SIZE(twl4030_digimicswap_texts),
  982. twl4030_digimicswap_texts);
  983. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  984. /* Codec operation mode control */
  985. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  986. snd_soc_get_enum_double,
  987. snd_soc_put_twl4030_opmode_enum_double),
  988. /* Common playback gain controls */
  989. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  990. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  991. 0, 0x3f, 0, digital_fine_tlv),
  992. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  993. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  994. 0, 0x3f, 0, digital_fine_tlv),
  995. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  996. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  997. 6, 0x2, 0, digital_coarse_tlv),
  998. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  999. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1000. 6, 0x2, 0, digital_coarse_tlv),
  1001. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1002. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1003. 3, 0x12, 1, analog_tlv),
  1004. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1005. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1006. 3, 0x12, 1, analog_tlv),
  1007. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1008. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1009. 1, 1, 0),
  1010. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1011. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1012. 1, 1, 0),
  1013. /* Common voice downlink gain controls */
  1014. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1015. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1016. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1017. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1018. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1019. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1020. /* Separate output gain controls */
  1021. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1022. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1023. 4, 3, 0, output_tvl),
  1024. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1025. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1026. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1027. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1028. 4, 3, 0, output_tvl),
  1029. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1030. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1031. /* Common capture gain controls */
  1032. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1033. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1034. 0, 0x1f, 0, digital_capture_tlv),
  1035. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1036. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1037. 0, 0x1f, 0, digital_capture_tlv),
  1038. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1039. 0, 3, 5, 0, input_gain_tlv),
  1040. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1041. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1042. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1043. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1044. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1045. };
  1046. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1047. /* Left channel inputs */
  1048. SND_SOC_DAPM_INPUT("MAINMIC"),
  1049. SND_SOC_DAPM_INPUT("HSMIC"),
  1050. SND_SOC_DAPM_INPUT("AUXL"),
  1051. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1052. /* Right channel inputs */
  1053. SND_SOC_DAPM_INPUT("SUBMIC"),
  1054. SND_SOC_DAPM_INPUT("AUXR"),
  1055. /* Digital microphones (Stereo) */
  1056. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1057. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1058. /* Outputs */
  1059. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1060. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1061. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1062. SND_SOC_DAPM_OUTPUT("HSOL"),
  1063. SND_SOC_DAPM_OUTPUT("HSOR"),
  1064. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1065. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1066. SND_SOC_DAPM_OUTPUT("HFL"),
  1067. SND_SOC_DAPM_OUTPUT("HFR"),
  1068. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1069. /* AIF and APLL clocks for running DAIs (including loopback) */
  1070. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1071. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1072. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1073. /* DACs */
  1074. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1075. SND_SOC_NOPM, 0, 0),
  1076. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1077. SND_SOC_NOPM, 0, 0),
  1078. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1079. SND_SOC_NOPM, 0, 0),
  1080. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1081. SND_SOC_NOPM, 0, 0),
  1082. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1083. SND_SOC_NOPM, 0, 0),
  1084. /* Analog bypasses */
  1085. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1086. &twl4030_dapm_abypassr1_control),
  1087. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1088. &twl4030_dapm_abypassl1_control),
  1089. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1090. &twl4030_dapm_abypassr2_control),
  1091. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1092. &twl4030_dapm_abypassl2_control),
  1093. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1094. &twl4030_dapm_abypassv_control),
  1095. /* Master analog loopback switch */
  1096. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1097. NULL, 0),
  1098. /* Digital bypasses */
  1099. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1100. &twl4030_dapm_dbypassl_control),
  1101. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1102. &twl4030_dapm_dbypassr_control),
  1103. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1104. &twl4030_dapm_dbypassv_control),
  1105. /* Digital mixers, power control for the physical DACs */
  1106. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1107. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1108. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1109. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1110. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1111. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1112. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1113. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1114. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1115. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1116. /* Analog mixers, power control for the physical PGAs */
  1117. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1118. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1119. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1120. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1121. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1122. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1123. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1124. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1125. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1126. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1127. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1128. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1129. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1130. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1131. /* Output MIXER controls */
  1132. /* Earpiece */
  1133. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1134. &twl4030_dapm_earpiece_controls[0],
  1135. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1136. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1137. 0, 0, NULL, 0, earpiecepga_event,
  1138. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1139. /* PreDrivL/R */
  1140. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1141. &twl4030_dapm_predrivel_controls[0],
  1142. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1143. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1144. 0, 0, NULL, 0, predrivelpga_event,
  1145. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1146. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1147. &twl4030_dapm_predriver_controls[0],
  1148. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1149. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1150. 0, 0, NULL, 0, predriverpga_event,
  1151. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1152. /* HeadsetL/R */
  1153. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1154. &twl4030_dapm_hsol_controls[0],
  1155. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1156. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1157. 0, 0, NULL, 0, headsetlpga_event,
  1158. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1159. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1160. &twl4030_dapm_hsor_controls[0],
  1161. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1162. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1163. 0, 0, NULL, 0, headsetrpga_event,
  1164. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1165. /* CarkitL/R */
  1166. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1167. &twl4030_dapm_carkitl_controls[0],
  1168. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1169. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1170. 0, 0, NULL, 0, carkitlpga_event,
  1171. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1172. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1173. &twl4030_dapm_carkitr_controls[0],
  1174. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1175. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1176. 0, 0, NULL, 0, carkitrpga_event,
  1177. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1178. /* Output MUX controls */
  1179. /* HandsfreeL/R */
  1180. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1181. &twl4030_dapm_handsfreel_control),
  1182. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1183. &twl4030_dapm_handsfreelmute_control),
  1184. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1185. 0, 0, NULL, 0, handsfreelpga_event,
  1186. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1187. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1188. &twl4030_dapm_handsfreer_control),
  1189. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1190. &twl4030_dapm_handsfreermute_control),
  1191. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1192. 0, 0, NULL, 0, handsfreerpga_event,
  1193. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1194. /* Vibra */
  1195. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1196. &twl4030_dapm_vibra_control, vibramux_event,
  1197. SND_SOC_DAPM_PRE_PMU),
  1198. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1199. &twl4030_dapm_vibrapath_control),
  1200. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1201. capture */
  1202. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1203. SND_SOC_NOPM, 0, 0),
  1204. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1205. SND_SOC_NOPM, 0, 0),
  1206. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1207. SND_SOC_NOPM, 0, 0),
  1208. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1209. SND_SOC_NOPM, 0, 0),
  1210. /* Analog/Digital mic path selection.
  1211. TX1 Left/Right: either analog Left/Right or Digimic0
  1212. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1213. SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1214. &twl4030_dapm_micpathtx1_control),
  1215. SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1216. &twl4030_dapm_micpathtx2_control),
  1217. /* Analog input mixers for the capture amplifiers */
  1218. SND_SOC_DAPM_MIXER("Analog Left",
  1219. TWL4030_REG_ANAMICL, 4, 0,
  1220. &twl4030_dapm_analoglmic_controls[0],
  1221. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1222. SND_SOC_DAPM_MIXER("Analog Right",
  1223. TWL4030_REG_ANAMICR, 4, 0,
  1224. &twl4030_dapm_analogrmic_controls[0],
  1225. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1226. SND_SOC_DAPM_PGA("ADC Physical Left",
  1227. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1228. SND_SOC_DAPM_PGA("ADC Physical Right",
  1229. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1230. SND_SOC_DAPM_PGA_E("Digimic0 Enable",
  1231. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
  1232. digimic_event, SND_SOC_DAPM_POST_PMU),
  1233. SND_SOC_DAPM_PGA_E("Digimic1 Enable",
  1234. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
  1235. digimic_event, SND_SOC_DAPM_POST_PMU),
  1236. SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
  1237. NULL, 0),
  1238. SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
  1239. NULL, 0),
  1240. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1241. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1242. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1243. };
  1244. static const struct snd_soc_dapm_route intercon[] = {
  1245. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1246. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1247. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1248. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1249. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1250. /* Supply for the digital part (APLL) */
  1251. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1252. {"DAC Left1", NULL, "AIF Enable"},
  1253. {"DAC Right1", NULL, "AIF Enable"},
  1254. {"DAC Left2", NULL, "AIF Enable"},
  1255. {"DAC Right1", NULL, "AIF Enable"},
  1256. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1257. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1258. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1259. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1260. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1261. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1262. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1263. /* Internal playback routings */
  1264. /* Earpiece */
  1265. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1266. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1267. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1268. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1269. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1270. /* PreDrivL */
  1271. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1272. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1273. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1274. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1275. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1276. /* PreDrivR */
  1277. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1278. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1279. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1280. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1281. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1282. /* HeadsetL */
  1283. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1284. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1285. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1286. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1287. /* HeadsetR */
  1288. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1289. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1290. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1291. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1292. /* CarkitL */
  1293. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1294. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1295. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1296. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1297. /* CarkitR */
  1298. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1299. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1300. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1301. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1302. /* HandsfreeL */
  1303. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1304. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1305. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1306. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1307. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1308. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1309. /* HandsfreeR */
  1310. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1311. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1312. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1313. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1314. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1315. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1316. /* Vibra */
  1317. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1318. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1319. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1320. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1321. /* outputs */
  1322. /* Must be always connected (for AIF and APLL) */
  1323. {"Virtual HiFi OUT", NULL, "DAC Left1"},
  1324. {"Virtual HiFi OUT", NULL, "DAC Right1"},
  1325. {"Virtual HiFi OUT", NULL, "DAC Left2"},
  1326. {"Virtual HiFi OUT", NULL, "DAC Right2"},
  1327. /* Must be always connected (for APLL) */
  1328. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1329. /* Physical outputs */
  1330. {"EARPIECE", NULL, "Earpiece PGA"},
  1331. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1332. {"PREDRIVER", NULL, "PredriveR PGA"},
  1333. {"HSOL", NULL, "HeadsetL PGA"},
  1334. {"HSOR", NULL, "HeadsetR PGA"},
  1335. {"CARKITL", NULL, "CarkitL PGA"},
  1336. {"CARKITR", NULL, "CarkitR PGA"},
  1337. {"HFL", NULL, "HandsfreeL PGA"},
  1338. {"HFR", NULL, "HandsfreeR PGA"},
  1339. {"Vibra Route", "Audio", "Vibra Mux"},
  1340. {"VIBRA", NULL, "Vibra Route"},
  1341. /* Capture path */
  1342. /* Must be always connected (for AIF and APLL) */
  1343. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1344. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1345. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1346. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1347. /* Physical inputs */
  1348. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1349. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1350. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1351. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1352. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1353. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1354. {"ADC Physical Left", NULL, "Analog Left"},
  1355. {"ADC Physical Right", NULL, "Analog Right"},
  1356. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1357. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1358. {"DIGIMIC0", NULL, "micbias1 select"},
  1359. {"DIGIMIC1", NULL, "micbias2 select"},
  1360. /* TX1 Left capture path */
  1361. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1362. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1363. /* TX1 Right capture path */
  1364. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1365. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1366. /* TX2 Left capture path */
  1367. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1368. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1369. /* TX2 Right capture path */
  1370. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1371. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1372. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1373. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1374. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1375. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1376. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1377. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1378. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1379. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1380. /* Analog bypass routes */
  1381. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1382. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1383. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1384. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1385. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1386. /* Supply for the Analog loopbacks */
  1387. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1388. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1389. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1390. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1391. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1392. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1393. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1394. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1395. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1396. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1397. /* Digital bypass routes */
  1398. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1399. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1400. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1401. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1402. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1403. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1404. };
  1405. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1406. {
  1407. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1408. ARRAY_SIZE(twl4030_dapm_widgets));
  1409. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1410. return 0;
  1411. }
  1412. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1413. enum snd_soc_bias_level level)
  1414. {
  1415. switch (level) {
  1416. case SND_SOC_BIAS_ON:
  1417. break;
  1418. case SND_SOC_BIAS_PREPARE:
  1419. break;
  1420. case SND_SOC_BIAS_STANDBY:
  1421. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1422. twl4030_codec_enable(codec, 1);
  1423. break;
  1424. case SND_SOC_BIAS_OFF:
  1425. twl4030_codec_enable(codec, 0);
  1426. break;
  1427. }
  1428. codec->bias_level = level;
  1429. return 0;
  1430. }
  1431. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1432. struct snd_pcm_substream *mst_substream)
  1433. {
  1434. struct snd_pcm_substream *slv_substream;
  1435. /* Pick the stream, which need to be constrained */
  1436. if (mst_substream == twl4030->master_substream)
  1437. slv_substream = twl4030->slave_substream;
  1438. else if (mst_substream == twl4030->slave_substream)
  1439. slv_substream = twl4030->master_substream;
  1440. else /* This should not happen.. */
  1441. return;
  1442. /* Set the constraints according to the already configured stream */
  1443. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1444. SNDRV_PCM_HW_PARAM_RATE,
  1445. twl4030->rate,
  1446. twl4030->rate);
  1447. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1448. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1449. twl4030->sample_bits,
  1450. twl4030->sample_bits);
  1451. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1452. SNDRV_PCM_HW_PARAM_CHANNELS,
  1453. twl4030->channels,
  1454. twl4030->channels);
  1455. }
  1456. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1457. * capture has to be enabled/disabled. */
  1458. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1459. int enable)
  1460. {
  1461. u8 reg, mask;
  1462. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1463. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1464. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1465. else
  1466. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1467. if (enable)
  1468. reg |= mask;
  1469. else
  1470. reg &= ~mask;
  1471. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1472. }
  1473. static int twl4030_startup(struct snd_pcm_substream *substream,
  1474. struct snd_soc_dai *dai)
  1475. {
  1476. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1477. struct snd_soc_device *socdev = rtd->socdev;
  1478. struct snd_soc_codec *codec = socdev->card->codec;
  1479. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1480. if (twl4030->master_substream) {
  1481. twl4030->slave_substream = substream;
  1482. /* The DAI has one configuration for playback and capture, so
  1483. * if the DAI has been already configured then constrain this
  1484. * substream to match it. */
  1485. if (twl4030->configured)
  1486. twl4030_constraints(twl4030, twl4030->master_substream);
  1487. } else {
  1488. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1489. TWL4030_OPTION_1)) {
  1490. /* In option2 4 channel is not supported, set the
  1491. * constraint for the first stream for channels, the
  1492. * second stream will 'inherit' this cosntraint */
  1493. snd_pcm_hw_constraint_minmax(substream->runtime,
  1494. SNDRV_PCM_HW_PARAM_CHANNELS,
  1495. 2, 2);
  1496. }
  1497. twl4030->master_substream = substream;
  1498. }
  1499. return 0;
  1500. }
  1501. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1502. struct snd_soc_dai *dai)
  1503. {
  1504. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1505. struct snd_soc_device *socdev = rtd->socdev;
  1506. struct snd_soc_codec *codec = socdev->card->codec;
  1507. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1508. if (twl4030->master_substream == substream)
  1509. twl4030->master_substream = twl4030->slave_substream;
  1510. twl4030->slave_substream = NULL;
  1511. /* If all streams are closed, or the remaining stream has not yet
  1512. * been configured than set the DAI as not configured. */
  1513. if (!twl4030->master_substream)
  1514. twl4030->configured = 0;
  1515. else if (!twl4030->master_substream->runtime->channels)
  1516. twl4030->configured = 0;
  1517. /* If the closing substream had 4 channel, do the necessary cleanup */
  1518. if (substream->runtime->channels == 4)
  1519. twl4030_tdm_enable(codec, substream->stream, 0);
  1520. }
  1521. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1522. struct snd_pcm_hw_params *params,
  1523. struct snd_soc_dai *dai)
  1524. {
  1525. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1526. struct snd_soc_device *socdev = rtd->socdev;
  1527. struct snd_soc_codec *codec = socdev->card->codec;
  1528. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1529. u8 mode, old_mode, format, old_format;
  1530. /* If the substream has 4 channel, do the necessary setup */
  1531. if (params_channels(params) == 4) {
  1532. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1533. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1534. /* Safety check: are we in the correct operating mode and
  1535. * the interface is in TDM mode? */
  1536. if ((mode & TWL4030_OPTION_1) &&
  1537. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1538. twl4030_tdm_enable(codec, substream->stream, 1);
  1539. else
  1540. return -EINVAL;
  1541. }
  1542. if (twl4030->configured)
  1543. /* Ignoring hw_params for already configured DAI */
  1544. return 0;
  1545. /* bit rate */
  1546. old_mode = twl4030_read_reg_cache(codec,
  1547. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1548. mode = old_mode & ~TWL4030_APLL_RATE;
  1549. switch (params_rate(params)) {
  1550. case 8000:
  1551. mode |= TWL4030_APLL_RATE_8000;
  1552. break;
  1553. case 11025:
  1554. mode |= TWL4030_APLL_RATE_11025;
  1555. break;
  1556. case 12000:
  1557. mode |= TWL4030_APLL_RATE_12000;
  1558. break;
  1559. case 16000:
  1560. mode |= TWL4030_APLL_RATE_16000;
  1561. break;
  1562. case 22050:
  1563. mode |= TWL4030_APLL_RATE_22050;
  1564. break;
  1565. case 24000:
  1566. mode |= TWL4030_APLL_RATE_24000;
  1567. break;
  1568. case 32000:
  1569. mode |= TWL4030_APLL_RATE_32000;
  1570. break;
  1571. case 44100:
  1572. mode |= TWL4030_APLL_RATE_44100;
  1573. break;
  1574. case 48000:
  1575. mode |= TWL4030_APLL_RATE_48000;
  1576. break;
  1577. case 96000:
  1578. mode |= TWL4030_APLL_RATE_96000;
  1579. break;
  1580. default:
  1581. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1582. params_rate(params));
  1583. return -EINVAL;
  1584. }
  1585. /* sample size */
  1586. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1587. format = old_format;
  1588. format &= ~TWL4030_DATA_WIDTH;
  1589. switch (params_format(params)) {
  1590. case SNDRV_PCM_FORMAT_S16_LE:
  1591. format |= TWL4030_DATA_WIDTH_16S_16W;
  1592. break;
  1593. case SNDRV_PCM_FORMAT_S24_LE:
  1594. format |= TWL4030_DATA_WIDTH_32S_24W;
  1595. break;
  1596. default:
  1597. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1598. params_format(params));
  1599. return -EINVAL;
  1600. }
  1601. if (format != old_format || mode != old_mode) {
  1602. if (twl4030->codec_powered) {
  1603. /*
  1604. * If the codec is powered, than we need to toggle the
  1605. * codec power.
  1606. */
  1607. twl4030_codec_enable(codec, 0);
  1608. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1609. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1610. twl4030_codec_enable(codec, 1);
  1611. } else {
  1612. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1613. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1614. }
  1615. }
  1616. /* Store the important parameters for the DAI configuration and set
  1617. * the DAI as configured */
  1618. twl4030->configured = 1;
  1619. twl4030->rate = params_rate(params);
  1620. twl4030->sample_bits = hw_param_interval(params,
  1621. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1622. twl4030->channels = params_channels(params);
  1623. /* If both playback and capture streams are open, and one of them
  1624. * is setting the hw parameters right now (since we are here), set
  1625. * constraints to the other stream to match the current one. */
  1626. if (twl4030->slave_substream)
  1627. twl4030_constraints(twl4030, substream);
  1628. return 0;
  1629. }
  1630. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1631. int clk_id, unsigned int freq, int dir)
  1632. {
  1633. struct snd_soc_codec *codec = codec_dai->codec;
  1634. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1635. switch (freq) {
  1636. case 19200000:
  1637. case 26000000:
  1638. case 38400000:
  1639. break;
  1640. default:
  1641. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1642. return -EINVAL;
  1643. }
  1644. if ((freq / 1000) != twl4030->sysclk) {
  1645. dev_err(codec->dev,
  1646. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1647. freq, twl4030->sysclk * 1000);
  1648. return -EINVAL;
  1649. }
  1650. return 0;
  1651. }
  1652. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1653. unsigned int fmt)
  1654. {
  1655. struct snd_soc_codec *codec = codec_dai->codec;
  1656. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1657. u8 old_format, format;
  1658. /* get format */
  1659. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1660. format = old_format;
  1661. /* set master/slave audio interface */
  1662. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1663. case SND_SOC_DAIFMT_CBM_CFM:
  1664. format &= ~(TWL4030_AIF_SLAVE_EN);
  1665. format &= ~(TWL4030_CLK256FS_EN);
  1666. break;
  1667. case SND_SOC_DAIFMT_CBS_CFS:
  1668. format |= TWL4030_AIF_SLAVE_EN;
  1669. format |= TWL4030_CLK256FS_EN;
  1670. break;
  1671. default:
  1672. return -EINVAL;
  1673. }
  1674. /* interface format */
  1675. format &= ~TWL4030_AIF_FORMAT;
  1676. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1677. case SND_SOC_DAIFMT_I2S:
  1678. format |= TWL4030_AIF_FORMAT_CODEC;
  1679. break;
  1680. case SND_SOC_DAIFMT_DSP_A:
  1681. format |= TWL4030_AIF_FORMAT_TDM;
  1682. break;
  1683. default:
  1684. return -EINVAL;
  1685. }
  1686. if (format != old_format) {
  1687. if (twl4030->codec_powered) {
  1688. /*
  1689. * If the codec is powered, than we need to toggle the
  1690. * codec power.
  1691. */
  1692. twl4030_codec_enable(codec, 0);
  1693. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1694. twl4030_codec_enable(codec, 1);
  1695. } else {
  1696. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1697. }
  1698. }
  1699. return 0;
  1700. }
  1701. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1702. {
  1703. struct snd_soc_codec *codec = dai->codec;
  1704. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1705. if (tristate)
  1706. reg |= TWL4030_AIF_TRI_EN;
  1707. else
  1708. reg &= ~TWL4030_AIF_TRI_EN;
  1709. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1710. }
  1711. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1712. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1713. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1714. int enable)
  1715. {
  1716. u8 reg, mask;
  1717. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1718. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1719. mask = TWL4030_ARXL1_VRX_EN;
  1720. else
  1721. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1722. if (enable)
  1723. reg |= mask;
  1724. else
  1725. reg &= ~mask;
  1726. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1727. }
  1728. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1729. struct snd_soc_dai *dai)
  1730. {
  1731. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1732. struct snd_soc_device *socdev = rtd->socdev;
  1733. struct snd_soc_codec *codec = socdev->card->codec;
  1734. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1735. u8 mode;
  1736. /* If the system master clock is not 26MHz, the voice PCM interface is
  1737. * not avilable.
  1738. */
  1739. if (twl4030->sysclk != 26000) {
  1740. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1741. "the Voice interface needs 26MHz APLL mclk\n",
  1742. twl4030->sysclk * 1000);
  1743. return -EINVAL;
  1744. }
  1745. /* If the codec mode is not option2, the voice PCM interface is not
  1746. * avilable.
  1747. */
  1748. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1749. & TWL4030_OPT_MODE;
  1750. if (mode != TWL4030_OPTION_2) {
  1751. printk(KERN_ERR "TWL4030 voice startup: "
  1752. "the codec mode is not option2\n");
  1753. return -EINVAL;
  1754. }
  1755. return 0;
  1756. }
  1757. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1758. struct snd_soc_dai *dai)
  1759. {
  1760. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1761. struct snd_soc_device *socdev = rtd->socdev;
  1762. struct snd_soc_codec *codec = socdev->card->codec;
  1763. /* Enable voice digital filters */
  1764. twl4030_voice_enable(codec, substream->stream, 0);
  1765. }
  1766. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1767. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1768. {
  1769. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1770. struct snd_soc_device *socdev = rtd->socdev;
  1771. struct snd_soc_codec *codec = socdev->card->codec;
  1772. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1773. u8 old_mode, mode;
  1774. /* Enable voice digital filters */
  1775. twl4030_voice_enable(codec, substream->stream, 1);
  1776. /* bit rate */
  1777. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1778. & ~(TWL4030_CODECPDZ);
  1779. mode = old_mode;
  1780. switch (params_rate(params)) {
  1781. case 8000:
  1782. mode &= ~(TWL4030_SEL_16K);
  1783. break;
  1784. case 16000:
  1785. mode |= TWL4030_SEL_16K;
  1786. break;
  1787. default:
  1788. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1789. params_rate(params));
  1790. return -EINVAL;
  1791. }
  1792. if (mode != old_mode) {
  1793. if (twl4030->codec_powered) {
  1794. /*
  1795. * If the codec is powered, than we need to toggle the
  1796. * codec power.
  1797. */
  1798. twl4030_codec_enable(codec, 0);
  1799. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1800. twl4030_codec_enable(codec, 1);
  1801. } else {
  1802. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1803. }
  1804. }
  1805. return 0;
  1806. }
  1807. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1808. int clk_id, unsigned int freq, int dir)
  1809. {
  1810. struct snd_soc_codec *codec = codec_dai->codec;
  1811. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1812. if (freq != 26000000) {
  1813. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1814. "interface needs 26MHz APLL mclk\n", freq);
  1815. return -EINVAL;
  1816. }
  1817. if ((freq / 1000) != twl4030->sysclk) {
  1818. dev_err(codec->dev,
  1819. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1820. freq, twl4030->sysclk * 1000);
  1821. return -EINVAL;
  1822. }
  1823. return 0;
  1824. }
  1825. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1826. unsigned int fmt)
  1827. {
  1828. struct snd_soc_codec *codec = codec_dai->codec;
  1829. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1830. u8 old_format, format;
  1831. /* get format */
  1832. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1833. format = old_format;
  1834. /* set master/slave audio interface */
  1835. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1836. case SND_SOC_DAIFMT_CBM_CFM:
  1837. format &= ~(TWL4030_VIF_SLAVE_EN);
  1838. break;
  1839. case SND_SOC_DAIFMT_CBS_CFS:
  1840. format |= TWL4030_VIF_SLAVE_EN;
  1841. break;
  1842. default:
  1843. return -EINVAL;
  1844. }
  1845. /* clock inversion */
  1846. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1847. case SND_SOC_DAIFMT_IB_NF:
  1848. format &= ~(TWL4030_VIF_FORMAT);
  1849. break;
  1850. case SND_SOC_DAIFMT_NB_IF:
  1851. format |= TWL4030_VIF_FORMAT;
  1852. break;
  1853. default:
  1854. return -EINVAL;
  1855. }
  1856. if (format != old_format) {
  1857. if (twl4030->codec_powered) {
  1858. /*
  1859. * If the codec is powered, than we need to toggle the
  1860. * codec power.
  1861. */
  1862. twl4030_codec_enable(codec, 0);
  1863. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1864. twl4030_codec_enable(codec, 1);
  1865. } else {
  1866. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1867. }
  1868. }
  1869. return 0;
  1870. }
  1871. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1872. {
  1873. struct snd_soc_codec *codec = dai->codec;
  1874. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1875. if (tristate)
  1876. reg |= TWL4030_VIF_TRI_EN;
  1877. else
  1878. reg &= ~TWL4030_VIF_TRI_EN;
  1879. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1880. }
  1881. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1882. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1883. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1884. .startup = twl4030_startup,
  1885. .shutdown = twl4030_shutdown,
  1886. .hw_params = twl4030_hw_params,
  1887. .set_sysclk = twl4030_set_dai_sysclk,
  1888. .set_fmt = twl4030_set_dai_fmt,
  1889. .set_tristate = twl4030_set_tristate,
  1890. };
  1891. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1892. .startup = twl4030_voice_startup,
  1893. .shutdown = twl4030_voice_shutdown,
  1894. .hw_params = twl4030_voice_hw_params,
  1895. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1896. .set_fmt = twl4030_voice_set_dai_fmt,
  1897. .set_tristate = twl4030_voice_set_tristate,
  1898. };
  1899. struct snd_soc_dai twl4030_dai[] = {
  1900. {
  1901. .name = "twl4030",
  1902. .playback = {
  1903. .stream_name = "HiFi Playback",
  1904. .channels_min = 2,
  1905. .channels_max = 4,
  1906. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1907. .formats = TWL4030_FORMATS,},
  1908. .capture = {
  1909. .stream_name = "Capture",
  1910. .channels_min = 2,
  1911. .channels_max = 4,
  1912. .rates = TWL4030_RATES,
  1913. .formats = TWL4030_FORMATS,},
  1914. .ops = &twl4030_dai_ops,
  1915. },
  1916. {
  1917. .name = "twl4030 Voice",
  1918. .playback = {
  1919. .stream_name = "Voice Playback",
  1920. .channels_min = 1,
  1921. .channels_max = 1,
  1922. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1923. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1924. .capture = {
  1925. .stream_name = "Capture",
  1926. .channels_min = 1,
  1927. .channels_max = 2,
  1928. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1929. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1930. .ops = &twl4030_dai_voice_ops,
  1931. },
  1932. };
  1933. EXPORT_SYMBOL_GPL(twl4030_dai);
  1934. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1935. {
  1936. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1937. struct snd_soc_codec *codec = socdev->card->codec;
  1938. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1939. return 0;
  1940. }
  1941. static int twl4030_soc_resume(struct platform_device *pdev)
  1942. {
  1943. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1944. struct snd_soc_codec *codec = socdev->card->codec;
  1945. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1946. return 0;
  1947. }
  1948. static struct snd_soc_codec *twl4030_codec;
  1949. static int twl4030_soc_probe(struct platform_device *pdev)
  1950. {
  1951. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1952. struct snd_soc_codec *codec;
  1953. int ret;
  1954. BUG_ON(!twl4030_codec);
  1955. codec = twl4030_codec;
  1956. socdev->card->codec = codec;
  1957. twl4030_init_chip(pdev);
  1958. /* register pcms */
  1959. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1960. if (ret < 0) {
  1961. dev_err(&pdev->dev, "failed to create pcms\n");
  1962. return ret;
  1963. }
  1964. snd_soc_add_controls(codec, twl4030_snd_controls,
  1965. ARRAY_SIZE(twl4030_snd_controls));
  1966. twl4030_add_widgets(codec);
  1967. return 0;
  1968. }
  1969. static int twl4030_soc_remove(struct platform_device *pdev)
  1970. {
  1971. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1972. struct snd_soc_codec *codec = socdev->card->codec;
  1973. /* Reset registers to their chip default before leaving */
  1974. twl4030_reset_registers(codec);
  1975. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1976. snd_soc_free_pcms(socdev);
  1977. snd_soc_dapm_free(socdev);
  1978. return 0;
  1979. }
  1980. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1981. {
  1982. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1983. struct snd_soc_codec *codec;
  1984. struct twl4030_priv *twl4030;
  1985. int ret;
  1986. if (!pdata) {
  1987. dev_err(&pdev->dev, "platform_data is missing\n");
  1988. return -EINVAL;
  1989. }
  1990. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1991. if (twl4030 == NULL) {
  1992. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1993. return -ENOMEM;
  1994. }
  1995. codec = &twl4030->codec;
  1996. snd_soc_codec_set_drvdata(codec, twl4030);
  1997. codec->dev = &pdev->dev;
  1998. twl4030_dai[0].dev = &pdev->dev;
  1999. twl4030_dai[1].dev = &pdev->dev;
  2000. mutex_init(&codec->mutex);
  2001. INIT_LIST_HEAD(&codec->dapm_widgets);
  2002. INIT_LIST_HEAD(&codec->dapm_paths);
  2003. codec->name = "twl4030";
  2004. codec->owner = THIS_MODULE;
  2005. codec->read = twl4030_read_reg_cache;
  2006. codec->write = twl4030_write;
  2007. codec->set_bias_level = twl4030_set_bias_level;
  2008. codec->idle_bias_off = 1;
  2009. codec->dai = twl4030_dai;
  2010. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  2011. codec->reg_cache_size = sizeof(twl4030_reg);
  2012. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  2013. GFP_KERNEL);
  2014. if (codec->reg_cache == NULL) {
  2015. ret = -ENOMEM;
  2016. goto error_cache;
  2017. }
  2018. platform_set_drvdata(pdev, twl4030);
  2019. twl4030_codec = codec;
  2020. /* Set the defaults, and power up the codec */
  2021. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  2022. codec->bias_level = SND_SOC_BIAS_OFF;
  2023. ret = snd_soc_register_codec(codec);
  2024. if (ret != 0) {
  2025. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2026. goto error_codec;
  2027. }
  2028. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2029. if (ret != 0) {
  2030. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2031. snd_soc_unregister_codec(codec);
  2032. goto error_codec;
  2033. }
  2034. return 0;
  2035. error_codec:
  2036. twl4030_codec_enable(codec, 0);
  2037. kfree(codec->reg_cache);
  2038. error_cache:
  2039. kfree(twl4030);
  2040. return ret;
  2041. }
  2042. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2043. {
  2044. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2045. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2046. snd_soc_unregister_codec(&twl4030->codec);
  2047. kfree(twl4030->codec.reg_cache);
  2048. kfree(twl4030);
  2049. twl4030_codec = NULL;
  2050. return 0;
  2051. }
  2052. MODULE_ALIAS("platform:twl4030_codec_audio");
  2053. static struct platform_driver twl4030_codec_driver = {
  2054. .probe = twl4030_codec_probe,
  2055. .remove = __devexit_p(twl4030_codec_remove),
  2056. .driver = {
  2057. .name = "twl4030_codec_audio",
  2058. .owner = THIS_MODULE,
  2059. },
  2060. };
  2061. static int __init twl4030_modinit(void)
  2062. {
  2063. return platform_driver_register(&twl4030_codec_driver);
  2064. }
  2065. module_init(twl4030_modinit);
  2066. static void __exit twl4030_exit(void)
  2067. {
  2068. platform_driver_unregister(&twl4030_codec_driver);
  2069. }
  2070. module_exit(twl4030_exit);
  2071. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2072. .probe = twl4030_soc_probe,
  2073. .remove = twl4030_soc_remove,
  2074. .suspend = twl4030_soc_suspend,
  2075. .resume = twl4030_soc_resume,
  2076. };
  2077. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2078. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2079. MODULE_AUTHOR("Steve Sakoman");
  2080. MODULE_LICENSE("GPL");