tlv320dac33.c 45 KB

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  1. /*
  2. * ALSA SoC Texas Instruments TLV320DAC33 codec driver
  3. *
  4. * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
  5. *
  6. * Copyright: (C) 2009 Nokia Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/pm.h>
  28. #include <linux/i2c.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/gpio.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/slab.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/pcm_params.h>
  37. #include <sound/soc.h>
  38. #include <sound/soc-dapm.h>
  39. #include <sound/initval.h>
  40. #include <sound/tlv.h>
  41. #include <sound/tlv320dac33-plat.h>
  42. #include "tlv320dac33.h"
  43. #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
  44. * 6144 stereo */
  45. #define DAC33_BUFFER_SIZE_SAMPLES 6144
  46. #define NSAMPLE_MAX 5700
  47. #define MODE7_LTHR 10
  48. #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
  49. #define BURST_BASEFREQ_HZ 49152000
  50. #define SAMPLES_TO_US(rate, samples) \
  51. (1000000000 / ((rate * 1000) / samples))
  52. #define US_TO_SAMPLES(rate, us) \
  53. (rate / (1000000 / us))
  54. #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  55. ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  56. static void dac33_calculate_times(struct snd_pcm_substream *substream);
  57. static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  58. static struct snd_soc_codec *tlv320dac33_codec;
  59. enum dac33_state {
  60. DAC33_IDLE = 0,
  61. DAC33_PREFILL,
  62. DAC33_PLAYBACK,
  63. DAC33_FLUSH,
  64. };
  65. enum dac33_fifo_modes {
  66. DAC33_FIFO_BYPASS = 0,
  67. DAC33_FIFO_MODE1,
  68. DAC33_FIFO_MODE7,
  69. DAC33_FIFO_LAST_MODE,
  70. };
  71. #define DAC33_NUM_SUPPLIES 3
  72. static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  73. "AVDD",
  74. "DVDD",
  75. "IOVDD",
  76. };
  77. struct tlv320dac33_priv {
  78. struct mutex mutex;
  79. struct workqueue_struct *dac33_wq;
  80. struct work_struct work;
  81. struct snd_soc_codec codec;
  82. struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  83. struct snd_pcm_substream *substream;
  84. int power_gpio;
  85. int chip_power;
  86. int irq;
  87. unsigned int refclk;
  88. unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
  89. unsigned int nsample_min; /* nsample should not be lower than
  90. * this */
  91. unsigned int nsample_max; /* nsample should not be higher than
  92. * this */
  93. enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
  94. unsigned int nsample; /* burst read amount from host */
  95. int mode1_latency; /* latency caused by the i2c writes in
  96. * us */
  97. int auto_fifo_config; /* Configure the FIFO based on the
  98. * period size */
  99. u8 burst_bclkdiv; /* BCLK divider value in burst mode */
  100. unsigned int burst_rate; /* Interface speed in Burst modes */
  101. int keep_bclk; /* Keep the BCLK continuously running
  102. * in FIFO modes */
  103. spinlock_t lock;
  104. unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
  105. unsigned long long t_stamp2; /* calculate the FIFO caused delay */
  106. unsigned int mode1_us_burst; /* Time to burst read n number of
  107. * samples */
  108. unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
  109. unsigned int uthr;
  110. enum dac33_state state;
  111. };
  112. static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
  113. 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
  114. 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
  115. 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
  116. 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
  117. 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
  118. 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
  119. 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
  120. 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
  121. 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
  122. 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
  123. 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
  124. 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
  125. 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
  126. 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
  127. 0x00, 0x00, /* 0x38 - 0x39 */
  128. /* Registers 0x3a - 0x3f are reserved */
  129. 0x00, 0x00, /* 0x3a - 0x3b */
  130. 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
  131. 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
  132. 0x00, 0x80, /* 0x44 - 0x45 */
  133. /* Registers 0x46 - 0x47 are reserved */
  134. 0x80, 0x80, /* 0x46 - 0x47 */
  135. 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
  136. /* Registers 0x4b - 0x7c are reserved */
  137. 0x00, /* 0x4b */
  138. 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
  139. 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
  140. 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
  141. 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
  142. 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
  143. 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
  144. 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
  145. 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
  146. 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
  147. 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
  148. 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
  149. 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
  150. 0x00, /* 0x7c */
  151. 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
  152. };
  153. /* Register read and write */
  154. static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
  155. unsigned reg)
  156. {
  157. u8 *cache = codec->reg_cache;
  158. if (reg >= DAC33_CACHEREGNUM)
  159. return 0;
  160. return cache[reg];
  161. }
  162. static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
  163. u8 reg, u8 value)
  164. {
  165. u8 *cache = codec->reg_cache;
  166. if (reg >= DAC33_CACHEREGNUM)
  167. return;
  168. cache[reg] = value;
  169. }
  170. static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
  171. u8 *value)
  172. {
  173. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  174. int val;
  175. *value = reg & 0xff;
  176. /* If powered off, return the cached value */
  177. if (dac33->chip_power) {
  178. val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
  179. if (val < 0) {
  180. dev_err(codec->dev, "Read failed (%d)\n", val);
  181. value[0] = dac33_read_reg_cache(codec, reg);
  182. } else {
  183. value[0] = val;
  184. dac33_write_reg_cache(codec, reg, val);
  185. }
  186. } else {
  187. value[0] = dac33_read_reg_cache(codec, reg);
  188. }
  189. return 0;
  190. }
  191. static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
  192. unsigned int value)
  193. {
  194. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  195. u8 data[2];
  196. int ret = 0;
  197. /*
  198. * data is
  199. * D15..D8 dac33 register offset
  200. * D7...D0 register data
  201. */
  202. data[0] = reg & 0xff;
  203. data[1] = value & 0xff;
  204. dac33_write_reg_cache(codec, data[0], data[1]);
  205. if (dac33->chip_power) {
  206. ret = codec->hw_write(codec->control_data, data, 2);
  207. if (ret != 2)
  208. dev_err(codec->dev, "Write failed (%d)\n", ret);
  209. else
  210. ret = 0;
  211. }
  212. return ret;
  213. }
  214. static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
  215. unsigned int value)
  216. {
  217. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  218. int ret;
  219. mutex_lock(&dac33->mutex);
  220. ret = dac33_write(codec, reg, value);
  221. mutex_unlock(&dac33->mutex);
  222. return ret;
  223. }
  224. #define DAC33_I2C_ADDR_AUTOINC 0x80
  225. static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
  226. unsigned int value)
  227. {
  228. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  229. u8 data[3];
  230. int ret = 0;
  231. /*
  232. * data is
  233. * D23..D16 dac33 register offset
  234. * D15..D8 register data MSB
  235. * D7...D0 register data LSB
  236. */
  237. data[0] = reg & 0xff;
  238. data[1] = (value >> 8) & 0xff;
  239. data[2] = value & 0xff;
  240. dac33_write_reg_cache(codec, data[0], data[1]);
  241. dac33_write_reg_cache(codec, data[0] + 1, data[2]);
  242. if (dac33->chip_power) {
  243. /* We need to set autoincrement mode for 16 bit writes */
  244. data[0] |= DAC33_I2C_ADDR_AUTOINC;
  245. ret = codec->hw_write(codec->control_data, data, 3);
  246. if (ret != 3)
  247. dev_err(codec->dev, "Write failed (%d)\n", ret);
  248. else
  249. ret = 0;
  250. }
  251. return ret;
  252. }
  253. static void dac33_init_chip(struct snd_soc_codec *codec)
  254. {
  255. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  256. if (unlikely(!dac33->chip_power))
  257. return;
  258. /* 44-46: DAC Control Registers */
  259. /* A : DAC sample rate Fsref/1.5 */
  260. dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
  261. /* B : DAC src=normal, not muted */
  262. dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
  263. DAC33_DACSRCL_LEFT);
  264. /* C : (defaults) */
  265. dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
  266. /* 73 : volume soft stepping control,
  267. clock source = internal osc (?) */
  268. dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
  269. dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
  270. /* Restore only selected registers (gains mostly) */
  271. dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
  272. dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
  273. dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
  274. dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
  275. dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
  276. dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
  277. dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
  278. dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
  279. }
  280. static inline void dac33_read_id(struct snd_soc_codec *codec)
  281. {
  282. u8 reg;
  283. dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
  284. dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
  285. dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
  286. }
  287. static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
  288. {
  289. u8 reg;
  290. reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
  291. if (power)
  292. reg |= DAC33_PDNALLB;
  293. else
  294. reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
  295. DAC33_DACRPDNB | DAC33_DACLPDNB);
  296. dac33_write(codec, DAC33_PWR_CTRL, reg);
  297. }
  298. static int dac33_hard_power(struct snd_soc_codec *codec, int power)
  299. {
  300. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  301. int ret = 0;
  302. mutex_lock(&dac33->mutex);
  303. /* Safety check */
  304. if (unlikely(power == dac33->chip_power)) {
  305. dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
  306. power ? "ON" : "OFF");
  307. goto exit;
  308. }
  309. if (power) {
  310. ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
  311. dac33->supplies);
  312. if (ret != 0) {
  313. dev_err(codec->dev,
  314. "Failed to enable supplies: %d\n", ret);
  315. goto exit;
  316. }
  317. if (dac33->power_gpio >= 0)
  318. gpio_set_value(dac33->power_gpio, 1);
  319. dac33->chip_power = 1;
  320. } else {
  321. dac33_soft_power(codec, 0);
  322. if (dac33->power_gpio >= 0)
  323. gpio_set_value(dac33->power_gpio, 0);
  324. ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
  325. dac33->supplies);
  326. if (ret != 0) {
  327. dev_err(codec->dev,
  328. "Failed to disable supplies: %d\n", ret);
  329. goto exit;
  330. }
  331. dac33->chip_power = 0;
  332. }
  333. exit:
  334. mutex_unlock(&dac33->mutex);
  335. return ret;
  336. }
  337. static int playback_event(struct snd_soc_dapm_widget *w,
  338. struct snd_kcontrol *kcontrol, int event)
  339. {
  340. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
  341. switch (event) {
  342. case SND_SOC_DAPM_PRE_PMU:
  343. if (likely(dac33->substream)) {
  344. dac33_calculate_times(dac33->substream);
  345. dac33_prepare_chip(dac33->substream);
  346. }
  347. break;
  348. }
  349. return 0;
  350. }
  351. static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
  352. struct snd_ctl_elem_value *ucontrol)
  353. {
  354. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  355. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  356. ucontrol->value.integer.value[0] = dac33->nsample;
  357. return 0;
  358. }
  359. static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
  360. struct snd_ctl_elem_value *ucontrol)
  361. {
  362. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  363. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  364. int ret = 0;
  365. if (dac33->nsample == ucontrol->value.integer.value[0])
  366. return 0;
  367. if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
  368. ucontrol->value.integer.value[0] > dac33->nsample_max) {
  369. ret = -EINVAL;
  370. } else {
  371. dac33->nsample = ucontrol->value.integer.value[0];
  372. /* Re calculate the burst time */
  373. dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
  374. dac33->nsample);
  375. }
  376. return ret;
  377. }
  378. static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
  379. struct snd_ctl_elem_value *ucontrol)
  380. {
  381. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  382. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  383. ucontrol->value.integer.value[0] = dac33->uthr;
  384. return 0;
  385. }
  386. static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
  387. struct snd_ctl_elem_value *ucontrol)
  388. {
  389. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  390. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  391. int ret = 0;
  392. if (dac33->substream)
  393. return -EBUSY;
  394. if (dac33->uthr == ucontrol->value.integer.value[0])
  395. return 0;
  396. if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
  397. ucontrol->value.integer.value[0] > MODE7_UTHR)
  398. ret = -EINVAL;
  399. else
  400. dac33->uthr = ucontrol->value.integer.value[0];
  401. return ret;
  402. }
  403. static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
  404. struct snd_ctl_elem_value *ucontrol)
  405. {
  406. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  407. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  408. ucontrol->value.integer.value[0] = dac33->fifo_mode;
  409. return 0;
  410. }
  411. static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
  412. struct snd_ctl_elem_value *ucontrol)
  413. {
  414. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  415. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  416. int ret = 0;
  417. if (dac33->fifo_mode == ucontrol->value.integer.value[0])
  418. return 0;
  419. /* Do not allow changes while stream is running*/
  420. if (codec->active)
  421. return -EPERM;
  422. if (ucontrol->value.integer.value[0] < 0 ||
  423. ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
  424. ret = -EINVAL;
  425. else
  426. dac33->fifo_mode = ucontrol->value.integer.value[0];
  427. return ret;
  428. }
  429. /* Codec operation modes */
  430. static const char *dac33_fifo_mode_texts[] = {
  431. "Bypass", "Mode 1", "Mode 7"
  432. };
  433. static const struct soc_enum dac33_fifo_mode_enum =
  434. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
  435. dac33_fifo_mode_texts);
  436. /*
  437. * DACL/R digital volume control:
  438. * from 0 dB to -63.5 in 0.5 dB steps
  439. * Need to be inverted later on:
  440. * 0x00 == 0 dB
  441. * 0x7f == -63.5 dB
  442. */
  443. static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
  444. static const struct snd_kcontrol_new dac33_snd_controls[] = {
  445. SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
  446. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
  447. 0, 0x7f, 1, dac_digivol_tlv),
  448. SOC_DOUBLE_R("DAC Digital Playback Switch",
  449. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
  450. SOC_DOUBLE_R("Line to Line Out Volume",
  451. DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
  452. };
  453. static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
  454. SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
  455. dac33_get_fifo_mode, dac33_set_fifo_mode),
  456. };
  457. static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
  458. SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
  459. dac33_get_nsample, dac33_set_nsample),
  460. SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
  461. dac33_get_uthr, dac33_set_uthr),
  462. };
  463. /* Analog bypass */
  464. static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
  465. SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
  466. static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
  467. SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
  468. static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
  469. SND_SOC_DAPM_OUTPUT("LEFT_LO"),
  470. SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
  471. SND_SOC_DAPM_INPUT("LINEL"),
  472. SND_SOC_DAPM_INPUT("LINER"),
  473. SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
  474. SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
  475. /* Analog bypass */
  476. SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
  477. &dac33_dapm_abypassl_control),
  478. SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
  479. &dac33_dapm_abypassr_control),
  480. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
  481. DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
  482. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
  483. DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
  484. SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
  485. };
  486. static const struct snd_soc_dapm_route audio_map[] = {
  487. /* Analog bypass */
  488. {"Analog Left Bypass", "Switch", "LINEL"},
  489. {"Analog Right Bypass", "Switch", "LINER"},
  490. {"Output Left Amp Power", NULL, "DACL"},
  491. {"Output Right Amp Power", NULL, "DACR"},
  492. {"Output Left Amp Power", NULL, "Analog Left Bypass"},
  493. {"Output Right Amp Power", NULL, "Analog Right Bypass"},
  494. /* output */
  495. {"LEFT_LO", NULL, "Output Left Amp Power"},
  496. {"RIGHT_LO", NULL, "Output Right Amp Power"},
  497. };
  498. static int dac33_add_widgets(struct snd_soc_codec *codec)
  499. {
  500. snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
  501. ARRAY_SIZE(dac33_dapm_widgets));
  502. /* set up audio path interconnects */
  503. snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
  504. return 0;
  505. }
  506. static int dac33_set_bias_level(struct snd_soc_codec *codec,
  507. enum snd_soc_bias_level level)
  508. {
  509. int ret;
  510. switch (level) {
  511. case SND_SOC_BIAS_ON:
  512. dac33_soft_power(codec, 1);
  513. break;
  514. case SND_SOC_BIAS_PREPARE:
  515. break;
  516. case SND_SOC_BIAS_STANDBY:
  517. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  518. /* Coming from OFF, switch on the codec */
  519. ret = dac33_hard_power(codec, 1);
  520. if (ret != 0)
  521. return ret;
  522. dac33_init_chip(codec);
  523. }
  524. break;
  525. case SND_SOC_BIAS_OFF:
  526. /* Do not power off, when the codec is already off */
  527. if (codec->bias_level == SND_SOC_BIAS_OFF)
  528. return 0;
  529. ret = dac33_hard_power(codec, 0);
  530. if (ret != 0)
  531. return ret;
  532. break;
  533. }
  534. codec->bias_level = level;
  535. return 0;
  536. }
  537. static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
  538. {
  539. struct snd_soc_codec *codec;
  540. codec = &dac33->codec;
  541. switch (dac33->fifo_mode) {
  542. case DAC33_FIFO_MODE1:
  543. dac33_write16(codec, DAC33_NSAMPLE_MSB,
  544. DAC33_THRREG(dac33->nsample));
  545. /* Take the timestamps */
  546. spin_lock_irq(&dac33->lock);
  547. dac33->t_stamp2 = ktime_to_us(ktime_get());
  548. dac33->t_stamp1 = dac33->t_stamp2;
  549. spin_unlock_irq(&dac33->lock);
  550. dac33_write16(codec, DAC33_PREFILL_MSB,
  551. DAC33_THRREG(dac33->alarm_threshold));
  552. /* Enable Alarm Threshold IRQ with a delay */
  553. udelay(SAMPLES_TO_US(dac33->burst_rate,
  554. dac33->alarm_threshold));
  555. dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
  556. break;
  557. case DAC33_FIFO_MODE7:
  558. /* Take the timestamp */
  559. spin_lock_irq(&dac33->lock);
  560. dac33->t_stamp1 = ktime_to_us(ktime_get());
  561. /* Move back the timestamp with drain time */
  562. dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
  563. spin_unlock_irq(&dac33->lock);
  564. dac33_write16(codec, DAC33_PREFILL_MSB,
  565. DAC33_THRREG(MODE7_LTHR));
  566. /* Enable Upper Threshold IRQ */
  567. dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
  568. break;
  569. default:
  570. dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
  571. dac33->fifo_mode);
  572. break;
  573. }
  574. }
  575. static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
  576. {
  577. struct snd_soc_codec *codec;
  578. codec = &dac33->codec;
  579. switch (dac33->fifo_mode) {
  580. case DAC33_FIFO_MODE1:
  581. /* Take the timestamp */
  582. spin_lock_irq(&dac33->lock);
  583. dac33->t_stamp2 = ktime_to_us(ktime_get());
  584. spin_unlock_irq(&dac33->lock);
  585. dac33_write16(codec, DAC33_NSAMPLE_MSB,
  586. DAC33_THRREG(dac33->nsample));
  587. break;
  588. case DAC33_FIFO_MODE7:
  589. /* At the moment we are not using interrupts in mode7 */
  590. break;
  591. default:
  592. dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
  593. dac33->fifo_mode);
  594. break;
  595. }
  596. }
  597. static void dac33_work(struct work_struct *work)
  598. {
  599. struct snd_soc_codec *codec;
  600. struct tlv320dac33_priv *dac33;
  601. u8 reg;
  602. dac33 = container_of(work, struct tlv320dac33_priv, work);
  603. codec = &dac33->codec;
  604. mutex_lock(&dac33->mutex);
  605. switch (dac33->state) {
  606. case DAC33_PREFILL:
  607. dac33->state = DAC33_PLAYBACK;
  608. dac33_prefill_handler(dac33);
  609. break;
  610. case DAC33_PLAYBACK:
  611. dac33_playback_handler(dac33);
  612. break;
  613. case DAC33_IDLE:
  614. break;
  615. case DAC33_FLUSH:
  616. dac33->state = DAC33_IDLE;
  617. /* Mask all interrupts from dac33 */
  618. dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
  619. /* flush fifo */
  620. reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
  621. reg |= DAC33_FIFOFLUSH;
  622. dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
  623. break;
  624. }
  625. mutex_unlock(&dac33->mutex);
  626. }
  627. static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
  628. {
  629. struct snd_soc_codec *codec = dev;
  630. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  631. spin_lock(&dac33->lock);
  632. dac33->t_stamp1 = ktime_to_us(ktime_get());
  633. spin_unlock(&dac33->lock);
  634. /* Do not schedule the workqueue in Mode7 */
  635. if (dac33->fifo_mode != DAC33_FIFO_MODE7)
  636. queue_work(dac33->dac33_wq, &dac33->work);
  637. return IRQ_HANDLED;
  638. }
  639. static void dac33_oscwait(struct snd_soc_codec *codec)
  640. {
  641. int timeout = 20;
  642. u8 reg;
  643. do {
  644. msleep(1);
  645. dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
  646. } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
  647. if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
  648. dev_err(codec->dev,
  649. "internal oscillator calibration failed\n");
  650. }
  651. static int dac33_startup(struct snd_pcm_substream *substream,
  652. struct snd_soc_dai *dai)
  653. {
  654. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  655. struct snd_soc_device *socdev = rtd->socdev;
  656. struct snd_soc_codec *codec = socdev->card->codec;
  657. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  658. /* Stream started, save the substream pointer */
  659. dac33->substream = substream;
  660. return 0;
  661. }
  662. static void dac33_shutdown(struct snd_pcm_substream *substream,
  663. struct snd_soc_dai *dai)
  664. {
  665. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  666. struct snd_soc_device *socdev = rtd->socdev;
  667. struct snd_soc_codec *codec = socdev->card->codec;
  668. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  669. dac33->substream = NULL;
  670. /* Reset the nSample restrictions */
  671. dac33->nsample_min = 0;
  672. dac33->nsample_max = NSAMPLE_MAX;
  673. }
  674. static int dac33_hw_params(struct snd_pcm_substream *substream,
  675. struct snd_pcm_hw_params *params,
  676. struct snd_soc_dai *dai)
  677. {
  678. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  679. struct snd_soc_device *socdev = rtd->socdev;
  680. struct snd_soc_codec *codec = socdev->card->codec;
  681. /* Check parameters for validity */
  682. switch (params_rate(params)) {
  683. case 44100:
  684. case 48000:
  685. break;
  686. default:
  687. dev_err(codec->dev, "unsupported rate %d\n",
  688. params_rate(params));
  689. return -EINVAL;
  690. }
  691. switch (params_format(params)) {
  692. case SNDRV_PCM_FORMAT_S16_LE:
  693. break;
  694. default:
  695. dev_err(codec->dev, "unsupported format %d\n",
  696. params_format(params));
  697. return -EINVAL;
  698. }
  699. return 0;
  700. }
  701. #define CALC_OSCSET(rate, refclk) ( \
  702. ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
  703. #define CALC_RATIOSET(rate, refclk) ( \
  704. ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
  705. /*
  706. * tlv320dac33 is strict on the sequence of the register writes, if the register
  707. * writes happens in different order, than dac33 might end up in unknown state.
  708. * Use the known, working sequence of register writes to initialize the dac33.
  709. */
  710. static int dac33_prepare_chip(struct snd_pcm_substream *substream)
  711. {
  712. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  713. struct snd_soc_device *socdev = rtd->socdev;
  714. struct snd_soc_codec *codec = socdev->card->codec;
  715. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  716. unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
  717. u8 aictrl_a, aictrl_b, fifoctrl_a;
  718. switch (substream->runtime->rate) {
  719. case 44100:
  720. case 48000:
  721. oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
  722. ratioset = CALC_RATIOSET(substream->runtime->rate,
  723. dac33->refclk);
  724. break;
  725. default:
  726. dev_err(codec->dev, "unsupported rate %d\n",
  727. substream->runtime->rate);
  728. return -EINVAL;
  729. }
  730. aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
  731. aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
  732. /* Read FIFO control A, and clear FIFO flush bit */
  733. fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
  734. fifoctrl_a &= ~DAC33_FIFOFLUSH;
  735. fifoctrl_a &= ~DAC33_WIDTH;
  736. switch (substream->runtime->format) {
  737. case SNDRV_PCM_FORMAT_S16_LE:
  738. aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
  739. fifoctrl_a |= DAC33_WIDTH;
  740. break;
  741. default:
  742. dev_err(codec->dev, "unsupported format %d\n",
  743. substream->runtime->format);
  744. return -EINVAL;
  745. }
  746. mutex_lock(&dac33->mutex);
  747. if (!dac33->chip_power) {
  748. /*
  749. * Chip is not powered yet.
  750. * Do the init in the dac33_set_bias_level later.
  751. */
  752. mutex_unlock(&dac33->mutex);
  753. return 0;
  754. }
  755. dac33_soft_power(codec, 0);
  756. dac33_soft_power(codec, 1);
  757. reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
  758. dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
  759. /* Write registers 0x08 and 0x09 (MSB, LSB) */
  760. dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
  761. /* calib time: 128 is a nice number ;) */
  762. dac33_write(codec, DAC33_CALIB_TIME, 128);
  763. /* adjustment treshold & step */
  764. dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
  765. DAC33_ADJSTEP(1));
  766. /* div=4 / gain=1 / div */
  767. dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
  768. pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
  769. pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
  770. dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
  771. dac33_oscwait(codec);
  772. if (dac33->fifo_mode) {
  773. /* Generic for all FIFO modes */
  774. /* 50-51 : ASRC Control registers */
  775. dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
  776. dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
  777. /* Write registers 0x34 and 0x35 (MSB, LSB) */
  778. dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
  779. /* Set interrupts to high active */
  780. dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
  781. } else {
  782. /* FIFO bypass mode */
  783. /* 50-51 : ASRC Control registers */
  784. dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
  785. dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
  786. }
  787. /* Interrupt behaviour configuration */
  788. switch (dac33->fifo_mode) {
  789. case DAC33_FIFO_MODE1:
  790. dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
  791. DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
  792. break;
  793. case DAC33_FIFO_MODE7:
  794. dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
  795. DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
  796. break;
  797. default:
  798. /* in FIFO bypass mode, the interrupts are not used */
  799. break;
  800. }
  801. aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
  802. switch (dac33->fifo_mode) {
  803. case DAC33_FIFO_MODE1:
  804. /*
  805. * For mode1:
  806. * Disable the FIFO bypass (Enable the use of FIFO)
  807. * Select nSample mode
  808. * BCLK is only running when data is needed by DAC33
  809. */
  810. fifoctrl_a &= ~DAC33_FBYPAS;
  811. fifoctrl_a &= ~DAC33_FAUTO;
  812. if (dac33->keep_bclk)
  813. aictrl_b |= DAC33_BCLKON;
  814. else
  815. aictrl_b &= ~DAC33_BCLKON;
  816. break;
  817. case DAC33_FIFO_MODE7:
  818. /*
  819. * For mode1:
  820. * Disable the FIFO bypass (Enable the use of FIFO)
  821. * Select Threshold mode
  822. * BCLK is only running when data is needed by DAC33
  823. */
  824. fifoctrl_a &= ~DAC33_FBYPAS;
  825. fifoctrl_a |= DAC33_FAUTO;
  826. if (dac33->keep_bclk)
  827. aictrl_b |= DAC33_BCLKON;
  828. else
  829. aictrl_b &= ~DAC33_BCLKON;
  830. break;
  831. default:
  832. /*
  833. * For FIFO bypass mode:
  834. * Enable the FIFO bypass (Disable the FIFO use)
  835. * Set the BCLK as continous
  836. */
  837. fifoctrl_a |= DAC33_FBYPAS;
  838. aictrl_b |= DAC33_BCLKON;
  839. break;
  840. }
  841. dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
  842. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  843. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
  844. /*
  845. * BCLK divide ratio
  846. * 0: 1.5
  847. * 1: 1
  848. * 2: 2
  849. * ...
  850. * 254: 254
  851. * 255: 255
  852. */
  853. if (dac33->fifo_mode)
  854. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
  855. dac33->burst_bclkdiv);
  856. else
  857. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
  858. switch (dac33->fifo_mode) {
  859. case DAC33_FIFO_MODE1:
  860. dac33_write16(codec, DAC33_ATHR_MSB,
  861. DAC33_THRREG(dac33->alarm_threshold));
  862. break;
  863. case DAC33_FIFO_MODE7:
  864. /*
  865. * Configure the threshold levels, and leave 10 sample space
  866. * at the bottom, and also at the top of the FIFO
  867. */
  868. dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
  869. dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
  870. break;
  871. default:
  872. break;
  873. }
  874. mutex_unlock(&dac33->mutex);
  875. return 0;
  876. }
  877. static void dac33_calculate_times(struct snd_pcm_substream *substream)
  878. {
  879. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  880. struct snd_soc_device *socdev = rtd->socdev;
  881. struct snd_soc_codec *codec = socdev->card->codec;
  882. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  883. unsigned int period_size = substream->runtime->period_size;
  884. unsigned int rate = substream->runtime->rate;
  885. unsigned int nsample_limit;
  886. /* In bypass mode we don't need to calculate */
  887. if (!dac33->fifo_mode)
  888. return;
  889. switch (dac33->fifo_mode) {
  890. case DAC33_FIFO_MODE1:
  891. /* Number of samples under i2c latency */
  892. dac33->alarm_threshold = US_TO_SAMPLES(rate,
  893. dac33->mode1_latency);
  894. if (dac33->auto_fifo_config) {
  895. if (period_size <= dac33->alarm_threshold)
  896. /*
  897. * Configure nSamaple to number of periods,
  898. * which covers the latency requironment.
  899. */
  900. dac33->nsample = period_size *
  901. ((dac33->alarm_threshold / period_size) +
  902. (dac33->alarm_threshold % period_size ?
  903. 1 : 0));
  904. else
  905. dac33->nsample = period_size;
  906. } else {
  907. /* nSample time shall not be shorter than i2c latency */
  908. dac33->nsample_min = dac33->alarm_threshold;
  909. /*
  910. * nSample should not be bigger than alsa buffer minus
  911. * size of one period to avoid overruns
  912. */
  913. dac33->nsample_max = substream->runtime->buffer_size -
  914. period_size;
  915. nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
  916. dac33->alarm_threshold;
  917. if (dac33->nsample_max > nsample_limit)
  918. dac33->nsample_max = nsample_limit;
  919. /* Correct the nSample if it is outside of the ranges */
  920. if (dac33->nsample < dac33->nsample_min)
  921. dac33->nsample = dac33->nsample_min;
  922. if (dac33->nsample > dac33->nsample_max)
  923. dac33->nsample = dac33->nsample_max;
  924. }
  925. dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
  926. dac33->nsample);
  927. dac33->t_stamp1 = 0;
  928. dac33->t_stamp2 = 0;
  929. break;
  930. case DAC33_FIFO_MODE7:
  931. if (dac33->auto_fifo_config) {
  932. dac33->uthr = UTHR_FROM_PERIOD_SIZE(
  933. period_size,
  934. rate,
  935. dac33->burst_rate) + 9;
  936. if (dac33->uthr > MODE7_UTHR)
  937. dac33->uthr = MODE7_UTHR;
  938. if (dac33->uthr < (MODE7_LTHR + 10))
  939. dac33->uthr = (MODE7_LTHR + 10);
  940. }
  941. dac33->mode7_us_to_lthr =
  942. SAMPLES_TO_US(substream->runtime->rate,
  943. dac33->uthr - MODE7_LTHR + 1);
  944. dac33->t_stamp1 = 0;
  945. break;
  946. default:
  947. break;
  948. }
  949. }
  950. static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
  951. struct snd_soc_dai *dai)
  952. {
  953. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  954. struct snd_soc_device *socdev = rtd->socdev;
  955. struct snd_soc_codec *codec = socdev->card->codec;
  956. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  957. int ret = 0;
  958. switch (cmd) {
  959. case SNDRV_PCM_TRIGGER_START:
  960. case SNDRV_PCM_TRIGGER_RESUME:
  961. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  962. if (dac33->fifo_mode) {
  963. dac33->state = DAC33_PREFILL;
  964. queue_work(dac33->dac33_wq, &dac33->work);
  965. }
  966. break;
  967. case SNDRV_PCM_TRIGGER_STOP:
  968. case SNDRV_PCM_TRIGGER_SUSPEND:
  969. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  970. if (dac33->fifo_mode) {
  971. dac33->state = DAC33_FLUSH;
  972. queue_work(dac33->dac33_wq, &dac33->work);
  973. }
  974. break;
  975. default:
  976. ret = -EINVAL;
  977. }
  978. return ret;
  979. }
  980. static snd_pcm_sframes_t dac33_dai_delay(
  981. struct snd_pcm_substream *substream,
  982. struct snd_soc_dai *dai)
  983. {
  984. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  985. struct snd_soc_device *socdev = rtd->socdev;
  986. struct snd_soc_codec *codec = socdev->card->codec;
  987. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  988. unsigned long long t0, t1, t_now;
  989. unsigned int time_delta, uthr;
  990. int samples_out, samples_in, samples;
  991. snd_pcm_sframes_t delay = 0;
  992. switch (dac33->fifo_mode) {
  993. case DAC33_FIFO_BYPASS:
  994. break;
  995. case DAC33_FIFO_MODE1:
  996. spin_lock(&dac33->lock);
  997. t0 = dac33->t_stamp1;
  998. t1 = dac33->t_stamp2;
  999. spin_unlock(&dac33->lock);
  1000. t_now = ktime_to_us(ktime_get());
  1001. /* We have not started to fill the FIFO yet, delay is 0 */
  1002. if (!t1)
  1003. goto out;
  1004. if (t0 > t1) {
  1005. /*
  1006. * Phase 1:
  1007. * After Alarm threshold, and before nSample write
  1008. */
  1009. time_delta = t_now - t0;
  1010. samples_out = time_delta ? US_TO_SAMPLES(
  1011. substream->runtime->rate,
  1012. time_delta) : 0;
  1013. if (likely(dac33->alarm_threshold > samples_out))
  1014. delay = dac33->alarm_threshold - samples_out;
  1015. else
  1016. delay = 0;
  1017. } else if ((t_now - t1) <= dac33->mode1_us_burst) {
  1018. /*
  1019. * Phase 2:
  1020. * After nSample write (during burst operation)
  1021. */
  1022. time_delta = t_now - t0;
  1023. samples_out = time_delta ? US_TO_SAMPLES(
  1024. substream->runtime->rate,
  1025. time_delta) : 0;
  1026. time_delta = t_now - t1;
  1027. samples_in = time_delta ? US_TO_SAMPLES(
  1028. dac33->burst_rate,
  1029. time_delta) : 0;
  1030. samples = dac33->alarm_threshold;
  1031. samples += (samples_in - samples_out);
  1032. if (likely(samples > 0))
  1033. delay = samples;
  1034. else
  1035. delay = 0;
  1036. } else {
  1037. /*
  1038. * Phase 3:
  1039. * After burst operation, before next alarm threshold
  1040. */
  1041. time_delta = t_now - t0;
  1042. samples_out = time_delta ? US_TO_SAMPLES(
  1043. substream->runtime->rate,
  1044. time_delta) : 0;
  1045. samples_in = dac33->nsample;
  1046. samples = dac33->alarm_threshold;
  1047. samples += (samples_in - samples_out);
  1048. if (likely(samples > 0))
  1049. delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
  1050. DAC33_BUFFER_SIZE_SAMPLES : samples;
  1051. else
  1052. delay = 0;
  1053. }
  1054. break;
  1055. case DAC33_FIFO_MODE7:
  1056. spin_lock(&dac33->lock);
  1057. t0 = dac33->t_stamp1;
  1058. uthr = dac33->uthr;
  1059. spin_unlock(&dac33->lock);
  1060. t_now = ktime_to_us(ktime_get());
  1061. /* We have not started to fill the FIFO yet, delay is 0 */
  1062. if (!t0)
  1063. goto out;
  1064. if (t_now <= t0) {
  1065. /*
  1066. * Either the timestamps are messed or equal. Report
  1067. * maximum delay
  1068. */
  1069. delay = uthr;
  1070. goto out;
  1071. }
  1072. time_delta = t_now - t0;
  1073. if (time_delta <= dac33->mode7_us_to_lthr) {
  1074. /*
  1075. * Phase 1:
  1076. * After burst (draining phase)
  1077. */
  1078. samples_out = US_TO_SAMPLES(
  1079. substream->runtime->rate,
  1080. time_delta);
  1081. if (likely(uthr > samples_out))
  1082. delay = uthr - samples_out;
  1083. else
  1084. delay = 0;
  1085. } else {
  1086. /*
  1087. * Phase 2:
  1088. * During burst operation
  1089. */
  1090. time_delta = time_delta - dac33->mode7_us_to_lthr;
  1091. samples_out = US_TO_SAMPLES(
  1092. substream->runtime->rate,
  1093. time_delta);
  1094. samples_in = US_TO_SAMPLES(
  1095. dac33->burst_rate,
  1096. time_delta);
  1097. delay = MODE7_LTHR + samples_in - samples_out;
  1098. if (unlikely(delay > uthr))
  1099. delay = uthr;
  1100. }
  1101. break;
  1102. default:
  1103. dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
  1104. dac33->fifo_mode);
  1105. break;
  1106. }
  1107. out:
  1108. return delay;
  1109. }
  1110. static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1111. int clk_id, unsigned int freq, int dir)
  1112. {
  1113. struct snd_soc_codec *codec = codec_dai->codec;
  1114. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  1115. u8 ioc_reg, asrcb_reg;
  1116. ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
  1117. asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
  1118. switch (clk_id) {
  1119. case TLV320DAC33_MCLK:
  1120. ioc_reg |= DAC33_REFSEL;
  1121. asrcb_reg |= DAC33_SRCREFSEL;
  1122. break;
  1123. case TLV320DAC33_SLEEPCLK:
  1124. ioc_reg &= ~DAC33_REFSEL;
  1125. asrcb_reg &= ~DAC33_SRCREFSEL;
  1126. break;
  1127. default:
  1128. dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
  1129. break;
  1130. }
  1131. dac33->refclk = freq;
  1132. dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
  1133. dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
  1134. return 0;
  1135. }
  1136. static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1137. unsigned int fmt)
  1138. {
  1139. struct snd_soc_codec *codec = codec_dai->codec;
  1140. struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
  1141. u8 aictrl_a, aictrl_b;
  1142. aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
  1143. aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
  1144. /* set master/slave audio interface */
  1145. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1146. case SND_SOC_DAIFMT_CBM_CFM:
  1147. /* Codec Master */
  1148. aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
  1149. break;
  1150. case SND_SOC_DAIFMT_CBS_CFS:
  1151. /* Codec Slave */
  1152. if (dac33->fifo_mode) {
  1153. dev_err(codec->dev, "FIFO mode requires master mode\n");
  1154. return -EINVAL;
  1155. } else
  1156. aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
  1157. break;
  1158. default:
  1159. return -EINVAL;
  1160. }
  1161. aictrl_a &= ~DAC33_AFMT_MASK;
  1162. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1163. case SND_SOC_DAIFMT_I2S:
  1164. aictrl_a |= DAC33_AFMT_I2S;
  1165. break;
  1166. case SND_SOC_DAIFMT_DSP_A:
  1167. aictrl_a |= DAC33_AFMT_DSP;
  1168. aictrl_b &= ~DAC33_DATA_DELAY_MASK;
  1169. aictrl_b |= DAC33_DATA_DELAY(0);
  1170. break;
  1171. case SND_SOC_DAIFMT_RIGHT_J:
  1172. aictrl_a |= DAC33_AFMT_RIGHT_J;
  1173. break;
  1174. case SND_SOC_DAIFMT_LEFT_J:
  1175. aictrl_a |= DAC33_AFMT_LEFT_J;
  1176. break;
  1177. default:
  1178. dev_err(codec->dev, "Unsupported format (%u)\n",
  1179. fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1180. return -EINVAL;
  1181. }
  1182. dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  1183. dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
  1184. return 0;
  1185. }
  1186. static int dac33_soc_probe(struct platform_device *pdev)
  1187. {
  1188. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1189. struct snd_soc_codec *codec;
  1190. struct tlv320dac33_priv *dac33;
  1191. int ret = 0;
  1192. BUG_ON(!tlv320dac33_codec);
  1193. codec = tlv320dac33_codec;
  1194. socdev->card->codec = codec;
  1195. dac33 = snd_soc_codec_get_drvdata(codec);
  1196. /* register pcms */
  1197. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1198. if (ret < 0) {
  1199. dev_err(codec->dev, "failed to create pcms\n");
  1200. goto pcm_err;
  1201. }
  1202. snd_soc_add_controls(codec, dac33_snd_controls,
  1203. ARRAY_SIZE(dac33_snd_controls));
  1204. /* Only add the FIFO controls, if we have valid IRQ number */
  1205. if (dac33->irq >= 0) {
  1206. snd_soc_add_controls(codec, dac33_mode_snd_controls,
  1207. ARRAY_SIZE(dac33_mode_snd_controls));
  1208. /* FIFO usage controls only, if autoio config is not selected */
  1209. if (!dac33->auto_fifo_config)
  1210. snd_soc_add_controls(codec, dac33_fifo_snd_controls,
  1211. ARRAY_SIZE(dac33_fifo_snd_controls));
  1212. }
  1213. dac33_add_widgets(codec);
  1214. return 0;
  1215. pcm_err:
  1216. dac33_hard_power(codec, 0);
  1217. return ret;
  1218. }
  1219. static int dac33_soc_remove(struct platform_device *pdev)
  1220. {
  1221. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1222. struct snd_soc_codec *codec = socdev->card->codec;
  1223. dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1224. snd_soc_free_pcms(socdev);
  1225. snd_soc_dapm_free(socdev);
  1226. return 0;
  1227. }
  1228. static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1229. {
  1230. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1231. struct snd_soc_codec *codec = socdev->card->codec;
  1232. dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1233. return 0;
  1234. }
  1235. static int dac33_soc_resume(struct platform_device *pdev)
  1236. {
  1237. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1238. struct snd_soc_codec *codec = socdev->card->codec;
  1239. dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1240. return 0;
  1241. }
  1242. struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
  1243. .probe = dac33_soc_probe,
  1244. .remove = dac33_soc_remove,
  1245. .suspend = dac33_soc_suspend,
  1246. .resume = dac33_soc_resume,
  1247. };
  1248. EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
  1249. #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
  1250. SNDRV_PCM_RATE_48000)
  1251. #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  1252. static struct snd_soc_dai_ops dac33_dai_ops = {
  1253. .startup = dac33_startup,
  1254. .shutdown = dac33_shutdown,
  1255. .hw_params = dac33_hw_params,
  1256. .trigger = dac33_pcm_trigger,
  1257. .delay = dac33_dai_delay,
  1258. .set_sysclk = dac33_set_dai_sysclk,
  1259. .set_fmt = dac33_set_dai_fmt,
  1260. };
  1261. struct snd_soc_dai dac33_dai = {
  1262. .name = "tlv320dac33",
  1263. .playback = {
  1264. .stream_name = "Playback",
  1265. .channels_min = 2,
  1266. .channels_max = 2,
  1267. .rates = DAC33_RATES,
  1268. .formats = DAC33_FORMATS,},
  1269. .ops = &dac33_dai_ops,
  1270. };
  1271. EXPORT_SYMBOL_GPL(dac33_dai);
  1272. static int __devinit dac33_i2c_probe(struct i2c_client *client,
  1273. const struct i2c_device_id *id)
  1274. {
  1275. struct tlv320dac33_platform_data *pdata;
  1276. struct tlv320dac33_priv *dac33;
  1277. struct snd_soc_codec *codec;
  1278. int ret, i;
  1279. if (client->dev.platform_data == NULL) {
  1280. dev_err(&client->dev, "Platform data not set\n");
  1281. return -ENODEV;
  1282. }
  1283. pdata = client->dev.platform_data;
  1284. dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
  1285. if (dac33 == NULL)
  1286. return -ENOMEM;
  1287. codec = &dac33->codec;
  1288. snd_soc_codec_set_drvdata(codec, dac33);
  1289. codec->control_data = client;
  1290. mutex_init(&codec->mutex);
  1291. mutex_init(&dac33->mutex);
  1292. spin_lock_init(&dac33->lock);
  1293. INIT_LIST_HEAD(&codec->dapm_widgets);
  1294. INIT_LIST_HEAD(&codec->dapm_paths);
  1295. codec->name = "tlv320dac33";
  1296. codec->owner = THIS_MODULE;
  1297. codec->read = dac33_read_reg_cache;
  1298. codec->write = dac33_write_locked;
  1299. codec->hw_write = (hw_write_t) i2c_master_send;
  1300. codec->bias_level = SND_SOC_BIAS_OFF;
  1301. codec->set_bias_level = dac33_set_bias_level;
  1302. codec->idle_bias_off = 1;
  1303. codec->dai = &dac33_dai;
  1304. codec->num_dai = 1;
  1305. codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
  1306. codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
  1307. GFP_KERNEL);
  1308. if (codec->reg_cache == NULL) {
  1309. ret = -ENOMEM;
  1310. goto error_reg;
  1311. }
  1312. i2c_set_clientdata(client, dac33);
  1313. dac33->power_gpio = pdata->power_gpio;
  1314. dac33->burst_bclkdiv = pdata->burst_bclkdiv;
  1315. /* Pre calculate the burst rate */
  1316. dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
  1317. dac33->keep_bclk = pdata->keep_bclk;
  1318. dac33->auto_fifo_config = pdata->auto_fifo_config;
  1319. dac33->mode1_latency = pdata->mode1_latency;
  1320. if (!dac33->mode1_latency)
  1321. dac33->mode1_latency = 10000; /* 10ms */
  1322. dac33->irq = client->irq;
  1323. dac33->nsample = NSAMPLE_MAX;
  1324. dac33->nsample_max = NSAMPLE_MAX;
  1325. dac33->uthr = MODE7_UTHR;
  1326. /* Disable FIFO use by default */
  1327. dac33->fifo_mode = DAC33_FIFO_BYPASS;
  1328. tlv320dac33_codec = codec;
  1329. codec->dev = &client->dev;
  1330. dac33_dai.dev = codec->dev;
  1331. /* Check if the reset GPIO number is valid and request it */
  1332. if (dac33->power_gpio >= 0) {
  1333. ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
  1334. if (ret < 0) {
  1335. dev_err(codec->dev,
  1336. "Failed to request reset GPIO (%d)\n",
  1337. dac33->power_gpio);
  1338. snd_soc_unregister_dai(&dac33_dai);
  1339. snd_soc_unregister_codec(codec);
  1340. goto error_gpio;
  1341. }
  1342. gpio_direction_output(dac33->power_gpio, 0);
  1343. }
  1344. /* Check if the IRQ number is valid and request it */
  1345. if (dac33->irq >= 0) {
  1346. ret = request_irq(dac33->irq, dac33_interrupt_handler,
  1347. IRQF_TRIGGER_RISING | IRQF_DISABLED,
  1348. codec->name, codec);
  1349. if (ret < 0) {
  1350. dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
  1351. dac33->irq, ret);
  1352. dac33->irq = -1;
  1353. }
  1354. if (dac33->irq != -1) {
  1355. /* Setup work queue */
  1356. dac33->dac33_wq =
  1357. create_singlethread_workqueue("tlv320dac33");
  1358. if (dac33->dac33_wq == NULL) {
  1359. free_irq(dac33->irq, &dac33->codec);
  1360. ret = -ENOMEM;
  1361. goto error_wq;
  1362. }
  1363. INIT_WORK(&dac33->work, dac33_work);
  1364. }
  1365. }
  1366. for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
  1367. dac33->supplies[i].supply = dac33_supply_names[i];
  1368. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
  1369. dac33->supplies);
  1370. if (ret != 0) {
  1371. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1372. goto err_get;
  1373. }
  1374. /* Read the tlv320dac33 ID registers */
  1375. ret = dac33_hard_power(codec, 1);
  1376. if (ret != 0) {
  1377. dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
  1378. goto error_codec;
  1379. }
  1380. dac33_read_id(codec);
  1381. dac33_hard_power(codec, 0);
  1382. ret = snd_soc_register_codec(codec);
  1383. if (ret != 0) {
  1384. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1385. goto error_codec;
  1386. }
  1387. ret = snd_soc_register_dai(&dac33_dai);
  1388. if (ret != 0) {
  1389. dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
  1390. snd_soc_unregister_codec(codec);
  1391. goto error_codec;
  1392. }
  1393. return ret;
  1394. error_codec:
  1395. regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
  1396. err_get:
  1397. if (dac33->irq >= 0) {
  1398. free_irq(dac33->irq, &dac33->codec);
  1399. destroy_workqueue(dac33->dac33_wq);
  1400. }
  1401. error_wq:
  1402. if (dac33->power_gpio >= 0)
  1403. gpio_free(dac33->power_gpio);
  1404. error_gpio:
  1405. kfree(codec->reg_cache);
  1406. error_reg:
  1407. tlv320dac33_codec = NULL;
  1408. kfree(dac33);
  1409. return ret;
  1410. }
  1411. static int __devexit dac33_i2c_remove(struct i2c_client *client)
  1412. {
  1413. struct tlv320dac33_priv *dac33;
  1414. dac33 = i2c_get_clientdata(client);
  1415. if (unlikely(dac33->chip_power))
  1416. dac33_hard_power(&dac33->codec, 0);
  1417. if (dac33->power_gpio >= 0)
  1418. gpio_free(dac33->power_gpio);
  1419. if (dac33->irq >= 0)
  1420. free_irq(dac33->irq, &dac33->codec);
  1421. regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
  1422. destroy_workqueue(dac33->dac33_wq);
  1423. snd_soc_unregister_dai(&dac33_dai);
  1424. snd_soc_unregister_codec(&dac33->codec);
  1425. kfree(dac33->codec.reg_cache);
  1426. kfree(dac33);
  1427. tlv320dac33_codec = NULL;
  1428. return 0;
  1429. }
  1430. static const struct i2c_device_id tlv320dac33_i2c_id[] = {
  1431. {
  1432. .name = "tlv320dac33",
  1433. .driver_data = 0,
  1434. },
  1435. { },
  1436. };
  1437. static struct i2c_driver tlv320dac33_i2c_driver = {
  1438. .driver = {
  1439. .name = "tlv320dac33",
  1440. .owner = THIS_MODULE,
  1441. },
  1442. .probe = dac33_i2c_probe,
  1443. .remove = __devexit_p(dac33_i2c_remove),
  1444. .id_table = tlv320dac33_i2c_id,
  1445. };
  1446. static int __init dac33_module_init(void)
  1447. {
  1448. int r;
  1449. r = i2c_add_driver(&tlv320dac33_i2c_driver);
  1450. if (r < 0) {
  1451. printk(KERN_ERR "DAC33: driver registration failed\n");
  1452. return r;
  1453. }
  1454. return 0;
  1455. }
  1456. module_init(dac33_module_init);
  1457. static void __exit dac33_module_exit(void)
  1458. {
  1459. i2c_del_driver(&tlv320dac33_i2c_driver);
  1460. }
  1461. module_exit(dac33_module_exit);
  1462. MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
  1463. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
  1464. MODULE_LICENSE("GPL");