tlv320aic3x.c 47 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501
  1. /*
  2. * ALSA SoC TLV320AIC3X codec driver
  3. *
  4. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  5. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  6. *
  7. * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * Notes:
  14. * The AIC3X is a driver for a low power stereo audio
  15. * codecs aic31, aic32, aic33.
  16. *
  17. * It supports full aic33 codec functionality.
  18. * The compatibility with aic32, aic31 is as follows:
  19. * aic32 | aic31
  20. * ---------------------------------------
  21. * MONO_LOUT -> N/A | MONO_LOUT -> N/A
  22. * | IN1L -> LINE1L
  23. * | IN1R -> LINE1R
  24. * | IN2L -> LINE2L
  25. * | IN2R -> LINE2R
  26. * | MIC3L/R -> N/A
  27. * truncated internal functionality in
  28. * accordance with documentation
  29. * ---------------------------------------
  30. *
  31. * Hence the machine layer should disable unsupported inputs/outputs by
  32. * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/init.h>
  37. #include <linux/delay.h>
  38. #include <linux/pm.h>
  39. #include <linux/i2c.h>
  40. #include <linux/gpio.h>
  41. #include <linux/regulator/consumer.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/slab.h>
  44. #include <sound/core.h>
  45. #include <sound/pcm.h>
  46. #include <sound/pcm_params.h>
  47. #include <sound/soc.h>
  48. #include <sound/soc-dapm.h>
  49. #include <sound/initval.h>
  50. #include <sound/tlv.h>
  51. #include <sound/tlv320aic3x.h>
  52. #include "tlv320aic3x.h"
  53. #define AIC3X_NUM_SUPPLIES 4
  54. static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
  55. "IOVDD", /* I/O Voltage */
  56. "DVDD", /* Digital Core Voltage */
  57. "AVDD", /* Analog DAC Voltage */
  58. "DRVDD", /* ADC Analog and Output Driver Voltage */
  59. };
  60. /* codec private data */
  61. struct aic3x_priv {
  62. struct snd_soc_codec codec;
  63. struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
  64. unsigned int sysclk;
  65. int master;
  66. int gpio_reset;
  67. };
  68. /*
  69. * AIC3X register cache
  70. * We can't read the AIC3X register space when we are
  71. * using 2 wire for device control, so we cache them instead.
  72. * There is no point in caching the reset register
  73. */
  74. static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
  75. 0x00, 0x00, 0x00, 0x10, /* 0 */
  76. 0x04, 0x00, 0x00, 0x00, /* 4 */
  77. 0x00, 0x00, 0x00, 0x01, /* 8 */
  78. 0x00, 0x00, 0x00, 0x80, /* 12 */
  79. 0x80, 0xff, 0xff, 0x78, /* 16 */
  80. 0x78, 0x78, 0x78, 0x78, /* 20 */
  81. 0x78, 0x00, 0x00, 0xfe, /* 24 */
  82. 0x00, 0x00, 0xfe, 0x00, /* 28 */
  83. 0x18, 0x18, 0x00, 0x00, /* 32 */
  84. 0x00, 0x00, 0x00, 0x00, /* 36 */
  85. 0x00, 0x00, 0x00, 0x80, /* 40 */
  86. 0x80, 0x00, 0x00, 0x00, /* 44 */
  87. 0x00, 0x00, 0x00, 0x04, /* 48 */
  88. 0x00, 0x00, 0x00, 0x00, /* 52 */
  89. 0x00, 0x00, 0x04, 0x00, /* 56 */
  90. 0x00, 0x00, 0x00, 0x00, /* 60 */
  91. 0x00, 0x04, 0x00, 0x00, /* 64 */
  92. 0x00, 0x00, 0x00, 0x00, /* 68 */
  93. 0x04, 0x00, 0x00, 0x00, /* 72 */
  94. 0x00, 0x00, 0x00, 0x00, /* 76 */
  95. 0x00, 0x00, 0x00, 0x00, /* 80 */
  96. 0x00, 0x00, 0x00, 0x00, /* 84 */
  97. 0x00, 0x00, 0x00, 0x00, /* 88 */
  98. 0x00, 0x00, 0x00, 0x00, /* 92 */
  99. 0x00, 0x00, 0x00, 0x00, /* 96 */
  100. 0x00, 0x00, 0x02, /* 100 */
  101. };
  102. /*
  103. * read aic3x register cache
  104. */
  105. static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
  106. unsigned int reg)
  107. {
  108. u8 *cache = codec->reg_cache;
  109. if (reg >= AIC3X_CACHEREGNUM)
  110. return -1;
  111. return cache[reg];
  112. }
  113. /*
  114. * write aic3x register cache
  115. */
  116. static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
  117. u8 reg, u8 value)
  118. {
  119. u8 *cache = codec->reg_cache;
  120. if (reg >= AIC3X_CACHEREGNUM)
  121. return;
  122. cache[reg] = value;
  123. }
  124. /*
  125. * write to the aic3x register space
  126. */
  127. static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
  128. unsigned int value)
  129. {
  130. u8 data[2];
  131. /* data is
  132. * D15..D8 aic3x register offset
  133. * D7...D0 register data
  134. */
  135. data[0] = reg & 0xff;
  136. data[1] = value & 0xff;
  137. aic3x_write_reg_cache(codec, data[0], data[1]);
  138. if (codec->hw_write(codec->control_data, data, 2) == 2)
  139. return 0;
  140. else
  141. return -EIO;
  142. }
  143. /*
  144. * read from the aic3x register space
  145. */
  146. static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
  147. u8 *value)
  148. {
  149. *value = reg & 0xff;
  150. value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
  151. aic3x_write_reg_cache(codec, reg, *value);
  152. return 0;
  153. }
  154. #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
  155. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  156. .info = snd_soc_info_volsw, \
  157. .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
  158. .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
  159. /*
  160. * All input lines are connected when !0xf and disconnected with 0xf bit field,
  161. * so we have to use specific dapm_put call for input mixer
  162. */
  163. static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
  164. struct snd_ctl_elem_value *ucontrol)
  165. {
  166. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  167. struct soc_mixer_control *mc =
  168. (struct soc_mixer_control *)kcontrol->private_value;
  169. unsigned int reg = mc->reg;
  170. unsigned int shift = mc->shift;
  171. int max = mc->max;
  172. unsigned int mask = (1 << fls(max)) - 1;
  173. unsigned int invert = mc->invert;
  174. unsigned short val, val_mask;
  175. int ret;
  176. struct snd_soc_dapm_path *path;
  177. int found = 0;
  178. val = (ucontrol->value.integer.value[0] & mask);
  179. mask = 0xf;
  180. if (val)
  181. val = mask;
  182. if (invert)
  183. val = mask - val;
  184. val_mask = mask << shift;
  185. val = val << shift;
  186. mutex_lock(&widget->codec->mutex);
  187. if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
  188. /* find dapm widget path assoc with kcontrol */
  189. list_for_each_entry(path, &widget->codec->dapm_paths, list) {
  190. if (path->kcontrol != kcontrol)
  191. continue;
  192. /* found, now check type */
  193. found = 1;
  194. if (val)
  195. /* new connection */
  196. path->connect = invert ? 0 : 1;
  197. else
  198. /* old connection must be powered down */
  199. path->connect = invert ? 1 : 0;
  200. break;
  201. }
  202. if (found)
  203. snd_soc_dapm_sync(widget->codec);
  204. }
  205. ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
  206. mutex_unlock(&widget->codec->mutex);
  207. return ret;
  208. }
  209. static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
  210. static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
  211. static const char *aic3x_left_hpcom_mux[] =
  212. { "differential of HPLOUT", "constant VCM", "single-ended" };
  213. static const char *aic3x_right_hpcom_mux[] =
  214. { "differential of HPROUT", "constant VCM", "single-ended",
  215. "differential of HPLCOM", "external feedback" };
  216. static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
  217. static const char *aic3x_adc_hpf[] =
  218. { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
  219. #define LDAC_ENUM 0
  220. #define RDAC_ENUM 1
  221. #define LHPCOM_ENUM 2
  222. #define RHPCOM_ENUM 3
  223. #define LINE1L_ENUM 4
  224. #define LINE1R_ENUM 5
  225. #define LINE2L_ENUM 6
  226. #define LINE2R_ENUM 7
  227. #define ADC_HPF_ENUM 8
  228. static const struct soc_enum aic3x_enum[] = {
  229. SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
  230. SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
  231. SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
  232. SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
  233. SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  234. SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  235. SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  236. SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  237. SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
  238. };
  239. /*
  240. * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
  241. */
  242. static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
  243. /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
  244. static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
  245. /*
  246. * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
  247. * Step size is approximately 0.5 dB over most of the scale but increasing
  248. * near the very low levels.
  249. * Define dB scale so that it is mostly correct for range about -55 to 0 dB
  250. * but having increasing dB difference below that (and where it doesn't count
  251. * so much). This setting shows -50 dB (actual is -50.3 dB) for register
  252. * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
  253. */
  254. static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
  255. static const struct snd_kcontrol_new aic3x_snd_controls[] = {
  256. /* Output */
  257. SOC_DOUBLE_R_TLV("PCM Playback Volume",
  258. LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
  259. SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
  260. DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
  261. 0, 118, 1, output_stage_tlv),
  262. SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
  263. SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
  264. SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
  265. DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
  266. 0, 118, 1, output_stage_tlv),
  267. SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
  268. PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  269. SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
  270. PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  271. SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
  272. LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
  273. 0, 118, 1, output_stage_tlv),
  274. SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
  275. LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
  276. 0, 118, 1, output_stage_tlv),
  277. SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
  278. DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
  279. 0, 118, 1, output_stage_tlv),
  280. SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
  281. SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
  282. PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
  283. 0, 118, 1, output_stage_tlv),
  284. SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
  285. LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
  286. 0, 118, 1, output_stage_tlv),
  287. SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
  288. DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
  289. 0, 118, 1, output_stage_tlv),
  290. SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
  291. 0x01, 0),
  292. SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
  293. PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
  294. 0, 118, 1, output_stage_tlv),
  295. SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
  296. PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  297. SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
  298. PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  299. SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
  300. LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
  301. 0, 118, 1, output_stage_tlv),
  302. SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
  303. DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
  304. 0, 118, 1, output_stage_tlv),
  305. SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
  306. 0x01, 0),
  307. SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
  308. PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  309. SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
  310. PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  311. SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
  312. LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
  313. 0, 118, 1, output_stage_tlv),
  314. /*
  315. * Note: enable Automatic input Gain Controller with care. It can
  316. * adjust PGA to max value when ADC is on and will never go back.
  317. */
  318. SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
  319. /* Input */
  320. SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
  321. 0, 119, 0, adc_tlv),
  322. SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
  323. SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
  324. };
  325. /* Left DAC Mux */
  326. static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
  327. SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
  328. /* Right DAC Mux */
  329. static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
  330. SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
  331. /* Left HPCOM Mux */
  332. static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
  333. SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
  334. /* Right HPCOM Mux */
  335. static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
  336. SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
  337. /* Left DAC_L1 Mixer */
  338. static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
  339. SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
  340. SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
  341. SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
  342. SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
  343. SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
  344. };
  345. /* Right DAC_R1 Mixer */
  346. static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
  347. SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
  348. SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
  349. SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
  350. SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
  351. SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
  352. };
  353. /* Left PGA Mixer */
  354. static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
  355. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
  356. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
  357. SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
  358. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
  359. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
  360. };
  361. /* Right PGA Mixer */
  362. static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
  363. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
  364. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
  365. SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
  366. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
  367. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
  368. };
  369. /* Left Line1 Mux */
  370. static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
  371. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
  372. /* Right Line1 Mux */
  373. static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
  374. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
  375. /* Left Line2 Mux */
  376. static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
  377. SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
  378. /* Right Line2 Mux */
  379. static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
  380. SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
  381. /* Left PGA Bypass Mixer */
  382. static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
  383. SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
  384. SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
  385. SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
  386. SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
  387. SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
  388. SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
  389. SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
  390. };
  391. /* Right PGA Bypass Mixer */
  392. static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
  393. SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
  394. SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
  395. SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
  396. SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
  397. SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
  398. SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
  399. SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
  400. };
  401. /* Left Line2 Bypass Mixer */
  402. static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
  403. SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
  404. SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
  405. SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
  406. SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
  407. SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
  408. };
  409. /* Right Line2 Bypass Mixer */
  410. static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
  411. SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
  412. SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
  413. SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
  414. SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
  415. SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
  416. };
  417. static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
  418. /* Left DAC to Left Outputs */
  419. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
  420. SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
  421. &aic3x_left_dac_mux_controls),
  422. SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
  423. &aic3x_left_dac_mixer_controls[0],
  424. ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
  425. SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
  426. &aic3x_left_hpcom_mux_controls),
  427. SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
  428. SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
  429. SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
  430. /* Right DAC to Right Outputs */
  431. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
  432. SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
  433. &aic3x_right_dac_mux_controls),
  434. SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
  435. &aic3x_right_dac_mixer_controls[0],
  436. ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
  437. SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
  438. &aic3x_right_hpcom_mux_controls),
  439. SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
  440. SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
  441. SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
  442. /* Mono Output */
  443. SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
  444. /* Inputs to Left ADC */
  445. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
  446. SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
  447. &aic3x_left_pga_mixer_controls[0],
  448. ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
  449. SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
  450. &aic3x_left_line1_mux_controls),
  451. SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
  452. &aic3x_left_line1_mux_controls),
  453. SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
  454. &aic3x_left_line2_mux_controls),
  455. /* Inputs to Right ADC */
  456. SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
  457. LINE1R_2_RADC_CTRL, 2, 0),
  458. SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
  459. &aic3x_right_pga_mixer_controls[0],
  460. ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
  461. SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
  462. &aic3x_right_line1_mux_controls),
  463. SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
  464. &aic3x_right_line1_mux_controls),
  465. SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
  466. &aic3x_right_line2_mux_controls),
  467. /*
  468. * Not a real mic bias widget but similar function. This is for dynamic
  469. * control of GPIO1 digital mic modulator clock output function when
  470. * using digital mic.
  471. */
  472. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
  473. AIC3X_GPIO1_REG, 4, 0xf,
  474. AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
  475. AIC3X_GPIO1_FUNC_DISABLED),
  476. /*
  477. * Also similar function like mic bias. Selects digital mic with
  478. * configurable oversampling rate instead of ADC converter.
  479. */
  480. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
  481. AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
  482. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
  483. AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
  484. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
  485. AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
  486. /* Mic Bias */
  487. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
  488. MICBIAS_CTRL, 6, 3, 1, 0),
  489. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
  490. MICBIAS_CTRL, 6, 3, 2, 0),
  491. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
  492. MICBIAS_CTRL, 6, 3, 3, 0),
  493. /* Left PGA to Left Output bypass */
  494. SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
  495. &aic3x_left_pga_bp_mixer_controls[0],
  496. ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
  497. /* Right PGA to Right Output bypass */
  498. SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
  499. &aic3x_right_pga_bp_mixer_controls[0],
  500. ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
  501. /* Left Line2 to Left Output bypass */
  502. SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
  503. &aic3x_left_line2_bp_mixer_controls[0],
  504. ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
  505. /* Right Line2 to Right Output bypass */
  506. SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
  507. &aic3x_right_line2_bp_mixer_controls[0],
  508. ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
  509. SND_SOC_DAPM_OUTPUT("LLOUT"),
  510. SND_SOC_DAPM_OUTPUT("RLOUT"),
  511. SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
  512. SND_SOC_DAPM_OUTPUT("HPLOUT"),
  513. SND_SOC_DAPM_OUTPUT("HPROUT"),
  514. SND_SOC_DAPM_OUTPUT("HPLCOM"),
  515. SND_SOC_DAPM_OUTPUT("HPRCOM"),
  516. SND_SOC_DAPM_INPUT("MIC3L"),
  517. SND_SOC_DAPM_INPUT("MIC3R"),
  518. SND_SOC_DAPM_INPUT("LINE1L"),
  519. SND_SOC_DAPM_INPUT("LINE1R"),
  520. SND_SOC_DAPM_INPUT("LINE2L"),
  521. SND_SOC_DAPM_INPUT("LINE2R"),
  522. };
  523. static const struct snd_soc_dapm_route intercon[] = {
  524. /* Left Output */
  525. {"Left DAC Mux", "DAC_L1", "Left DAC"},
  526. {"Left DAC Mux", "DAC_L2", "Left DAC"},
  527. {"Left DAC Mux", "DAC_L3", "Left DAC"},
  528. {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
  529. {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
  530. {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
  531. {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
  532. {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
  533. {"Left Line Out", NULL, "Left DAC Mux"},
  534. {"Left HP Out", NULL, "Left DAC Mux"},
  535. {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
  536. {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
  537. {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
  538. {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
  539. {"Mono Out", NULL, "Left DAC_L1 Mixer"},
  540. {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
  541. {"Left HP Com", NULL, "Left HPCOM Mux"},
  542. {"LLOUT", NULL, "Left Line Out"},
  543. {"LLOUT", NULL, "Left Line Out"},
  544. {"HPLOUT", NULL, "Left HP Out"},
  545. {"HPLCOM", NULL, "Left HP Com"},
  546. /* Right Output */
  547. {"Right DAC Mux", "DAC_R1", "Right DAC"},
  548. {"Right DAC Mux", "DAC_R2", "Right DAC"},
  549. {"Right DAC Mux", "DAC_R3", "Right DAC"},
  550. {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
  551. {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
  552. {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
  553. {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
  554. {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
  555. {"Right Line Out", NULL, "Right DAC Mux"},
  556. {"Right HP Out", NULL, "Right DAC Mux"},
  557. {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
  558. {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
  559. {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
  560. {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
  561. {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
  562. {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
  563. {"Mono Out", NULL, "Right DAC_R1 Mixer"},
  564. {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
  565. {"Right HP Com", NULL, "Right HPCOM Mux"},
  566. {"RLOUT", NULL, "Right Line Out"},
  567. {"RLOUT", NULL, "Right Line Out"},
  568. {"HPROUT", NULL, "Right HP Out"},
  569. {"HPRCOM", NULL, "Right HP Com"},
  570. /* Mono Output */
  571. {"MONO_LOUT", NULL, "Mono Out"},
  572. {"MONO_LOUT", NULL, "Mono Out"},
  573. /* Left Input */
  574. {"Left Line1L Mux", "single-ended", "LINE1L"},
  575. {"Left Line1L Mux", "differential", "LINE1L"},
  576. {"Left Line2L Mux", "single-ended", "LINE2L"},
  577. {"Left Line2L Mux", "differential", "LINE2L"},
  578. {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
  579. {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
  580. {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
  581. {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
  582. {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
  583. {"Left ADC", NULL, "Left PGA Mixer"},
  584. {"Left ADC", NULL, "GPIO1 dmic modclk"},
  585. /* Right Input */
  586. {"Right Line1R Mux", "single-ended", "LINE1R"},
  587. {"Right Line1R Mux", "differential", "LINE1R"},
  588. {"Right Line2R Mux", "single-ended", "LINE2R"},
  589. {"Right Line2R Mux", "differential", "LINE2R"},
  590. {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
  591. {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
  592. {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
  593. {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
  594. {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
  595. {"Right ADC", NULL, "Right PGA Mixer"},
  596. {"Right ADC", NULL, "GPIO1 dmic modclk"},
  597. /* Left PGA Bypass */
  598. {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
  599. {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
  600. {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
  601. {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
  602. {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
  603. {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
  604. {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
  605. {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
  606. {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
  607. {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
  608. {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
  609. {"Mono Out", NULL, "Left PGA Bypass Mixer"},
  610. {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
  611. /* Right PGA Bypass */
  612. {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
  613. {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
  614. {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
  615. {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
  616. {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
  617. {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
  618. {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
  619. {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
  620. {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
  621. {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
  622. {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
  623. {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
  624. {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
  625. {"Mono Out", NULL, "Right PGA Bypass Mixer"},
  626. {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
  627. /* Left Line2 Bypass */
  628. {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
  629. {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
  630. {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
  631. {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
  632. {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
  633. {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
  634. {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
  635. {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
  636. {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
  637. {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
  638. {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
  639. /* Right Line2 Bypass */
  640. {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
  641. {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
  642. {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
  643. {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
  644. {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
  645. {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
  646. {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
  647. {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
  648. {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
  649. {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
  650. {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
  651. {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
  652. {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
  653. /*
  654. * Logical path between digital mic enable and GPIO1 modulator clock
  655. * output function
  656. */
  657. {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
  658. {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
  659. {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
  660. };
  661. static int aic3x_add_widgets(struct snd_soc_codec *codec)
  662. {
  663. snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
  664. ARRAY_SIZE(aic3x_dapm_widgets));
  665. /* set up audio path interconnects */
  666. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  667. return 0;
  668. }
  669. static int aic3x_hw_params(struct snd_pcm_substream *substream,
  670. struct snd_pcm_hw_params *params,
  671. struct snd_soc_dai *dai)
  672. {
  673. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  674. struct snd_soc_device *socdev = rtd->socdev;
  675. struct snd_soc_codec *codec = socdev->card->codec;
  676. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  677. int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
  678. u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
  679. u16 d, pll_d = 1;
  680. u8 reg;
  681. int clk;
  682. /* select data word length */
  683. data =
  684. aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
  685. switch (params_format(params)) {
  686. case SNDRV_PCM_FORMAT_S16_LE:
  687. break;
  688. case SNDRV_PCM_FORMAT_S20_3LE:
  689. data |= (0x01 << 4);
  690. break;
  691. case SNDRV_PCM_FORMAT_S24_LE:
  692. data |= (0x02 << 4);
  693. break;
  694. case SNDRV_PCM_FORMAT_S32_LE:
  695. data |= (0x03 << 4);
  696. break;
  697. }
  698. aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
  699. /* Fsref can be 44100 or 48000 */
  700. fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
  701. /* Try to find a value for Q which allows us to bypass the PLL and
  702. * generate CODEC_CLK directly. */
  703. for (pll_q = 2; pll_q < 18; pll_q++)
  704. if (aic3x->sysclk / (128 * pll_q) == fsref) {
  705. bypass_pll = 1;
  706. break;
  707. }
  708. if (bypass_pll) {
  709. pll_q &= 0xf;
  710. aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
  711. aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
  712. /* disable PLL if it is bypassed */
  713. reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
  714. aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
  715. } else {
  716. aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
  717. /* enable PLL when it is used */
  718. reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
  719. aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
  720. }
  721. /* Route Left DAC to left channel input and
  722. * right DAC to right channel input */
  723. data = (LDAC2LCH | RDAC2RCH);
  724. data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
  725. if (params_rate(params) >= 64000)
  726. data |= DUAL_RATE_MODE;
  727. aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
  728. /* codec sample rate select */
  729. data = (fsref * 20) / params_rate(params);
  730. if (params_rate(params) < 64000)
  731. data /= 2;
  732. data /= 5;
  733. data -= 2;
  734. data |= (data << 4);
  735. aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
  736. if (bypass_pll)
  737. return 0;
  738. /* Use PLL, compute apropriate setup for j, d, r and p, the closest
  739. * one wins the game. Try with d==0 first, next with d!=0.
  740. * Constraints for j are according to the datasheet.
  741. * The sysclk is divided by 1000 to prevent integer overflows.
  742. */
  743. codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
  744. for (r = 1; r <= 16; r++)
  745. for (p = 1; p <= 8; p++) {
  746. for (j = 4; j <= 55; j++) {
  747. /* This is actually 1000*((j+(d/10000))*r)/p
  748. * The term had to be converted to get
  749. * rid of the division by 10000; d = 0 here
  750. */
  751. int tmp_clk = (1000 * j * r) / p;
  752. /* Check whether this values get closer than
  753. * the best ones we had before
  754. */
  755. if (abs(codec_clk - tmp_clk) <
  756. abs(codec_clk - last_clk)) {
  757. pll_j = j; pll_d = 0;
  758. pll_r = r; pll_p = p;
  759. last_clk = tmp_clk;
  760. }
  761. /* Early exit for exact matches */
  762. if (tmp_clk == codec_clk)
  763. goto found;
  764. }
  765. }
  766. /* try with d != 0 */
  767. for (p = 1; p <= 8; p++) {
  768. j = codec_clk * p / 1000;
  769. if (j < 4 || j > 11)
  770. continue;
  771. /* do not use codec_clk here since we'd loose precision */
  772. d = ((2048 * p * fsref) - j * aic3x->sysclk)
  773. * 100 / (aic3x->sysclk/100);
  774. clk = (10000 * j + d) / (10 * p);
  775. /* check whether this values get closer than the best
  776. * ones we had before */
  777. if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
  778. pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
  779. last_clk = clk;
  780. }
  781. /* Early exit for exact matches */
  782. if (clk == codec_clk)
  783. goto found;
  784. }
  785. if (last_clk == 0) {
  786. printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
  787. return -EINVAL;
  788. }
  789. found:
  790. data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
  791. aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
  792. aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
  793. aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
  794. aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
  795. aic3x_write(codec, AIC3X_PLL_PROGD_REG,
  796. (pll_d & 0x3F) << PLLD_LSB_SHIFT);
  797. return 0;
  798. }
  799. static int aic3x_mute(struct snd_soc_dai *dai, int mute)
  800. {
  801. struct snd_soc_codec *codec = dai->codec;
  802. u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
  803. u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
  804. if (mute) {
  805. aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
  806. aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
  807. } else {
  808. aic3x_write(codec, LDAC_VOL, ldac_reg);
  809. aic3x_write(codec, RDAC_VOL, rdac_reg);
  810. }
  811. return 0;
  812. }
  813. static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  814. int clk_id, unsigned int freq, int dir)
  815. {
  816. struct snd_soc_codec *codec = codec_dai->codec;
  817. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  818. aic3x->sysclk = freq;
  819. return 0;
  820. }
  821. static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
  822. unsigned int fmt)
  823. {
  824. struct snd_soc_codec *codec = codec_dai->codec;
  825. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  826. u8 iface_areg, iface_breg;
  827. int delay = 0;
  828. iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
  829. iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
  830. /* set master/slave audio interface */
  831. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  832. case SND_SOC_DAIFMT_CBM_CFM:
  833. aic3x->master = 1;
  834. iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
  835. break;
  836. case SND_SOC_DAIFMT_CBS_CFS:
  837. aic3x->master = 0;
  838. break;
  839. default:
  840. return -EINVAL;
  841. }
  842. /*
  843. * match both interface format and signal polarities since they
  844. * are fixed
  845. */
  846. switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
  847. SND_SOC_DAIFMT_INV_MASK)) {
  848. case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
  849. break;
  850. case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
  851. delay = 1;
  852. case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
  853. iface_breg |= (0x01 << 6);
  854. break;
  855. case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
  856. iface_breg |= (0x02 << 6);
  857. break;
  858. case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
  859. iface_breg |= (0x03 << 6);
  860. break;
  861. default:
  862. return -EINVAL;
  863. }
  864. /* set iface */
  865. aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
  866. aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
  867. aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
  868. return 0;
  869. }
  870. static int aic3x_set_bias_level(struct snd_soc_codec *codec,
  871. enum snd_soc_bias_level level)
  872. {
  873. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  874. u8 reg;
  875. switch (level) {
  876. case SND_SOC_BIAS_ON:
  877. break;
  878. case SND_SOC_BIAS_PREPARE:
  879. if (aic3x->master) {
  880. /* enable pll */
  881. reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
  882. aic3x_write(codec, AIC3X_PLL_PROGA_REG,
  883. reg | PLL_ENABLE);
  884. }
  885. break;
  886. case SND_SOC_BIAS_STANDBY:
  887. /* fall through and disable pll */
  888. case SND_SOC_BIAS_OFF:
  889. if (aic3x->master) {
  890. /* disable pll */
  891. reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
  892. aic3x_write(codec, AIC3X_PLL_PROGA_REG,
  893. reg & ~PLL_ENABLE);
  894. }
  895. break;
  896. }
  897. codec->bias_level = level;
  898. return 0;
  899. }
  900. void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
  901. {
  902. u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
  903. u8 bit = gpio ? 3: 0;
  904. u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
  905. aic3x_write(codec, reg, val | (!!state << bit));
  906. }
  907. EXPORT_SYMBOL_GPL(aic3x_set_gpio);
  908. int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
  909. {
  910. u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
  911. u8 val, bit = gpio ? 2: 1;
  912. aic3x_read(codec, reg, &val);
  913. return (val >> bit) & 1;
  914. }
  915. EXPORT_SYMBOL_GPL(aic3x_get_gpio);
  916. void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
  917. int headset_debounce, int button_debounce)
  918. {
  919. u8 val;
  920. val = ((detect & AIC3X_HEADSET_DETECT_MASK)
  921. << AIC3X_HEADSET_DETECT_SHIFT) |
  922. ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
  923. << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
  924. ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
  925. << AIC3X_BUTTON_DEBOUNCE_SHIFT);
  926. if (detect & AIC3X_HEADSET_DETECT_MASK)
  927. val |= AIC3X_HEADSET_DETECT_ENABLED;
  928. aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
  929. }
  930. EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
  931. int aic3x_headset_detected(struct snd_soc_codec *codec)
  932. {
  933. u8 val;
  934. aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
  935. return (val >> 4) & 1;
  936. }
  937. EXPORT_SYMBOL_GPL(aic3x_headset_detected);
  938. int aic3x_button_pressed(struct snd_soc_codec *codec)
  939. {
  940. u8 val;
  941. aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
  942. return (val >> 5) & 1;
  943. }
  944. EXPORT_SYMBOL_GPL(aic3x_button_pressed);
  945. #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
  946. #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  947. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  948. static struct snd_soc_dai_ops aic3x_dai_ops = {
  949. .hw_params = aic3x_hw_params,
  950. .digital_mute = aic3x_mute,
  951. .set_sysclk = aic3x_set_dai_sysclk,
  952. .set_fmt = aic3x_set_dai_fmt,
  953. };
  954. struct snd_soc_dai aic3x_dai = {
  955. .name = "tlv320aic3x",
  956. .playback = {
  957. .stream_name = "Playback",
  958. .channels_min = 1,
  959. .channels_max = 2,
  960. .rates = AIC3X_RATES,
  961. .formats = AIC3X_FORMATS,},
  962. .capture = {
  963. .stream_name = "Capture",
  964. .channels_min = 1,
  965. .channels_max = 2,
  966. .rates = AIC3X_RATES,
  967. .formats = AIC3X_FORMATS,},
  968. .ops = &aic3x_dai_ops,
  969. };
  970. EXPORT_SYMBOL_GPL(aic3x_dai);
  971. static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
  972. {
  973. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  974. struct snd_soc_codec *codec = socdev->card->codec;
  975. aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  976. return 0;
  977. }
  978. static int aic3x_resume(struct platform_device *pdev)
  979. {
  980. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  981. struct snd_soc_codec *codec = socdev->card->codec;
  982. int i;
  983. u8 data[2];
  984. u8 *cache = codec->reg_cache;
  985. /* Sync reg_cache with the hardware */
  986. for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
  987. data[0] = i;
  988. data[1] = cache[i];
  989. codec->hw_write(codec->control_data, data, 2);
  990. }
  991. aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  992. return 0;
  993. }
  994. /*
  995. * initialise the AIC3X driver
  996. * register the mixer and dsp interfaces with the kernel
  997. */
  998. static int aic3x_init(struct snd_soc_codec *codec)
  999. {
  1000. int reg;
  1001. mutex_init(&codec->mutex);
  1002. INIT_LIST_HEAD(&codec->dapm_widgets);
  1003. INIT_LIST_HEAD(&codec->dapm_paths);
  1004. codec->name = "tlv320aic3x";
  1005. codec->owner = THIS_MODULE;
  1006. codec->read = aic3x_read_reg_cache;
  1007. codec->write = aic3x_write;
  1008. codec->set_bias_level = aic3x_set_bias_level;
  1009. codec->dai = &aic3x_dai;
  1010. codec->num_dai = 1;
  1011. codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
  1012. codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
  1013. if (codec->reg_cache == NULL)
  1014. return -ENOMEM;
  1015. aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
  1016. aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
  1017. /* DAC default volume and mute */
  1018. aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1019. aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1020. /* DAC to HP default volume and route to Output mixer */
  1021. aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1022. aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1023. aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1024. aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1025. /* DAC to Line Out default volume and route to Output mixer */
  1026. aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1027. aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1028. /* DAC to Mono Line Out default volume and route to Output mixer */
  1029. aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1030. aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1031. /* unmute all outputs */
  1032. reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
  1033. aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
  1034. reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
  1035. aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
  1036. reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
  1037. aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
  1038. reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
  1039. aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
  1040. reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
  1041. aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
  1042. reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
  1043. aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
  1044. reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
  1045. aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
  1046. /* ADC default volume and unmute */
  1047. aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
  1048. aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
  1049. /* By default route Line1 to ADC PGA mixer */
  1050. aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
  1051. aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
  1052. /* PGA to HP Bypass default volume, disconnect from Output Mixer */
  1053. aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
  1054. aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
  1055. aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
  1056. aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
  1057. /* PGA to Line Out default volume, disconnect from Output Mixer */
  1058. aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
  1059. aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
  1060. /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
  1061. aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
  1062. aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
  1063. /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
  1064. aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
  1065. aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
  1066. aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
  1067. aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
  1068. /* Line2 Line Out default volume, disconnect from Output Mixer */
  1069. aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
  1070. aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
  1071. /* Line2 to Mono Out default volume, disconnect from Output Mixer */
  1072. aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
  1073. aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
  1074. /* off, with power on */
  1075. aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1076. return 0;
  1077. }
  1078. static struct snd_soc_codec *aic3x_codec;
  1079. static int aic3x_register(struct snd_soc_codec *codec)
  1080. {
  1081. int ret;
  1082. ret = aic3x_init(codec);
  1083. if (ret < 0) {
  1084. dev_err(codec->dev, "Failed to initialise device\n");
  1085. return ret;
  1086. }
  1087. aic3x_codec = codec;
  1088. ret = snd_soc_register_codec(codec);
  1089. if (ret) {
  1090. dev_err(codec->dev, "Failed to register codec\n");
  1091. return ret;
  1092. }
  1093. ret = snd_soc_register_dai(&aic3x_dai);
  1094. if (ret) {
  1095. dev_err(codec->dev, "Failed to register dai\n");
  1096. snd_soc_unregister_codec(codec);
  1097. return ret;
  1098. }
  1099. return 0;
  1100. }
  1101. static int aic3x_unregister(struct aic3x_priv *aic3x)
  1102. {
  1103. aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF);
  1104. snd_soc_unregister_dai(&aic3x_dai);
  1105. snd_soc_unregister_codec(&aic3x->codec);
  1106. if (aic3x->gpio_reset >= 0) {
  1107. gpio_set_value(aic3x->gpio_reset, 0);
  1108. gpio_free(aic3x->gpio_reset);
  1109. }
  1110. regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
  1111. regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
  1112. kfree(aic3x);
  1113. aic3x_codec = NULL;
  1114. return 0;
  1115. }
  1116. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1117. /*
  1118. * AIC3X 2 wire address can be up to 4 devices with device addresses
  1119. * 0x18, 0x19, 0x1A, 0x1B
  1120. */
  1121. /*
  1122. * If the i2c layer weren't so broken, we could pass this kind of data
  1123. * around
  1124. */
  1125. static int aic3x_i2c_probe(struct i2c_client *i2c,
  1126. const struct i2c_device_id *id)
  1127. {
  1128. struct snd_soc_codec *codec;
  1129. struct aic3x_priv *aic3x;
  1130. struct aic3x_pdata *pdata = i2c->dev.platform_data;
  1131. int ret, i;
  1132. aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
  1133. if (aic3x == NULL) {
  1134. dev_err(&i2c->dev, "failed to create private data\n");
  1135. return -ENOMEM;
  1136. }
  1137. codec = &aic3x->codec;
  1138. codec->dev = &i2c->dev;
  1139. snd_soc_codec_set_drvdata(codec, aic3x);
  1140. codec->control_data = i2c;
  1141. codec->hw_write = (hw_write_t) i2c_master_send;
  1142. i2c_set_clientdata(i2c, aic3x);
  1143. aic3x->gpio_reset = -1;
  1144. if (pdata && pdata->gpio_reset >= 0) {
  1145. ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
  1146. if (ret != 0)
  1147. goto err_gpio;
  1148. aic3x->gpio_reset = pdata->gpio_reset;
  1149. gpio_direction_output(aic3x->gpio_reset, 0);
  1150. }
  1151. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
  1152. aic3x->supplies[i].supply = aic3x_supply_names[i];
  1153. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
  1154. aic3x->supplies);
  1155. if (ret != 0) {
  1156. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1157. goto err_get;
  1158. }
  1159. ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
  1160. aic3x->supplies);
  1161. if (ret != 0) {
  1162. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  1163. goto err_enable;
  1164. }
  1165. if (aic3x->gpio_reset >= 0) {
  1166. udelay(1);
  1167. gpio_set_value(aic3x->gpio_reset, 1);
  1168. }
  1169. return aic3x_register(codec);
  1170. err_enable:
  1171. regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
  1172. err_get:
  1173. if (aic3x->gpio_reset >= 0)
  1174. gpio_free(aic3x->gpio_reset);
  1175. err_gpio:
  1176. kfree(aic3x);
  1177. return ret;
  1178. }
  1179. static int aic3x_i2c_remove(struct i2c_client *client)
  1180. {
  1181. struct aic3x_priv *aic3x = i2c_get_clientdata(client);
  1182. return aic3x_unregister(aic3x);
  1183. }
  1184. static const struct i2c_device_id aic3x_i2c_id[] = {
  1185. { "tlv320aic3x", 0 },
  1186. { "tlv320aic33", 0 },
  1187. { }
  1188. };
  1189. MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
  1190. /* machine i2c codec control layer */
  1191. static struct i2c_driver aic3x_i2c_driver = {
  1192. .driver = {
  1193. .name = "aic3x I2C Codec",
  1194. .owner = THIS_MODULE,
  1195. },
  1196. .probe = aic3x_i2c_probe,
  1197. .remove = aic3x_i2c_remove,
  1198. .id_table = aic3x_i2c_id,
  1199. };
  1200. static inline void aic3x_i2c_init(void)
  1201. {
  1202. int ret;
  1203. ret = i2c_add_driver(&aic3x_i2c_driver);
  1204. if (ret)
  1205. printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
  1206. __func__, ret);
  1207. }
  1208. static inline void aic3x_i2c_exit(void)
  1209. {
  1210. i2c_del_driver(&aic3x_i2c_driver);
  1211. }
  1212. #else
  1213. static inline void aic3x_i2c_init(void) { }
  1214. static inline void aic3x_i2c_exit(void) { }
  1215. #endif
  1216. static int aic3x_probe(struct platform_device *pdev)
  1217. {
  1218. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1219. struct aic3x_setup_data *setup;
  1220. struct snd_soc_codec *codec;
  1221. int ret = 0;
  1222. codec = aic3x_codec;
  1223. if (!codec) {
  1224. dev_err(&pdev->dev, "Codec not registered\n");
  1225. return -ENODEV;
  1226. }
  1227. socdev->card->codec = codec;
  1228. setup = socdev->codec_data;
  1229. if (setup) {
  1230. /* setup GPIO functions */
  1231. aic3x_write(codec, AIC3X_GPIO1_REG,
  1232. (setup->gpio_func[0] & 0xf) << 4);
  1233. aic3x_write(codec, AIC3X_GPIO2_REG,
  1234. (setup->gpio_func[1] & 0xf) << 4);
  1235. }
  1236. /* register pcms */
  1237. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1238. if (ret < 0) {
  1239. printk(KERN_ERR "aic3x: failed to create pcms\n");
  1240. goto pcm_err;
  1241. }
  1242. snd_soc_add_controls(codec, aic3x_snd_controls,
  1243. ARRAY_SIZE(aic3x_snd_controls));
  1244. aic3x_add_widgets(codec);
  1245. return ret;
  1246. pcm_err:
  1247. kfree(codec->reg_cache);
  1248. return ret;
  1249. }
  1250. static int aic3x_remove(struct platform_device *pdev)
  1251. {
  1252. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1253. struct snd_soc_codec *codec = socdev->card->codec;
  1254. /* power down chip */
  1255. if (codec->control_data)
  1256. aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1257. snd_soc_free_pcms(socdev);
  1258. snd_soc_dapm_free(socdev);
  1259. kfree(codec->reg_cache);
  1260. return 0;
  1261. }
  1262. struct snd_soc_codec_device soc_codec_dev_aic3x = {
  1263. .probe = aic3x_probe,
  1264. .remove = aic3x_remove,
  1265. .suspend = aic3x_suspend,
  1266. .resume = aic3x_resume,
  1267. };
  1268. EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
  1269. static int __init aic3x_modinit(void)
  1270. {
  1271. aic3x_i2c_init();
  1272. return 0;
  1273. }
  1274. module_init(aic3x_modinit);
  1275. static void __exit aic3x_exit(void)
  1276. {
  1277. aic3x_i2c_exit();
  1278. }
  1279. module_exit(aic3x_exit);
  1280. MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
  1281. MODULE_AUTHOR("Vladimir Barinov");
  1282. MODULE_LICENSE("GPL");