jz4740.c 13 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * You should have received a copy of the GNU General Public License along
  9. * with this program; if not, write to the Free Software Foundation, Inc.,
  10. * 675 Mass Ave, Cambridge, MA 02139, USA.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/delay.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/soc.h>
  24. #define JZ4740_REG_CODEC_1 0x0
  25. #define JZ4740_REG_CODEC_2 0x1
  26. #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
  27. #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
  28. #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
  29. #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
  30. #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
  31. #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
  32. #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
  33. #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
  34. #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
  35. #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
  36. #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
  37. #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
  38. #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
  39. #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
  40. #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
  41. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
  42. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
  43. #define JZ4740_CODEC_1_SUSPEND BIT(1)
  44. #define JZ4740_CODEC_1_RESET BIT(0)
  45. #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
  46. #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
  47. #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
  48. #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
  49. #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
  50. #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
  51. #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
  52. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
  53. #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
  54. #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
  55. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
  56. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
  57. #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
  58. #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
  59. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
  60. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
  61. static const uint32_t jz4740_codec_regs[] = {
  62. 0x021b2302, 0x00170803,
  63. };
  64. struct jz4740_codec {
  65. void __iomem *base;
  66. struct resource *mem;
  67. uint32_t reg_cache[2];
  68. struct snd_soc_codec codec;
  69. };
  70. static inline struct jz4740_codec *codec_to_jz4740(struct snd_soc_codec *codec)
  71. {
  72. return container_of(codec, struct jz4740_codec, codec);
  73. }
  74. static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
  75. unsigned int reg)
  76. {
  77. struct jz4740_codec *jz4740_codec = codec_to_jz4740(codec);
  78. return readl(jz4740_codec->base + (reg << 2));
  79. }
  80. static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  81. unsigned int val)
  82. {
  83. struct jz4740_codec *jz4740_codec = codec_to_jz4740(codec);
  84. jz4740_codec->reg_cache[reg] = val;
  85. writel(val, jz4740_codec->base + (reg << 2));
  86. return 0;
  87. }
  88. static const struct snd_kcontrol_new jz4740_codec_controls[] = {
  89. SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
  90. JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
  91. SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
  92. JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
  93. SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
  94. JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
  95. SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
  96. JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
  97. };
  98. static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
  99. SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
  100. JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
  101. SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
  102. JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
  103. };
  104. static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
  105. SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
  106. JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
  107. SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
  108. JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
  109. };
  110. static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
  111. SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
  112. JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
  113. SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
  114. JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
  115. SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
  116. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
  117. jz4740_codec_output_controls,
  118. ARRAY_SIZE(jz4740_codec_output_controls)),
  119. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
  120. jz4740_codec_input_controls,
  121. ARRAY_SIZE(jz4740_codec_input_controls)),
  122. SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  123. SND_SOC_DAPM_OUTPUT("LOUT"),
  124. SND_SOC_DAPM_OUTPUT("ROUT"),
  125. SND_SOC_DAPM_INPUT("MIC"),
  126. SND_SOC_DAPM_INPUT("LIN"),
  127. SND_SOC_DAPM_INPUT("RIN"),
  128. };
  129. static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
  130. {"Line Input", NULL, "LIN"},
  131. {"Line Input", NULL, "RIN"},
  132. {"Input Mixer", "Line Capture Switch", "Line Input"},
  133. {"Input Mixer", "Mic Capture Switch", "MIC"},
  134. {"ADC", NULL, "Input Mixer"},
  135. {"Output Mixer", "Bypass Switch", "Input Mixer"},
  136. {"Output Mixer", "DAC Switch", "DAC"},
  137. {"LOUT", NULL, "Output Mixer"},
  138. {"ROUT", NULL, "Output Mixer"},
  139. };
  140. static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
  141. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  142. {
  143. uint32_t val;
  144. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  145. struct snd_soc_device *socdev = rtd->socdev;
  146. struct snd_soc_codec *codec = socdev->card->codec;
  147. switch (params_rate(params)) {
  148. case 8000:
  149. val = 0;
  150. break;
  151. case 11025:
  152. val = 1;
  153. break;
  154. case 12000:
  155. val = 2;
  156. break;
  157. case 16000:
  158. val = 3;
  159. break;
  160. case 22050:
  161. val = 4;
  162. break;
  163. case 24000:
  164. val = 5;
  165. break;
  166. case 32000:
  167. val = 6;
  168. break;
  169. case 44100:
  170. val = 7;
  171. break;
  172. case 48000:
  173. val = 8;
  174. break;
  175. default:
  176. return -EINVAL;
  177. }
  178. val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
  179. snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
  180. JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
  181. return 0;
  182. }
  183. static struct snd_soc_dai_ops jz4740_codec_dai_ops = {
  184. .hw_params = jz4740_codec_hw_params,
  185. };
  186. struct snd_soc_dai jz4740_codec_dai = {
  187. .name = "jz4740",
  188. .playback = {
  189. .stream_name = "Playback",
  190. .channels_min = 2,
  191. .channels_max = 2,
  192. .rates = SNDRV_PCM_RATE_8000_48000,
  193. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  194. },
  195. .capture = {
  196. .stream_name = "Capture",
  197. .channels_min = 2,
  198. .channels_max = 2,
  199. .rates = SNDRV_PCM_RATE_8000_48000,
  200. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  201. },
  202. .ops = &jz4740_codec_dai_ops,
  203. .symmetric_rates = 1,
  204. };
  205. EXPORT_SYMBOL_GPL(jz4740_codec_dai);
  206. static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
  207. {
  208. int i;
  209. uint32_t *cache = codec->reg_cache;
  210. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  211. JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
  212. udelay(2);
  213. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  214. JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
  215. for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
  216. jz4740_codec_write(codec, i, cache[i]);
  217. }
  218. static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
  219. enum snd_soc_bias_level level)
  220. {
  221. unsigned int mask;
  222. unsigned int value;
  223. switch (level) {
  224. case SND_SOC_BIAS_ON:
  225. break;
  226. case SND_SOC_BIAS_PREPARE:
  227. mask = JZ4740_CODEC_1_VREF_DISABLE |
  228. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  229. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  230. value = 0;
  231. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  232. break;
  233. case SND_SOC_BIAS_STANDBY:
  234. /* The only way to clear the suspend flag is to reset the codec */
  235. if (codec->bias_level == SND_SOC_BIAS_OFF)
  236. jz4740_codec_wakeup(codec);
  237. mask = JZ4740_CODEC_1_VREF_DISABLE |
  238. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  239. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  240. value = JZ4740_CODEC_1_VREF_DISABLE |
  241. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  242. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  243. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  244. break;
  245. case SND_SOC_BIAS_OFF:
  246. mask = JZ4740_CODEC_1_SUSPEND;
  247. value = JZ4740_CODEC_1_SUSPEND;
  248. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  249. break;
  250. default:
  251. break;
  252. }
  253. codec->bias_level = level;
  254. return 0;
  255. }
  256. static struct snd_soc_codec *jz4740_codec_codec;
  257. static int jz4740_codec_dev_probe(struct platform_device *pdev)
  258. {
  259. int ret;
  260. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  261. struct snd_soc_codec *codec = jz4740_codec_codec;
  262. BUG_ON(!codec);
  263. socdev->card->codec = codec;
  264. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  265. if (ret) {
  266. dev_err(&pdev->dev, "Failed to create pcms: %d\n", ret);
  267. return ret;
  268. }
  269. snd_soc_add_controls(codec, jz4740_codec_controls,
  270. ARRAY_SIZE(jz4740_codec_controls));
  271. snd_soc_dapm_new_controls(codec, jz4740_codec_dapm_widgets,
  272. ARRAY_SIZE(jz4740_codec_dapm_widgets));
  273. snd_soc_dapm_add_routes(codec, jz4740_codec_dapm_routes,
  274. ARRAY_SIZE(jz4740_codec_dapm_routes));
  275. snd_soc_dapm_new_widgets(codec);
  276. return 0;
  277. }
  278. static int jz4740_codec_dev_remove(struct platform_device *pdev)
  279. {
  280. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  281. snd_soc_free_pcms(socdev);
  282. snd_soc_dapm_free(socdev);
  283. return 0;
  284. }
  285. #ifdef CONFIG_PM_SLEEP
  286. static int jz4740_codec_suspend(struct platform_device *pdev, pm_message_t state)
  287. {
  288. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  289. struct snd_soc_codec *codec = socdev->card->codec;
  290. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  291. }
  292. static int jz4740_codec_resume(struct platform_device *pdev)
  293. {
  294. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  295. struct snd_soc_codec *codec = socdev->card->codec;
  296. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  297. }
  298. #else
  299. #define jz4740_codec_suspend NULL
  300. #define jz4740_codec_resume NULL
  301. #endif
  302. struct snd_soc_codec_device soc_codec_dev_jz4740_codec = {
  303. .probe = jz4740_codec_dev_probe,
  304. .remove = jz4740_codec_dev_remove,
  305. .suspend = jz4740_codec_suspend,
  306. .resume = jz4740_codec_resume,
  307. };
  308. EXPORT_SYMBOL_GPL(soc_codec_dev_jz4740_codec);
  309. static int __devinit jz4740_codec_probe(struct platform_device *pdev)
  310. {
  311. int ret;
  312. struct jz4740_codec *jz4740_codec;
  313. struct snd_soc_codec *codec;
  314. struct resource *mem;
  315. jz4740_codec = kzalloc(sizeof(*jz4740_codec), GFP_KERNEL);
  316. if (!jz4740_codec)
  317. return -ENOMEM;
  318. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  319. if (!mem) {
  320. dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
  321. ret = -ENOENT;
  322. goto err_free_codec;
  323. }
  324. mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
  325. if (!mem) {
  326. dev_err(&pdev->dev, "Failed to request mmio memory region\n");
  327. ret = -EBUSY;
  328. goto err_free_codec;
  329. }
  330. jz4740_codec->base = ioremap(mem->start, resource_size(mem));
  331. if (!jz4740_codec->base) {
  332. dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
  333. ret = -EBUSY;
  334. goto err_release_mem_region;
  335. }
  336. jz4740_codec->mem = mem;
  337. jz4740_codec_dai.dev = &pdev->dev;
  338. codec = &jz4740_codec->codec;
  339. codec->dev = &pdev->dev;
  340. codec->name = "jz4740";
  341. codec->owner = THIS_MODULE;
  342. codec->read = jz4740_codec_read;
  343. codec->write = jz4740_codec_write;
  344. codec->set_bias_level = jz4740_codec_set_bias_level;
  345. codec->bias_level = SND_SOC_BIAS_OFF;
  346. codec->dai = &jz4740_codec_dai;
  347. codec->num_dai = 1;
  348. codec->reg_cache = jz4740_codec->reg_cache;
  349. codec->reg_cache_size = 2;
  350. memcpy(codec->reg_cache, jz4740_codec_regs, sizeof(jz4740_codec_regs));
  351. mutex_init(&codec->mutex);
  352. INIT_LIST_HEAD(&codec->dapm_widgets);
  353. INIT_LIST_HEAD(&codec->dapm_paths);
  354. jz4740_codec_codec = codec;
  355. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  356. JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
  357. platform_set_drvdata(pdev, jz4740_codec);
  358. ret = snd_soc_register_codec(codec);
  359. if (ret) {
  360. dev_err(&pdev->dev, "Failed to register codec\n");
  361. goto err_iounmap;
  362. }
  363. ret = snd_soc_register_dai(&jz4740_codec_dai);
  364. if (ret) {
  365. dev_err(&pdev->dev, "Failed to register codec dai\n");
  366. goto err_unregister_codec;
  367. }
  368. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  369. return 0;
  370. err_unregister_codec:
  371. snd_soc_unregister_codec(codec);
  372. err_iounmap:
  373. iounmap(jz4740_codec->base);
  374. err_release_mem_region:
  375. release_mem_region(mem->start, resource_size(mem));
  376. err_free_codec:
  377. kfree(jz4740_codec);
  378. return ret;
  379. }
  380. static int __devexit jz4740_codec_remove(struct platform_device *pdev)
  381. {
  382. struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
  383. struct resource *mem = jz4740_codec->mem;
  384. snd_soc_unregister_dai(&jz4740_codec_dai);
  385. snd_soc_unregister_codec(&jz4740_codec->codec);
  386. iounmap(jz4740_codec->base);
  387. release_mem_region(mem->start, resource_size(mem));
  388. platform_set_drvdata(pdev, NULL);
  389. kfree(jz4740_codec);
  390. return 0;
  391. }
  392. static struct platform_driver jz4740_codec_driver = {
  393. .probe = jz4740_codec_probe,
  394. .remove = __devexit_p(jz4740_codec_remove),
  395. .driver = {
  396. .name = "jz4740-codec",
  397. .owner = THIS_MODULE,
  398. },
  399. };
  400. static int __init jz4740_codec_init(void)
  401. {
  402. return platform_driver_register(&jz4740_codec_driver);
  403. }
  404. module_init(jz4740_codec_init);
  405. static void __exit jz4740_codec_exit(void)
  406. {
  407. platform_driver_unregister(&jz4740_codec_driver);
  408. }
  409. module_exit(jz4740_codec_exit);
  410. MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
  411. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  412. MODULE_LICENSE("GPL v2");
  413. MODULE_ALIAS("platform:jz4740-codec");