qla_nx.h 33 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #ifndef __QLA_NX_H
  8. #define __QLA_NX_H
  9. /*
  10. * Following are the states of the Phantom. Phantom will set them and
  11. * Host will read to check if the fields are correct.
  12. */
  13. #define PHAN_INITIALIZE_FAILED 0xffff
  14. #define PHAN_INITIALIZE_COMPLETE 0xff01
  15. /* Host writes the following to notify that it has done the init-handshake */
  16. #define PHAN_INITIALIZE_ACK 0xf00f
  17. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  18. /*CRB_RELATED*/
  19. #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
  20. #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
  21. #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
  22. #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
  23. #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
  24. #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
  25. #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
  26. #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
  27. #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
  28. #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
  29. #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
  30. #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
  31. #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
  32. /* Hub 0 */
  33. #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
  34. #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
  35. /* Hub 1 */
  36. #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
  37. #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
  38. #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
  39. #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
  40. #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
  41. #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
  42. #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
  43. #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
  44. #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
  45. #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
  46. #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
  47. #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
  48. #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
  49. #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
  50. #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
  51. /* Hub 2 */
  52. #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
  53. #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
  54. #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
  55. #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
  56. #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
  57. #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
  58. #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
  59. #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
  60. #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
  61. #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
  62. #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
  63. #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
  64. #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
  65. #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
  66. #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
  67. #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
  68. /* Hub 3 */
  69. #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
  70. #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
  71. #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
  72. #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
  73. /* Hub 4 */
  74. #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
  75. #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
  76. #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
  77. #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
  78. #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
  79. #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
  80. #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
  81. #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
  82. #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
  83. #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
  84. #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
  85. #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
  86. /* Hub 5 */
  87. #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
  88. #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
  89. #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
  90. #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
  91. #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
  92. #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
  93. #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
  94. /* Hub 6 */
  95. #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
  96. #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
  97. #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
  98. #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
  99. #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
  100. #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
  101. #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
  102. #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
  103. #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
  104. /* This field defines PCI/X adr [25:20] of agents on the CRB */
  105. /* */
  106. #define QLA82XX_HW_PX_MAP_CRB_PH 0
  107. #define QLA82XX_HW_PX_MAP_CRB_PS 1
  108. #define QLA82XX_HW_PX_MAP_CRB_MN 2
  109. #define QLA82XX_HW_PX_MAP_CRB_MS 3
  110. #define QLA82XX_HW_PX_MAP_CRB_SRE 5
  111. #define QLA82XX_HW_PX_MAP_CRB_NIU 6
  112. #define QLA82XX_HW_PX_MAP_CRB_QMN 7
  113. #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
  114. #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
  115. #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
  116. #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
  117. #define QLA82XX_HW_PX_MAP_CRB_QMS 12
  118. #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
  119. #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
  120. #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
  121. #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
  122. #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
  123. #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
  124. #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
  125. #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
  126. #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
  127. #define QLA82XX_HW_PX_MAP_CRB_PGND 21
  128. #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
  129. #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
  130. #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
  131. #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
  132. #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
  133. #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
  134. #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
  135. #define QLA82XX_HW_PX_MAP_CRB_SN 29
  136. #define QLA82XX_HW_PX_MAP_CRB_EG 31
  137. #define QLA82XX_HW_PX_MAP_CRB_PH2 32
  138. #define QLA82XX_HW_PX_MAP_CRB_PS2 33
  139. #define QLA82XX_HW_PX_MAP_CRB_CAM 34
  140. #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
  141. #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
  142. #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
  143. #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
  144. #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
  145. #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
  146. #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
  147. #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
  148. #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
  149. #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
  150. #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
  151. #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
  152. #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
  153. #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
  154. #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
  155. #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
  156. #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
  157. #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
  158. #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
  159. #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
  160. #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
  161. #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
  162. #define QLA82XX_HW_PX_MAP_CRB_SMB 58
  163. #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
  164. #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
  165. #define QLA82XX_HW_PX_MAP_CRB_LPC 61
  166. #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
  167. #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
  168. #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
  169. #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
  170. #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
  171. /* This field defines CRB adr [31:20] of the agents */
  172. /* */
  173. #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  174. QLA82XX_HW_MN_CRB_AGT_ADR)
  175. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  176. QLA82XX_HW_PH_CRB_AGT_ADR)
  177. #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  178. QLA82XX_HW_MS_CRB_AGT_ADR)
  179. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  180. QLA82XX_HW_PS_CRB_AGT_ADR)
  181. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  182. QLA82XX_HW_SS_CRB_AGT_ADR)
  183. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  184. QLA82XX_HW_RPMX3_CRB_AGT_ADR)
  185. #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  186. QLA82XX_HW_QMS_CRB_AGT_ADR)
  187. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  188. QLA82XX_HW_SQGS0_CRB_AGT_ADR)
  189. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  190. QLA82XX_HW_SQGS1_CRB_AGT_ADR)
  191. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  192. QLA82XX_HW_SQGS2_CRB_AGT_ADR)
  193. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  194. QLA82XX_HW_SQGS3_CRB_AGT_ADR)
  195. #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  196. QLA82XX_HW_C2C0_CRB_AGT_ADR)
  197. #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  198. QLA82XX_HW_C2C1_CRB_AGT_ADR)
  199. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  200. QLA82XX_HW_RPMX2_CRB_AGT_ADR)
  201. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  202. QLA82XX_HW_RPMX4_CRB_AGT_ADR)
  203. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  204. QLA82XX_HW_RPMX7_CRB_AGT_ADR)
  205. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  206. QLA82XX_HW_RPMX9_CRB_AGT_ADR)
  207. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  208. QLA82XX_HW_SMB_CRB_AGT_ADR)
  209. #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  210. QLA82XX_HW_NIU_CRB_AGT_ADR)
  211. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  212. QLA82XX_HW_I2C0_CRB_AGT_ADR)
  213. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  214. QLA82XX_HW_I2C1_CRB_AGT_ADR)
  215. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  216. QLA82XX_HW_SRE_CRB_AGT_ADR)
  217. #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  218. QLA82XX_HW_EG_CRB_AGT_ADR)
  219. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  220. QLA82XX_HW_RPMX0_CRB_AGT_ADR)
  221. #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  222. QLA82XX_HW_QM_CRB_AGT_ADR)
  223. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  224. QLA82XX_HW_SQG0_CRB_AGT_ADR)
  225. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  226. QLA82XX_HW_SQG1_CRB_AGT_ADR)
  227. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  228. QLA82XX_HW_SQG2_CRB_AGT_ADR)
  229. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  230. QLA82XX_HW_SQG3_CRB_AGT_ADR)
  231. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  232. QLA82XX_HW_RPMX1_CRB_AGT_ADR)
  233. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  234. QLA82XX_HW_RPMX5_CRB_AGT_ADR)
  235. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  236. QLA82XX_HW_RPMX6_CRB_AGT_ADR)
  237. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  238. QLA82XX_HW_RPMX8_CRB_AGT_ADR)
  239. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  240. QLA82XX_HW_CAS0_CRB_AGT_ADR)
  241. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  242. QLA82XX_HW_CAS1_CRB_AGT_ADR)
  243. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  244. QLA82XX_HW_CAS2_CRB_AGT_ADR)
  245. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  246. QLA82XX_HW_CAS3_CRB_AGT_ADR)
  247. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  248. QLA82XX_HW_PEGNI_CRB_AGT_ADR)
  249. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  250. QLA82XX_HW_PEGND_CRB_AGT_ADR)
  251. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  252. QLA82XX_HW_PEGN0_CRB_AGT_ADR)
  253. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  254. QLA82XX_HW_PEGN1_CRB_AGT_ADR)
  255. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  256. QLA82XX_HW_PEGN2_CRB_AGT_ADR)
  257. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  258. QLA82XX_HW_PEGN3_CRB_AGT_ADR)
  259. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  260. QLA82XX_HW_PEGN4_CRB_AGT_ADR)
  261. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  262. QLA82XX_HW_PEGNC_CRB_AGT_ADR)
  263. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  264. QLA82XX_HW_PEGR0_CRB_AGT_ADR)
  265. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  266. QLA82XX_HW_PEGR1_CRB_AGT_ADR)
  267. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  268. QLA82XX_HW_PEGR2_CRB_AGT_ADR)
  269. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  270. QLA82XX_HW_PEGR3_CRB_AGT_ADR)
  271. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  272. QLA82XX_HW_PEGSI_CRB_AGT_ADR)
  273. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  274. QLA82XX_HW_PEGSD_CRB_AGT_ADR)
  275. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  276. QLA82XX_HW_PEGS0_CRB_AGT_ADR)
  277. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  278. QLA82XX_HW_PEGS1_CRB_AGT_ADR)
  279. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  280. QLA82XX_HW_PEGS2_CRB_AGT_ADR)
  281. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  282. QLA82XX_HW_PEGS3_CRB_AGT_ADR)
  283. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  284. QLA82XX_HW_PEGSC_CRB_AGT_ADR)
  285. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  286. QLA82XX_HW_NCM_CRB_AGT_ADR)
  287. #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  288. QLA82XX_HW_TMR_CRB_AGT_ADR)
  289. #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  290. QLA82XX_HW_XDMA_CRB_AGT_ADR)
  291. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  292. QLA82XX_HW_SN_CRB_AGT_ADR)
  293. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  294. QLA82XX_HW_I2Q_CRB_AGT_ADR)
  295. #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  296. QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
  297. #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  298. QLA82XX_HW_OCM0_CRB_AGT_ADR)
  299. #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  300. QLA82XX_HW_OCM1_CRB_AGT_ADR)
  301. #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  302. QLA82XX_HW_LPC_CRB_AGT_ADR)
  303. #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
  304. #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
  305. #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
  306. #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
  307. #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
  308. #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
  309. #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
  310. #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
  311. #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
  312. #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
  313. #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
  314. #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
  315. /* Lock IDs for ROM lock */
  316. #define ROM_LOCK_DRIVER 0x0d417340
  317. #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
  318. #define QLA82XX_PCI_CRB_WINDOW(A) \
  319. (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
  320. #define QLA82XX_CRB_C2C_0 \
  321. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
  322. #define QLA82XX_CRB_C2C_1 \
  323. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
  324. #define QLA82XX_CRB_C2C_2 \
  325. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
  326. #define QLA82XX_CRB_CAM \
  327. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
  328. #define QLA82XX_CRB_CASPER \
  329. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
  330. #define QLA82XX_CRB_CASPER_0 \
  331. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
  332. #define QLA82XX_CRB_CASPER_1 \
  333. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
  334. #define QLA82XX_CRB_CASPER_2 \
  335. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
  336. #define QLA82XX_CRB_DDR_MD \
  337. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
  338. #define QLA82XX_CRB_DDR_NET \
  339. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
  340. #define QLA82XX_CRB_EPG \
  341. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
  342. #define QLA82XX_CRB_I2Q \
  343. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
  344. #define QLA82XX_CRB_NIU \
  345. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
  346. #define QLA82XX_CRB_PCIX_HOST \
  347. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
  348. #define QLA82XX_CRB_PCIX_HOST2 \
  349. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
  350. #define QLA82XX_CRB_PCIX_MD \
  351. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
  352. #define QLA82XX_CRB_PCIE \
  353. QLA82XX_CRB_PCIX_MD
  354. /* window 1 pcie slot */
  355. #define QLA82XX_CRB_PCIE2 \
  356. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
  357. #define QLA82XX_CRB_PEG_MD_0 \
  358. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
  359. #define QLA82XX_CRB_PEG_MD_1 \
  360. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
  361. #define QLA82XX_CRB_PEG_MD_2 \
  362. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
  363. #define QLA82XX_CRB_PEG_MD_3 \
  364. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
  365. #define QLA82XX_CRB_PEG_MD_3 \
  366. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
  367. #define QLA82XX_CRB_PEG_MD_D \
  368. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
  369. #define QLA82XX_CRB_PEG_MD_I \
  370. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
  371. #define QLA82XX_CRB_PEG_NET_0 \
  372. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
  373. #define QLA82XX_CRB_PEG_NET_1 \
  374. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
  375. #define QLA82XX_CRB_PEG_NET_2 \
  376. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
  377. #define QLA82XX_CRB_PEG_NET_3 \
  378. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
  379. #define QLA82XX_CRB_PEG_NET_4 \
  380. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
  381. #define QLA82XX_CRB_PEG_NET_D \
  382. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
  383. #define QLA82XX_CRB_PEG_NET_I \
  384. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
  385. #define QLA82XX_CRB_PQM_MD \
  386. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
  387. #define QLA82XX_CRB_PQM_NET \
  388. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
  389. #define QLA82XX_CRB_QDR_MD \
  390. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
  391. #define QLA82XX_CRB_QDR_NET \
  392. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
  393. #define QLA82XX_CRB_ROMUSB \
  394. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
  395. #define QLA82XX_CRB_RPMX_0 \
  396. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
  397. #define QLA82XX_CRB_RPMX_1 \
  398. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
  399. #define QLA82XX_CRB_RPMX_2 \
  400. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
  401. #define QLA82XX_CRB_RPMX_3 \
  402. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
  403. #define QLA82XX_CRB_RPMX_4 \
  404. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
  405. #define QLA82XX_CRB_RPMX_5 \
  406. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
  407. #define QLA82XX_CRB_RPMX_6 \
  408. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
  409. #define QLA82XX_CRB_RPMX_7 \
  410. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
  411. #define QLA82XX_CRB_SQM_MD_0 \
  412. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
  413. #define QLA82XX_CRB_SQM_MD_1 \
  414. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
  415. #define QLA82XX_CRB_SQM_MD_2 \
  416. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
  417. #define QLA82XX_CRB_SQM_MD_3 \
  418. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
  419. #define QLA82XX_CRB_SQM_NET_0 \
  420. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
  421. #define QLA82XX_CRB_SQM_NET_1 \
  422. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
  423. #define QLA82XX_CRB_SQM_NET_2 \
  424. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
  425. #define QLA82XX_CRB_SQM_NET_3 \
  426. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
  427. #define QLA82XX_CRB_SRE \
  428. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
  429. #define QLA82XX_CRB_TIMER \
  430. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
  431. #define QLA82XX_CRB_XDMA \
  432. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
  433. #define QLA82XX_CRB_I2C0 \
  434. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
  435. #define QLA82XX_CRB_I2C1 \
  436. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
  437. #define QLA82XX_CRB_OCM0 \
  438. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
  439. #define QLA82XX_CRB_SMB \
  440. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
  441. #define QLA82XX_CRB_MAX \
  442. QLA82XX_PCI_CRB_WINDOW(64)
  443. /*
  444. * ====================== BASE ADDRESSES ON-CHIP ======================
  445. * Base addresses of major components on-chip.
  446. * ====================== BASE ADDRESSES ON-CHIP ======================
  447. */
  448. #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
  449. #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
  450. /* Imbus address bit used to indicate a host address. This bit is
  451. * eliminated by the pcie bar and bar select before presentation
  452. * over pcie. */
  453. /* host memory via IMBUS */
  454. #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
  455. #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
  456. #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
  457. #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
  458. #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
  459. #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
  460. #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
  461. #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
  462. #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
  463. #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
  464. #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
  465. #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
  466. #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
  467. #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
  468. #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
  469. #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
  470. #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
  471. /*
  472. * Register offsets for MN
  473. */
  474. #define MIU_CONTROL (0x000)
  475. #define MIU_TAG (0x004)
  476. #define MIU_TEST_AGT_CTRL (0x090)
  477. #define MIU_TEST_AGT_ADDR_LO (0x094)
  478. #define MIU_TEST_AGT_ADDR_HI (0x098)
  479. #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
  480. #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
  481. #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
  482. #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
  483. #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
  484. #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
  485. #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
  486. #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
  487. /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
  488. #define MIU_TA_CTL_START 1
  489. #define MIU_TA_CTL_ENABLE 2
  490. #define MIU_TA_CTL_WRITE 4
  491. #define MIU_TA_CTL_BUSY 8
  492. /*CAM RAM */
  493. # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
  494. # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
  495. #define QLA82XX_PEG_TUNE_MN_SPD_ZEROED 0x80000000
  496. #define QLA82XX_BOOT_LOADER_MN_ISSUE 0xff00ffff
  497. #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
  498. #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
  499. #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
  500. #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
  501. #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
  502. #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
  503. #define HALT_STATUS_UNRECOVERABLE 0x80000000
  504. #define HALT_STATUS_RECOVERABLE 0x40000000
  505. /* Driver Coexistence Defines */
  506. #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
  507. #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
  508. #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
  509. #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
  510. #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
  511. #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
  512. /* Every driver should use these Device State */
  513. #define QLA82XX_DEV_COLD 1
  514. #define QLA82XX_DEV_INITIALIZING 2
  515. #define QLA82XX_DEV_READY 3
  516. #define QLA82XX_DEV_NEED_RESET 4
  517. #define QLA82XX_DEV_NEED_QUIESCENT 5
  518. #define QLA82XX_DEV_FAILED 6
  519. #define QLA82XX_DEV_QUIESCENT 7
  520. #define MAX_STATES 8 /* Increment if new state added */
  521. #define QLA82XX_IDC_VERSION 1
  522. #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30
  523. #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10
  524. #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
  525. #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
  526. #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
  527. #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
  528. #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
  529. #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
  530. #define PCIE_CHICKEN3 (0x120c8)
  531. #define PCIE_SETUP_FUNCTION (0x12040)
  532. #define PCIE_SETUP_FUNCTION2 (0x12048)
  533. #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
  534. #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
  535. #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
  536. #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
  537. #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
  538. #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
  539. #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
  540. #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
  541. /* Different drive state */
  542. #define QLA82XX_DRVST_NOT_RDY 0
  543. #define QLA82XX_DRVST_RST_RDY 1
  544. #define QLA82XX_DRVST_QSNT_RDY 2
  545. /*
  546. * The PCI VendorID and DeviceID for our board.
  547. */
  548. #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
  549. #define QLA82XX_MSIX_TBL_SPACE 8192
  550. #define QLA82XX_PCI_REG_MSIX_TBL 0x44
  551. #define QLA82XX_PCI_MSIX_CONTROL 0x40
  552. struct crb_128M_2M_sub_block_map {
  553. unsigned valid;
  554. unsigned start_128M;
  555. unsigned end_128M;
  556. unsigned start_2M;
  557. };
  558. struct crb_128M_2M_block_map {
  559. struct crb_128M_2M_sub_block_map sub_block[16];
  560. };
  561. struct crb_addr_pair {
  562. long addr;
  563. long data;
  564. };
  565. #define ADDR_ERROR ((unsigned long) 0xffffffff)
  566. #define MAX_CTL_CHECK 1000
  567. /***************************************************************************
  568. * PCI related defines.
  569. **************************************************************************/
  570. /*
  571. * Interrupt related defines.
  572. */
  573. #define PCIX_TARGET_STATUS (0x10118)
  574. #define PCIX_TARGET_STATUS_F1 (0x10160)
  575. #define PCIX_TARGET_STATUS_F2 (0x10164)
  576. #define PCIX_TARGET_STATUS_F3 (0x10168)
  577. #define PCIX_TARGET_STATUS_F4 (0x10360)
  578. #define PCIX_TARGET_STATUS_F5 (0x10364)
  579. #define PCIX_TARGET_STATUS_F6 (0x10368)
  580. #define PCIX_TARGET_STATUS_F7 (0x1036c)
  581. #define PCIX_TARGET_MASK (0x10128)
  582. #define PCIX_TARGET_MASK_F1 (0x10170)
  583. #define PCIX_TARGET_MASK_F2 (0x10174)
  584. #define PCIX_TARGET_MASK_F3 (0x10178)
  585. #define PCIX_TARGET_MASK_F4 (0x10370)
  586. #define PCIX_TARGET_MASK_F5 (0x10374)
  587. #define PCIX_TARGET_MASK_F6 (0x10378)
  588. #define PCIX_TARGET_MASK_F7 (0x1037c)
  589. /*
  590. * Message Signaled Interrupts
  591. */
  592. #define PCIX_MSI_F0 (0x13000)
  593. #define PCIX_MSI_F1 (0x13004)
  594. #define PCIX_MSI_F2 (0x13008)
  595. #define PCIX_MSI_F3 (0x1300c)
  596. #define PCIX_MSI_F4 (0x13010)
  597. #define PCIX_MSI_F5 (0x13014)
  598. #define PCIX_MSI_F6 (0x13018)
  599. #define PCIX_MSI_F7 (0x1301c)
  600. #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
  601. #define PCIX_INT_VECTOR (0x10100)
  602. #define PCIX_INT_MASK (0x10104)
  603. /*
  604. * Interrupt state machine and other bits.
  605. */
  606. #define PCIE_MISCCFG_RC (0x1206c)
  607. #define ISR_INT_TARGET_STATUS \
  608. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
  609. #define ISR_INT_TARGET_STATUS_F1 \
  610. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
  611. #define ISR_INT_TARGET_STATUS_F2 \
  612. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
  613. #define ISR_INT_TARGET_STATUS_F3 \
  614. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
  615. #define ISR_INT_TARGET_STATUS_F4 \
  616. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
  617. #define ISR_INT_TARGET_STATUS_F5 \
  618. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
  619. #define ISR_INT_TARGET_STATUS_F6 \
  620. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
  621. #define ISR_INT_TARGET_STATUS_F7 \
  622. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
  623. #define ISR_INT_TARGET_MASK \
  624. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
  625. #define ISR_INT_TARGET_MASK_F1 \
  626. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
  627. #define ISR_INT_TARGET_MASK_F2 \
  628. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
  629. #define ISR_INT_TARGET_MASK_F3 \
  630. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
  631. #define ISR_INT_TARGET_MASK_F4 \
  632. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
  633. #define ISR_INT_TARGET_MASK_F5 \
  634. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
  635. #define ISR_INT_TARGET_MASK_F6 \
  636. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
  637. #define ISR_INT_TARGET_MASK_F7 \
  638. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
  639. #define ISR_INT_VECTOR \
  640. (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
  641. #define ISR_INT_MASK \
  642. (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
  643. #define ISR_INT_STATE_REG \
  644. (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
  645. #define ISR_MSI_INT_TRIGGER(FUNC) \
  646. (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
  647. #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
  648. #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
  649. /*
  650. * PCI Interrupt Vector Values.
  651. */
  652. #define PCIX_INT_VECTOR_BIT_F0 0x0080
  653. #define PCIX_INT_VECTOR_BIT_F1 0x0100
  654. #define PCIX_INT_VECTOR_BIT_F2 0x0200
  655. #define PCIX_INT_VECTOR_BIT_F3 0x0400
  656. #define PCIX_INT_VECTOR_BIT_F4 0x0800
  657. #define PCIX_INT_VECTOR_BIT_F5 0x1000
  658. #define PCIX_INT_VECTOR_BIT_F6 0x2000
  659. #define PCIX_INT_VECTOR_BIT_F7 0x4000
  660. struct qla82xx_legacy_intr_set {
  661. uint32_t int_vec_bit;
  662. uint32_t tgt_status_reg;
  663. uint32_t tgt_mask_reg;
  664. uint32_t pci_int_reg;
  665. };
  666. #define QLA82XX_LEGACY_INTR_CONFIG \
  667. { \
  668. { \
  669. .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
  670. .tgt_status_reg = ISR_INT_TARGET_STATUS, \
  671. .tgt_mask_reg = ISR_INT_TARGET_MASK, \
  672. .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
  673. \
  674. { \
  675. .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
  676. .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
  677. .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
  678. .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
  679. \
  680. { \
  681. .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
  682. .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
  683. .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
  684. .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
  685. \
  686. { \
  687. .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
  688. .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
  689. .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
  690. .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
  691. \
  692. { \
  693. .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
  694. .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
  695. .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
  696. .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
  697. \
  698. { \
  699. .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
  700. .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
  701. .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
  702. .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
  703. \
  704. { \
  705. .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
  706. .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
  707. .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
  708. .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
  709. \
  710. { \
  711. .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
  712. .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
  713. .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
  714. .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
  715. }
  716. #define BRDCFG_START 0x4000
  717. #define BOOTLD_START 0x10000
  718. #define IMAGE_START 0x100000
  719. #define FLASH_ADDR_START 0x43000
  720. /* Magic number to let user know flash is programmed */
  721. #define QLA82XX_BDINFO_MAGIC 0x12345678
  722. #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
  723. #define FW_SIZE_OFFSET (0x3e840c)
  724. #define QLA82XX_FW_MIN_SIZE 0x3fffff
  725. /* UNIFIED ROMIMAGE START */
  726. #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
  727. #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
  728. #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
  729. #define QLA82XX_URI_DIR_SECT_FW 0x7
  730. /* Offsets */
  731. #define QLA82XX_URI_CHIP_REV_OFF 10
  732. #define QLA82XX_URI_FLAGS_OFF 11
  733. #define QLA82XX_URI_BIOS_VERSION_OFF 12
  734. #define QLA82XX_URI_BOOTLD_IDX_OFF 27
  735. #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
  736. struct qla82xx_uri_table_desc{
  737. uint32_t findex;
  738. uint32_t num_entries;
  739. uint32_t entry_size;
  740. uint32_t reserved[5];
  741. };
  742. struct qla82xx_uri_data_desc{
  743. uint32_t findex;
  744. uint32_t size;
  745. uint32_t reserved[5];
  746. };
  747. /* UNIFIED ROMIMAGE END */
  748. #define QLA82XX_UNIFIED_ROMIMAGE 3
  749. #define QLA82XX_FLASH_ROMIMAGE 4
  750. #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
  751. #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
  752. #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
  753. #ifndef readq
  754. static inline u64 readq(void __iomem *addr)
  755. {
  756. return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  757. }
  758. #endif
  759. #ifndef writeq
  760. static inline void writeq(u64 val, void __iomem *addr)
  761. {
  762. writel(((u32) (val)), (addr));
  763. writel(((u32) (val >> 32)), (addr + 4));
  764. }
  765. #endif
  766. /* Request and response queue size */
  767. #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */
  768. #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/
  769. /*
  770. * ISP 8021 I/O Register Set structure definitions.
  771. */
  772. struct device_reg_82xx {
  773. uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
  774. uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
  775. uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
  776. uint16_t mailbox_in[32]; /* Mail box In registers */
  777. uint16_t unused_1[32];
  778. uint32_t hint; /* Host interrupt register */
  779. #define HINT_MBX_INT_PENDING BIT_0
  780. uint16_t unused_2[62];
  781. uint16_t mailbox_out[32]; /* Mail box Out registers */
  782. uint32_t unused_3[48];
  783. uint32_t host_status; /* host status */
  784. #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
  785. #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
  786. uint32_t host_int; /* Interrupt status. */
  787. #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
  788. };
  789. struct fcp_cmnd {
  790. struct scsi_lun lun;
  791. uint8_t crn;
  792. uint8_t task_attribute;
  793. uint8_t task_management;
  794. uint8_t additional_cdb_len;
  795. uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */
  796. };
  797. struct dsd_dma {
  798. struct list_head list;
  799. dma_addr_t dsd_list_dma;
  800. void *dsd_addr;
  801. };
  802. #define QLA_DSDS_PER_IOCB 37
  803. #define QLA_DSD_SIZE 12
  804. struct ct6_dsd {
  805. uint16_t fcp_cmnd_len;
  806. dma_addr_t fcp_cmnd_dma;
  807. struct fcp_cmnd *fcp_cmnd;
  808. int dsd_use_cnt;
  809. struct list_head dsd_list;
  810. };
  811. #define MBC_TOGGLE_INTERRUPT 0x10
  812. /* Flash offset */
  813. #define FLT_REG_BOOTLOAD_82XX 0x72
  814. #define FLT_REG_BOOT_CODE_82XX 0x78
  815. #define FLT_REG_FW_82XX 0x74
  816. #define FLT_REG_GOLD_FW_82XX 0x75
  817. #define FLT_REG_VPD_82XX 0x81
  818. #define FA_VPD_SIZE_82XX 0x400
  819. #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
  820. /******************************************************************************
  821. *
  822. * Definitions specific to M25P flash
  823. *
  824. *******************************************************************************
  825. * Instructions
  826. */
  827. #define M25P_INSTR_WREN 0x06
  828. #define M25P_INSTR_WRDI 0x04
  829. #define M25P_INSTR_RDID 0x9f
  830. #define M25P_INSTR_RDSR 0x05
  831. #define M25P_INSTR_WRSR 0x01
  832. #define M25P_INSTR_READ 0x03
  833. #define M25P_INSTR_FAST_READ 0x0b
  834. #define M25P_INSTR_PP 0x02
  835. #define M25P_INSTR_SE 0xd8
  836. #define M25P_INSTR_BE 0xc7
  837. #define M25P_INSTR_DP 0xb9
  838. #define M25P_INSTR_RES 0xab
  839. #endif