cxgb3i_ddp.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773
  1. /*
  2. * cxgb3i_ddp.c: Chelsio S3xx iSCSI DDP Manager.
  3. *
  4. * Copyright (c) 2008 Chelsio Communications, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Written by: Karen Xie (kxie@chelsio.com)
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/skbuff.h>
  14. #include <linux/scatterlist.h>
  15. /* from cxgb3 LLD */
  16. #include "common.h"
  17. #include "t3_cpl.h"
  18. #include "t3cdev.h"
  19. #include "cxgb3_ctl_defs.h"
  20. #include "cxgb3_offload.h"
  21. #include "firmware_exports.h"
  22. #include "cxgb3i_ddp.h"
  23. #define ddp_log_error(fmt...) printk(KERN_ERR "cxgb3i_ddp: ERR! " fmt)
  24. #define ddp_log_warn(fmt...) printk(KERN_WARNING "cxgb3i_ddp: WARN! " fmt)
  25. #define ddp_log_info(fmt...) printk(KERN_INFO "cxgb3i_ddp: " fmt)
  26. #ifdef __DEBUG_CXGB3I_DDP__
  27. #define ddp_log_debug(fmt, args...) \
  28. printk(KERN_INFO "cxgb3i_ddp: %s - " fmt, __func__ , ## args)
  29. #else
  30. #define ddp_log_debug(fmt...)
  31. #endif
  32. /*
  33. * iSCSI Direct Data Placement
  34. *
  35. * T3 h/w can directly place the iSCSI Data-In or Data-Out PDU's payload into
  36. * pre-posted final destination host-memory buffers based on the Initiator
  37. * Task Tag (ITT) in Data-In or Target Task Tag (TTT) in Data-Out PDUs.
  38. *
  39. * The host memory address is programmed into h/w in the format of pagepod
  40. * entries.
  41. * The location of the pagepod entry is encoded into ddp tag which is used or
  42. * is the base for ITT/TTT.
  43. */
  44. #define DDP_PGIDX_MAX 4
  45. #define DDP_THRESHOLD 2048
  46. static unsigned char ddp_page_order[DDP_PGIDX_MAX] = {0, 1, 2, 4};
  47. static unsigned char ddp_page_shift[DDP_PGIDX_MAX] = {12, 13, 14, 16};
  48. static unsigned char page_idx = DDP_PGIDX_MAX;
  49. /*
  50. * functions to program the pagepod in h/w
  51. */
  52. static inline void ulp_mem_io_set_hdr(struct sk_buff *skb, unsigned int addr)
  53. {
  54. struct ulp_mem_io *req = (struct ulp_mem_io *)skb->head;
  55. req->wr.wr_lo = 0;
  56. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS));
  57. req->cmd_lock_addr = htonl(V_ULP_MEMIO_ADDR(addr >> 5) |
  58. V_ULPTX_CMD(ULP_MEM_WRITE));
  59. req->len = htonl(V_ULP_MEMIO_DATA_LEN(PPOD_SIZE >> 5) |
  60. V_ULPTX_NFLITS((PPOD_SIZE >> 3) + 1));
  61. }
  62. static int set_ddp_map(struct cxgb3i_ddp_info *ddp, struct pagepod_hdr *hdr,
  63. unsigned int idx, unsigned int npods,
  64. struct cxgb3i_gather_list *gl)
  65. {
  66. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  67. int i;
  68. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  69. struct sk_buff *skb = ddp->gl_skb[idx];
  70. struct pagepod *ppod;
  71. int j, pidx;
  72. /* hold on to the skb until we clear the ddp mapping */
  73. skb_get(skb);
  74. ulp_mem_io_set_hdr(skb, pm_addr);
  75. ppod = (struct pagepod *)
  76. (skb->head + sizeof(struct ulp_mem_io));
  77. memcpy(&(ppod->hdr), hdr, sizeof(struct pagepod));
  78. for (pidx = 4 * i, j = 0; j < 5; ++j, ++pidx)
  79. ppod->addr[j] = pidx < gl->nelem ?
  80. cpu_to_be64(gl->phys_addr[pidx]) : 0UL;
  81. skb->priority = CPL_PRIORITY_CONTROL;
  82. cxgb3_ofld_send(ddp->tdev, skb);
  83. }
  84. return 0;
  85. }
  86. static void clear_ddp_map(struct cxgb3i_ddp_info *ddp, unsigned int tag,
  87. unsigned int idx, unsigned int npods)
  88. {
  89. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  90. int i;
  91. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  92. struct sk_buff *skb = ddp->gl_skb[idx];
  93. if (!skb) {
  94. ddp_log_error("ddp tag 0x%x, 0x%x, %d/%u, skb NULL.\n",
  95. tag, idx, i, npods);
  96. continue;
  97. }
  98. ddp->gl_skb[idx] = NULL;
  99. memset((skb->head + sizeof(struct ulp_mem_io)), 0, PPOD_SIZE);
  100. ulp_mem_io_set_hdr(skb, pm_addr);
  101. skb->priority = CPL_PRIORITY_CONTROL;
  102. cxgb3_ofld_send(ddp->tdev, skb);
  103. }
  104. }
  105. static inline int ddp_find_unused_entries(struct cxgb3i_ddp_info *ddp,
  106. unsigned int start, unsigned int max,
  107. unsigned int count,
  108. struct cxgb3i_gather_list *gl)
  109. {
  110. unsigned int i, j, k;
  111. /* not enough entries */
  112. if ((max - start) < count)
  113. return -EBUSY;
  114. max -= count;
  115. spin_lock(&ddp->map_lock);
  116. for (i = start; i < max;) {
  117. for (j = 0, k = i; j < count; j++, k++) {
  118. if (ddp->gl_map[k])
  119. break;
  120. }
  121. if (j == count) {
  122. for (j = 0, k = i; j < count; j++, k++)
  123. ddp->gl_map[k] = gl;
  124. spin_unlock(&ddp->map_lock);
  125. return i;
  126. }
  127. i += j + 1;
  128. }
  129. spin_unlock(&ddp->map_lock);
  130. return -EBUSY;
  131. }
  132. static inline void ddp_unmark_entries(struct cxgb3i_ddp_info *ddp,
  133. int start, int count)
  134. {
  135. spin_lock(&ddp->map_lock);
  136. memset(&ddp->gl_map[start], 0,
  137. count * sizeof(struct cxgb3i_gather_list *));
  138. spin_unlock(&ddp->map_lock);
  139. }
  140. static inline void ddp_free_gl_skb(struct cxgb3i_ddp_info *ddp,
  141. int idx, int count)
  142. {
  143. int i;
  144. for (i = 0; i < count; i++, idx++)
  145. if (ddp->gl_skb[idx]) {
  146. kfree_skb(ddp->gl_skb[idx]);
  147. ddp->gl_skb[idx] = NULL;
  148. }
  149. }
  150. static inline int ddp_alloc_gl_skb(struct cxgb3i_ddp_info *ddp, int idx,
  151. int count, gfp_t gfp)
  152. {
  153. int i;
  154. for (i = 0; i < count; i++) {
  155. struct sk_buff *skb = alloc_skb(sizeof(struct ulp_mem_io) +
  156. PPOD_SIZE, gfp);
  157. if (skb) {
  158. ddp->gl_skb[idx + i] = skb;
  159. skb_put(skb, sizeof(struct ulp_mem_io) + PPOD_SIZE);
  160. } else {
  161. ddp_free_gl_skb(ddp, idx, i);
  162. return -ENOMEM;
  163. }
  164. }
  165. return 0;
  166. }
  167. /**
  168. * cxgb3i_ddp_find_page_index - return ddp page index for a given page size
  169. * @pgsz: page size
  170. * return the ddp page index, if no match is found return DDP_PGIDX_MAX.
  171. */
  172. int cxgb3i_ddp_find_page_index(unsigned long pgsz)
  173. {
  174. int i;
  175. for (i = 0; i < DDP_PGIDX_MAX; i++) {
  176. if (pgsz == (1UL << ddp_page_shift[i]))
  177. return i;
  178. }
  179. ddp_log_debug("ddp page size 0x%lx not supported.\n", pgsz);
  180. return DDP_PGIDX_MAX;
  181. }
  182. /**
  183. * cxgb3i_ddp_adjust_page_table - adjust page table with PAGE_SIZE
  184. * return the ddp page index, if no match is found return DDP_PGIDX_MAX.
  185. */
  186. int cxgb3i_ddp_adjust_page_table(void)
  187. {
  188. int i;
  189. unsigned int base_order, order;
  190. if (PAGE_SIZE < (1UL << ddp_page_shift[0])) {
  191. ddp_log_info("PAGE_SIZE 0x%lx too small, min. 0x%lx.\n",
  192. PAGE_SIZE, 1UL << ddp_page_shift[0]);
  193. return -EINVAL;
  194. }
  195. base_order = get_order(1UL << ddp_page_shift[0]);
  196. order = get_order(1 << PAGE_SHIFT);
  197. for (i = 0; i < DDP_PGIDX_MAX; i++) {
  198. /* first is the kernel page size, then just doubling the size */
  199. ddp_page_order[i] = order - base_order + i;
  200. ddp_page_shift[i] = PAGE_SHIFT + i;
  201. }
  202. return 0;
  203. }
  204. static inline void ddp_gl_unmap(struct pci_dev *pdev,
  205. struct cxgb3i_gather_list *gl)
  206. {
  207. int i;
  208. for (i = 0; i < gl->nelem; i++)
  209. pci_unmap_page(pdev, gl->phys_addr[i], PAGE_SIZE,
  210. PCI_DMA_FROMDEVICE);
  211. }
  212. static inline int ddp_gl_map(struct pci_dev *pdev,
  213. struct cxgb3i_gather_list *gl)
  214. {
  215. int i;
  216. for (i = 0; i < gl->nelem; i++) {
  217. gl->phys_addr[i] = pci_map_page(pdev, gl->pages[i], 0,
  218. PAGE_SIZE,
  219. PCI_DMA_FROMDEVICE);
  220. if (unlikely(pci_dma_mapping_error(pdev, gl->phys_addr[i])))
  221. goto unmap;
  222. }
  223. return i;
  224. unmap:
  225. if (i) {
  226. unsigned int nelem = gl->nelem;
  227. gl->nelem = i;
  228. ddp_gl_unmap(pdev, gl);
  229. gl->nelem = nelem;
  230. }
  231. return -ENOMEM;
  232. }
  233. /**
  234. * cxgb3i_ddp_make_gl - build ddp page buffer list
  235. * @xferlen: total buffer length
  236. * @sgl: page buffer scatter-gather list
  237. * @sgcnt: # of page buffers
  238. * @pdev: pci_dev, used for pci map
  239. * @gfp: allocation mode
  240. *
  241. * construct a ddp page buffer list from the scsi scattergather list.
  242. * coalesce buffers as much as possible, and obtain dma addresses for
  243. * each page.
  244. *
  245. * Return the cxgb3i_gather_list constructed from the page buffers if the
  246. * memory can be used for ddp. Return NULL otherwise.
  247. */
  248. struct cxgb3i_gather_list *cxgb3i_ddp_make_gl(unsigned int xferlen,
  249. struct scatterlist *sgl,
  250. unsigned int sgcnt,
  251. struct pci_dev *pdev,
  252. gfp_t gfp)
  253. {
  254. struct cxgb3i_gather_list *gl;
  255. struct scatterlist *sg = sgl;
  256. struct page *sgpage = sg_page(sg);
  257. unsigned int sglen = sg->length;
  258. unsigned int sgoffset = sg->offset;
  259. unsigned int npages = (xferlen + sgoffset + PAGE_SIZE - 1) >>
  260. PAGE_SHIFT;
  261. int i = 1, j = 0;
  262. if (xferlen < DDP_THRESHOLD) {
  263. ddp_log_debug("xfer %u < threshold %u, no ddp.\n",
  264. xferlen, DDP_THRESHOLD);
  265. return NULL;
  266. }
  267. gl = kzalloc(sizeof(struct cxgb3i_gather_list) +
  268. npages * (sizeof(dma_addr_t) + sizeof(struct page *)),
  269. gfp);
  270. if (!gl)
  271. return NULL;
  272. gl->pages = (struct page **)&gl->phys_addr[npages];
  273. gl->length = xferlen;
  274. gl->offset = sgoffset;
  275. gl->pages[0] = sgpage;
  276. sg = sg_next(sg);
  277. while (sg) {
  278. struct page *page = sg_page(sg);
  279. if (sgpage == page && sg->offset == sgoffset + sglen)
  280. sglen += sg->length;
  281. else {
  282. /* make sure the sgl is fit for ddp:
  283. * each has the same page size, and
  284. * all of the middle pages are used completely
  285. */
  286. if ((j && sgoffset) ||
  287. ((i != sgcnt - 1) &&
  288. ((sglen + sgoffset) & ~PAGE_MASK)))
  289. goto error_out;
  290. j++;
  291. if (j == gl->nelem || sg->offset)
  292. goto error_out;
  293. gl->pages[j] = page;
  294. sglen = sg->length;
  295. sgoffset = sg->offset;
  296. sgpage = page;
  297. }
  298. i++;
  299. sg = sg_next(sg);
  300. }
  301. gl->nelem = ++j;
  302. if (ddp_gl_map(pdev, gl) < 0)
  303. goto error_out;
  304. return gl;
  305. error_out:
  306. kfree(gl);
  307. return NULL;
  308. }
  309. /**
  310. * cxgb3i_ddp_release_gl - release a page buffer list
  311. * @gl: a ddp page buffer list
  312. * @pdev: pci_dev used for pci_unmap
  313. * free a ddp page buffer list resulted from cxgb3i_ddp_make_gl().
  314. */
  315. void cxgb3i_ddp_release_gl(struct cxgb3i_gather_list *gl,
  316. struct pci_dev *pdev)
  317. {
  318. ddp_gl_unmap(pdev, gl);
  319. kfree(gl);
  320. }
  321. /**
  322. * cxgb3i_ddp_tag_reserve - set up ddp for a data transfer
  323. * @tdev: t3cdev adapter
  324. * @tid: connection id
  325. * @tformat: tag format
  326. * @tagp: contains s/w tag initially, will be updated with ddp/hw tag
  327. * @gl: the page momory list
  328. * @gfp: allocation mode
  329. *
  330. * ddp setup for a given page buffer list and construct the ddp tag.
  331. * return 0 if success, < 0 otherwise.
  332. */
  333. int cxgb3i_ddp_tag_reserve(struct t3cdev *tdev, unsigned int tid,
  334. struct cxgb3i_tag_format *tformat, u32 *tagp,
  335. struct cxgb3i_gather_list *gl, gfp_t gfp)
  336. {
  337. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  338. struct pagepod_hdr hdr;
  339. unsigned int npods;
  340. int idx = -1;
  341. int err = -ENOMEM;
  342. u32 sw_tag = *tagp;
  343. u32 tag;
  344. if (page_idx >= DDP_PGIDX_MAX || !ddp || !gl || !gl->nelem ||
  345. gl->length < DDP_THRESHOLD) {
  346. ddp_log_debug("pgidx %u, xfer %u/%u, NO ddp.\n",
  347. page_idx, gl->length, DDP_THRESHOLD);
  348. return -EINVAL;
  349. }
  350. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  351. if (ddp->idx_last == ddp->nppods)
  352. idx = ddp_find_unused_entries(ddp, 0, ddp->nppods, npods, gl);
  353. else {
  354. idx = ddp_find_unused_entries(ddp, ddp->idx_last + 1,
  355. ddp->nppods, npods, gl);
  356. if (idx < 0 && ddp->idx_last >= npods) {
  357. idx = ddp_find_unused_entries(ddp, 0,
  358. min(ddp->idx_last + npods, ddp->nppods),
  359. npods, gl);
  360. }
  361. }
  362. if (idx < 0) {
  363. ddp_log_debug("xferlen %u, gl %u, npods %u NO DDP.\n",
  364. gl->length, gl->nelem, npods);
  365. return idx;
  366. }
  367. err = ddp_alloc_gl_skb(ddp, idx, npods, gfp);
  368. if (err < 0)
  369. goto unmark_entries;
  370. tag = cxgb3i_ddp_tag_base(tformat, sw_tag);
  371. tag |= idx << PPOD_IDX_SHIFT;
  372. hdr.rsvd = 0;
  373. hdr.vld_tid = htonl(F_PPOD_VALID | V_PPOD_TID(tid));
  374. hdr.pgsz_tag_clr = htonl(tag & ddp->rsvd_tag_mask);
  375. hdr.maxoffset = htonl(gl->length);
  376. hdr.pgoffset = htonl(gl->offset);
  377. err = set_ddp_map(ddp, &hdr, idx, npods, gl);
  378. if (err < 0)
  379. goto free_gl_skb;
  380. ddp->idx_last = idx;
  381. ddp_log_debug("xfer %u, gl %u,%u, tid 0x%x, 0x%x -> 0x%x(%u,%u).\n",
  382. gl->length, gl->nelem, gl->offset, tid, sw_tag, tag,
  383. idx, npods);
  384. *tagp = tag;
  385. return 0;
  386. free_gl_skb:
  387. ddp_free_gl_skb(ddp, idx, npods);
  388. unmark_entries:
  389. ddp_unmark_entries(ddp, idx, npods);
  390. return err;
  391. }
  392. /**
  393. * cxgb3i_ddp_tag_release - release a ddp tag
  394. * @tdev: t3cdev adapter
  395. * @tag: ddp tag
  396. * ddp cleanup for a given ddp tag and release all the resources held
  397. */
  398. void cxgb3i_ddp_tag_release(struct t3cdev *tdev, u32 tag)
  399. {
  400. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  401. u32 idx;
  402. if (!ddp) {
  403. ddp_log_error("release ddp tag 0x%x, ddp NULL.\n", tag);
  404. return;
  405. }
  406. idx = (tag >> PPOD_IDX_SHIFT) & ddp->idx_mask;
  407. if (idx < ddp->nppods) {
  408. struct cxgb3i_gather_list *gl = ddp->gl_map[idx];
  409. unsigned int npods;
  410. if (!gl || !gl->nelem) {
  411. ddp_log_error("release 0x%x, idx 0x%x, gl 0x%p, %u.\n",
  412. tag, idx, gl, gl ? gl->nelem : 0);
  413. return;
  414. }
  415. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  416. ddp_log_debug("ddp tag 0x%x, release idx 0x%x, npods %u.\n",
  417. tag, idx, npods);
  418. clear_ddp_map(ddp, tag, idx, npods);
  419. ddp_unmark_entries(ddp, idx, npods);
  420. cxgb3i_ddp_release_gl(gl, ddp->pdev);
  421. } else
  422. ddp_log_error("ddp tag 0x%x, idx 0x%x > max 0x%x.\n",
  423. tag, idx, ddp->nppods);
  424. }
  425. static int setup_conn_pgidx(struct t3cdev *tdev, unsigned int tid, int pg_idx,
  426. int reply)
  427. {
  428. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  429. GFP_KERNEL);
  430. struct cpl_set_tcb_field *req;
  431. u64 val = pg_idx < DDP_PGIDX_MAX ? pg_idx : 0;
  432. if (!skb)
  433. return -ENOMEM;
  434. /* set up ulp submode and page size */
  435. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  436. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  437. req->wr.wr_lo = 0;
  438. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  439. req->reply = V_NO_REPLY(reply ? 0 : 1);
  440. req->cpu_idx = 0;
  441. req->word = htons(31);
  442. req->mask = cpu_to_be64(0xF0000000);
  443. req->val = cpu_to_be64(val << 28);
  444. skb->priority = CPL_PRIORITY_CONTROL;
  445. cxgb3_ofld_send(tdev, skb);
  446. return 0;
  447. }
  448. /**
  449. * cxgb3i_setup_conn_host_pagesize - setup the conn.'s ddp page size
  450. * @tdev: t3cdev adapter
  451. * @tid: connection id
  452. * @reply: request reply from h/w
  453. * set up the ddp page size based on the host PAGE_SIZE for a connection
  454. * identified by tid
  455. */
  456. int cxgb3i_setup_conn_host_pagesize(struct t3cdev *tdev, unsigned int tid,
  457. int reply)
  458. {
  459. return setup_conn_pgidx(tdev, tid, page_idx, reply);
  460. }
  461. /**
  462. * cxgb3i_setup_conn_pagesize - setup the conn.'s ddp page size
  463. * @tdev: t3cdev adapter
  464. * @tid: connection id
  465. * @reply: request reply from h/w
  466. * @pgsz: ddp page size
  467. * set up the ddp page size for a connection identified by tid
  468. */
  469. int cxgb3i_setup_conn_pagesize(struct t3cdev *tdev, unsigned int tid,
  470. int reply, unsigned long pgsz)
  471. {
  472. int pgidx = cxgb3i_ddp_find_page_index(pgsz);
  473. return setup_conn_pgidx(tdev, tid, pgidx, reply);
  474. }
  475. /**
  476. * cxgb3i_setup_conn_digest - setup conn. digest setting
  477. * @tdev: t3cdev adapter
  478. * @tid: connection id
  479. * @hcrc: header digest enabled
  480. * @dcrc: data digest enabled
  481. * @reply: request reply from h/w
  482. * set up the iscsi digest settings for a connection identified by tid
  483. */
  484. int cxgb3i_setup_conn_digest(struct t3cdev *tdev, unsigned int tid,
  485. int hcrc, int dcrc, int reply)
  486. {
  487. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  488. GFP_KERNEL);
  489. struct cpl_set_tcb_field *req;
  490. u64 val = (hcrc ? 1 : 0) | (dcrc ? 2 : 0);
  491. if (!skb)
  492. return -ENOMEM;
  493. /* set up ulp submode and page size */
  494. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  495. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  496. req->wr.wr_lo = 0;
  497. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  498. req->reply = V_NO_REPLY(reply ? 0 : 1);
  499. req->cpu_idx = 0;
  500. req->word = htons(31);
  501. req->mask = cpu_to_be64(0x0F000000);
  502. req->val = cpu_to_be64(val << 24);
  503. skb->priority = CPL_PRIORITY_CONTROL;
  504. cxgb3_ofld_send(tdev, skb);
  505. return 0;
  506. }
  507. /**
  508. * cxgb3i_adapter_ddp_info - read the adapter's ddp information
  509. * @tdev: t3cdev adapter
  510. * @tformat: tag format
  511. * @txsz: max tx pdu payload size, filled in by this func.
  512. * @rxsz: max rx pdu payload size, filled in by this func.
  513. * setup the tag format for a given iscsi entity
  514. */
  515. int cxgb3i_adapter_ddp_info(struct t3cdev *tdev,
  516. struct cxgb3i_tag_format *tformat,
  517. unsigned int *txsz, unsigned int *rxsz)
  518. {
  519. struct cxgb3i_ddp_info *ddp;
  520. unsigned char idx_bits;
  521. if (!tformat)
  522. return -EINVAL;
  523. if (!tdev->ulp_iscsi)
  524. return -EINVAL;
  525. ddp = (struct cxgb3i_ddp_info *)tdev->ulp_iscsi;
  526. idx_bits = 32 - tformat->sw_bits;
  527. tformat->rsvd_bits = ddp->idx_bits;
  528. tformat->rsvd_shift = PPOD_IDX_SHIFT;
  529. tformat->rsvd_mask = (1 << tformat->rsvd_bits) - 1;
  530. ddp_log_info("tag format: sw %u, rsvd %u,%u, mask 0x%x.\n",
  531. tformat->sw_bits, tformat->rsvd_bits,
  532. tformat->rsvd_shift, tformat->rsvd_mask);
  533. *txsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  534. ddp->max_txsz - ISCSI_PDU_NONPAYLOAD_LEN);
  535. *rxsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  536. ddp->max_rxsz - ISCSI_PDU_NONPAYLOAD_LEN);
  537. ddp_log_info("max payload size: %u/%u, %u/%u.\n",
  538. *txsz, ddp->max_txsz, *rxsz, ddp->max_rxsz);
  539. return 0;
  540. }
  541. /**
  542. * cxgb3i_ddp_cleanup - release the cxgb3 adapter's ddp resource
  543. * @tdev: t3cdev adapter
  544. * release all the resource held by the ddp pagepod manager for a given
  545. * adapter if needed
  546. */
  547. static void ddp_cleanup(struct kref *kref)
  548. {
  549. struct cxgb3i_ddp_info *ddp = container_of(kref,
  550. struct cxgb3i_ddp_info,
  551. refcnt);
  552. int i = 0;
  553. ddp_log_info("kref release ddp 0x%p, t3dev 0x%p.\n", ddp, ddp->tdev);
  554. ddp->tdev->ulp_iscsi = NULL;
  555. while (i < ddp->nppods) {
  556. struct cxgb3i_gather_list *gl = ddp->gl_map[i];
  557. if (gl) {
  558. int npods = (gl->nelem + PPOD_PAGES_MAX - 1)
  559. >> PPOD_PAGES_SHIFT;
  560. ddp_log_info("t3dev 0x%p, ddp %d + %d.\n",
  561. ddp->tdev, i, npods);
  562. kfree(gl);
  563. ddp_free_gl_skb(ddp, i, npods);
  564. i += npods;
  565. } else
  566. i++;
  567. }
  568. cxgb3i_free_big_mem(ddp);
  569. }
  570. void cxgb3i_ddp_cleanup(struct t3cdev *tdev)
  571. {
  572. struct cxgb3i_ddp_info *ddp = (struct cxgb3i_ddp_info *)tdev->ulp_iscsi;
  573. ddp_log_info("t3dev 0x%p, release ddp 0x%p.\n", tdev, ddp);
  574. if (ddp)
  575. kref_put(&ddp->refcnt, ddp_cleanup);
  576. }
  577. /**
  578. * ddp_init - initialize the cxgb3 adapter's ddp resource
  579. * @tdev: t3cdev adapter
  580. * initialize the ddp pagepod manager for a given adapter
  581. */
  582. static void ddp_init(struct t3cdev *tdev)
  583. {
  584. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  585. struct ulp_iscsi_info uinfo;
  586. unsigned int ppmax, bits;
  587. int i, err;
  588. if (ddp) {
  589. kref_get(&ddp->refcnt);
  590. ddp_log_warn("t3dev 0x%p, ddp 0x%p already set up.\n",
  591. tdev, tdev->ulp_iscsi);
  592. return;
  593. }
  594. err = tdev->ctl(tdev, ULP_ISCSI_GET_PARAMS, &uinfo);
  595. if (err < 0) {
  596. ddp_log_error("%s, failed to get iscsi param err=%d.\n",
  597. tdev->name, err);
  598. return;
  599. }
  600. ppmax = (uinfo.ulimit - uinfo.llimit + 1) >> PPOD_SIZE_SHIFT;
  601. bits = __ilog2_u32(ppmax) + 1;
  602. if (bits > PPOD_IDX_MAX_SIZE)
  603. bits = PPOD_IDX_MAX_SIZE;
  604. ppmax = (1 << (bits - 1)) - 1;
  605. ddp = cxgb3i_alloc_big_mem(sizeof(struct cxgb3i_ddp_info) +
  606. ppmax *
  607. (sizeof(struct cxgb3i_gather_list *) +
  608. sizeof(struct sk_buff *)),
  609. GFP_KERNEL);
  610. if (!ddp) {
  611. ddp_log_warn("%s unable to alloc ddp 0x%d, ddp disabled.\n",
  612. tdev->name, ppmax);
  613. return;
  614. }
  615. ddp->gl_map = (struct cxgb3i_gather_list **)(ddp + 1);
  616. ddp->gl_skb = (struct sk_buff **)(((char *)ddp->gl_map) +
  617. ppmax *
  618. sizeof(struct cxgb3i_gather_list *));
  619. spin_lock_init(&ddp->map_lock);
  620. kref_init(&ddp->refcnt);
  621. ddp->tdev = tdev;
  622. ddp->pdev = uinfo.pdev;
  623. ddp->max_txsz = min_t(unsigned int, uinfo.max_txsz, ULP2_MAX_PKT_SIZE);
  624. ddp->max_rxsz = min_t(unsigned int, uinfo.max_rxsz, ULP2_MAX_PKT_SIZE);
  625. ddp->llimit = uinfo.llimit;
  626. ddp->ulimit = uinfo.ulimit;
  627. ddp->nppods = ppmax;
  628. ddp->idx_last = ppmax;
  629. ddp->idx_bits = bits;
  630. ddp->idx_mask = (1 << bits) - 1;
  631. ddp->rsvd_tag_mask = (1 << (bits + PPOD_IDX_SHIFT)) - 1;
  632. uinfo.tagmask = ddp->idx_mask << PPOD_IDX_SHIFT;
  633. for (i = 0; i < DDP_PGIDX_MAX; i++)
  634. uinfo.pgsz_factor[i] = ddp_page_order[i];
  635. uinfo.ulimit = uinfo.llimit + (ppmax << PPOD_SIZE_SHIFT);
  636. err = tdev->ctl(tdev, ULP_ISCSI_SET_PARAMS, &uinfo);
  637. if (err < 0) {
  638. ddp_log_warn("%s unable to set iscsi param err=%d, "
  639. "ddp disabled.\n", tdev->name, err);
  640. goto free_ddp_map;
  641. }
  642. tdev->ulp_iscsi = ddp;
  643. ddp_log_info("tdev 0x%p, nppods %u, bits %u, mask 0x%x,0x%x pkt %u/%u,"
  644. " %u/%u.\n",
  645. tdev, ppmax, ddp->idx_bits, ddp->idx_mask,
  646. ddp->rsvd_tag_mask, ddp->max_txsz, uinfo.max_txsz,
  647. ddp->max_rxsz, uinfo.max_rxsz);
  648. return;
  649. free_ddp_map:
  650. cxgb3i_free_big_mem(ddp);
  651. }
  652. /**
  653. * cxgb3i_ddp_init - initialize ddp functions
  654. */
  655. void cxgb3i_ddp_init(struct t3cdev *tdev)
  656. {
  657. if (page_idx == DDP_PGIDX_MAX) {
  658. page_idx = cxgb3i_ddp_find_page_index(PAGE_SIZE);
  659. if (page_idx == DDP_PGIDX_MAX) {
  660. ddp_log_info("system PAGE_SIZE %lu, update hw.\n",
  661. PAGE_SIZE);
  662. if (cxgb3i_ddp_adjust_page_table() < 0) {
  663. ddp_log_info("PAGE_SIZE %lu, ddp disabled.\n",
  664. PAGE_SIZE);
  665. return;
  666. }
  667. page_idx = cxgb3i_ddp_find_page_index(PAGE_SIZE);
  668. }
  669. ddp_log_info("system PAGE_SIZE %lu, ddp idx %u.\n",
  670. PAGE_SIZE, page_idx);
  671. }
  672. ddp_init(tdev);
  673. }