iwl-agn.c 129 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/slab.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/delay.h>
  37. #include <linux/sched.h>
  38. #include <linux/skbuff.h>
  39. #include <linux/netdevice.h>
  40. #include <linux/wireless.h>
  41. #include <linux/firmware.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/if_arp.h>
  44. #include <net/mac80211.h>
  45. #include <asm/div64.h>
  46. #define DRV_NAME "iwlagn"
  47. #include "iwl-eeprom.h"
  48. #include "iwl-dev.h"
  49. #include "iwl-core.h"
  50. #include "iwl-io.h"
  51. #include "iwl-helpers.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-calib.h"
  54. #include "iwl-agn.h"
  55. /******************************************************************************
  56. *
  57. * module boiler plate
  58. *
  59. ******************************************************************************/
  60. /*
  61. * module name, copyright, version, etc.
  62. */
  63. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  64. #ifdef CONFIG_IWLWIFI_DEBUG
  65. #define VD "d"
  66. #else
  67. #define VD
  68. #endif
  69. #define DRV_VERSION IWLWIFI_VERSION VD
  70. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  71. MODULE_VERSION(DRV_VERSION);
  72. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  73. MODULE_LICENSE("GPL");
  74. MODULE_ALIAS("iwl4965");
  75. /**
  76. * iwl_commit_rxon - commit staging_rxon to hardware
  77. *
  78. * The RXON command in staging_rxon is committed to the hardware and
  79. * the active_rxon structure is updated with the new data. This
  80. * function correctly transitions out of the RXON_ASSOC_MSK state if
  81. * a HW tune is required based on the RXON structure changes.
  82. */
  83. int iwl_commit_rxon(struct iwl_priv *priv)
  84. {
  85. /* cast away the const for active_rxon in this function */
  86. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  87. int ret;
  88. bool new_assoc =
  89. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  90. if (!iwl_is_alive(priv))
  91. return -EBUSY;
  92. /* always get timestamp with Rx frame */
  93. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  94. ret = iwl_check_rxon_cmd(priv);
  95. if (ret) {
  96. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  97. return -EINVAL;
  98. }
  99. /*
  100. * receive commit_rxon request
  101. * abort any previous channel switch if still in process
  102. */
  103. if (priv->switch_rxon.switch_in_progress &&
  104. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  105. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  106. le16_to_cpu(priv->switch_rxon.channel));
  107. iwl_chswitch_done(priv, false);
  108. }
  109. /* If we don't need to send a full RXON, we can use
  110. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  111. * and other flags for the current radio configuration. */
  112. if (!iwl_full_rxon_required(priv)) {
  113. ret = iwl_send_rxon_assoc(priv);
  114. if (ret) {
  115. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  116. return ret;
  117. }
  118. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  119. iwl_print_rx_config_cmd(priv);
  120. return 0;
  121. }
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. iwl_clear_ucode_stations(priv);
  140. iwl_restore_stations(priv);
  141. ret = iwl_restore_default_wep_keys(priv);
  142. if (ret) {
  143. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  144. return ret;
  145. }
  146. }
  147. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  148. "* with%s RXON_FILTER_ASSOC_MSK\n"
  149. "* channel = %d\n"
  150. "* bssid = %pM\n",
  151. (new_assoc ? "" : "out"),
  152. le16_to_cpu(priv->staging_rxon.channel),
  153. priv->staging_rxon.bssid_addr);
  154. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  155. /* Apply the new configuration
  156. * RXON unassoc clears the station table in uCode so restoration of
  157. * stations is needed after it (the RXON command) completes
  158. */
  159. if (!new_assoc) {
  160. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  161. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  162. if (ret) {
  163. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  164. return ret;
  165. }
  166. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  167. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  168. iwl_clear_ucode_stations(priv);
  169. iwl_restore_stations(priv);
  170. ret = iwl_restore_default_wep_keys(priv);
  171. if (ret) {
  172. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  173. return ret;
  174. }
  175. }
  176. priv->start_calib = 0;
  177. if (new_assoc) {
  178. /* Apply the new configuration
  179. * RXON assoc doesn't clear the station table in uCode,
  180. */
  181. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  182. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  183. if (ret) {
  184. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  185. return ret;
  186. }
  187. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  188. }
  189. iwl_print_rx_config_cmd(priv);
  190. iwl_init_sensitivity(priv);
  191. /* If we issue a new RXON command which required a tune then we must
  192. * send a new TXPOWER command or we won't be able to Tx any frames */
  193. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  194. if (ret) {
  195. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  196. return ret;
  197. }
  198. return 0;
  199. }
  200. void iwl_update_chain_flags(struct iwl_priv *priv)
  201. {
  202. if (priv->cfg->ops->hcmd->set_rxon_chain)
  203. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  204. iwlcore_commit_rxon(priv);
  205. }
  206. static void iwl_clear_free_frames(struct iwl_priv *priv)
  207. {
  208. struct list_head *element;
  209. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  210. priv->frames_count);
  211. while (!list_empty(&priv->free_frames)) {
  212. element = priv->free_frames.next;
  213. list_del(element);
  214. kfree(list_entry(element, struct iwl_frame, list));
  215. priv->frames_count--;
  216. }
  217. if (priv->frames_count) {
  218. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  219. priv->frames_count);
  220. priv->frames_count = 0;
  221. }
  222. }
  223. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  224. {
  225. struct iwl_frame *frame;
  226. struct list_head *element;
  227. if (list_empty(&priv->free_frames)) {
  228. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  229. if (!frame) {
  230. IWL_ERR(priv, "Could not allocate frame!\n");
  231. return NULL;
  232. }
  233. priv->frames_count++;
  234. return frame;
  235. }
  236. element = priv->free_frames.next;
  237. list_del(element);
  238. return list_entry(element, struct iwl_frame, list);
  239. }
  240. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  241. {
  242. memset(frame, 0, sizeof(*frame));
  243. list_add(&frame->list, &priv->free_frames);
  244. }
  245. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  246. struct ieee80211_hdr *hdr,
  247. int left)
  248. {
  249. if (!priv->ibss_beacon)
  250. return 0;
  251. if (priv->ibss_beacon->len > left)
  252. return 0;
  253. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  254. return priv->ibss_beacon->len;
  255. }
  256. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  257. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  258. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  259. u8 *beacon, u32 frame_size)
  260. {
  261. u16 tim_idx;
  262. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  263. /*
  264. * The index is relative to frame start but we start looking at the
  265. * variable-length part of the beacon.
  266. */
  267. tim_idx = mgmt->u.beacon.variable - beacon;
  268. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  269. while ((tim_idx < (frame_size - 2)) &&
  270. (beacon[tim_idx] != WLAN_EID_TIM))
  271. tim_idx += beacon[tim_idx+1] + 2;
  272. /* If TIM field was found, set variables */
  273. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  274. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  275. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  276. } else
  277. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  278. }
  279. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  280. struct iwl_frame *frame)
  281. {
  282. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  283. u32 frame_size;
  284. u32 rate_flags;
  285. u32 rate;
  286. /*
  287. * We have to set up the TX command, the TX Beacon command, and the
  288. * beacon contents.
  289. */
  290. /* Initialize memory */
  291. tx_beacon_cmd = &frame->u.beacon;
  292. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  293. /* Set up TX beacon contents */
  294. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  295. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  296. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  297. return 0;
  298. /* Set up TX command fields */
  299. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  300. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  301. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  302. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  303. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  304. /* Set up TX beacon command fields */
  305. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  306. frame_size);
  307. /* Set up packet rate and flags */
  308. rate = iwl_rate_get_lowest_plcp(priv);
  309. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  310. priv->hw_params.valid_tx_ant);
  311. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  312. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  313. rate_flags |= RATE_MCS_CCK_MSK;
  314. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  315. rate_flags);
  316. return sizeof(*tx_beacon_cmd) + frame_size;
  317. }
  318. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  319. {
  320. struct iwl_frame *frame;
  321. unsigned int frame_size;
  322. int rc;
  323. frame = iwl_get_free_frame(priv);
  324. if (!frame) {
  325. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  326. "command.\n");
  327. return -ENOMEM;
  328. }
  329. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  330. if (!frame_size) {
  331. IWL_ERR(priv, "Error configuring the beacon command\n");
  332. iwl_free_frame(priv, frame);
  333. return -EINVAL;
  334. }
  335. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  336. &frame->u.cmd[0]);
  337. iwl_free_frame(priv, frame);
  338. return rc;
  339. }
  340. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  341. {
  342. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  343. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  344. if (sizeof(dma_addr_t) > sizeof(u32))
  345. addr |=
  346. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  347. return addr;
  348. }
  349. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  350. {
  351. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  352. return le16_to_cpu(tb->hi_n_len) >> 4;
  353. }
  354. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  355. dma_addr_t addr, u16 len)
  356. {
  357. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  358. u16 hi_n_len = len << 4;
  359. put_unaligned_le32(addr, &tb->lo);
  360. if (sizeof(dma_addr_t) > sizeof(u32))
  361. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  362. tb->hi_n_len = cpu_to_le16(hi_n_len);
  363. tfd->num_tbs = idx + 1;
  364. }
  365. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  366. {
  367. return tfd->num_tbs & 0x1f;
  368. }
  369. /**
  370. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  371. * @priv - driver private data
  372. * @txq - tx queue
  373. *
  374. * Does NOT advance any TFD circular buffer read/write indexes
  375. * Does NOT free the TFD itself (which is within circular buffer)
  376. */
  377. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  378. {
  379. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  380. struct iwl_tfd *tfd;
  381. struct pci_dev *dev = priv->pci_dev;
  382. int index = txq->q.read_ptr;
  383. int i;
  384. int num_tbs;
  385. tfd = &tfd_tmp[index];
  386. /* Sanity check on number of chunks */
  387. num_tbs = iwl_tfd_get_num_tbs(tfd);
  388. if (num_tbs >= IWL_NUM_OF_TBS) {
  389. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  390. /* @todo issue fatal error, it is quite serious situation */
  391. return;
  392. }
  393. /* Unmap tx_cmd */
  394. if (num_tbs)
  395. pci_unmap_single(dev,
  396. dma_unmap_addr(&txq->meta[index], mapping),
  397. dma_unmap_len(&txq->meta[index], len),
  398. PCI_DMA_BIDIRECTIONAL);
  399. /* Unmap chunks, if any. */
  400. for (i = 1; i < num_tbs; i++)
  401. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  402. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  403. /* free SKB */
  404. if (txq->txb) {
  405. struct sk_buff *skb;
  406. skb = txq->txb[txq->q.read_ptr].skb;
  407. /* can be called from irqs-disabled context */
  408. if (skb) {
  409. dev_kfree_skb_any(skb);
  410. txq->txb[txq->q.read_ptr].skb = NULL;
  411. }
  412. }
  413. }
  414. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  415. struct iwl_tx_queue *txq,
  416. dma_addr_t addr, u16 len,
  417. u8 reset, u8 pad)
  418. {
  419. struct iwl_queue *q;
  420. struct iwl_tfd *tfd, *tfd_tmp;
  421. u32 num_tbs;
  422. q = &txq->q;
  423. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  424. tfd = &tfd_tmp[q->write_ptr];
  425. if (reset)
  426. memset(tfd, 0, sizeof(*tfd));
  427. num_tbs = iwl_tfd_get_num_tbs(tfd);
  428. /* Each TFD can point to a maximum 20 Tx buffers */
  429. if (num_tbs >= IWL_NUM_OF_TBS) {
  430. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  431. IWL_NUM_OF_TBS);
  432. return -EINVAL;
  433. }
  434. BUG_ON(addr & ~DMA_BIT_MASK(36));
  435. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  436. IWL_ERR(priv, "Unaligned address = %llx\n",
  437. (unsigned long long)addr);
  438. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  439. return 0;
  440. }
  441. /*
  442. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  443. * given Tx queue, and enable the DMA channel used for that queue.
  444. *
  445. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  446. * channels supported in hardware.
  447. */
  448. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  449. struct iwl_tx_queue *txq)
  450. {
  451. int txq_id = txq->q.id;
  452. /* Circular buffer (TFD queue in DRAM) physical base address */
  453. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  454. txq->q.dma_addr >> 8);
  455. return 0;
  456. }
  457. /******************************************************************************
  458. *
  459. * Generic RX handler implementations
  460. *
  461. ******************************************************************************/
  462. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  463. struct iwl_rx_mem_buffer *rxb)
  464. {
  465. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  466. struct iwl_alive_resp *palive;
  467. struct delayed_work *pwork;
  468. palive = &pkt->u.alive_frame;
  469. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  470. "0x%01X 0x%01X\n",
  471. palive->is_valid, palive->ver_type,
  472. palive->ver_subtype);
  473. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  474. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  475. memcpy(&priv->card_alive_init,
  476. &pkt->u.alive_frame,
  477. sizeof(struct iwl_init_alive_resp));
  478. pwork = &priv->init_alive_start;
  479. } else {
  480. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  481. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  482. sizeof(struct iwl_alive_resp));
  483. pwork = &priv->alive_start;
  484. }
  485. /* We delay the ALIVE response by 5ms to
  486. * give the HW RF Kill time to activate... */
  487. if (palive->is_valid == UCODE_VALID_OK)
  488. queue_delayed_work(priv->workqueue, pwork,
  489. msecs_to_jiffies(5));
  490. else
  491. IWL_WARN(priv, "uCode did not respond OK.\n");
  492. }
  493. static void iwl_bg_beacon_update(struct work_struct *work)
  494. {
  495. struct iwl_priv *priv =
  496. container_of(work, struct iwl_priv, beacon_update);
  497. struct sk_buff *beacon;
  498. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  499. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  500. if (!beacon) {
  501. IWL_ERR(priv, "update beacon failed\n");
  502. return;
  503. }
  504. mutex_lock(&priv->mutex);
  505. /* new beacon skb is allocated every time; dispose previous.*/
  506. if (priv->ibss_beacon)
  507. dev_kfree_skb(priv->ibss_beacon);
  508. priv->ibss_beacon = beacon;
  509. mutex_unlock(&priv->mutex);
  510. iwl_send_beacon_cmd(priv);
  511. }
  512. /**
  513. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  514. *
  515. * This callback is provided in order to send a statistics request.
  516. *
  517. * This timer function is continually reset to execute within
  518. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  519. * was received. We need to ensure we receive the statistics in order
  520. * to update the temperature used for calibrating the TXPOWER.
  521. */
  522. static void iwl_bg_statistics_periodic(unsigned long data)
  523. {
  524. struct iwl_priv *priv = (struct iwl_priv *)data;
  525. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  526. return;
  527. /* dont send host command if rf-kill is on */
  528. if (!iwl_is_ready_rf(priv))
  529. return;
  530. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  531. }
  532. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  533. u32 start_idx, u32 num_events,
  534. u32 mode)
  535. {
  536. u32 i;
  537. u32 ptr; /* SRAM byte address of log data */
  538. u32 ev, time, data; /* event log data */
  539. unsigned long reg_flags;
  540. if (mode == 0)
  541. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  542. else
  543. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  544. /* Make sure device is powered up for SRAM reads */
  545. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  546. if (iwl_grab_nic_access(priv)) {
  547. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  548. return;
  549. }
  550. /* Set starting address; reads will auto-increment */
  551. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  552. rmb();
  553. /*
  554. * "time" is actually "data" for mode 0 (no timestamp).
  555. * place event id # at far right for easier visual parsing.
  556. */
  557. for (i = 0; i < num_events; i++) {
  558. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  559. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  560. if (mode == 0) {
  561. trace_iwlwifi_dev_ucode_cont_event(priv,
  562. 0, time, ev);
  563. } else {
  564. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  565. trace_iwlwifi_dev_ucode_cont_event(priv,
  566. time, data, ev);
  567. }
  568. }
  569. /* Allow device to power down */
  570. iwl_release_nic_access(priv);
  571. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  572. }
  573. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  574. {
  575. u32 capacity; /* event log capacity in # entries */
  576. u32 base; /* SRAM byte address of event log header */
  577. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  578. u32 num_wraps; /* # times uCode wrapped to top of log */
  579. u32 next_entry; /* index of next entry to be written by uCode */
  580. if (priv->ucode_type == UCODE_INIT)
  581. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  582. else
  583. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  584. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  585. capacity = iwl_read_targ_mem(priv, base);
  586. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  587. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  588. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  589. } else
  590. return;
  591. if (num_wraps == priv->event_log.num_wraps) {
  592. iwl_print_cont_event_trace(priv,
  593. base, priv->event_log.next_entry,
  594. next_entry - priv->event_log.next_entry,
  595. mode);
  596. priv->event_log.non_wraps_count++;
  597. } else {
  598. if ((num_wraps - priv->event_log.num_wraps) > 1)
  599. priv->event_log.wraps_more_count++;
  600. else
  601. priv->event_log.wraps_once_count++;
  602. trace_iwlwifi_dev_ucode_wrap_event(priv,
  603. num_wraps - priv->event_log.num_wraps,
  604. next_entry, priv->event_log.next_entry);
  605. if (next_entry < priv->event_log.next_entry) {
  606. iwl_print_cont_event_trace(priv, base,
  607. priv->event_log.next_entry,
  608. capacity - priv->event_log.next_entry,
  609. mode);
  610. iwl_print_cont_event_trace(priv, base, 0,
  611. next_entry, mode);
  612. } else {
  613. iwl_print_cont_event_trace(priv, base,
  614. next_entry, capacity - next_entry,
  615. mode);
  616. iwl_print_cont_event_trace(priv, base, 0,
  617. next_entry, mode);
  618. }
  619. }
  620. priv->event_log.num_wraps = num_wraps;
  621. priv->event_log.next_entry = next_entry;
  622. }
  623. /**
  624. * iwl_bg_ucode_trace - Timer callback to log ucode event
  625. *
  626. * The timer is continually set to execute every
  627. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  628. * this function is to perform continuous uCode event logging operation
  629. * if enabled
  630. */
  631. static void iwl_bg_ucode_trace(unsigned long data)
  632. {
  633. struct iwl_priv *priv = (struct iwl_priv *)data;
  634. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  635. return;
  636. if (priv->event_log.ucode_trace) {
  637. iwl_continuous_event_trace(priv);
  638. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  639. mod_timer(&priv->ucode_trace,
  640. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  641. }
  642. }
  643. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  644. struct iwl_rx_mem_buffer *rxb)
  645. {
  646. #ifdef CONFIG_IWLWIFI_DEBUG
  647. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  648. struct iwl4965_beacon_notif *beacon =
  649. (struct iwl4965_beacon_notif *)pkt->u.raw;
  650. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  651. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  652. "tsf %d %d rate %d\n",
  653. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  654. beacon->beacon_notify_hdr.failure_frame,
  655. le32_to_cpu(beacon->ibss_mgr_status),
  656. le32_to_cpu(beacon->high_tsf),
  657. le32_to_cpu(beacon->low_tsf), rate);
  658. #endif
  659. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  660. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  661. queue_work(priv->workqueue, &priv->beacon_update);
  662. }
  663. /* Handle notification from uCode that card's power state is changing
  664. * due to software, hardware, or critical temperature RFKILL */
  665. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  666. struct iwl_rx_mem_buffer *rxb)
  667. {
  668. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  669. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  670. unsigned long status = priv->status;
  671. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  672. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  673. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  674. (flags & CT_CARD_DISABLED) ?
  675. "Reached" : "Not reached");
  676. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  677. CT_CARD_DISABLED)) {
  678. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  679. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  680. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  681. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  682. if (!(flags & RXON_CARD_DISABLED)) {
  683. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  684. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  685. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  686. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  687. }
  688. if (flags & CT_CARD_DISABLED)
  689. iwl_tt_enter_ct_kill(priv);
  690. }
  691. if (!(flags & CT_CARD_DISABLED))
  692. iwl_tt_exit_ct_kill(priv);
  693. if (flags & HW_CARD_DISABLED)
  694. set_bit(STATUS_RF_KILL_HW, &priv->status);
  695. else
  696. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  697. if (!(flags & RXON_CARD_DISABLED))
  698. iwl_scan_cancel(priv);
  699. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  700. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  701. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  702. test_bit(STATUS_RF_KILL_HW, &priv->status));
  703. else
  704. wake_up_interruptible(&priv->wait_command_queue);
  705. }
  706. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  707. {
  708. if (src == IWL_PWR_SRC_VAUX) {
  709. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  710. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  711. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  712. ~APMG_PS_CTRL_MSK_PWR_SRC);
  713. } else {
  714. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  715. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  716. ~APMG_PS_CTRL_MSK_PWR_SRC);
  717. }
  718. return 0;
  719. }
  720. static void iwl_bg_tx_flush(struct work_struct *work)
  721. {
  722. struct iwl_priv *priv =
  723. container_of(work, struct iwl_priv, tx_flush);
  724. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  725. return;
  726. /* do nothing if rf-kill is on */
  727. if (!iwl_is_ready_rf(priv))
  728. return;
  729. if (priv->cfg->ops->lib->txfifo_flush) {
  730. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  731. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  732. }
  733. }
  734. /**
  735. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  736. *
  737. * Setup the RX handlers for each of the reply types sent from the uCode
  738. * to the host.
  739. *
  740. * This function chains into the hardware specific files for them to setup
  741. * any hardware specific handlers as well.
  742. */
  743. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  744. {
  745. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  746. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  747. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  748. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  749. iwl_rx_spectrum_measure_notif;
  750. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  751. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  752. iwl_rx_pm_debug_statistics_notif;
  753. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  754. /*
  755. * The same handler is used for both the REPLY to a discrete
  756. * statistics request from the host as well as for the periodic
  757. * statistics notifications (after received beacons) from the uCode.
  758. */
  759. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  760. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  761. iwl_setup_rx_scan_handlers(priv);
  762. /* status change handler */
  763. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  764. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  765. iwl_rx_missed_beacon_notif;
  766. /* Rx handlers */
  767. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  768. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  769. /* block ack */
  770. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  771. /* Set up hardware specific Rx handlers */
  772. priv->cfg->ops->lib->rx_handler_setup(priv);
  773. }
  774. /**
  775. * iwl_rx_handle - Main entry function for receiving responses from uCode
  776. *
  777. * Uses the priv->rx_handlers callback function array to invoke
  778. * the appropriate handlers, including command responses,
  779. * frame-received notifications, and other notifications.
  780. */
  781. void iwl_rx_handle(struct iwl_priv *priv)
  782. {
  783. struct iwl_rx_mem_buffer *rxb;
  784. struct iwl_rx_packet *pkt;
  785. struct iwl_rx_queue *rxq = &priv->rxq;
  786. u32 r, i;
  787. int reclaim;
  788. unsigned long flags;
  789. u8 fill_rx = 0;
  790. u32 count = 8;
  791. int total_empty;
  792. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  793. * buffer that the driver may process (last buffer filled by ucode). */
  794. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  795. i = rxq->read;
  796. /* Rx interrupt, but nothing sent from uCode */
  797. if (i == r)
  798. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  799. /* calculate total frames need to be restock after handling RX */
  800. total_empty = r - rxq->write_actual;
  801. if (total_empty < 0)
  802. total_empty += RX_QUEUE_SIZE;
  803. if (total_empty > (RX_QUEUE_SIZE / 2))
  804. fill_rx = 1;
  805. while (i != r) {
  806. int len;
  807. rxb = rxq->queue[i];
  808. /* If an RXB doesn't have a Rx queue slot associated with it,
  809. * then a bug has been introduced in the queue refilling
  810. * routines -- catch it here */
  811. BUG_ON(rxb == NULL);
  812. rxq->queue[i] = NULL;
  813. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  814. PAGE_SIZE << priv->hw_params.rx_page_order,
  815. PCI_DMA_FROMDEVICE);
  816. pkt = rxb_addr(rxb);
  817. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  818. len += sizeof(u32); /* account for status word */
  819. trace_iwlwifi_dev_rx(priv, pkt, len);
  820. /* Reclaim a command buffer only if this packet is a response
  821. * to a (driver-originated) command.
  822. * If the packet (e.g. Rx frame) originated from uCode,
  823. * there is no command buffer to reclaim.
  824. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  825. * but apparently a few don't get set; catch them here. */
  826. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  827. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  828. (pkt->hdr.cmd != REPLY_RX) &&
  829. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  830. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  831. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  832. (pkt->hdr.cmd != REPLY_TX);
  833. /* Based on type of command response or notification,
  834. * handle those that need handling via function in
  835. * rx_handlers table. See iwl_setup_rx_handlers() */
  836. if (priv->rx_handlers[pkt->hdr.cmd]) {
  837. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  838. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  839. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  840. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  841. } else {
  842. /* No handling needed */
  843. IWL_DEBUG_RX(priv,
  844. "r %d i %d No handler needed for %s, 0x%02x\n",
  845. r, i, get_cmd_string(pkt->hdr.cmd),
  846. pkt->hdr.cmd);
  847. }
  848. /*
  849. * XXX: After here, we should always check rxb->page
  850. * against NULL before touching it or its virtual
  851. * memory (pkt). Because some rx_handler might have
  852. * already taken or freed the pages.
  853. */
  854. if (reclaim) {
  855. /* Invoke any callbacks, transfer the buffer to caller,
  856. * and fire off the (possibly) blocking iwl_send_cmd()
  857. * as we reclaim the driver command queue */
  858. if (rxb->page)
  859. iwl_tx_cmd_complete(priv, rxb);
  860. else
  861. IWL_WARN(priv, "Claim null rxb?\n");
  862. }
  863. /* Reuse the page if possible. For notification packets and
  864. * SKBs that fail to Rx correctly, add them back into the
  865. * rx_free list for reuse later. */
  866. spin_lock_irqsave(&rxq->lock, flags);
  867. if (rxb->page != NULL) {
  868. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  869. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  870. PCI_DMA_FROMDEVICE);
  871. list_add_tail(&rxb->list, &rxq->rx_free);
  872. rxq->free_count++;
  873. } else
  874. list_add_tail(&rxb->list, &rxq->rx_used);
  875. spin_unlock_irqrestore(&rxq->lock, flags);
  876. i = (i + 1) & RX_QUEUE_MASK;
  877. /* If there are a lot of unused frames,
  878. * restock the Rx queue so ucode wont assert. */
  879. if (fill_rx) {
  880. count++;
  881. if (count >= 8) {
  882. rxq->read = i;
  883. iwlagn_rx_replenish_now(priv);
  884. count = 0;
  885. }
  886. }
  887. }
  888. /* Backtrack one entry */
  889. rxq->read = i;
  890. if (fill_rx)
  891. iwlagn_rx_replenish_now(priv);
  892. else
  893. iwlagn_rx_queue_restock(priv);
  894. }
  895. /* call this function to flush any scheduled tasklet */
  896. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  897. {
  898. /* wait to make sure we flush pending tasklet*/
  899. synchronize_irq(priv->pci_dev->irq);
  900. tasklet_kill(&priv->irq_tasklet);
  901. }
  902. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  903. {
  904. u32 inta, handled = 0;
  905. u32 inta_fh;
  906. unsigned long flags;
  907. u32 i;
  908. #ifdef CONFIG_IWLWIFI_DEBUG
  909. u32 inta_mask;
  910. #endif
  911. spin_lock_irqsave(&priv->lock, flags);
  912. /* Ack/clear/reset pending uCode interrupts.
  913. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  914. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  915. inta = iwl_read32(priv, CSR_INT);
  916. iwl_write32(priv, CSR_INT, inta);
  917. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  918. * Any new interrupts that happen after this, either while we're
  919. * in this tasklet, or later, will show up in next ISR/tasklet. */
  920. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  921. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  922. #ifdef CONFIG_IWLWIFI_DEBUG
  923. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  924. /* just for debug */
  925. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  926. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  927. inta, inta_mask, inta_fh);
  928. }
  929. #endif
  930. spin_unlock_irqrestore(&priv->lock, flags);
  931. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  932. * atomic, make sure that inta covers all the interrupts that
  933. * we've discovered, even if FH interrupt came in just after
  934. * reading CSR_INT. */
  935. if (inta_fh & CSR49_FH_INT_RX_MASK)
  936. inta |= CSR_INT_BIT_FH_RX;
  937. if (inta_fh & CSR49_FH_INT_TX_MASK)
  938. inta |= CSR_INT_BIT_FH_TX;
  939. /* Now service all interrupt bits discovered above. */
  940. if (inta & CSR_INT_BIT_HW_ERR) {
  941. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  942. /* Tell the device to stop sending interrupts */
  943. iwl_disable_interrupts(priv);
  944. priv->isr_stats.hw++;
  945. iwl_irq_handle_error(priv);
  946. handled |= CSR_INT_BIT_HW_ERR;
  947. return;
  948. }
  949. #ifdef CONFIG_IWLWIFI_DEBUG
  950. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  951. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  952. if (inta & CSR_INT_BIT_SCD) {
  953. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  954. "the frame/frames.\n");
  955. priv->isr_stats.sch++;
  956. }
  957. /* Alive notification via Rx interrupt will do the real work */
  958. if (inta & CSR_INT_BIT_ALIVE) {
  959. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  960. priv->isr_stats.alive++;
  961. }
  962. }
  963. #endif
  964. /* Safely ignore these bits for debug checks below */
  965. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  966. /* HW RF KILL switch toggled */
  967. if (inta & CSR_INT_BIT_RF_KILL) {
  968. int hw_rf_kill = 0;
  969. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  970. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  971. hw_rf_kill = 1;
  972. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  973. hw_rf_kill ? "disable radio" : "enable radio");
  974. priv->isr_stats.rfkill++;
  975. /* driver only loads ucode once setting the interface up.
  976. * the driver allows loading the ucode even if the radio
  977. * is killed. Hence update the killswitch state here. The
  978. * rfkill handler will care about restarting if needed.
  979. */
  980. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  981. if (hw_rf_kill)
  982. set_bit(STATUS_RF_KILL_HW, &priv->status);
  983. else
  984. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  985. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  986. }
  987. handled |= CSR_INT_BIT_RF_KILL;
  988. }
  989. /* Chip got too hot and stopped itself */
  990. if (inta & CSR_INT_BIT_CT_KILL) {
  991. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  992. priv->isr_stats.ctkill++;
  993. handled |= CSR_INT_BIT_CT_KILL;
  994. }
  995. /* Error detected by uCode */
  996. if (inta & CSR_INT_BIT_SW_ERR) {
  997. IWL_ERR(priv, "Microcode SW error detected. "
  998. " Restarting 0x%X.\n", inta);
  999. priv->isr_stats.sw++;
  1000. priv->isr_stats.sw_err = inta;
  1001. iwl_irq_handle_error(priv);
  1002. handled |= CSR_INT_BIT_SW_ERR;
  1003. }
  1004. /*
  1005. * uCode wakes up after power-down sleep.
  1006. * Tell device about any new tx or host commands enqueued,
  1007. * and about any Rx buffers made available while asleep.
  1008. */
  1009. if (inta & CSR_INT_BIT_WAKEUP) {
  1010. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1011. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1012. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1013. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1014. priv->isr_stats.wakeup++;
  1015. handled |= CSR_INT_BIT_WAKEUP;
  1016. }
  1017. /* All uCode command responses, including Tx command responses,
  1018. * Rx "responses" (frame-received notification), and other
  1019. * notifications from uCode come through here*/
  1020. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1021. iwl_rx_handle(priv);
  1022. priv->isr_stats.rx++;
  1023. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1024. }
  1025. /* This "Tx" DMA channel is used only for loading uCode */
  1026. if (inta & CSR_INT_BIT_FH_TX) {
  1027. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1028. priv->isr_stats.tx++;
  1029. handled |= CSR_INT_BIT_FH_TX;
  1030. /* Wake up uCode load routine, now that load is complete */
  1031. priv->ucode_write_complete = 1;
  1032. wake_up_interruptible(&priv->wait_command_queue);
  1033. }
  1034. if (inta & ~handled) {
  1035. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1036. priv->isr_stats.unhandled++;
  1037. }
  1038. if (inta & ~(priv->inta_mask)) {
  1039. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1040. inta & ~priv->inta_mask);
  1041. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1042. }
  1043. /* Re-enable all interrupts */
  1044. /* only Re-enable if diabled by irq */
  1045. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1046. iwl_enable_interrupts(priv);
  1047. #ifdef CONFIG_IWLWIFI_DEBUG
  1048. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1049. inta = iwl_read32(priv, CSR_INT);
  1050. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1051. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1052. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1053. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1054. }
  1055. #endif
  1056. }
  1057. /* tasklet for iwlagn interrupt */
  1058. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1059. {
  1060. u32 inta = 0;
  1061. u32 handled = 0;
  1062. unsigned long flags;
  1063. u32 i;
  1064. #ifdef CONFIG_IWLWIFI_DEBUG
  1065. u32 inta_mask;
  1066. #endif
  1067. spin_lock_irqsave(&priv->lock, flags);
  1068. /* Ack/clear/reset pending uCode interrupts.
  1069. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1070. */
  1071. /* There is a hardware bug in the interrupt mask function that some
  1072. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1073. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1074. * ICT interrupt handling mechanism has another bug that might cause
  1075. * these unmasked interrupts fail to be detected. We workaround the
  1076. * hardware bugs here by ACKing all the possible interrupts so that
  1077. * interrupt coalescing can still be achieved.
  1078. */
  1079. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1080. inta = priv->_agn.inta;
  1081. #ifdef CONFIG_IWLWIFI_DEBUG
  1082. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1083. /* just for debug */
  1084. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1085. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1086. inta, inta_mask);
  1087. }
  1088. #endif
  1089. spin_unlock_irqrestore(&priv->lock, flags);
  1090. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1091. priv->_agn.inta = 0;
  1092. /* Now service all interrupt bits discovered above. */
  1093. if (inta & CSR_INT_BIT_HW_ERR) {
  1094. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1095. /* Tell the device to stop sending interrupts */
  1096. iwl_disable_interrupts(priv);
  1097. priv->isr_stats.hw++;
  1098. iwl_irq_handle_error(priv);
  1099. handled |= CSR_INT_BIT_HW_ERR;
  1100. return;
  1101. }
  1102. #ifdef CONFIG_IWLWIFI_DEBUG
  1103. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1104. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1105. if (inta & CSR_INT_BIT_SCD) {
  1106. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1107. "the frame/frames.\n");
  1108. priv->isr_stats.sch++;
  1109. }
  1110. /* Alive notification via Rx interrupt will do the real work */
  1111. if (inta & CSR_INT_BIT_ALIVE) {
  1112. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1113. priv->isr_stats.alive++;
  1114. }
  1115. }
  1116. #endif
  1117. /* Safely ignore these bits for debug checks below */
  1118. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1119. /* HW RF KILL switch toggled */
  1120. if (inta & CSR_INT_BIT_RF_KILL) {
  1121. int hw_rf_kill = 0;
  1122. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1123. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1124. hw_rf_kill = 1;
  1125. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1126. hw_rf_kill ? "disable radio" : "enable radio");
  1127. priv->isr_stats.rfkill++;
  1128. /* driver only loads ucode once setting the interface up.
  1129. * the driver allows loading the ucode even if the radio
  1130. * is killed. Hence update the killswitch state here. The
  1131. * rfkill handler will care about restarting if needed.
  1132. */
  1133. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1134. if (hw_rf_kill)
  1135. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1136. else
  1137. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1138. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1139. }
  1140. handled |= CSR_INT_BIT_RF_KILL;
  1141. }
  1142. /* Chip got too hot and stopped itself */
  1143. if (inta & CSR_INT_BIT_CT_KILL) {
  1144. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1145. priv->isr_stats.ctkill++;
  1146. handled |= CSR_INT_BIT_CT_KILL;
  1147. }
  1148. /* Error detected by uCode */
  1149. if (inta & CSR_INT_BIT_SW_ERR) {
  1150. IWL_ERR(priv, "Microcode SW error detected. "
  1151. " Restarting 0x%X.\n", inta);
  1152. priv->isr_stats.sw++;
  1153. priv->isr_stats.sw_err = inta;
  1154. iwl_irq_handle_error(priv);
  1155. handled |= CSR_INT_BIT_SW_ERR;
  1156. }
  1157. /* uCode wakes up after power-down sleep */
  1158. if (inta & CSR_INT_BIT_WAKEUP) {
  1159. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1160. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1161. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1162. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1163. priv->isr_stats.wakeup++;
  1164. handled |= CSR_INT_BIT_WAKEUP;
  1165. }
  1166. /* All uCode command responses, including Tx command responses,
  1167. * Rx "responses" (frame-received notification), and other
  1168. * notifications from uCode come through here*/
  1169. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1170. CSR_INT_BIT_RX_PERIODIC)) {
  1171. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1172. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1173. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1174. iwl_write32(priv, CSR_FH_INT_STATUS,
  1175. CSR49_FH_INT_RX_MASK);
  1176. }
  1177. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1178. handled |= CSR_INT_BIT_RX_PERIODIC;
  1179. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1180. }
  1181. /* Sending RX interrupt require many steps to be done in the
  1182. * the device:
  1183. * 1- write interrupt to current index in ICT table.
  1184. * 2- dma RX frame.
  1185. * 3- update RX shared data to indicate last write index.
  1186. * 4- send interrupt.
  1187. * This could lead to RX race, driver could receive RX interrupt
  1188. * but the shared data changes does not reflect this;
  1189. * periodic interrupt will detect any dangling Rx activity.
  1190. */
  1191. /* Disable periodic interrupt; we use it as just a one-shot. */
  1192. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1193. CSR_INT_PERIODIC_DIS);
  1194. iwl_rx_handle(priv);
  1195. /*
  1196. * Enable periodic interrupt in 8 msec only if we received
  1197. * real RX interrupt (instead of just periodic int), to catch
  1198. * any dangling Rx interrupt. If it was just the periodic
  1199. * interrupt, there was no dangling Rx activity, and no need
  1200. * to extend the periodic interrupt; one-shot is enough.
  1201. */
  1202. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1203. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1204. CSR_INT_PERIODIC_ENA);
  1205. priv->isr_stats.rx++;
  1206. }
  1207. /* This "Tx" DMA channel is used only for loading uCode */
  1208. if (inta & CSR_INT_BIT_FH_TX) {
  1209. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1210. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1211. priv->isr_stats.tx++;
  1212. handled |= CSR_INT_BIT_FH_TX;
  1213. /* Wake up uCode load routine, now that load is complete */
  1214. priv->ucode_write_complete = 1;
  1215. wake_up_interruptible(&priv->wait_command_queue);
  1216. }
  1217. if (inta & ~handled) {
  1218. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1219. priv->isr_stats.unhandled++;
  1220. }
  1221. if (inta & ~(priv->inta_mask)) {
  1222. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1223. inta & ~priv->inta_mask);
  1224. }
  1225. /* Re-enable all interrupts */
  1226. /* only Re-enable if diabled by irq */
  1227. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1228. iwl_enable_interrupts(priv);
  1229. }
  1230. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1231. #define ACK_CNT_RATIO (50)
  1232. #define BA_TIMEOUT_CNT (5)
  1233. #define BA_TIMEOUT_MAX (16)
  1234. /**
  1235. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1236. *
  1237. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1238. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1239. * operation state.
  1240. */
  1241. bool iwl_good_ack_health(struct iwl_priv *priv,
  1242. struct iwl_rx_packet *pkt)
  1243. {
  1244. bool rc = true;
  1245. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1246. int ba_timeout_delta;
  1247. actual_ack_cnt_delta =
  1248. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1249. le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
  1250. expected_ack_cnt_delta =
  1251. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1252. le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
  1253. ba_timeout_delta =
  1254. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1255. le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
  1256. if ((priv->_agn.agg_tids_count > 0) &&
  1257. (expected_ack_cnt_delta > 0) &&
  1258. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1259. < ACK_CNT_RATIO) &&
  1260. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1261. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1262. " expected_ack_cnt = %d\n",
  1263. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1264. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1265. /*
  1266. * This is ifdef'ed on DEBUGFS because otherwise the
  1267. * statistics aren't available. If DEBUGFS is set but
  1268. * DEBUG is not, these will just compile out.
  1269. */
  1270. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1271. priv->_agn.delta_statistics.tx.rx_detected_cnt);
  1272. IWL_DEBUG_RADIO(priv,
  1273. "ack_or_ba_timeout_collision delta = %d\n",
  1274. priv->_agn.delta_statistics.tx.
  1275. ack_or_ba_timeout_collision);
  1276. #endif
  1277. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1278. ba_timeout_delta);
  1279. if (!actual_ack_cnt_delta &&
  1280. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1281. rc = false;
  1282. }
  1283. return rc;
  1284. }
  1285. /*****************************************************************************
  1286. *
  1287. * sysfs attributes
  1288. *
  1289. *****************************************************************************/
  1290. #ifdef CONFIG_IWLWIFI_DEBUG
  1291. /*
  1292. * The following adds a new attribute to the sysfs representation
  1293. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1294. * used for controlling the debug level.
  1295. *
  1296. * See the level definitions in iwl for details.
  1297. *
  1298. * The debug_level being managed using sysfs below is a per device debug
  1299. * level that is used instead of the global debug level if it (the per
  1300. * device debug level) is set.
  1301. */
  1302. static ssize_t show_debug_level(struct device *d,
  1303. struct device_attribute *attr, char *buf)
  1304. {
  1305. struct iwl_priv *priv = dev_get_drvdata(d);
  1306. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  1307. }
  1308. static ssize_t store_debug_level(struct device *d,
  1309. struct device_attribute *attr,
  1310. const char *buf, size_t count)
  1311. {
  1312. struct iwl_priv *priv = dev_get_drvdata(d);
  1313. unsigned long val;
  1314. int ret;
  1315. ret = strict_strtoul(buf, 0, &val);
  1316. if (ret)
  1317. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1318. else {
  1319. priv->debug_level = val;
  1320. if (iwl_alloc_traffic_mem(priv))
  1321. IWL_ERR(priv,
  1322. "Not enough memory to generate traffic log\n");
  1323. }
  1324. return strnlen(buf, count);
  1325. }
  1326. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1327. show_debug_level, store_debug_level);
  1328. #endif /* CONFIG_IWLWIFI_DEBUG */
  1329. static ssize_t show_temperature(struct device *d,
  1330. struct device_attribute *attr, char *buf)
  1331. {
  1332. struct iwl_priv *priv = dev_get_drvdata(d);
  1333. if (!iwl_is_alive(priv))
  1334. return -EAGAIN;
  1335. return sprintf(buf, "%d\n", priv->temperature);
  1336. }
  1337. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1338. static ssize_t show_tx_power(struct device *d,
  1339. struct device_attribute *attr, char *buf)
  1340. {
  1341. struct iwl_priv *priv = dev_get_drvdata(d);
  1342. if (!iwl_is_ready_rf(priv))
  1343. return sprintf(buf, "off\n");
  1344. else
  1345. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1346. }
  1347. static ssize_t store_tx_power(struct device *d,
  1348. struct device_attribute *attr,
  1349. const char *buf, size_t count)
  1350. {
  1351. struct iwl_priv *priv = dev_get_drvdata(d);
  1352. unsigned long val;
  1353. int ret;
  1354. ret = strict_strtoul(buf, 10, &val);
  1355. if (ret)
  1356. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1357. else {
  1358. ret = iwl_set_tx_power(priv, val, false);
  1359. if (ret)
  1360. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  1361. ret);
  1362. else
  1363. ret = count;
  1364. }
  1365. return ret;
  1366. }
  1367. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1368. static struct attribute *iwl_sysfs_entries[] = {
  1369. &dev_attr_temperature.attr,
  1370. &dev_attr_tx_power.attr,
  1371. #ifdef CONFIG_IWLWIFI_DEBUG
  1372. &dev_attr_debug_level.attr,
  1373. #endif
  1374. NULL
  1375. };
  1376. static struct attribute_group iwl_attribute_group = {
  1377. .name = NULL, /* put in device directory */
  1378. .attrs = iwl_sysfs_entries,
  1379. };
  1380. /******************************************************************************
  1381. *
  1382. * uCode download functions
  1383. *
  1384. ******************************************************************************/
  1385. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1386. {
  1387. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1388. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1389. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1390. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1391. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1392. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1393. }
  1394. static void iwl_nic_start(struct iwl_priv *priv)
  1395. {
  1396. /* Remove all resets to allow NIC to operate */
  1397. iwl_write32(priv, CSR_RESET, 0);
  1398. }
  1399. struct iwlagn_ucode_capabilities {
  1400. u32 max_probe_length;
  1401. u32 standard_phy_calibration_size;
  1402. };
  1403. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1404. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1405. struct iwlagn_ucode_capabilities *capa);
  1406. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1407. {
  1408. const char *name_pre = priv->cfg->fw_name_pre;
  1409. if (first)
  1410. priv->fw_index = priv->cfg->ucode_api_max;
  1411. else
  1412. priv->fw_index--;
  1413. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1414. IWL_ERR(priv, "no suitable firmware found!\n");
  1415. return -ENOENT;
  1416. }
  1417. sprintf(priv->firmware_name, "%s%d%s",
  1418. name_pre, priv->fw_index, ".ucode");
  1419. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1420. priv->firmware_name);
  1421. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1422. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1423. iwl_ucode_callback);
  1424. }
  1425. struct iwlagn_firmware_pieces {
  1426. const void *inst, *data, *init, *init_data, *boot;
  1427. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1428. u32 build;
  1429. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1430. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1431. };
  1432. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1433. const struct firmware *ucode_raw,
  1434. struct iwlagn_firmware_pieces *pieces)
  1435. {
  1436. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1437. u32 api_ver, hdr_size;
  1438. const u8 *src;
  1439. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1440. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1441. switch (api_ver) {
  1442. default:
  1443. /*
  1444. * 4965 doesn't revision the firmware file format
  1445. * along with the API version, it always uses v1
  1446. * file format.
  1447. */
  1448. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1449. CSR_HW_REV_TYPE_4965) {
  1450. hdr_size = 28;
  1451. if (ucode_raw->size < hdr_size) {
  1452. IWL_ERR(priv, "File size too small!\n");
  1453. return -EINVAL;
  1454. }
  1455. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1456. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1457. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1458. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1459. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1460. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1461. src = ucode->u.v2.data;
  1462. break;
  1463. }
  1464. /* fall through for 4965 */
  1465. case 0:
  1466. case 1:
  1467. case 2:
  1468. hdr_size = 24;
  1469. if (ucode_raw->size < hdr_size) {
  1470. IWL_ERR(priv, "File size too small!\n");
  1471. return -EINVAL;
  1472. }
  1473. pieces->build = 0;
  1474. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1475. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1476. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1477. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1478. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1479. src = ucode->u.v1.data;
  1480. break;
  1481. }
  1482. /* Verify size of file vs. image size info in file's header */
  1483. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1484. pieces->data_size + pieces->init_size +
  1485. pieces->init_data_size + pieces->boot_size) {
  1486. IWL_ERR(priv,
  1487. "uCode file size %d does not match expected size\n",
  1488. (int)ucode_raw->size);
  1489. return -EINVAL;
  1490. }
  1491. pieces->inst = src;
  1492. src += pieces->inst_size;
  1493. pieces->data = src;
  1494. src += pieces->data_size;
  1495. pieces->init = src;
  1496. src += pieces->init_size;
  1497. pieces->init_data = src;
  1498. src += pieces->init_data_size;
  1499. pieces->boot = src;
  1500. src += pieces->boot_size;
  1501. return 0;
  1502. }
  1503. static int iwlagn_wanted_ucode_alternative = 1;
  1504. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1505. const struct firmware *ucode_raw,
  1506. struct iwlagn_firmware_pieces *pieces,
  1507. struct iwlagn_ucode_capabilities *capa)
  1508. {
  1509. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1510. struct iwl_ucode_tlv *tlv;
  1511. size_t len = ucode_raw->size;
  1512. const u8 *data;
  1513. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1514. u64 alternatives;
  1515. u32 tlv_len;
  1516. enum iwl_ucode_tlv_type tlv_type;
  1517. const u8 *tlv_data;
  1518. if (len < sizeof(*ucode)) {
  1519. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  1520. return -EINVAL;
  1521. }
  1522. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  1523. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  1524. le32_to_cpu(ucode->magic));
  1525. return -EINVAL;
  1526. }
  1527. /*
  1528. * Check which alternatives are present, and "downgrade"
  1529. * when the chosen alternative is not present, warning
  1530. * the user when that happens. Some files may not have
  1531. * any alternatives, so don't warn in that case.
  1532. */
  1533. alternatives = le64_to_cpu(ucode->alternatives);
  1534. tmp = wanted_alternative;
  1535. if (wanted_alternative > 63)
  1536. wanted_alternative = 63;
  1537. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1538. wanted_alternative--;
  1539. if (wanted_alternative && wanted_alternative != tmp)
  1540. IWL_WARN(priv,
  1541. "uCode alternative %d not available, choosing %d\n",
  1542. tmp, wanted_alternative);
  1543. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1544. pieces->build = le32_to_cpu(ucode->build);
  1545. data = ucode->data;
  1546. len -= sizeof(*ucode);
  1547. while (len >= sizeof(*tlv)) {
  1548. u16 tlv_alt;
  1549. len -= sizeof(*tlv);
  1550. tlv = (void *)data;
  1551. tlv_len = le32_to_cpu(tlv->length);
  1552. tlv_type = le16_to_cpu(tlv->type);
  1553. tlv_alt = le16_to_cpu(tlv->alternative);
  1554. tlv_data = tlv->data;
  1555. if (len < tlv_len) {
  1556. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  1557. len, tlv_len);
  1558. return -EINVAL;
  1559. }
  1560. len -= ALIGN(tlv_len, 4);
  1561. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1562. /*
  1563. * Alternative 0 is always valid.
  1564. *
  1565. * Skip alternative TLVs that are not selected.
  1566. */
  1567. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1568. continue;
  1569. switch (tlv_type) {
  1570. case IWL_UCODE_TLV_INST:
  1571. pieces->inst = tlv_data;
  1572. pieces->inst_size = tlv_len;
  1573. break;
  1574. case IWL_UCODE_TLV_DATA:
  1575. pieces->data = tlv_data;
  1576. pieces->data_size = tlv_len;
  1577. break;
  1578. case IWL_UCODE_TLV_INIT:
  1579. pieces->init = tlv_data;
  1580. pieces->init_size = tlv_len;
  1581. break;
  1582. case IWL_UCODE_TLV_INIT_DATA:
  1583. pieces->init_data = tlv_data;
  1584. pieces->init_data_size = tlv_len;
  1585. break;
  1586. case IWL_UCODE_TLV_BOOT:
  1587. pieces->boot = tlv_data;
  1588. pieces->boot_size = tlv_len;
  1589. break;
  1590. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1591. if (tlv_len != sizeof(u32))
  1592. goto invalid_tlv_len;
  1593. capa->max_probe_length =
  1594. le32_to_cpup((__le32 *)tlv_data);
  1595. break;
  1596. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1597. if (tlv_len != sizeof(u32))
  1598. goto invalid_tlv_len;
  1599. pieces->init_evtlog_ptr =
  1600. le32_to_cpup((__le32 *)tlv_data);
  1601. break;
  1602. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1603. if (tlv_len != sizeof(u32))
  1604. goto invalid_tlv_len;
  1605. pieces->init_evtlog_size =
  1606. le32_to_cpup((__le32 *)tlv_data);
  1607. break;
  1608. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1609. if (tlv_len != sizeof(u32))
  1610. goto invalid_tlv_len;
  1611. pieces->init_errlog_ptr =
  1612. le32_to_cpup((__le32 *)tlv_data);
  1613. break;
  1614. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1615. if (tlv_len != sizeof(u32))
  1616. goto invalid_tlv_len;
  1617. pieces->inst_evtlog_ptr =
  1618. le32_to_cpup((__le32 *)tlv_data);
  1619. break;
  1620. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1621. if (tlv_len != sizeof(u32))
  1622. goto invalid_tlv_len;
  1623. pieces->inst_evtlog_size =
  1624. le32_to_cpup((__le32 *)tlv_data);
  1625. break;
  1626. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1627. if (tlv_len != sizeof(u32))
  1628. goto invalid_tlv_len;
  1629. pieces->inst_errlog_ptr =
  1630. le32_to_cpup((__le32 *)tlv_data);
  1631. break;
  1632. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1633. if (tlv_len)
  1634. goto invalid_tlv_len;
  1635. priv->enhance_sensitivity_table = true;
  1636. break;
  1637. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1638. if (tlv_len != sizeof(u32))
  1639. goto invalid_tlv_len;
  1640. capa->standard_phy_calibration_size =
  1641. le32_to_cpup((__le32 *)tlv_data);
  1642. break;
  1643. default:
  1644. IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
  1645. break;
  1646. }
  1647. }
  1648. if (len) {
  1649. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1650. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1651. return -EINVAL;
  1652. }
  1653. return 0;
  1654. invalid_tlv_len:
  1655. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1656. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1657. return -EINVAL;
  1658. }
  1659. /**
  1660. * iwl_ucode_callback - callback when firmware was loaded
  1661. *
  1662. * If loaded successfully, copies the firmware into buffers
  1663. * for the card to fetch (via DMA).
  1664. */
  1665. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1666. {
  1667. struct iwl_priv *priv = context;
  1668. struct iwl_ucode_header *ucode;
  1669. int err;
  1670. struct iwlagn_firmware_pieces pieces;
  1671. const unsigned int api_max = priv->cfg->ucode_api_max;
  1672. const unsigned int api_min = priv->cfg->ucode_api_min;
  1673. u32 api_ver;
  1674. char buildstr[25];
  1675. u32 build;
  1676. struct iwlagn_ucode_capabilities ucode_capa = {
  1677. .max_probe_length = 200,
  1678. .standard_phy_calibration_size =
  1679. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1680. };
  1681. memset(&pieces, 0, sizeof(pieces));
  1682. if (!ucode_raw) {
  1683. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1684. priv->firmware_name);
  1685. goto try_again;
  1686. }
  1687. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1688. priv->firmware_name, ucode_raw->size);
  1689. /* Make sure that we got at least the API version number */
  1690. if (ucode_raw->size < 4) {
  1691. IWL_ERR(priv, "File size way too small!\n");
  1692. goto try_again;
  1693. }
  1694. /* Data from ucode file: header followed by uCode images */
  1695. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1696. if (ucode->ver)
  1697. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1698. else
  1699. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1700. &ucode_capa);
  1701. if (err)
  1702. goto try_again;
  1703. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1704. build = pieces.build;
  1705. /*
  1706. * api_ver should match the api version forming part of the
  1707. * firmware filename ... but we don't check for that and only rely
  1708. * on the API version read from firmware header from here on forward
  1709. */
  1710. if (api_ver < api_min || api_ver > api_max) {
  1711. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1712. "Driver supports v%u, firmware is v%u.\n",
  1713. api_max, api_ver);
  1714. goto try_again;
  1715. }
  1716. if (api_ver != api_max)
  1717. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1718. "got v%u. New firmware can be obtained "
  1719. "from http://www.intellinuxwireless.org.\n",
  1720. api_max, api_ver);
  1721. if (build)
  1722. sprintf(buildstr, " build %u", build);
  1723. else
  1724. buildstr[0] = '\0';
  1725. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1726. IWL_UCODE_MAJOR(priv->ucode_ver),
  1727. IWL_UCODE_MINOR(priv->ucode_ver),
  1728. IWL_UCODE_API(priv->ucode_ver),
  1729. IWL_UCODE_SERIAL(priv->ucode_ver),
  1730. buildstr);
  1731. snprintf(priv->hw->wiphy->fw_version,
  1732. sizeof(priv->hw->wiphy->fw_version),
  1733. "%u.%u.%u.%u%s",
  1734. IWL_UCODE_MAJOR(priv->ucode_ver),
  1735. IWL_UCODE_MINOR(priv->ucode_ver),
  1736. IWL_UCODE_API(priv->ucode_ver),
  1737. IWL_UCODE_SERIAL(priv->ucode_ver),
  1738. buildstr);
  1739. /*
  1740. * For any of the failures below (before allocating pci memory)
  1741. * we will try to load a version with a smaller API -- maybe the
  1742. * user just got a corrupted version of the latest API.
  1743. */
  1744. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1745. priv->ucode_ver);
  1746. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1747. pieces.inst_size);
  1748. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1749. pieces.data_size);
  1750. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1751. pieces.init_size);
  1752. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1753. pieces.init_data_size);
  1754. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1755. pieces.boot_size);
  1756. /* Verify that uCode images will fit in card's SRAM */
  1757. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1758. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1759. pieces.inst_size);
  1760. goto try_again;
  1761. }
  1762. if (pieces.data_size > priv->hw_params.max_data_size) {
  1763. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1764. pieces.data_size);
  1765. goto try_again;
  1766. }
  1767. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1768. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1769. pieces.init_size);
  1770. goto try_again;
  1771. }
  1772. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1773. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1774. pieces.init_data_size);
  1775. goto try_again;
  1776. }
  1777. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1778. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1779. pieces.boot_size);
  1780. goto try_again;
  1781. }
  1782. /* Allocate ucode buffers for card's bus-master loading ... */
  1783. /* Runtime instructions and 2 copies of data:
  1784. * 1) unmodified from disk
  1785. * 2) backup cache for save/restore during power-downs */
  1786. priv->ucode_code.len = pieces.inst_size;
  1787. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1788. priv->ucode_data.len = pieces.data_size;
  1789. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1790. priv->ucode_data_backup.len = pieces.data_size;
  1791. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1792. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1793. !priv->ucode_data_backup.v_addr)
  1794. goto err_pci_alloc;
  1795. /* Initialization instructions and data */
  1796. if (pieces.init_size && pieces.init_data_size) {
  1797. priv->ucode_init.len = pieces.init_size;
  1798. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1799. priv->ucode_init_data.len = pieces.init_data_size;
  1800. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1801. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1802. goto err_pci_alloc;
  1803. }
  1804. /* Bootstrap (instructions only, no data) */
  1805. if (pieces.boot_size) {
  1806. priv->ucode_boot.len = pieces.boot_size;
  1807. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1808. if (!priv->ucode_boot.v_addr)
  1809. goto err_pci_alloc;
  1810. }
  1811. /* Now that we can no longer fail, copy information */
  1812. /*
  1813. * The (size - 16) / 12 formula is based on the information recorded
  1814. * for each event, which is of mode 1 (including timestamp) for all
  1815. * new microcodes that include this information.
  1816. */
  1817. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1818. if (pieces.init_evtlog_size)
  1819. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1820. else
  1821. priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
  1822. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1823. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1824. if (pieces.inst_evtlog_size)
  1825. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1826. else
  1827. priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
  1828. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1829. /* Copy images into buffers for card's bus-master reads ... */
  1830. /* Runtime instructions (first block of data in file) */
  1831. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1832. pieces.inst_size);
  1833. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1834. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1835. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1836. /*
  1837. * Runtime data
  1838. * NOTE: Copy into backup buffer will be done in iwl_up()
  1839. */
  1840. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1841. pieces.data_size);
  1842. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1843. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1844. /* Initialization instructions */
  1845. if (pieces.init_size) {
  1846. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1847. pieces.init_size);
  1848. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1849. }
  1850. /* Initialization data */
  1851. if (pieces.init_data_size) {
  1852. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1853. pieces.init_data_size);
  1854. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1855. pieces.init_data_size);
  1856. }
  1857. /* Bootstrap instructions */
  1858. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1859. pieces.boot_size);
  1860. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1861. /*
  1862. * figure out the offset of chain noise reset and gain commands
  1863. * base on the size of standard phy calibration commands table size
  1864. */
  1865. if (ucode_capa.standard_phy_calibration_size >
  1866. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1867. ucode_capa.standard_phy_calibration_size =
  1868. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1869. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1870. ucode_capa.standard_phy_calibration_size;
  1871. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1872. ucode_capa.standard_phy_calibration_size + 1;
  1873. /**************************************************
  1874. * This is still part of probe() in a sense...
  1875. *
  1876. * 9. Setup and register with mac80211 and debugfs
  1877. **************************************************/
  1878. err = iwl_mac_setup_register(priv, &ucode_capa);
  1879. if (err)
  1880. goto out_unbind;
  1881. err = iwl_dbgfs_register(priv, DRV_NAME);
  1882. if (err)
  1883. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1884. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1885. &iwl_attribute_group);
  1886. if (err) {
  1887. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1888. goto out_unbind;
  1889. }
  1890. /* We have our copies now, allow OS release its copies */
  1891. release_firmware(ucode_raw);
  1892. complete(&priv->_agn.firmware_loading_complete);
  1893. return;
  1894. try_again:
  1895. /* try next, if any */
  1896. if (iwl_request_firmware(priv, false))
  1897. goto out_unbind;
  1898. release_firmware(ucode_raw);
  1899. return;
  1900. err_pci_alloc:
  1901. IWL_ERR(priv, "failed to allocate pci memory\n");
  1902. iwl_dealloc_ucode_pci(priv);
  1903. out_unbind:
  1904. complete(&priv->_agn.firmware_loading_complete);
  1905. device_release_driver(&priv->pci_dev->dev);
  1906. release_firmware(ucode_raw);
  1907. }
  1908. static const char *desc_lookup_text[] = {
  1909. "OK",
  1910. "FAIL",
  1911. "BAD_PARAM",
  1912. "BAD_CHECKSUM",
  1913. "NMI_INTERRUPT_WDG",
  1914. "SYSASSERT",
  1915. "FATAL_ERROR",
  1916. "BAD_COMMAND",
  1917. "HW_ERROR_TUNE_LOCK",
  1918. "HW_ERROR_TEMPERATURE",
  1919. "ILLEGAL_CHAN_FREQ",
  1920. "VCC_NOT_STABLE",
  1921. "FH_ERROR",
  1922. "NMI_INTERRUPT_HOST",
  1923. "NMI_INTERRUPT_ACTION_PT",
  1924. "NMI_INTERRUPT_UNKNOWN",
  1925. "UCODE_VERSION_MISMATCH",
  1926. "HW_ERROR_ABS_LOCK",
  1927. "HW_ERROR_CAL_LOCK_FAIL",
  1928. "NMI_INTERRUPT_INST_ACTION_PT",
  1929. "NMI_INTERRUPT_DATA_ACTION_PT",
  1930. "NMI_TRM_HW_ER",
  1931. "NMI_INTERRUPT_TRM",
  1932. "NMI_INTERRUPT_BREAK_POINT"
  1933. "DEBUG_0",
  1934. "DEBUG_1",
  1935. "DEBUG_2",
  1936. "DEBUG_3",
  1937. };
  1938. static struct { char *name; u8 num; } advanced_lookup[] = {
  1939. { "NMI_INTERRUPT_WDG", 0x34 },
  1940. { "SYSASSERT", 0x35 },
  1941. { "UCODE_VERSION_MISMATCH", 0x37 },
  1942. { "BAD_COMMAND", 0x38 },
  1943. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1944. { "FATAL_ERROR", 0x3D },
  1945. { "NMI_TRM_HW_ERR", 0x46 },
  1946. { "NMI_INTERRUPT_TRM", 0x4C },
  1947. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1948. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1949. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1950. { "NMI_INTERRUPT_HOST", 0x66 },
  1951. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1952. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1953. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1954. { "ADVANCED_SYSASSERT", 0 },
  1955. };
  1956. static const char *desc_lookup(u32 num)
  1957. {
  1958. int i;
  1959. int max = ARRAY_SIZE(desc_lookup_text);
  1960. if (num < max)
  1961. return desc_lookup_text[num];
  1962. max = ARRAY_SIZE(advanced_lookup) - 1;
  1963. for (i = 0; i < max; i++) {
  1964. if (advanced_lookup[i].num == num)
  1965. break;;
  1966. }
  1967. return advanced_lookup[i].name;
  1968. }
  1969. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1970. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1971. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1972. {
  1973. u32 data2, line;
  1974. u32 desc, time, count, base, data1;
  1975. u32 blink1, blink2, ilink1, ilink2;
  1976. u32 pc, hcmd;
  1977. if (priv->ucode_type == UCODE_INIT) {
  1978. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1979. if (!base)
  1980. base = priv->_agn.init_errlog_ptr;
  1981. } else {
  1982. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1983. if (!base)
  1984. base = priv->_agn.inst_errlog_ptr;
  1985. }
  1986. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1987. IWL_ERR(priv,
  1988. "Not valid error log pointer 0x%08X for %s uCode\n",
  1989. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1990. return;
  1991. }
  1992. count = iwl_read_targ_mem(priv, base);
  1993. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1994. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1995. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1996. priv->status, count);
  1997. }
  1998. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1999. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  2000. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  2001. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  2002. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  2003. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  2004. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  2005. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  2006. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  2007. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  2008. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  2009. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  2010. blink1, blink2, ilink1, ilink2);
  2011. IWL_ERR(priv, "Desc Time "
  2012. "data1 data2 line\n");
  2013. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  2014. desc_lookup(desc), desc, time, data1, data2, line);
  2015. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  2016. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  2017. pc, blink1, blink2, ilink1, ilink2, hcmd);
  2018. }
  2019. #define EVENT_START_OFFSET (4 * sizeof(u32))
  2020. /**
  2021. * iwl_print_event_log - Dump error event log to syslog
  2022. *
  2023. */
  2024. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  2025. u32 num_events, u32 mode,
  2026. int pos, char **buf, size_t bufsz)
  2027. {
  2028. u32 i;
  2029. u32 base; /* SRAM byte address of event log header */
  2030. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  2031. u32 ptr; /* SRAM byte address of log data */
  2032. u32 ev, time, data; /* event log data */
  2033. unsigned long reg_flags;
  2034. if (num_events == 0)
  2035. return pos;
  2036. if (priv->ucode_type == UCODE_INIT) {
  2037. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2038. if (!base)
  2039. base = priv->_agn.init_evtlog_ptr;
  2040. } else {
  2041. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2042. if (!base)
  2043. base = priv->_agn.inst_evtlog_ptr;
  2044. }
  2045. if (mode == 0)
  2046. event_size = 2 * sizeof(u32);
  2047. else
  2048. event_size = 3 * sizeof(u32);
  2049. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  2050. /* Make sure device is powered up for SRAM reads */
  2051. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  2052. iwl_grab_nic_access(priv);
  2053. /* Set starting address; reads will auto-increment */
  2054. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  2055. rmb();
  2056. /* "time" is actually "data" for mode 0 (no timestamp).
  2057. * place event id # at far right for easier visual parsing. */
  2058. for (i = 0; i < num_events; i++) {
  2059. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2060. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2061. if (mode == 0) {
  2062. /* data, ev */
  2063. if (bufsz) {
  2064. pos += scnprintf(*buf + pos, bufsz - pos,
  2065. "EVT_LOG:0x%08x:%04u\n",
  2066. time, ev);
  2067. } else {
  2068. trace_iwlwifi_dev_ucode_event(priv, 0,
  2069. time, ev);
  2070. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  2071. time, ev);
  2072. }
  2073. } else {
  2074. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2075. if (bufsz) {
  2076. pos += scnprintf(*buf + pos, bufsz - pos,
  2077. "EVT_LOGT:%010u:0x%08x:%04u\n",
  2078. time, data, ev);
  2079. } else {
  2080. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  2081. time, data, ev);
  2082. trace_iwlwifi_dev_ucode_event(priv, time,
  2083. data, ev);
  2084. }
  2085. }
  2086. }
  2087. /* Allow device to power down */
  2088. iwl_release_nic_access(priv);
  2089. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  2090. return pos;
  2091. }
  2092. /**
  2093. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  2094. */
  2095. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  2096. u32 num_wraps, u32 next_entry,
  2097. u32 size, u32 mode,
  2098. int pos, char **buf, size_t bufsz)
  2099. {
  2100. /*
  2101. * display the newest DEFAULT_LOG_ENTRIES entries
  2102. * i.e the entries just before the next ont that uCode would fill.
  2103. */
  2104. if (num_wraps) {
  2105. if (next_entry < size) {
  2106. pos = iwl_print_event_log(priv,
  2107. capacity - (size - next_entry),
  2108. size - next_entry, mode,
  2109. pos, buf, bufsz);
  2110. pos = iwl_print_event_log(priv, 0,
  2111. next_entry, mode,
  2112. pos, buf, bufsz);
  2113. } else
  2114. pos = iwl_print_event_log(priv, next_entry - size,
  2115. size, mode, pos, buf, bufsz);
  2116. } else {
  2117. if (next_entry < size) {
  2118. pos = iwl_print_event_log(priv, 0, next_entry,
  2119. mode, pos, buf, bufsz);
  2120. } else {
  2121. pos = iwl_print_event_log(priv, next_entry - size,
  2122. size, mode, pos, buf, bufsz);
  2123. }
  2124. }
  2125. return pos;
  2126. }
  2127. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  2128. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  2129. char **buf, bool display)
  2130. {
  2131. u32 base; /* SRAM byte address of event log header */
  2132. u32 capacity; /* event log capacity in # entries */
  2133. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  2134. u32 num_wraps; /* # times uCode wrapped to top of log */
  2135. u32 next_entry; /* index of next entry to be written by uCode */
  2136. u32 size; /* # entries that we'll print */
  2137. u32 logsize;
  2138. int pos = 0;
  2139. size_t bufsz = 0;
  2140. if (priv->ucode_type == UCODE_INIT) {
  2141. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2142. logsize = priv->_agn.init_evtlog_size;
  2143. if (!base)
  2144. base = priv->_agn.init_evtlog_ptr;
  2145. } else {
  2146. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2147. logsize = priv->_agn.inst_evtlog_size;
  2148. if (!base)
  2149. base = priv->_agn.inst_evtlog_ptr;
  2150. }
  2151. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  2152. IWL_ERR(priv,
  2153. "Invalid event log pointer 0x%08X for %s uCode\n",
  2154. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  2155. return -EINVAL;
  2156. }
  2157. /* event log header */
  2158. capacity = iwl_read_targ_mem(priv, base);
  2159. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  2160. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  2161. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  2162. if (capacity > logsize) {
  2163. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  2164. capacity, logsize);
  2165. capacity = logsize;
  2166. }
  2167. if (next_entry > logsize) {
  2168. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  2169. next_entry, logsize);
  2170. next_entry = logsize;
  2171. }
  2172. size = num_wraps ? capacity : next_entry;
  2173. /* bail out if nothing in log */
  2174. if (size == 0) {
  2175. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  2176. return pos;
  2177. }
  2178. #ifdef CONFIG_IWLWIFI_DEBUG
  2179. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  2180. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2181. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2182. #else
  2183. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2184. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2185. #endif
  2186. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  2187. size);
  2188. #ifdef CONFIG_IWLWIFI_DEBUG
  2189. if (display) {
  2190. if (full_log)
  2191. bufsz = capacity * 48;
  2192. else
  2193. bufsz = size * 48;
  2194. *buf = kmalloc(bufsz, GFP_KERNEL);
  2195. if (!*buf)
  2196. return -ENOMEM;
  2197. }
  2198. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  2199. /*
  2200. * if uCode has wrapped back to top of log,
  2201. * start at the oldest entry,
  2202. * i.e the next one that uCode would fill.
  2203. */
  2204. if (num_wraps)
  2205. pos = iwl_print_event_log(priv, next_entry,
  2206. capacity - next_entry, mode,
  2207. pos, buf, bufsz);
  2208. /* (then/else) start at top of log */
  2209. pos = iwl_print_event_log(priv, 0,
  2210. next_entry, mode, pos, buf, bufsz);
  2211. } else
  2212. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2213. next_entry, size, mode,
  2214. pos, buf, bufsz);
  2215. #else
  2216. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2217. next_entry, size, mode,
  2218. pos, buf, bufsz);
  2219. #endif
  2220. return pos;
  2221. }
  2222. /**
  2223. * iwl_alive_start - called after REPLY_ALIVE notification received
  2224. * from protocol/runtime uCode (initialization uCode's
  2225. * Alive gets handled by iwl_init_alive_start()).
  2226. */
  2227. static void iwl_alive_start(struct iwl_priv *priv)
  2228. {
  2229. int ret = 0;
  2230. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2231. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2232. /* We had an error bringing up the hardware, so take it
  2233. * all the way back down so we can try again */
  2234. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2235. goto restart;
  2236. }
  2237. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2238. * This is a paranoid check, because we would not have gotten the
  2239. * "runtime" alive if code weren't properly loaded. */
  2240. if (iwl_verify_ucode(priv)) {
  2241. /* Runtime instruction load was bad;
  2242. * take it all the way back down so we can try again */
  2243. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2244. goto restart;
  2245. }
  2246. ret = priv->cfg->ops->lib->alive_notify(priv);
  2247. if (ret) {
  2248. IWL_WARN(priv,
  2249. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  2250. goto restart;
  2251. }
  2252. /* After the ALIVE response, we can send host commands to the uCode */
  2253. set_bit(STATUS_ALIVE, &priv->status);
  2254. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2255. /* Enable timer to monitor the driver queues */
  2256. mod_timer(&priv->monitor_recover,
  2257. jiffies +
  2258. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2259. }
  2260. if (iwl_is_rfkill(priv))
  2261. return;
  2262. ieee80211_wake_queues(priv->hw);
  2263. priv->active_rate = IWL_RATES_MASK;
  2264. /* Configure Tx antenna selection based on H/W config */
  2265. if (priv->cfg->ops->hcmd->set_tx_ant)
  2266. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2267. if (iwl_is_associated(priv)) {
  2268. struct iwl_rxon_cmd *active_rxon =
  2269. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2270. /* apply any changes in staging */
  2271. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2272. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2273. } else {
  2274. /* Initialize our rx_config data */
  2275. iwl_connection_init_rx_config(priv, NULL);
  2276. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2277. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2278. }
  2279. /* Configure Bluetooth device coexistence support */
  2280. priv->cfg->ops->hcmd->send_bt_config(priv);
  2281. iwl_reset_run_time_calib(priv);
  2282. /* Configure the adapter for unassociated operation */
  2283. iwlcore_commit_rxon(priv);
  2284. /* At this point, the NIC is initialized and operational */
  2285. iwl_rf_kill_ct_config(priv);
  2286. iwl_leds_init(priv);
  2287. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2288. set_bit(STATUS_READY, &priv->status);
  2289. wake_up_interruptible(&priv->wait_command_queue);
  2290. iwl_power_update_mode(priv, true);
  2291. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2292. return;
  2293. restart:
  2294. queue_work(priv->workqueue, &priv->restart);
  2295. }
  2296. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2297. static void __iwl_down(struct iwl_priv *priv)
  2298. {
  2299. unsigned long flags;
  2300. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2301. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2302. if (!exit_pending)
  2303. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2304. iwl_clear_ucode_stations(priv);
  2305. iwl_dealloc_bcast_station(priv);
  2306. iwl_clear_driver_stations(priv);
  2307. /* Unblock any waiting calls */
  2308. wake_up_interruptible_all(&priv->wait_command_queue);
  2309. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2310. * exiting the module */
  2311. if (!exit_pending)
  2312. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2313. /* stop and reset the on-board processor */
  2314. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2315. /* tell the device to stop sending interrupts */
  2316. spin_lock_irqsave(&priv->lock, flags);
  2317. iwl_disable_interrupts(priv);
  2318. spin_unlock_irqrestore(&priv->lock, flags);
  2319. iwl_synchronize_irq(priv);
  2320. if (priv->mac80211_registered)
  2321. ieee80211_stop_queues(priv->hw);
  2322. /* If we have not previously called iwl_init() then
  2323. * clear all bits but the RF Kill bit and return */
  2324. if (!iwl_is_init(priv)) {
  2325. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2326. STATUS_RF_KILL_HW |
  2327. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2328. STATUS_GEO_CONFIGURED |
  2329. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2330. STATUS_EXIT_PENDING;
  2331. goto exit;
  2332. }
  2333. /* ...otherwise clear out all the status bits but the RF Kill
  2334. * bit and continue taking the NIC down. */
  2335. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2336. STATUS_RF_KILL_HW |
  2337. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2338. STATUS_GEO_CONFIGURED |
  2339. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2340. STATUS_FW_ERROR |
  2341. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2342. STATUS_EXIT_PENDING;
  2343. /* device going down, Stop using ICT table */
  2344. iwl_disable_ict(priv);
  2345. iwlagn_txq_ctx_stop(priv);
  2346. iwlagn_rxq_stop(priv);
  2347. /* Power-down device's busmaster DMA clocks */
  2348. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2349. udelay(5);
  2350. /* Make sure (redundant) we've released our request to stay awake */
  2351. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2352. /* Stop the device, and put it in low power state */
  2353. priv->cfg->ops->lib->apm_ops.stop(priv);
  2354. exit:
  2355. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2356. if (priv->ibss_beacon)
  2357. dev_kfree_skb(priv->ibss_beacon);
  2358. priv->ibss_beacon = NULL;
  2359. /* clear out any free frames */
  2360. iwl_clear_free_frames(priv);
  2361. }
  2362. static void iwl_down(struct iwl_priv *priv)
  2363. {
  2364. mutex_lock(&priv->mutex);
  2365. __iwl_down(priv);
  2366. mutex_unlock(&priv->mutex);
  2367. iwl_cancel_deferred_work(priv);
  2368. }
  2369. #define HW_READY_TIMEOUT (50)
  2370. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2371. {
  2372. int ret = 0;
  2373. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2374. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2375. /* See if we got it */
  2376. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2377. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2378. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2379. HW_READY_TIMEOUT);
  2380. if (ret != -ETIMEDOUT)
  2381. priv->hw_ready = true;
  2382. else
  2383. priv->hw_ready = false;
  2384. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2385. (priv->hw_ready == 1) ? "ready" : "not ready");
  2386. return ret;
  2387. }
  2388. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2389. {
  2390. int ret = 0;
  2391. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2392. ret = iwl_set_hw_ready(priv);
  2393. if (priv->hw_ready)
  2394. return ret;
  2395. /* If HW is not ready, prepare the conditions to check again */
  2396. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2397. CSR_HW_IF_CONFIG_REG_PREPARE);
  2398. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2399. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2400. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2401. /* HW should be ready by now, check again. */
  2402. if (ret != -ETIMEDOUT)
  2403. iwl_set_hw_ready(priv);
  2404. return ret;
  2405. }
  2406. #define MAX_HW_RESTARTS 5
  2407. static int __iwl_up(struct iwl_priv *priv)
  2408. {
  2409. int i;
  2410. int ret;
  2411. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2412. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2413. return -EIO;
  2414. }
  2415. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2416. IWL_ERR(priv, "ucode not available for device bringup\n");
  2417. return -EIO;
  2418. }
  2419. ret = iwl_alloc_bcast_station(priv, true);
  2420. if (ret)
  2421. return ret;
  2422. iwl_prepare_card_hw(priv);
  2423. if (!priv->hw_ready) {
  2424. IWL_WARN(priv, "Exit HW not ready\n");
  2425. return -EIO;
  2426. }
  2427. /* If platform's RF_KILL switch is NOT set to KILL */
  2428. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2429. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2430. else
  2431. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2432. if (iwl_is_rfkill(priv)) {
  2433. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2434. iwl_enable_interrupts(priv);
  2435. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2436. return 0;
  2437. }
  2438. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2439. ret = iwlagn_hw_nic_init(priv);
  2440. if (ret) {
  2441. IWL_ERR(priv, "Unable to init nic\n");
  2442. return ret;
  2443. }
  2444. /* make sure rfkill handshake bits are cleared */
  2445. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2446. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2447. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2448. /* clear (again), then enable host interrupts */
  2449. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2450. iwl_enable_interrupts(priv);
  2451. /* really make sure rfkill handshake bits are cleared */
  2452. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2453. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2454. /* Copy original ucode data image from disk into backup cache.
  2455. * This will be used to initialize the on-board processor's
  2456. * data SRAM for a clean start when the runtime program first loads. */
  2457. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2458. priv->ucode_data.len);
  2459. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2460. /* load bootstrap state machine,
  2461. * load bootstrap program into processor's memory,
  2462. * prepare to load the "initialize" uCode */
  2463. ret = priv->cfg->ops->lib->load_ucode(priv);
  2464. if (ret) {
  2465. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2466. ret);
  2467. continue;
  2468. }
  2469. /* start card; "initialize" will load runtime ucode */
  2470. iwl_nic_start(priv);
  2471. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2472. return 0;
  2473. }
  2474. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2475. __iwl_down(priv);
  2476. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2477. /* tried to restart and config the device for as long as our
  2478. * patience could withstand */
  2479. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2480. return -EIO;
  2481. }
  2482. /*****************************************************************************
  2483. *
  2484. * Workqueue callbacks
  2485. *
  2486. *****************************************************************************/
  2487. static void iwl_bg_init_alive_start(struct work_struct *data)
  2488. {
  2489. struct iwl_priv *priv =
  2490. container_of(data, struct iwl_priv, init_alive_start.work);
  2491. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2492. return;
  2493. mutex_lock(&priv->mutex);
  2494. priv->cfg->ops->lib->init_alive_start(priv);
  2495. mutex_unlock(&priv->mutex);
  2496. }
  2497. static void iwl_bg_alive_start(struct work_struct *data)
  2498. {
  2499. struct iwl_priv *priv =
  2500. container_of(data, struct iwl_priv, alive_start.work);
  2501. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2502. return;
  2503. /* enable dram interrupt */
  2504. iwl_reset_ict(priv);
  2505. mutex_lock(&priv->mutex);
  2506. iwl_alive_start(priv);
  2507. mutex_unlock(&priv->mutex);
  2508. }
  2509. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2510. {
  2511. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2512. run_time_calib_work);
  2513. mutex_lock(&priv->mutex);
  2514. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2515. test_bit(STATUS_SCANNING, &priv->status)) {
  2516. mutex_unlock(&priv->mutex);
  2517. return;
  2518. }
  2519. if (priv->start_calib) {
  2520. if (priv->cfg->bt_statistics) {
  2521. iwl_chain_noise_calibration(priv,
  2522. (void *)&priv->_agn.statistics_bt);
  2523. iwl_sensitivity_calibration(priv,
  2524. (void *)&priv->_agn.statistics_bt);
  2525. } else {
  2526. iwl_chain_noise_calibration(priv,
  2527. (void *)&priv->_agn.statistics);
  2528. iwl_sensitivity_calibration(priv,
  2529. (void *)&priv->_agn.statistics);
  2530. }
  2531. }
  2532. mutex_unlock(&priv->mutex);
  2533. }
  2534. static void iwl_bg_restart(struct work_struct *data)
  2535. {
  2536. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2537. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2538. return;
  2539. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2540. mutex_lock(&priv->mutex);
  2541. priv->vif = NULL;
  2542. priv->is_open = 0;
  2543. mutex_unlock(&priv->mutex);
  2544. iwl_down(priv);
  2545. ieee80211_restart_hw(priv->hw);
  2546. } else {
  2547. iwl_down(priv);
  2548. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2549. return;
  2550. mutex_lock(&priv->mutex);
  2551. __iwl_up(priv);
  2552. mutex_unlock(&priv->mutex);
  2553. }
  2554. }
  2555. static void iwl_bg_rx_replenish(struct work_struct *data)
  2556. {
  2557. struct iwl_priv *priv =
  2558. container_of(data, struct iwl_priv, rx_replenish);
  2559. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2560. return;
  2561. mutex_lock(&priv->mutex);
  2562. iwlagn_rx_replenish(priv);
  2563. mutex_unlock(&priv->mutex);
  2564. }
  2565. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2566. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2567. {
  2568. struct ieee80211_conf *conf = NULL;
  2569. int ret = 0;
  2570. if (!vif || !priv->is_open)
  2571. return;
  2572. if (vif->type == NL80211_IFTYPE_AP) {
  2573. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2574. return;
  2575. }
  2576. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2577. return;
  2578. iwl_scan_cancel_timeout(priv, 200);
  2579. conf = ieee80211_get_hw_conf(priv->hw);
  2580. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2581. iwlcore_commit_rxon(priv);
  2582. iwl_setup_rxon_timing(priv, vif);
  2583. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2584. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2585. if (ret)
  2586. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2587. "Attempting to continue.\n");
  2588. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2589. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2590. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2591. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2592. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2593. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2594. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2595. if (vif->bss_conf.use_short_preamble)
  2596. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2597. else
  2598. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2599. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2600. if (vif->bss_conf.use_short_slot)
  2601. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2602. else
  2603. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2604. }
  2605. iwlcore_commit_rxon(priv);
  2606. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2607. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2608. switch (vif->type) {
  2609. case NL80211_IFTYPE_STATION:
  2610. break;
  2611. case NL80211_IFTYPE_ADHOC:
  2612. iwl_send_beacon_cmd(priv);
  2613. break;
  2614. default:
  2615. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2616. __func__, vif->type);
  2617. break;
  2618. }
  2619. /* the chain noise calibration will enabled PM upon completion
  2620. * If chain noise has already been run, then we need to enable
  2621. * power management here */
  2622. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2623. iwl_power_update_mode(priv, false);
  2624. /* Enable Rx differential gain and sensitivity calibrations */
  2625. iwl_chain_noise_reset(priv);
  2626. priv->start_calib = 1;
  2627. }
  2628. /*****************************************************************************
  2629. *
  2630. * mac80211 entry point functions
  2631. *
  2632. *****************************************************************************/
  2633. #define UCODE_READY_TIMEOUT (4 * HZ)
  2634. /*
  2635. * Not a mac80211 entry point function, but it fits in with all the
  2636. * other mac80211 functions grouped here.
  2637. */
  2638. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2639. struct iwlagn_ucode_capabilities *capa)
  2640. {
  2641. int ret;
  2642. struct ieee80211_hw *hw = priv->hw;
  2643. hw->rate_control_algorithm = "iwl-agn-rs";
  2644. /* Tell mac80211 our characteristics */
  2645. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2646. IEEE80211_HW_AMPDU_AGGREGATION |
  2647. IEEE80211_HW_SPECTRUM_MGMT;
  2648. if (!priv->cfg->broken_powersave)
  2649. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2650. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2651. if (priv->cfg->sku & IWL_SKU_N)
  2652. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2653. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2654. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2655. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2656. hw->wiphy->interface_modes =
  2657. BIT(NL80211_IFTYPE_STATION) |
  2658. BIT(NL80211_IFTYPE_ADHOC);
  2659. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2660. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2661. /*
  2662. * For now, disable PS by default because it affects
  2663. * RX performance significantly.
  2664. */
  2665. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2666. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2667. /* we create the 802.11 header and a zero-length SSID element */
  2668. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2669. /* Default value; 4 EDCA QOS priorities */
  2670. hw->queues = 4;
  2671. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2672. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2673. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2674. &priv->bands[IEEE80211_BAND_2GHZ];
  2675. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2676. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2677. &priv->bands[IEEE80211_BAND_5GHZ];
  2678. ret = ieee80211_register_hw(priv->hw);
  2679. if (ret) {
  2680. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2681. return ret;
  2682. }
  2683. priv->mac80211_registered = 1;
  2684. return 0;
  2685. }
  2686. static int iwl_mac_start(struct ieee80211_hw *hw)
  2687. {
  2688. struct iwl_priv *priv = hw->priv;
  2689. int ret;
  2690. IWL_DEBUG_MAC80211(priv, "enter\n");
  2691. /* we should be verifying the device is ready to be opened */
  2692. mutex_lock(&priv->mutex);
  2693. ret = __iwl_up(priv);
  2694. mutex_unlock(&priv->mutex);
  2695. if (ret)
  2696. return ret;
  2697. if (iwl_is_rfkill(priv))
  2698. goto out;
  2699. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2700. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2701. * mac80211 will not be run successfully. */
  2702. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2703. test_bit(STATUS_READY, &priv->status),
  2704. UCODE_READY_TIMEOUT);
  2705. if (!ret) {
  2706. if (!test_bit(STATUS_READY, &priv->status)) {
  2707. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2708. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2709. return -ETIMEDOUT;
  2710. }
  2711. }
  2712. iwl_led_start(priv);
  2713. out:
  2714. priv->is_open = 1;
  2715. IWL_DEBUG_MAC80211(priv, "leave\n");
  2716. return 0;
  2717. }
  2718. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2719. {
  2720. struct iwl_priv *priv = hw->priv;
  2721. IWL_DEBUG_MAC80211(priv, "enter\n");
  2722. if (!priv->is_open)
  2723. return;
  2724. priv->is_open = 0;
  2725. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2726. /* stop mac, cancel any scan request and clear
  2727. * RXON_FILTER_ASSOC_MSK BIT
  2728. */
  2729. mutex_lock(&priv->mutex);
  2730. iwl_scan_cancel_timeout(priv, 100);
  2731. mutex_unlock(&priv->mutex);
  2732. }
  2733. iwl_down(priv);
  2734. flush_workqueue(priv->workqueue);
  2735. /* enable interrupts again in order to receive rfkill changes */
  2736. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2737. iwl_enable_interrupts(priv);
  2738. IWL_DEBUG_MAC80211(priv, "leave\n");
  2739. }
  2740. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2741. {
  2742. struct iwl_priv *priv = hw->priv;
  2743. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2744. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2745. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2746. if (iwlagn_tx_skb(priv, skb))
  2747. dev_kfree_skb_any(skb);
  2748. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2749. return NETDEV_TX_OK;
  2750. }
  2751. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2752. {
  2753. int ret = 0;
  2754. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2755. return;
  2756. /* The following should be done only at AP bring up */
  2757. if (!iwl_is_associated(priv)) {
  2758. /* RXON - unassoc (to set timing command) */
  2759. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2760. iwlcore_commit_rxon(priv);
  2761. /* RXON Timing */
  2762. iwl_setup_rxon_timing(priv, vif);
  2763. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2764. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2765. if (ret)
  2766. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2767. "Attempting to continue.\n");
  2768. /* AP has all antennas */
  2769. priv->chain_noise_data.active_chains =
  2770. priv->hw_params.valid_rx_ant;
  2771. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2772. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2773. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2774. priv->staging_rxon.assoc_id = 0;
  2775. if (vif->bss_conf.use_short_preamble)
  2776. priv->staging_rxon.flags |=
  2777. RXON_FLG_SHORT_PREAMBLE_MSK;
  2778. else
  2779. priv->staging_rxon.flags &=
  2780. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2781. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2782. if (vif->bss_conf.use_short_slot)
  2783. priv->staging_rxon.flags |=
  2784. RXON_FLG_SHORT_SLOT_MSK;
  2785. else
  2786. priv->staging_rxon.flags &=
  2787. ~RXON_FLG_SHORT_SLOT_MSK;
  2788. }
  2789. /* restore RXON assoc */
  2790. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2791. iwlcore_commit_rxon(priv);
  2792. }
  2793. iwl_send_beacon_cmd(priv);
  2794. /* FIXME - we need to add code here to detect a totally new
  2795. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2796. * clear sta table, add BCAST sta... */
  2797. }
  2798. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2799. struct ieee80211_vif *vif,
  2800. struct ieee80211_key_conf *keyconf,
  2801. struct ieee80211_sta *sta,
  2802. u32 iv32, u16 *phase1key)
  2803. {
  2804. struct iwl_priv *priv = hw->priv;
  2805. IWL_DEBUG_MAC80211(priv, "enter\n");
  2806. iwl_update_tkip_key(priv, keyconf, sta,
  2807. iv32, phase1key);
  2808. IWL_DEBUG_MAC80211(priv, "leave\n");
  2809. }
  2810. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2811. struct ieee80211_vif *vif,
  2812. struct ieee80211_sta *sta,
  2813. struct ieee80211_key_conf *key)
  2814. {
  2815. struct iwl_priv *priv = hw->priv;
  2816. int ret;
  2817. u8 sta_id;
  2818. bool is_default_wep_key = false;
  2819. IWL_DEBUG_MAC80211(priv, "enter\n");
  2820. if (priv->cfg->mod_params->sw_crypto) {
  2821. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2822. return -EOPNOTSUPP;
  2823. }
  2824. sta_id = iwl_sta_id_or_broadcast(priv, sta);
  2825. if (sta_id == IWL_INVALID_STATION)
  2826. return -EINVAL;
  2827. mutex_lock(&priv->mutex);
  2828. iwl_scan_cancel_timeout(priv, 100);
  2829. /*
  2830. * If we are getting WEP group key and we didn't receive any key mapping
  2831. * so far, we are in legacy wep mode (group key only), otherwise we are
  2832. * in 1X mode.
  2833. * In legacy wep mode, we use another host command to the uCode.
  2834. */
  2835. if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
  2836. if (cmd == SET_KEY)
  2837. is_default_wep_key = !priv->key_mapping_key;
  2838. else
  2839. is_default_wep_key =
  2840. (key->hw_key_idx == HW_KEY_DEFAULT);
  2841. }
  2842. switch (cmd) {
  2843. case SET_KEY:
  2844. if (is_default_wep_key)
  2845. ret = iwl_set_default_wep_key(priv, key);
  2846. else
  2847. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2848. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2849. break;
  2850. case DISABLE_KEY:
  2851. if (is_default_wep_key)
  2852. ret = iwl_remove_default_wep_key(priv, key);
  2853. else
  2854. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2855. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2856. break;
  2857. default:
  2858. ret = -EINVAL;
  2859. }
  2860. mutex_unlock(&priv->mutex);
  2861. IWL_DEBUG_MAC80211(priv, "leave\n");
  2862. return ret;
  2863. }
  2864. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2865. struct ieee80211_vif *vif,
  2866. enum ieee80211_ampdu_mlme_action action,
  2867. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2868. {
  2869. struct iwl_priv *priv = hw->priv;
  2870. int ret = -EINVAL;
  2871. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2872. sta->addr, tid);
  2873. if (!(priv->cfg->sku & IWL_SKU_N))
  2874. return -EACCES;
  2875. mutex_lock(&priv->mutex);
  2876. switch (action) {
  2877. case IEEE80211_AMPDU_RX_START:
  2878. IWL_DEBUG_HT(priv, "start Rx\n");
  2879. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2880. break;
  2881. case IEEE80211_AMPDU_RX_STOP:
  2882. IWL_DEBUG_HT(priv, "stop Rx\n");
  2883. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2884. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2885. ret = 0;
  2886. break;
  2887. case IEEE80211_AMPDU_TX_START:
  2888. IWL_DEBUG_HT(priv, "start Tx\n");
  2889. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2890. if (ret == 0) {
  2891. priv->_agn.agg_tids_count++;
  2892. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2893. priv->_agn.agg_tids_count);
  2894. }
  2895. break;
  2896. case IEEE80211_AMPDU_TX_STOP:
  2897. IWL_DEBUG_HT(priv, "stop Tx\n");
  2898. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2899. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2900. priv->_agn.agg_tids_count--;
  2901. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2902. priv->_agn.agg_tids_count);
  2903. }
  2904. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2905. ret = 0;
  2906. if (priv->cfg->use_rts_for_aggregation) {
  2907. struct iwl_station_priv *sta_priv =
  2908. (void *) sta->drv_priv;
  2909. /*
  2910. * switch off RTS/CTS if it was previously enabled
  2911. */
  2912. sta_priv->lq_sta.lq.general_params.flags &=
  2913. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2914. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  2915. CMD_ASYNC, false);
  2916. }
  2917. break;
  2918. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2919. if (priv->cfg->use_rts_for_aggregation) {
  2920. struct iwl_station_priv *sta_priv =
  2921. (void *) sta->drv_priv;
  2922. /*
  2923. * switch to RTS/CTS if it is the prefer protection
  2924. * method for HT traffic
  2925. */
  2926. sta_priv->lq_sta.lq.general_params.flags |=
  2927. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2928. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  2929. CMD_ASYNC, false);
  2930. }
  2931. ret = 0;
  2932. break;
  2933. }
  2934. mutex_unlock(&priv->mutex);
  2935. return ret;
  2936. }
  2937. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2938. struct ieee80211_vif *vif,
  2939. enum sta_notify_cmd cmd,
  2940. struct ieee80211_sta *sta)
  2941. {
  2942. struct iwl_priv *priv = hw->priv;
  2943. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2944. int sta_id;
  2945. switch (cmd) {
  2946. case STA_NOTIFY_SLEEP:
  2947. WARN_ON(!sta_priv->client);
  2948. sta_priv->asleep = true;
  2949. if (atomic_read(&sta_priv->pending_frames) > 0)
  2950. ieee80211_sta_block_awake(hw, sta, true);
  2951. break;
  2952. case STA_NOTIFY_AWAKE:
  2953. WARN_ON(!sta_priv->client);
  2954. if (!sta_priv->asleep)
  2955. break;
  2956. sta_priv->asleep = false;
  2957. sta_id = iwl_sta_id(sta);
  2958. if (sta_id != IWL_INVALID_STATION)
  2959. iwl_sta_modify_ps_wake(priv, sta_id);
  2960. break;
  2961. default:
  2962. break;
  2963. }
  2964. }
  2965. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2966. struct ieee80211_vif *vif,
  2967. struct ieee80211_sta *sta)
  2968. {
  2969. struct iwl_priv *priv = hw->priv;
  2970. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2971. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2972. int ret;
  2973. u8 sta_id;
  2974. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2975. sta->addr);
  2976. mutex_lock(&priv->mutex);
  2977. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2978. sta->addr);
  2979. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2980. atomic_set(&sta_priv->pending_frames, 0);
  2981. if (vif->type == NL80211_IFTYPE_AP)
  2982. sta_priv->client = true;
  2983. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2984. &sta_id);
  2985. if (ret) {
  2986. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2987. sta->addr, ret);
  2988. /* Should we return success if return code is EEXIST ? */
  2989. mutex_unlock(&priv->mutex);
  2990. return ret;
  2991. }
  2992. sta_priv->common.sta_id = sta_id;
  2993. /* Initialize rate scaling */
  2994. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2995. sta->addr);
  2996. iwl_rs_rate_init(priv, sta, sta_id);
  2997. mutex_unlock(&priv->mutex);
  2998. return 0;
  2999. }
  3000. static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
  3001. struct ieee80211_channel_switch *ch_switch)
  3002. {
  3003. struct iwl_priv *priv = hw->priv;
  3004. const struct iwl_channel_info *ch_info;
  3005. struct ieee80211_conf *conf = &hw->conf;
  3006. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  3007. u16 ch;
  3008. unsigned long flags = 0;
  3009. IWL_DEBUG_MAC80211(priv, "enter\n");
  3010. if (iwl_is_rfkill(priv))
  3011. goto out_exit;
  3012. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  3013. test_bit(STATUS_SCANNING, &priv->status))
  3014. goto out_exit;
  3015. if (!iwl_is_associated(priv))
  3016. goto out_exit;
  3017. /* channel switch in progress */
  3018. if (priv->switch_rxon.switch_in_progress == true)
  3019. goto out_exit;
  3020. mutex_lock(&priv->mutex);
  3021. if (priv->cfg->ops->lib->set_channel_switch) {
  3022. ch = ieee80211_frequency_to_channel(
  3023. ch_switch->channel->center_freq);
  3024. if (le16_to_cpu(priv->active_rxon.channel) != ch) {
  3025. ch_info = iwl_get_channel_info(priv,
  3026. conf->channel->band,
  3027. ch);
  3028. if (!is_channel_valid(ch_info)) {
  3029. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  3030. goto out;
  3031. }
  3032. spin_lock_irqsave(&priv->lock, flags);
  3033. priv->current_ht_config.smps = conf->smps_mode;
  3034. /* Configure HT40 channels */
  3035. ht_conf->is_ht = conf_is_ht(conf);
  3036. if (ht_conf->is_ht) {
  3037. if (conf_is_ht40_minus(conf)) {
  3038. ht_conf->extension_chan_offset =
  3039. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  3040. ht_conf->is_40mhz = true;
  3041. } else if (conf_is_ht40_plus(conf)) {
  3042. ht_conf->extension_chan_offset =
  3043. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  3044. ht_conf->is_40mhz = true;
  3045. } else {
  3046. ht_conf->extension_chan_offset =
  3047. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  3048. ht_conf->is_40mhz = false;
  3049. }
  3050. } else
  3051. ht_conf->is_40mhz = false;
  3052. /* if we are switching from ht to 2.4 clear flags
  3053. * from any ht related info since 2.4 does not
  3054. * support ht */
  3055. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  3056. priv->staging_rxon.flags = 0;
  3057. iwl_set_rxon_channel(priv, conf->channel);
  3058. iwl_set_rxon_ht(priv, ht_conf);
  3059. iwl_set_flags_for_band(priv, conf->channel->band,
  3060. priv->vif);
  3061. spin_unlock_irqrestore(&priv->lock, flags);
  3062. iwl_set_rate(priv);
  3063. /*
  3064. * at this point, staging_rxon has the
  3065. * configuration for channel switch
  3066. */
  3067. if (priv->cfg->ops->lib->set_channel_switch(priv,
  3068. ch_switch))
  3069. priv->switch_rxon.switch_in_progress = false;
  3070. }
  3071. }
  3072. out:
  3073. mutex_unlock(&priv->mutex);
  3074. out_exit:
  3075. if (!priv->switch_rxon.switch_in_progress)
  3076. ieee80211_chswitch_done(priv->vif, false);
  3077. IWL_DEBUG_MAC80211(priv, "leave\n");
  3078. }
  3079. static void iwlagn_configure_filter(struct ieee80211_hw *hw,
  3080. unsigned int changed_flags,
  3081. unsigned int *total_flags,
  3082. u64 multicast)
  3083. {
  3084. struct iwl_priv *priv = hw->priv;
  3085. __le32 filter_or = 0, filter_nand = 0;
  3086. #define CHK(test, flag) do { \
  3087. if (*total_flags & (test)) \
  3088. filter_or |= (flag); \
  3089. else \
  3090. filter_nand |= (flag); \
  3091. } while (0)
  3092. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  3093. changed_flags, *total_flags);
  3094. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  3095. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  3096. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  3097. #undef CHK
  3098. mutex_lock(&priv->mutex);
  3099. priv->staging_rxon.filter_flags &= ~filter_nand;
  3100. priv->staging_rxon.filter_flags |= filter_or;
  3101. iwlcore_commit_rxon(priv);
  3102. mutex_unlock(&priv->mutex);
  3103. /*
  3104. * Receiving all multicast frames is always enabled by the
  3105. * default flags setup in iwl_connection_init_rx_config()
  3106. * since we currently do not support programming multicast
  3107. * filters into the device.
  3108. */
  3109. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  3110. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  3111. }
  3112. static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
  3113. {
  3114. struct iwl_priv *priv = hw->priv;
  3115. mutex_lock(&priv->mutex);
  3116. IWL_DEBUG_MAC80211(priv, "enter\n");
  3117. /* do not support "flush" */
  3118. if (!priv->cfg->ops->lib->txfifo_flush)
  3119. goto done;
  3120. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3121. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  3122. goto done;
  3123. }
  3124. if (iwl_is_rfkill(priv)) {
  3125. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  3126. goto done;
  3127. }
  3128. /*
  3129. * mac80211 will not push any more frames for transmit
  3130. * until the flush is completed
  3131. */
  3132. if (drop) {
  3133. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  3134. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  3135. IWL_ERR(priv, "flush request fail\n");
  3136. goto done;
  3137. }
  3138. }
  3139. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  3140. iwlagn_wait_tx_queue_empty(priv);
  3141. done:
  3142. mutex_unlock(&priv->mutex);
  3143. IWL_DEBUG_MAC80211(priv, "leave\n");
  3144. }
  3145. /*****************************************************************************
  3146. *
  3147. * driver setup and teardown
  3148. *
  3149. *****************************************************************************/
  3150. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  3151. {
  3152. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3153. init_waitqueue_head(&priv->wait_command_queue);
  3154. INIT_WORK(&priv->restart, iwl_bg_restart);
  3155. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  3156. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  3157. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  3158. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  3159. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  3160. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  3161. iwl_setup_scan_deferred_work(priv);
  3162. if (priv->cfg->ops->lib->setup_deferred_work)
  3163. priv->cfg->ops->lib->setup_deferred_work(priv);
  3164. init_timer(&priv->statistics_periodic);
  3165. priv->statistics_periodic.data = (unsigned long)priv;
  3166. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  3167. init_timer(&priv->ucode_trace);
  3168. priv->ucode_trace.data = (unsigned long)priv;
  3169. priv->ucode_trace.function = iwl_bg_ucode_trace;
  3170. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3171. init_timer(&priv->monitor_recover);
  3172. priv->monitor_recover.data = (unsigned long)priv;
  3173. priv->monitor_recover.function =
  3174. priv->cfg->ops->lib->recover_from_tx_stall;
  3175. }
  3176. if (!priv->cfg->use_isr_legacy)
  3177. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3178. iwl_irq_tasklet, (unsigned long)priv);
  3179. else
  3180. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3181. iwl_irq_tasklet_legacy, (unsigned long)priv);
  3182. }
  3183. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  3184. {
  3185. if (priv->cfg->ops->lib->cancel_deferred_work)
  3186. priv->cfg->ops->lib->cancel_deferred_work(priv);
  3187. cancel_delayed_work_sync(&priv->init_alive_start);
  3188. cancel_delayed_work(&priv->scan_check);
  3189. cancel_work_sync(&priv->start_internal_scan);
  3190. cancel_delayed_work(&priv->alive_start);
  3191. cancel_work_sync(&priv->run_time_calib_work);
  3192. cancel_work_sync(&priv->beacon_update);
  3193. del_timer_sync(&priv->statistics_periodic);
  3194. del_timer_sync(&priv->ucode_trace);
  3195. if (priv->cfg->ops->lib->recover_from_tx_stall)
  3196. del_timer_sync(&priv->monitor_recover);
  3197. }
  3198. static void iwl_init_hw_rates(struct iwl_priv *priv,
  3199. struct ieee80211_rate *rates)
  3200. {
  3201. int i;
  3202. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  3203. rates[i].bitrate = iwl_rates[i].ieee * 5;
  3204. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3205. rates[i].hw_value_short = i;
  3206. rates[i].flags = 0;
  3207. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  3208. /*
  3209. * If CCK != 1M then set short preamble rate flag.
  3210. */
  3211. rates[i].flags |=
  3212. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  3213. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3214. }
  3215. }
  3216. }
  3217. static int iwl_init_drv(struct iwl_priv *priv)
  3218. {
  3219. int ret;
  3220. priv->ibss_beacon = NULL;
  3221. spin_lock_init(&priv->sta_lock);
  3222. spin_lock_init(&priv->hcmd_lock);
  3223. INIT_LIST_HEAD(&priv->free_frames);
  3224. mutex_init(&priv->mutex);
  3225. mutex_init(&priv->sync_cmd_mutex);
  3226. priv->ieee_channels = NULL;
  3227. priv->ieee_rates = NULL;
  3228. priv->band = IEEE80211_BAND_2GHZ;
  3229. priv->iw_mode = NL80211_IFTYPE_STATION;
  3230. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  3231. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3232. priv->_agn.agg_tids_count = 0;
  3233. /* initialize force reset */
  3234. priv->force_reset[IWL_RF_RESET].reset_duration =
  3235. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3236. priv->force_reset[IWL_FW_RESET].reset_duration =
  3237. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3238. /* Choose which receivers/antennas to use */
  3239. if (priv->cfg->ops->hcmd->set_rxon_chain)
  3240. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  3241. iwl_init_scan_params(priv);
  3242. /* Set the tx_power_user_lmt to the lowest power level
  3243. * this value will get overwritten by channel max power avg
  3244. * from eeprom */
  3245. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3246. ret = iwl_init_channel_map(priv);
  3247. if (ret) {
  3248. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3249. goto err;
  3250. }
  3251. ret = iwlcore_init_geos(priv);
  3252. if (ret) {
  3253. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3254. goto err_free_channel_map;
  3255. }
  3256. iwl_init_hw_rates(priv, priv->ieee_rates);
  3257. return 0;
  3258. err_free_channel_map:
  3259. iwl_free_channel_map(priv);
  3260. err:
  3261. return ret;
  3262. }
  3263. static void iwl_uninit_drv(struct iwl_priv *priv)
  3264. {
  3265. iwl_calib_free_results(priv);
  3266. iwlcore_free_geos(priv);
  3267. iwl_free_channel_map(priv);
  3268. kfree(priv->scan_cmd);
  3269. }
  3270. static struct ieee80211_ops iwl_hw_ops = {
  3271. .tx = iwl_mac_tx,
  3272. .start = iwl_mac_start,
  3273. .stop = iwl_mac_stop,
  3274. .add_interface = iwl_mac_add_interface,
  3275. .remove_interface = iwl_mac_remove_interface,
  3276. .config = iwl_mac_config,
  3277. .configure_filter = iwlagn_configure_filter,
  3278. .set_key = iwl_mac_set_key,
  3279. .update_tkip_key = iwl_mac_update_tkip_key,
  3280. .conf_tx = iwl_mac_conf_tx,
  3281. .reset_tsf = iwl_mac_reset_tsf,
  3282. .bss_info_changed = iwl_bss_info_changed,
  3283. .ampdu_action = iwl_mac_ampdu_action,
  3284. .hw_scan = iwl_mac_hw_scan,
  3285. .sta_notify = iwl_mac_sta_notify,
  3286. .sta_add = iwlagn_mac_sta_add,
  3287. .sta_remove = iwl_mac_sta_remove,
  3288. .channel_switch = iwl_mac_channel_switch,
  3289. .flush = iwl_mac_flush,
  3290. };
  3291. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3292. {
  3293. int err = 0;
  3294. struct iwl_priv *priv;
  3295. struct ieee80211_hw *hw;
  3296. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3297. unsigned long flags;
  3298. u16 pci_cmd, num_mac;
  3299. /************************
  3300. * 1. Allocating HW data
  3301. ************************/
  3302. /* Disabling hardware scan means that mac80211 will perform scans
  3303. * "the hard way", rather than using device's scan. */
  3304. if (cfg->mod_params->disable_hw_scan) {
  3305. if (iwl_debug_level & IWL_DL_INFO)
  3306. dev_printk(KERN_DEBUG, &(pdev->dev),
  3307. "Disabling hw_scan\n");
  3308. iwl_hw_ops.hw_scan = NULL;
  3309. }
  3310. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3311. if (!hw) {
  3312. err = -ENOMEM;
  3313. goto out;
  3314. }
  3315. priv = hw->priv;
  3316. /* At this point both hw and priv are allocated. */
  3317. SET_IEEE80211_DEV(hw, &pdev->dev);
  3318. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3319. priv->cfg = cfg;
  3320. priv->pci_dev = pdev;
  3321. priv->inta_mask = CSR_INI_SET_MASK;
  3322. if (iwl_alloc_traffic_mem(priv))
  3323. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3324. /**************************
  3325. * 2. Initializing PCI bus
  3326. **************************/
  3327. if (pci_enable_device(pdev)) {
  3328. err = -ENODEV;
  3329. goto out_ieee80211_free_hw;
  3330. }
  3331. pci_set_master(pdev);
  3332. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3333. if (!err)
  3334. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3335. if (err) {
  3336. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3337. if (!err)
  3338. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3339. /* both attempts failed: */
  3340. if (err) {
  3341. IWL_WARN(priv, "No suitable DMA available.\n");
  3342. goto out_pci_disable_device;
  3343. }
  3344. }
  3345. err = pci_request_regions(pdev, DRV_NAME);
  3346. if (err)
  3347. goto out_pci_disable_device;
  3348. pci_set_drvdata(pdev, priv);
  3349. /***********************
  3350. * 3. Read REV register
  3351. ***********************/
  3352. priv->hw_base = pci_iomap(pdev, 0, 0);
  3353. if (!priv->hw_base) {
  3354. err = -ENODEV;
  3355. goto out_pci_release_regions;
  3356. }
  3357. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3358. (unsigned long long) pci_resource_len(pdev, 0));
  3359. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3360. /* these spin locks will be used in apm_ops.init and EEPROM access
  3361. * we should init now
  3362. */
  3363. spin_lock_init(&priv->reg_lock);
  3364. spin_lock_init(&priv->lock);
  3365. /*
  3366. * stop and reset the on-board processor just in case it is in a
  3367. * strange state ... like being left stranded by a primary kernel
  3368. * and this is now the kdump kernel trying to start up
  3369. */
  3370. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3371. iwl_hw_detect(priv);
  3372. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3373. priv->cfg->name, priv->hw_rev);
  3374. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3375. * PCI Tx retries from interfering with C3 CPU state */
  3376. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3377. iwl_prepare_card_hw(priv);
  3378. if (!priv->hw_ready) {
  3379. IWL_WARN(priv, "Failed, HW not ready\n");
  3380. goto out_iounmap;
  3381. }
  3382. /*****************
  3383. * 4. Read EEPROM
  3384. *****************/
  3385. /* Read the EEPROM */
  3386. err = iwl_eeprom_init(priv);
  3387. if (err) {
  3388. IWL_ERR(priv, "Unable to init EEPROM\n");
  3389. goto out_iounmap;
  3390. }
  3391. err = iwl_eeprom_check_version(priv);
  3392. if (err)
  3393. goto out_free_eeprom;
  3394. /* extract MAC Address */
  3395. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3396. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3397. priv->hw->wiphy->addresses = priv->addresses;
  3398. priv->hw->wiphy->n_addresses = 1;
  3399. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3400. if (num_mac > 1) {
  3401. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3402. ETH_ALEN);
  3403. priv->addresses[1].addr[5]++;
  3404. priv->hw->wiphy->n_addresses++;
  3405. }
  3406. /************************
  3407. * 5. Setup HW constants
  3408. ************************/
  3409. if (iwl_set_hw_params(priv)) {
  3410. IWL_ERR(priv, "failed to set hw parameters\n");
  3411. goto out_free_eeprom;
  3412. }
  3413. /*******************
  3414. * 6. Setup priv
  3415. *******************/
  3416. err = iwl_init_drv(priv);
  3417. if (err)
  3418. goto out_free_eeprom;
  3419. /* At this point both hw and priv are initialized. */
  3420. /********************
  3421. * 7. Setup services
  3422. ********************/
  3423. spin_lock_irqsave(&priv->lock, flags);
  3424. iwl_disable_interrupts(priv);
  3425. spin_unlock_irqrestore(&priv->lock, flags);
  3426. pci_enable_msi(priv->pci_dev);
  3427. iwl_alloc_isr_ict(priv);
  3428. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3429. IRQF_SHARED, DRV_NAME, priv);
  3430. if (err) {
  3431. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3432. goto out_disable_msi;
  3433. }
  3434. iwl_setup_deferred_work(priv);
  3435. iwl_setup_rx_handlers(priv);
  3436. /*********************************************
  3437. * 8. Enable interrupts and read RFKILL state
  3438. *********************************************/
  3439. /* enable interrupts if needed: hw bug w/a */
  3440. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3441. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3442. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3443. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3444. }
  3445. iwl_enable_interrupts(priv);
  3446. /* If platform's RF_KILL switch is NOT set to KILL */
  3447. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3448. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3449. else
  3450. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3451. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3452. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3453. iwl_power_initialize(priv);
  3454. iwl_tt_initialize(priv);
  3455. init_completion(&priv->_agn.firmware_loading_complete);
  3456. err = iwl_request_firmware(priv, true);
  3457. if (err)
  3458. goto out_destroy_workqueue;
  3459. return 0;
  3460. out_destroy_workqueue:
  3461. destroy_workqueue(priv->workqueue);
  3462. priv->workqueue = NULL;
  3463. free_irq(priv->pci_dev->irq, priv);
  3464. iwl_free_isr_ict(priv);
  3465. out_disable_msi:
  3466. pci_disable_msi(priv->pci_dev);
  3467. iwl_uninit_drv(priv);
  3468. out_free_eeprom:
  3469. iwl_eeprom_free(priv);
  3470. out_iounmap:
  3471. pci_iounmap(pdev, priv->hw_base);
  3472. out_pci_release_regions:
  3473. pci_set_drvdata(pdev, NULL);
  3474. pci_release_regions(pdev);
  3475. out_pci_disable_device:
  3476. pci_disable_device(pdev);
  3477. out_ieee80211_free_hw:
  3478. iwl_free_traffic_mem(priv);
  3479. ieee80211_free_hw(priv->hw);
  3480. out:
  3481. return err;
  3482. }
  3483. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3484. {
  3485. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3486. unsigned long flags;
  3487. if (!priv)
  3488. return;
  3489. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3490. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3491. iwl_dbgfs_unregister(priv);
  3492. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3493. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3494. * to be called and iwl_down since we are removing the device
  3495. * we need to set STATUS_EXIT_PENDING bit.
  3496. */
  3497. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3498. if (priv->mac80211_registered) {
  3499. ieee80211_unregister_hw(priv->hw);
  3500. priv->mac80211_registered = 0;
  3501. } else {
  3502. iwl_down(priv);
  3503. }
  3504. /*
  3505. * Make sure device is reset to low power before unloading driver.
  3506. * This may be redundant with iwl_down(), but there are paths to
  3507. * run iwl_down() without calling apm_ops.stop(), and there are
  3508. * paths to avoid running iwl_down() at all before leaving driver.
  3509. * This (inexpensive) call *makes sure* device is reset.
  3510. */
  3511. priv->cfg->ops->lib->apm_ops.stop(priv);
  3512. iwl_tt_exit(priv);
  3513. /* make sure we flush any pending irq or
  3514. * tasklet for the driver
  3515. */
  3516. spin_lock_irqsave(&priv->lock, flags);
  3517. iwl_disable_interrupts(priv);
  3518. spin_unlock_irqrestore(&priv->lock, flags);
  3519. iwl_synchronize_irq(priv);
  3520. iwl_dealloc_ucode_pci(priv);
  3521. if (priv->rxq.bd)
  3522. iwlagn_rx_queue_free(priv, &priv->rxq);
  3523. iwlagn_hw_txq_ctx_free(priv);
  3524. iwl_eeprom_free(priv);
  3525. /*netif_stop_queue(dev); */
  3526. flush_workqueue(priv->workqueue);
  3527. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3528. * priv->workqueue... so we can't take down the workqueue
  3529. * until now... */
  3530. destroy_workqueue(priv->workqueue);
  3531. priv->workqueue = NULL;
  3532. iwl_free_traffic_mem(priv);
  3533. free_irq(priv->pci_dev->irq, priv);
  3534. pci_disable_msi(priv->pci_dev);
  3535. pci_iounmap(pdev, priv->hw_base);
  3536. pci_release_regions(pdev);
  3537. pci_disable_device(pdev);
  3538. pci_set_drvdata(pdev, NULL);
  3539. iwl_uninit_drv(priv);
  3540. iwl_free_isr_ict(priv);
  3541. if (priv->ibss_beacon)
  3542. dev_kfree_skb(priv->ibss_beacon);
  3543. ieee80211_free_hw(priv->hw);
  3544. }
  3545. /*****************************************************************************
  3546. *
  3547. * driver and module entry point
  3548. *
  3549. *****************************************************************************/
  3550. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3551. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3552. #ifdef CONFIG_IWL4965
  3553. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3554. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3555. #endif /* CONFIG_IWL4965 */
  3556. #ifdef CONFIG_IWL5000
  3557. /* 5100 Series WiFi */
  3558. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3559. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3560. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3561. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3562. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3563. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3564. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3565. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3566. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3567. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3568. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3569. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3570. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3571. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3572. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3573. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3574. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3575. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3576. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3577. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3578. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3579. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3580. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3581. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3582. /* 5300 Series WiFi */
  3583. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3584. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3585. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3586. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3587. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3588. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3589. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3590. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3591. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3592. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3593. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3594. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3595. /* 5350 Series WiFi/WiMax */
  3596. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3597. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3598. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3599. /* 5150 Series Wifi/WiMax */
  3600. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3601. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3602. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3603. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3604. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3605. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3606. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3607. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3608. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3609. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3610. /* 6x00 Series */
  3611. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3612. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3613. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3614. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3615. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3616. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3617. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3618. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3619. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3620. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3621. /* 6x00 Series Gen2a */
  3622. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3623. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3624. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3625. {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
  3626. {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
  3627. {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
  3628. {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
  3629. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
  3630. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
  3631. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
  3632. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
  3633. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
  3634. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
  3635. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
  3636. /* 6x00 Series Gen2b */
  3637. {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
  3638. {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
  3639. {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
  3640. {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
  3641. {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
  3642. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3643. {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
  3644. {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
  3645. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3646. {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
  3647. {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
  3648. {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
  3649. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
  3650. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
  3651. {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
  3652. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
  3653. {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
  3654. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
  3655. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3656. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
  3657. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3658. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
  3659. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
  3660. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
  3661. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
  3662. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
  3663. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
  3664. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
  3665. /* 6x50 WiFi/WiMax Series */
  3666. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3667. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3668. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3669. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3670. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3671. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3672. /* 6x50 WiFi/WiMax Series Gen2 */
  3673. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
  3674. {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
  3675. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
  3676. {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
  3677. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
  3678. {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
  3679. /* 1000 Series WiFi */
  3680. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3681. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3682. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3683. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3684. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3685. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3686. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3687. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3688. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3689. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3690. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3691. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3692. #endif /* CONFIG_IWL5000 */
  3693. {0}
  3694. };
  3695. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3696. static struct pci_driver iwl_driver = {
  3697. .name = DRV_NAME,
  3698. .id_table = iwl_hw_card_ids,
  3699. .probe = iwl_pci_probe,
  3700. .remove = __devexit_p(iwl_pci_remove),
  3701. #ifdef CONFIG_PM
  3702. .suspend = iwl_pci_suspend,
  3703. .resume = iwl_pci_resume,
  3704. #endif
  3705. };
  3706. static int __init iwl_init(void)
  3707. {
  3708. int ret;
  3709. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3710. pr_info(DRV_COPYRIGHT "\n");
  3711. ret = iwlagn_rate_control_register();
  3712. if (ret) {
  3713. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3714. return ret;
  3715. }
  3716. ret = pci_register_driver(&iwl_driver);
  3717. if (ret) {
  3718. pr_err("Unable to initialize PCI module\n");
  3719. goto error_register;
  3720. }
  3721. return ret;
  3722. error_register:
  3723. iwlagn_rate_control_unregister();
  3724. return ret;
  3725. }
  3726. static void __exit iwl_exit(void)
  3727. {
  3728. pci_unregister_driver(&iwl_driver);
  3729. iwlagn_rate_control_unregister();
  3730. }
  3731. module_exit(iwl_exit);
  3732. module_init(iwl_init);
  3733. #ifdef CONFIG_IWLWIFI_DEBUG
  3734. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3735. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3736. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3737. MODULE_PARM_DESC(debug, "debug output mask");
  3738. #endif
  3739. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3740. MODULE_PARM_DESC(swcrypto50,
  3741. "using crypto in software (default 0 [hardware]) (deprecated)");
  3742. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3743. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3744. module_param_named(queues_num50,
  3745. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3746. MODULE_PARM_DESC(queues_num50,
  3747. "number of hw queues in 50xx series (deprecated)");
  3748. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3749. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3750. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3751. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3752. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3753. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3754. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3755. int, S_IRUGO);
  3756. MODULE_PARM_DESC(amsdu_size_8K50,
  3757. "enable 8K amsdu size in 50XX series (deprecated)");
  3758. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3759. int, S_IRUGO);
  3760. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3761. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3762. MODULE_PARM_DESC(fw_restart50,
  3763. "restart firmware in case of error (deprecated)");
  3764. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3765. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3766. module_param_named(
  3767. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3768. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3769. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3770. S_IRUGO);
  3771. MODULE_PARM_DESC(ucode_alternative,
  3772. "specify ucode alternative to use from ucode file");