base.c 95 KB

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  1. /*-
  2. * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
  3. * Copyright (c) 2004-2005 Atheros Communications, Inc.
  4. * Copyright (c) 2006 Devicescape Software, Inc.
  5. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  6. * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
  7. *
  8. * All rights reserved.
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions
  12. * are met:
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer,
  15. * without modification.
  16. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17. * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18. * redistribution must be conditioned upon including a substantially
  19. * similar Disclaimer requirement for further binary redistribution.
  20. * 3. Neither the names of the above-listed copyright holders nor the names
  21. * of any contributors may be used to endorse or promote products derived
  22. * from this software without specific prior written permission.
  23. *
  24. * Alternatively, this software may be distributed under the terms of the
  25. * GNU General Public License ("GPL") version 2 as published by the Free
  26. * Software Foundation.
  27. *
  28. * NO WARRANTY
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32. * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33. * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34. * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37. * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39. * THE POSSIBILITY OF SUCH DAMAGES.
  40. *
  41. */
  42. #include <linux/module.h>
  43. #include <linux/delay.h>
  44. #include <linux/hardirq.h>
  45. #include <linux/if.h>
  46. #include <linux/io.h>
  47. #include <linux/netdevice.h>
  48. #include <linux/cache.h>
  49. #include <linux/pci.h>
  50. #include <linux/pci-aspm.h>
  51. #include <linux/ethtool.h>
  52. #include <linux/uaccess.h>
  53. #include <linux/slab.h>
  54. #include <net/ieee80211_radiotap.h>
  55. #include <asm/unaligned.h>
  56. #include "base.h"
  57. #include "reg.h"
  58. #include "debug.h"
  59. #include "ani.h"
  60. static int modparam_nohwcrypt;
  61. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  62. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  63. static int modparam_all_channels;
  64. module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
  65. MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
  66. /******************\
  67. * Internal defines *
  68. \******************/
  69. /* Module info */
  70. MODULE_AUTHOR("Jiri Slaby");
  71. MODULE_AUTHOR("Nick Kossifidis");
  72. MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  73. MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  74. MODULE_LICENSE("Dual BSD/GPL");
  75. MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  76. /* Known PCI ids */
  77. static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
  78. { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
  79. { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
  80. { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
  81. { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
  82. { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
  83. { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
  84. { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
  85. { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
  86. { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
  87. { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
  88. { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
  89. { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
  90. { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
  91. { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
  92. { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
  93. { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
  94. { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
  95. { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
  96. { 0 }
  97. };
  98. MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
  99. /* Known SREVs */
  100. static const struct ath5k_srev_name srev_names[] = {
  101. { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
  102. { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
  103. { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
  104. { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
  105. { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
  106. { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
  107. { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
  108. { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
  109. { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
  110. { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
  111. { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
  112. { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
  113. { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
  114. { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
  115. { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
  116. { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
  117. { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
  118. { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
  119. { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
  120. { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
  121. { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
  122. { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
  123. { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
  124. { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
  125. { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
  126. { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
  127. { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
  128. { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
  129. { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
  130. { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
  131. { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
  132. { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
  133. { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
  134. { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
  135. { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
  136. { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
  137. };
  138. static const struct ieee80211_rate ath5k_rates[] = {
  139. { .bitrate = 10,
  140. .hw_value = ATH5K_RATE_CODE_1M, },
  141. { .bitrate = 20,
  142. .hw_value = ATH5K_RATE_CODE_2M,
  143. .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
  144. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  145. { .bitrate = 55,
  146. .hw_value = ATH5K_RATE_CODE_5_5M,
  147. .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
  148. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  149. { .bitrate = 110,
  150. .hw_value = ATH5K_RATE_CODE_11M,
  151. .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
  152. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  153. { .bitrate = 60,
  154. .hw_value = ATH5K_RATE_CODE_6M,
  155. .flags = 0 },
  156. { .bitrate = 90,
  157. .hw_value = ATH5K_RATE_CODE_9M,
  158. .flags = 0 },
  159. { .bitrate = 120,
  160. .hw_value = ATH5K_RATE_CODE_12M,
  161. .flags = 0 },
  162. { .bitrate = 180,
  163. .hw_value = ATH5K_RATE_CODE_18M,
  164. .flags = 0 },
  165. { .bitrate = 240,
  166. .hw_value = ATH5K_RATE_CODE_24M,
  167. .flags = 0 },
  168. { .bitrate = 360,
  169. .hw_value = ATH5K_RATE_CODE_36M,
  170. .flags = 0 },
  171. { .bitrate = 480,
  172. .hw_value = ATH5K_RATE_CODE_48M,
  173. .flags = 0 },
  174. { .bitrate = 540,
  175. .hw_value = ATH5K_RATE_CODE_54M,
  176. .flags = 0 },
  177. /* XR missing */
  178. };
  179. /*
  180. * Prototypes - PCI stack related functions
  181. */
  182. static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
  183. const struct pci_device_id *id);
  184. static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
  185. #ifdef CONFIG_PM_SLEEP
  186. static int ath5k_pci_suspend(struct device *dev);
  187. static int ath5k_pci_resume(struct device *dev);
  188. static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
  189. #define ATH5K_PM_OPS (&ath5k_pm_ops)
  190. #else
  191. #define ATH5K_PM_OPS NULL
  192. #endif /* CONFIG_PM_SLEEP */
  193. static struct pci_driver ath5k_pci_driver = {
  194. .name = KBUILD_MODNAME,
  195. .id_table = ath5k_pci_id_table,
  196. .probe = ath5k_pci_probe,
  197. .remove = __devexit_p(ath5k_pci_remove),
  198. .driver.pm = ATH5K_PM_OPS,
  199. };
  200. /*
  201. * Prototypes - MAC 802.11 stack related functions
  202. */
  203. static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
  204. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  205. struct ath5k_txq *txq);
  206. static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
  207. static int ath5k_start(struct ieee80211_hw *hw);
  208. static void ath5k_stop(struct ieee80211_hw *hw);
  209. static int ath5k_add_interface(struct ieee80211_hw *hw,
  210. struct ieee80211_vif *vif);
  211. static void ath5k_remove_interface(struct ieee80211_hw *hw,
  212. struct ieee80211_vif *vif);
  213. static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
  214. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  215. struct netdev_hw_addr_list *mc_list);
  216. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  217. unsigned int changed_flags,
  218. unsigned int *new_flags,
  219. u64 multicast);
  220. static int ath5k_set_key(struct ieee80211_hw *hw,
  221. enum set_key_cmd cmd,
  222. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  223. struct ieee80211_key_conf *key);
  224. static int ath5k_get_stats(struct ieee80211_hw *hw,
  225. struct ieee80211_low_level_stats *stats);
  226. static int ath5k_get_survey(struct ieee80211_hw *hw,
  227. int idx, struct survey_info *survey);
  228. static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
  229. static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
  230. static void ath5k_reset_tsf(struct ieee80211_hw *hw);
  231. static int ath5k_beacon_update(struct ieee80211_hw *hw,
  232. struct ieee80211_vif *vif);
  233. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  234. struct ieee80211_vif *vif,
  235. struct ieee80211_bss_conf *bss_conf,
  236. u32 changes);
  237. static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
  238. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
  239. static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
  240. u8 coverage_class);
  241. static const struct ieee80211_ops ath5k_hw_ops = {
  242. .tx = ath5k_tx,
  243. .start = ath5k_start,
  244. .stop = ath5k_stop,
  245. .add_interface = ath5k_add_interface,
  246. .remove_interface = ath5k_remove_interface,
  247. .config = ath5k_config,
  248. .prepare_multicast = ath5k_prepare_multicast,
  249. .configure_filter = ath5k_configure_filter,
  250. .set_key = ath5k_set_key,
  251. .get_stats = ath5k_get_stats,
  252. .get_survey = ath5k_get_survey,
  253. .conf_tx = NULL,
  254. .get_tsf = ath5k_get_tsf,
  255. .set_tsf = ath5k_set_tsf,
  256. .reset_tsf = ath5k_reset_tsf,
  257. .bss_info_changed = ath5k_bss_info_changed,
  258. .sw_scan_start = ath5k_sw_scan_start,
  259. .sw_scan_complete = ath5k_sw_scan_complete,
  260. .set_coverage_class = ath5k_set_coverage_class,
  261. };
  262. /*
  263. * Prototypes - Internal functions
  264. */
  265. /* Attach detach */
  266. static int ath5k_attach(struct pci_dev *pdev,
  267. struct ieee80211_hw *hw);
  268. static void ath5k_detach(struct pci_dev *pdev,
  269. struct ieee80211_hw *hw);
  270. /* Channel/mode setup */
  271. static inline short ath5k_ieee2mhz(short chan);
  272. static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
  273. struct ieee80211_channel *channels,
  274. unsigned int mode,
  275. unsigned int max);
  276. static int ath5k_setup_bands(struct ieee80211_hw *hw);
  277. static int ath5k_chan_set(struct ath5k_softc *sc,
  278. struct ieee80211_channel *chan);
  279. static void ath5k_setcurmode(struct ath5k_softc *sc,
  280. unsigned int mode);
  281. static void ath5k_mode_setup(struct ath5k_softc *sc);
  282. /* Descriptor setup */
  283. static int ath5k_desc_alloc(struct ath5k_softc *sc,
  284. struct pci_dev *pdev);
  285. static void ath5k_desc_free(struct ath5k_softc *sc,
  286. struct pci_dev *pdev);
  287. /* Buffers setup */
  288. static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
  289. struct ath5k_buf *bf);
  290. static int ath5k_txbuf_setup(struct ath5k_softc *sc,
  291. struct ath5k_buf *bf,
  292. struct ath5k_txq *txq, int padsize);
  293. static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
  294. struct ath5k_buf *bf)
  295. {
  296. BUG_ON(!bf);
  297. if (!bf->skb)
  298. return;
  299. pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
  300. PCI_DMA_TODEVICE);
  301. dev_kfree_skb_any(bf->skb);
  302. bf->skb = NULL;
  303. bf->skbaddr = 0;
  304. bf->desc->ds_data = 0;
  305. }
  306. static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
  307. struct ath5k_buf *bf)
  308. {
  309. struct ath5k_hw *ah = sc->ah;
  310. struct ath_common *common = ath5k_hw_common(ah);
  311. BUG_ON(!bf);
  312. if (!bf->skb)
  313. return;
  314. pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
  315. PCI_DMA_FROMDEVICE);
  316. dev_kfree_skb_any(bf->skb);
  317. bf->skb = NULL;
  318. bf->skbaddr = 0;
  319. bf->desc->ds_data = 0;
  320. }
  321. /* Queues setup */
  322. static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
  323. int qtype, int subtype);
  324. static int ath5k_beaconq_setup(struct ath5k_hw *ah);
  325. static int ath5k_beaconq_config(struct ath5k_softc *sc);
  326. static void ath5k_txq_drainq(struct ath5k_softc *sc,
  327. struct ath5k_txq *txq);
  328. static void ath5k_txq_cleanup(struct ath5k_softc *sc);
  329. static void ath5k_txq_release(struct ath5k_softc *sc);
  330. /* Rx handling */
  331. static int ath5k_rx_start(struct ath5k_softc *sc);
  332. static void ath5k_rx_stop(struct ath5k_softc *sc);
  333. static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
  334. struct sk_buff *skb,
  335. struct ath5k_rx_status *rs);
  336. static void ath5k_tasklet_rx(unsigned long data);
  337. /* Tx handling */
  338. static void ath5k_tx_processq(struct ath5k_softc *sc,
  339. struct ath5k_txq *txq);
  340. static void ath5k_tasklet_tx(unsigned long data);
  341. /* Beacon handling */
  342. static int ath5k_beacon_setup(struct ath5k_softc *sc,
  343. struct ath5k_buf *bf);
  344. static void ath5k_beacon_send(struct ath5k_softc *sc);
  345. static void ath5k_beacon_config(struct ath5k_softc *sc);
  346. static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
  347. static void ath5k_tasklet_beacon(unsigned long data);
  348. static void ath5k_tasklet_ani(unsigned long data);
  349. static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
  350. {
  351. u64 tsf = ath5k_hw_get_tsf64(ah);
  352. if ((tsf & 0x7fff) < rstamp)
  353. tsf -= 0x8000;
  354. return (tsf & ~0x7fff) | rstamp;
  355. }
  356. /* Interrupt handling */
  357. static int ath5k_init(struct ath5k_softc *sc);
  358. static int ath5k_stop_locked(struct ath5k_softc *sc);
  359. static int ath5k_stop_hw(struct ath5k_softc *sc);
  360. static irqreturn_t ath5k_intr(int irq, void *dev_id);
  361. static void ath5k_reset_work(struct work_struct *work);
  362. static void ath5k_tasklet_calibrate(unsigned long data);
  363. /*
  364. * Module init/exit functions
  365. */
  366. static int __init
  367. init_ath5k_pci(void)
  368. {
  369. int ret;
  370. ath5k_debug_init();
  371. ret = pci_register_driver(&ath5k_pci_driver);
  372. if (ret) {
  373. printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
  374. return ret;
  375. }
  376. return 0;
  377. }
  378. static void __exit
  379. exit_ath5k_pci(void)
  380. {
  381. pci_unregister_driver(&ath5k_pci_driver);
  382. ath5k_debug_finish();
  383. }
  384. module_init(init_ath5k_pci);
  385. module_exit(exit_ath5k_pci);
  386. /********************\
  387. * PCI Initialization *
  388. \********************/
  389. static const char *
  390. ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
  391. {
  392. const char *name = "xxxxx";
  393. unsigned int i;
  394. for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
  395. if (srev_names[i].sr_type != type)
  396. continue;
  397. if ((val & 0xf0) == srev_names[i].sr_val)
  398. name = srev_names[i].sr_name;
  399. if ((val & 0xff) == srev_names[i].sr_val) {
  400. name = srev_names[i].sr_name;
  401. break;
  402. }
  403. }
  404. return name;
  405. }
  406. static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
  407. {
  408. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  409. return ath5k_hw_reg_read(ah, reg_offset);
  410. }
  411. static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
  412. {
  413. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  414. ath5k_hw_reg_write(ah, val, reg_offset);
  415. }
  416. static const struct ath_ops ath5k_common_ops = {
  417. .read = ath5k_ioread32,
  418. .write = ath5k_iowrite32,
  419. };
  420. static int __devinit
  421. ath5k_pci_probe(struct pci_dev *pdev,
  422. const struct pci_device_id *id)
  423. {
  424. void __iomem *mem;
  425. struct ath5k_softc *sc;
  426. struct ath_common *common;
  427. struct ieee80211_hw *hw;
  428. int ret;
  429. u8 csz;
  430. /*
  431. * L0s needs to be disabled on all ath5k cards.
  432. *
  433. * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
  434. * by default in the future in 2.6.36) this will also mean both L1 and
  435. * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
  436. * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
  437. * though but cannot currently undue the effect of a blacklist, for
  438. * details you can read pcie_aspm_sanity_check() and see how it adjusts
  439. * the device link capability.
  440. *
  441. * It may be possible in the future to implement some PCI API to allow
  442. * drivers to override blacklists for pre 1.1 PCIe but for now it is
  443. * best to accept that both L0s and L1 will be disabled completely for
  444. * distributions shipping with CONFIG_PCIEASPM rather than having this
  445. * issue present. Motivation for adding this new API will be to help
  446. * with power consumption for some of these devices.
  447. */
  448. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
  449. ret = pci_enable_device(pdev);
  450. if (ret) {
  451. dev_err(&pdev->dev, "can't enable device\n");
  452. goto err;
  453. }
  454. /* XXX 32-bit addressing only */
  455. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  456. if (ret) {
  457. dev_err(&pdev->dev, "32-bit DMA not available\n");
  458. goto err_dis;
  459. }
  460. /*
  461. * Cache line size is used to size and align various
  462. * structures used to communicate with the hardware.
  463. */
  464. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  465. if (csz == 0) {
  466. /*
  467. * Linux 2.4.18 (at least) writes the cache line size
  468. * register as a 16-bit wide register which is wrong.
  469. * We must have this setup properly for rx buffer
  470. * DMA to work so force a reasonable value here if it
  471. * comes up zero.
  472. */
  473. csz = L1_CACHE_BYTES >> 2;
  474. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  475. }
  476. /*
  477. * The default setting of latency timer yields poor results,
  478. * set it to the value used by other systems. It may be worth
  479. * tweaking this setting more.
  480. */
  481. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  482. /* Enable bus mastering */
  483. pci_set_master(pdev);
  484. /*
  485. * Disable the RETRY_TIMEOUT register (0x41) to keep
  486. * PCI Tx retries from interfering with C3 CPU state.
  487. */
  488. pci_write_config_byte(pdev, 0x41, 0);
  489. ret = pci_request_region(pdev, 0, "ath5k");
  490. if (ret) {
  491. dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
  492. goto err_dis;
  493. }
  494. mem = pci_iomap(pdev, 0, 0);
  495. if (!mem) {
  496. dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
  497. ret = -EIO;
  498. goto err_reg;
  499. }
  500. /*
  501. * Allocate hw (mac80211 main struct)
  502. * and hw->priv (driver private data)
  503. */
  504. hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
  505. if (hw == NULL) {
  506. dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
  507. ret = -ENOMEM;
  508. goto err_map;
  509. }
  510. dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
  511. /* Initialize driver private data */
  512. SET_IEEE80211_DEV(hw, &pdev->dev);
  513. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  514. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  515. IEEE80211_HW_SIGNAL_DBM;
  516. hw->wiphy->interface_modes =
  517. BIT(NL80211_IFTYPE_AP) |
  518. BIT(NL80211_IFTYPE_STATION) |
  519. BIT(NL80211_IFTYPE_ADHOC) |
  520. BIT(NL80211_IFTYPE_MESH_POINT);
  521. hw->extra_tx_headroom = 2;
  522. hw->channel_change_time = 5000;
  523. sc = hw->priv;
  524. sc->hw = hw;
  525. sc->pdev = pdev;
  526. ath5k_debug_init_device(sc);
  527. /*
  528. * Mark the device as detached to avoid processing
  529. * interrupts until setup is complete.
  530. */
  531. __set_bit(ATH_STAT_INVALID, sc->status);
  532. sc->iobase = mem; /* So we can unmap it on detach */
  533. sc->opmode = NL80211_IFTYPE_STATION;
  534. sc->bintval = 1000;
  535. mutex_init(&sc->lock);
  536. spin_lock_init(&sc->rxbuflock);
  537. spin_lock_init(&sc->txbuflock);
  538. spin_lock_init(&sc->block);
  539. /* Set private data */
  540. pci_set_drvdata(pdev, sc);
  541. /* Setup interrupt handler */
  542. ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
  543. if (ret) {
  544. ATH5K_ERR(sc, "request_irq failed\n");
  545. goto err_free;
  546. }
  547. /*If we passed the test malloc a ath5k_hw struct*/
  548. sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
  549. if (!sc->ah) {
  550. ret = -ENOMEM;
  551. ATH5K_ERR(sc, "out of memory\n");
  552. goto err_irq;
  553. }
  554. sc->ah->ah_sc = sc;
  555. sc->ah->ah_iobase = sc->iobase;
  556. common = ath5k_hw_common(sc->ah);
  557. common->ops = &ath5k_common_ops;
  558. common->ah = sc->ah;
  559. common->hw = hw;
  560. common->cachelsz = csz << 2; /* convert to bytes */
  561. /* Initialize device */
  562. ret = ath5k_hw_attach(sc);
  563. if (ret) {
  564. goto err_free_ah;
  565. }
  566. /* set up multi-rate retry capabilities */
  567. if (sc->ah->ah_version == AR5K_AR5212) {
  568. hw->max_rates = 4;
  569. hw->max_rate_tries = 11;
  570. }
  571. /* Finish private driver data initialization */
  572. ret = ath5k_attach(pdev, hw);
  573. if (ret)
  574. goto err_ah;
  575. ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
  576. ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
  577. sc->ah->ah_mac_srev,
  578. sc->ah->ah_phy_revision);
  579. if (!sc->ah->ah_single_chip) {
  580. /* Single chip radio (!RF5111) */
  581. if (sc->ah->ah_radio_5ghz_revision &&
  582. !sc->ah->ah_radio_2ghz_revision) {
  583. /* No 5GHz support -> report 2GHz radio */
  584. if (!test_bit(AR5K_MODE_11A,
  585. sc->ah->ah_capabilities.cap_mode)) {
  586. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  587. ath5k_chip_name(AR5K_VERSION_RAD,
  588. sc->ah->ah_radio_5ghz_revision),
  589. sc->ah->ah_radio_5ghz_revision);
  590. /* No 2GHz support (5110 and some
  591. * 5Ghz only cards) -> report 5Ghz radio */
  592. } else if (!test_bit(AR5K_MODE_11B,
  593. sc->ah->ah_capabilities.cap_mode)) {
  594. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  595. ath5k_chip_name(AR5K_VERSION_RAD,
  596. sc->ah->ah_radio_5ghz_revision),
  597. sc->ah->ah_radio_5ghz_revision);
  598. /* Multiband radio */
  599. } else {
  600. ATH5K_INFO(sc, "RF%s multiband radio found"
  601. " (0x%x)\n",
  602. ath5k_chip_name(AR5K_VERSION_RAD,
  603. sc->ah->ah_radio_5ghz_revision),
  604. sc->ah->ah_radio_5ghz_revision);
  605. }
  606. }
  607. /* Multi chip radio (RF5111 - RF2111) ->
  608. * report both 2GHz/5GHz radios */
  609. else if (sc->ah->ah_radio_5ghz_revision &&
  610. sc->ah->ah_radio_2ghz_revision){
  611. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  612. ath5k_chip_name(AR5K_VERSION_RAD,
  613. sc->ah->ah_radio_5ghz_revision),
  614. sc->ah->ah_radio_5ghz_revision);
  615. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  616. ath5k_chip_name(AR5K_VERSION_RAD,
  617. sc->ah->ah_radio_2ghz_revision),
  618. sc->ah->ah_radio_2ghz_revision);
  619. }
  620. }
  621. /* ready to process interrupts */
  622. __clear_bit(ATH_STAT_INVALID, sc->status);
  623. return 0;
  624. err_ah:
  625. ath5k_hw_detach(sc->ah);
  626. err_irq:
  627. free_irq(pdev->irq, sc);
  628. err_free_ah:
  629. kfree(sc->ah);
  630. err_free:
  631. ieee80211_free_hw(hw);
  632. err_map:
  633. pci_iounmap(pdev, mem);
  634. err_reg:
  635. pci_release_region(pdev, 0);
  636. err_dis:
  637. pci_disable_device(pdev);
  638. err:
  639. return ret;
  640. }
  641. static void __devexit
  642. ath5k_pci_remove(struct pci_dev *pdev)
  643. {
  644. struct ath5k_softc *sc = pci_get_drvdata(pdev);
  645. ath5k_debug_finish_device(sc);
  646. ath5k_detach(pdev, sc->hw);
  647. ath5k_hw_detach(sc->ah);
  648. kfree(sc->ah);
  649. free_irq(pdev->irq, sc);
  650. pci_iounmap(pdev, sc->iobase);
  651. pci_release_region(pdev, 0);
  652. pci_disable_device(pdev);
  653. ieee80211_free_hw(sc->hw);
  654. }
  655. #ifdef CONFIG_PM_SLEEP
  656. static int ath5k_pci_suspend(struct device *dev)
  657. {
  658. struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
  659. ath5k_led_off(sc);
  660. return 0;
  661. }
  662. static int ath5k_pci_resume(struct device *dev)
  663. {
  664. struct pci_dev *pdev = to_pci_dev(dev);
  665. struct ath5k_softc *sc = pci_get_drvdata(pdev);
  666. /*
  667. * Suspend/Resume resets the PCI configuration space, so we have to
  668. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  669. * PCI Tx retries from interfering with C3 CPU state
  670. */
  671. pci_write_config_byte(pdev, 0x41, 0);
  672. ath5k_led_enable(sc);
  673. return 0;
  674. }
  675. #endif /* CONFIG_PM_SLEEP */
  676. /***********************\
  677. * Driver Initialization *
  678. \***********************/
  679. static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
  680. {
  681. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  682. struct ath5k_softc *sc = hw->priv;
  683. struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
  684. return ath_reg_notifier_apply(wiphy, request, regulatory);
  685. }
  686. static int
  687. ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  688. {
  689. struct ath5k_softc *sc = hw->priv;
  690. struct ath5k_hw *ah = sc->ah;
  691. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  692. u8 mac[ETH_ALEN] = {};
  693. int ret;
  694. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
  695. /*
  696. * Check if the MAC has multi-rate retry support.
  697. * We do this by trying to setup a fake extended
  698. * descriptor. MAC's that don't have support will
  699. * return false w/o doing anything. MAC's that do
  700. * support it will return true w/o doing anything.
  701. */
  702. ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
  703. if (ret < 0)
  704. goto err;
  705. if (ret > 0)
  706. __set_bit(ATH_STAT_MRRETRY, sc->status);
  707. /*
  708. * Collect the channel list. The 802.11 layer
  709. * is resposible for filtering this list based
  710. * on settings like the phy mode and regulatory
  711. * domain restrictions.
  712. */
  713. ret = ath5k_setup_bands(hw);
  714. if (ret) {
  715. ATH5K_ERR(sc, "can't get channels\n");
  716. goto err;
  717. }
  718. /* NB: setup here so ath5k_rate_update is happy */
  719. if (test_bit(AR5K_MODE_11A, ah->ah_modes))
  720. ath5k_setcurmode(sc, AR5K_MODE_11A);
  721. else
  722. ath5k_setcurmode(sc, AR5K_MODE_11B);
  723. /*
  724. * Allocate tx+rx descriptors and populate the lists.
  725. */
  726. ret = ath5k_desc_alloc(sc, pdev);
  727. if (ret) {
  728. ATH5K_ERR(sc, "can't allocate descriptors\n");
  729. goto err;
  730. }
  731. /*
  732. * Allocate hardware transmit queues: one queue for
  733. * beacon frames and one data queue for each QoS
  734. * priority. Note that hw functions handle reseting
  735. * these queues at the needed time.
  736. */
  737. ret = ath5k_beaconq_setup(ah);
  738. if (ret < 0) {
  739. ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
  740. goto err_desc;
  741. }
  742. sc->bhalq = ret;
  743. sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
  744. if (IS_ERR(sc->cabq)) {
  745. ATH5K_ERR(sc, "can't setup cab queue\n");
  746. ret = PTR_ERR(sc->cabq);
  747. goto err_bhal;
  748. }
  749. sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
  750. if (IS_ERR(sc->txq)) {
  751. ATH5K_ERR(sc, "can't setup xmit queue\n");
  752. ret = PTR_ERR(sc->txq);
  753. goto err_queues;
  754. }
  755. tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
  756. tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
  757. tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
  758. tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
  759. tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
  760. INIT_WORK(&sc->reset_work, ath5k_reset_work);
  761. ret = ath5k_eeprom_read_mac(ah, mac);
  762. if (ret) {
  763. ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
  764. sc->pdev->device);
  765. goto err_queues;
  766. }
  767. SET_IEEE80211_PERM_ADDR(hw, mac);
  768. /* All MAC address bits matter for ACKs */
  769. memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
  770. ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
  771. regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
  772. ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
  773. if (ret) {
  774. ATH5K_ERR(sc, "can't initialize regulatory system\n");
  775. goto err_queues;
  776. }
  777. ret = ieee80211_register_hw(hw);
  778. if (ret) {
  779. ATH5K_ERR(sc, "can't register ieee80211 hw\n");
  780. goto err_queues;
  781. }
  782. if (!ath_is_world_regd(regulatory))
  783. regulatory_hint(hw->wiphy, regulatory->alpha2);
  784. ath5k_init_leds(sc);
  785. ath5k_sysfs_register(sc);
  786. return 0;
  787. err_queues:
  788. ath5k_txq_release(sc);
  789. err_bhal:
  790. ath5k_hw_release_tx_queue(ah, sc->bhalq);
  791. err_desc:
  792. ath5k_desc_free(sc, pdev);
  793. err:
  794. return ret;
  795. }
  796. static void
  797. ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  798. {
  799. struct ath5k_softc *sc = hw->priv;
  800. /*
  801. * NB: the order of these is important:
  802. * o call the 802.11 layer before detaching ath5k_hw to
  803. * insure callbacks into the driver to delete global
  804. * key cache entries can be handled
  805. * o reclaim the tx queue data structures after calling
  806. * the 802.11 layer as we'll get called back to reclaim
  807. * node state and potentially want to use them
  808. * o to cleanup the tx queues the hal is called, so detach
  809. * it last
  810. * XXX: ??? detach ath5k_hw ???
  811. * Other than that, it's straightforward...
  812. */
  813. ieee80211_unregister_hw(hw);
  814. ath5k_desc_free(sc, pdev);
  815. ath5k_txq_release(sc);
  816. ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
  817. ath5k_unregister_leds(sc);
  818. ath5k_sysfs_unregister(sc);
  819. /*
  820. * NB: can't reclaim these until after ieee80211_ifdetach
  821. * returns because we'll get called back to reclaim node
  822. * state and potentially want to use them.
  823. */
  824. }
  825. /********************\
  826. * Channel/mode setup *
  827. \********************/
  828. /*
  829. * Convert IEEE channel number to MHz frequency.
  830. */
  831. static inline short
  832. ath5k_ieee2mhz(short chan)
  833. {
  834. if (chan <= 14 || chan >= 27)
  835. return ieee80211chan2mhz(chan);
  836. else
  837. return 2212 + chan * 20;
  838. }
  839. /*
  840. * Returns true for the channel numbers used without all_channels modparam.
  841. */
  842. static bool ath5k_is_standard_channel(short chan)
  843. {
  844. return ((chan <= 14) ||
  845. /* UNII 1,2 */
  846. ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
  847. /* midband */
  848. ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
  849. /* UNII-3 */
  850. ((chan & 3) == 1 && chan >= 149 && chan <= 165));
  851. }
  852. static unsigned int
  853. ath5k_copy_channels(struct ath5k_hw *ah,
  854. struct ieee80211_channel *channels,
  855. unsigned int mode,
  856. unsigned int max)
  857. {
  858. unsigned int i, count, size, chfreq, freq, ch;
  859. if (!test_bit(mode, ah->ah_modes))
  860. return 0;
  861. switch (mode) {
  862. case AR5K_MODE_11A:
  863. case AR5K_MODE_11A_TURBO:
  864. /* 1..220, but 2GHz frequencies are filtered by check_channel */
  865. size = 220 ;
  866. chfreq = CHANNEL_5GHZ;
  867. break;
  868. case AR5K_MODE_11B:
  869. case AR5K_MODE_11G:
  870. case AR5K_MODE_11G_TURBO:
  871. size = 26;
  872. chfreq = CHANNEL_2GHZ;
  873. break;
  874. default:
  875. ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
  876. return 0;
  877. }
  878. for (i = 0, count = 0; i < size && max > 0; i++) {
  879. ch = i + 1 ;
  880. freq = ath5k_ieee2mhz(ch);
  881. /* Check if channel is supported by the chipset */
  882. if (!ath5k_channel_ok(ah, freq, chfreq))
  883. continue;
  884. if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
  885. continue;
  886. /* Write channel info and increment counter */
  887. channels[count].center_freq = freq;
  888. channels[count].band = (chfreq == CHANNEL_2GHZ) ?
  889. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  890. switch (mode) {
  891. case AR5K_MODE_11A:
  892. case AR5K_MODE_11G:
  893. channels[count].hw_value = chfreq | CHANNEL_OFDM;
  894. break;
  895. case AR5K_MODE_11A_TURBO:
  896. case AR5K_MODE_11G_TURBO:
  897. channels[count].hw_value = chfreq |
  898. CHANNEL_OFDM | CHANNEL_TURBO;
  899. break;
  900. case AR5K_MODE_11B:
  901. channels[count].hw_value = CHANNEL_B;
  902. }
  903. count++;
  904. max--;
  905. }
  906. return count;
  907. }
  908. static void
  909. ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
  910. {
  911. u8 i;
  912. for (i = 0; i < AR5K_MAX_RATES; i++)
  913. sc->rate_idx[b->band][i] = -1;
  914. for (i = 0; i < b->n_bitrates; i++) {
  915. sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
  916. if (b->bitrates[i].hw_value_short)
  917. sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
  918. }
  919. }
  920. static int
  921. ath5k_setup_bands(struct ieee80211_hw *hw)
  922. {
  923. struct ath5k_softc *sc = hw->priv;
  924. struct ath5k_hw *ah = sc->ah;
  925. struct ieee80211_supported_band *sband;
  926. int max_c, count_c = 0;
  927. int i;
  928. BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
  929. max_c = ARRAY_SIZE(sc->channels);
  930. /* 2GHz band */
  931. sband = &sc->sbands[IEEE80211_BAND_2GHZ];
  932. sband->band = IEEE80211_BAND_2GHZ;
  933. sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
  934. if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
  935. /* G mode */
  936. memcpy(sband->bitrates, &ath5k_rates[0],
  937. sizeof(struct ieee80211_rate) * 12);
  938. sband->n_bitrates = 12;
  939. sband->channels = sc->channels;
  940. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  941. AR5K_MODE_11G, max_c);
  942. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  943. count_c = sband->n_channels;
  944. max_c -= count_c;
  945. } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
  946. /* B mode */
  947. memcpy(sband->bitrates, &ath5k_rates[0],
  948. sizeof(struct ieee80211_rate) * 4);
  949. sband->n_bitrates = 4;
  950. /* 5211 only supports B rates and uses 4bit rate codes
  951. * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
  952. * fix them up here:
  953. */
  954. if (ah->ah_version == AR5K_AR5211) {
  955. for (i = 0; i < 4; i++) {
  956. sband->bitrates[i].hw_value =
  957. sband->bitrates[i].hw_value & 0xF;
  958. sband->bitrates[i].hw_value_short =
  959. sband->bitrates[i].hw_value_short & 0xF;
  960. }
  961. }
  962. sband->channels = sc->channels;
  963. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  964. AR5K_MODE_11B, max_c);
  965. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  966. count_c = sband->n_channels;
  967. max_c -= count_c;
  968. }
  969. ath5k_setup_rate_idx(sc, sband);
  970. /* 5GHz band, A mode */
  971. if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
  972. sband = &sc->sbands[IEEE80211_BAND_5GHZ];
  973. sband->band = IEEE80211_BAND_5GHZ;
  974. sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
  975. memcpy(sband->bitrates, &ath5k_rates[4],
  976. sizeof(struct ieee80211_rate) * 8);
  977. sband->n_bitrates = 8;
  978. sband->channels = &sc->channels[count_c];
  979. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  980. AR5K_MODE_11A, max_c);
  981. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
  982. }
  983. ath5k_setup_rate_idx(sc, sband);
  984. ath5k_debug_dump_bands(sc);
  985. return 0;
  986. }
  987. /*
  988. * Set/change channels. We always reset the chip.
  989. * To accomplish this we must first cleanup any pending DMA,
  990. * then restart stuff after a la ath5k_init.
  991. *
  992. * Called with sc->lock.
  993. */
  994. static int
  995. ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  996. {
  997. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  998. "channel set, resetting (%u -> %u MHz)\n",
  999. sc->curchan->center_freq, chan->center_freq);
  1000. /*
  1001. * To switch channels clear any pending DMA operations;
  1002. * wait long enough for the RX fifo to drain, reset the
  1003. * hardware at the new frequency, and then re-enable
  1004. * the relevant bits of the h/w.
  1005. */
  1006. return ath5k_reset(sc, chan);
  1007. }
  1008. static void
  1009. ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
  1010. {
  1011. sc->curmode = mode;
  1012. if (mode == AR5K_MODE_11A) {
  1013. sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
  1014. } else {
  1015. sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
  1016. }
  1017. }
  1018. static void
  1019. ath5k_mode_setup(struct ath5k_softc *sc)
  1020. {
  1021. struct ath5k_hw *ah = sc->ah;
  1022. u32 rfilt;
  1023. /* configure rx filter */
  1024. rfilt = sc->filter_flags;
  1025. ath5k_hw_set_rx_filter(ah, rfilt);
  1026. if (ath5k_hw_hasbssidmask(ah))
  1027. ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
  1028. /* configure operational mode */
  1029. ath5k_hw_set_opmode(ah, sc->opmode);
  1030. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
  1031. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
  1032. }
  1033. static inline int
  1034. ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
  1035. {
  1036. int rix;
  1037. /* return base rate on errors */
  1038. if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
  1039. "hw_rix out of bounds: %x\n", hw_rix))
  1040. return 0;
  1041. rix = sc->rate_idx[sc->curband->band][hw_rix];
  1042. if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
  1043. rix = 0;
  1044. return rix;
  1045. }
  1046. /***************\
  1047. * Buffers setup *
  1048. \***************/
  1049. static
  1050. struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
  1051. {
  1052. struct ath_common *common = ath5k_hw_common(sc->ah);
  1053. struct sk_buff *skb;
  1054. /*
  1055. * Allocate buffer with headroom_needed space for the
  1056. * fake physical layer header at the start.
  1057. */
  1058. skb = ath_rxbuf_alloc(common,
  1059. common->rx_bufsize,
  1060. GFP_ATOMIC);
  1061. if (!skb) {
  1062. ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
  1063. common->rx_bufsize);
  1064. return NULL;
  1065. }
  1066. *skb_addr = pci_map_single(sc->pdev,
  1067. skb->data, common->rx_bufsize,
  1068. PCI_DMA_FROMDEVICE);
  1069. if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
  1070. ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
  1071. dev_kfree_skb(skb);
  1072. return NULL;
  1073. }
  1074. return skb;
  1075. }
  1076. static int
  1077. ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1078. {
  1079. struct ath5k_hw *ah = sc->ah;
  1080. struct sk_buff *skb = bf->skb;
  1081. struct ath5k_desc *ds;
  1082. int ret;
  1083. if (!skb) {
  1084. skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
  1085. if (!skb)
  1086. return -ENOMEM;
  1087. bf->skb = skb;
  1088. }
  1089. /*
  1090. * Setup descriptors. For receive we always terminate
  1091. * the descriptor list with a self-linked entry so we'll
  1092. * not get overrun under high load (as can happen with a
  1093. * 5212 when ANI processing enables PHY error frames).
  1094. *
  1095. * To ensure the last descriptor is self-linked we create
  1096. * each descriptor as self-linked and add it to the end. As
  1097. * each additional descriptor is added the previous self-linked
  1098. * entry is "fixed" naturally. This should be safe even
  1099. * if DMA is happening. When processing RX interrupts we
  1100. * never remove/process the last, self-linked, entry on the
  1101. * descriptor list. This ensures the hardware always has
  1102. * someplace to write a new frame.
  1103. */
  1104. ds = bf->desc;
  1105. ds->ds_link = bf->daddr; /* link to self */
  1106. ds->ds_data = bf->skbaddr;
  1107. ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
  1108. if (ret) {
  1109. ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
  1110. return ret;
  1111. }
  1112. if (sc->rxlink != NULL)
  1113. *sc->rxlink = bf->daddr;
  1114. sc->rxlink = &ds->ds_link;
  1115. return 0;
  1116. }
  1117. static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  1118. {
  1119. struct ieee80211_hdr *hdr;
  1120. enum ath5k_pkt_type htype;
  1121. __le16 fc;
  1122. hdr = (struct ieee80211_hdr *)skb->data;
  1123. fc = hdr->frame_control;
  1124. if (ieee80211_is_beacon(fc))
  1125. htype = AR5K_PKT_TYPE_BEACON;
  1126. else if (ieee80211_is_probe_resp(fc))
  1127. htype = AR5K_PKT_TYPE_PROBE_RESP;
  1128. else if (ieee80211_is_atim(fc))
  1129. htype = AR5K_PKT_TYPE_ATIM;
  1130. else if (ieee80211_is_pspoll(fc))
  1131. htype = AR5K_PKT_TYPE_PSPOLL;
  1132. else
  1133. htype = AR5K_PKT_TYPE_NORMAL;
  1134. return htype;
  1135. }
  1136. static int
  1137. ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
  1138. struct ath5k_txq *txq, int padsize)
  1139. {
  1140. struct ath5k_hw *ah = sc->ah;
  1141. struct ath5k_desc *ds = bf->desc;
  1142. struct sk_buff *skb = bf->skb;
  1143. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1144. unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
  1145. struct ieee80211_rate *rate;
  1146. unsigned int mrr_rate[3], mrr_tries[3];
  1147. int i, ret;
  1148. u16 hw_rate;
  1149. u16 cts_rate = 0;
  1150. u16 duration = 0;
  1151. u8 rc_flags;
  1152. flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
  1153. /* XXX endianness */
  1154. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1155. PCI_DMA_TODEVICE);
  1156. rate = ieee80211_get_tx_rate(sc->hw, info);
  1157. if (!rate) {
  1158. ret = -EINVAL;
  1159. goto err_unmap;
  1160. }
  1161. if (info->flags & IEEE80211_TX_CTL_NO_ACK)
  1162. flags |= AR5K_TXDESC_NOACK;
  1163. rc_flags = info->control.rates[0].flags;
  1164. hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
  1165. rate->hw_value_short : rate->hw_value;
  1166. pktlen = skb->len;
  1167. /* FIXME: If we are in g mode and rate is a CCK rate
  1168. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1169. * from tx power (value is in dB units already) */
  1170. if (info->control.hw_key) {
  1171. keyidx = info->control.hw_key->hw_key_idx;
  1172. pktlen += info->control.hw_key->icv_len;
  1173. }
  1174. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1175. flags |= AR5K_TXDESC_RTSENA;
  1176. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1177. duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
  1178. sc->vif, pktlen, info));
  1179. }
  1180. if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1181. flags |= AR5K_TXDESC_CTSENA;
  1182. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1183. duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
  1184. sc->vif, pktlen, info));
  1185. }
  1186. ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
  1187. ieee80211_get_hdrlen_from_skb(skb), padsize,
  1188. get_hw_packet_type(skb),
  1189. (sc->power_level * 2),
  1190. hw_rate,
  1191. info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
  1192. cts_rate, duration);
  1193. if (ret)
  1194. goto err_unmap;
  1195. memset(mrr_rate, 0, sizeof(mrr_rate));
  1196. memset(mrr_tries, 0, sizeof(mrr_tries));
  1197. for (i = 0; i < 3; i++) {
  1198. rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
  1199. if (!rate)
  1200. break;
  1201. mrr_rate[i] = rate->hw_value;
  1202. mrr_tries[i] = info->control.rates[i + 1].count;
  1203. }
  1204. ath5k_hw_setup_mrr_tx_desc(ah, ds,
  1205. mrr_rate[0], mrr_tries[0],
  1206. mrr_rate[1], mrr_tries[1],
  1207. mrr_rate[2], mrr_tries[2]);
  1208. ds->ds_link = 0;
  1209. ds->ds_data = bf->skbaddr;
  1210. spin_lock_bh(&txq->lock);
  1211. list_add_tail(&bf->list, &txq->q);
  1212. if (txq->link == NULL) /* is this first packet? */
  1213. ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
  1214. else /* no, so only link it */
  1215. *txq->link = bf->daddr;
  1216. txq->link = &ds->ds_link;
  1217. ath5k_hw_start_tx_dma(ah, txq->qnum);
  1218. mmiowb();
  1219. spin_unlock_bh(&txq->lock);
  1220. return 0;
  1221. err_unmap:
  1222. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1223. return ret;
  1224. }
  1225. /*******************\
  1226. * Descriptors setup *
  1227. \*******************/
  1228. static int
  1229. ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
  1230. {
  1231. struct ath5k_desc *ds;
  1232. struct ath5k_buf *bf;
  1233. dma_addr_t da;
  1234. unsigned int i;
  1235. int ret;
  1236. /* allocate descriptors */
  1237. sc->desc_len = sizeof(struct ath5k_desc) *
  1238. (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
  1239. sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
  1240. if (sc->desc == NULL) {
  1241. ATH5K_ERR(sc, "can't allocate descriptors\n");
  1242. ret = -ENOMEM;
  1243. goto err;
  1244. }
  1245. ds = sc->desc;
  1246. da = sc->desc_daddr;
  1247. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
  1248. ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
  1249. bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
  1250. sizeof(struct ath5k_buf), GFP_KERNEL);
  1251. if (bf == NULL) {
  1252. ATH5K_ERR(sc, "can't allocate bufptr\n");
  1253. ret = -ENOMEM;
  1254. goto err_free;
  1255. }
  1256. sc->bufptr = bf;
  1257. INIT_LIST_HEAD(&sc->rxbuf);
  1258. for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  1259. bf->desc = ds;
  1260. bf->daddr = da;
  1261. list_add_tail(&bf->list, &sc->rxbuf);
  1262. }
  1263. INIT_LIST_HEAD(&sc->txbuf);
  1264. sc->txbuf_len = ATH_TXBUF;
  1265. for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
  1266. da += sizeof(*ds)) {
  1267. bf->desc = ds;
  1268. bf->daddr = da;
  1269. list_add_tail(&bf->list, &sc->txbuf);
  1270. }
  1271. /* beacon buffer */
  1272. bf->desc = ds;
  1273. bf->daddr = da;
  1274. sc->bbuf = bf;
  1275. return 0;
  1276. err_free:
  1277. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1278. err:
  1279. sc->desc = NULL;
  1280. return ret;
  1281. }
  1282. static void
  1283. ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
  1284. {
  1285. struct ath5k_buf *bf;
  1286. ath5k_txbuf_free_skb(sc, sc->bbuf);
  1287. list_for_each_entry(bf, &sc->txbuf, list)
  1288. ath5k_txbuf_free_skb(sc, bf);
  1289. list_for_each_entry(bf, &sc->rxbuf, list)
  1290. ath5k_rxbuf_free_skb(sc, bf);
  1291. /* Free memory associated with all descriptors */
  1292. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1293. sc->desc = NULL;
  1294. sc->desc_daddr = 0;
  1295. kfree(sc->bufptr);
  1296. sc->bufptr = NULL;
  1297. sc->bbuf = NULL;
  1298. }
  1299. /**************\
  1300. * Queues setup *
  1301. \**************/
  1302. static struct ath5k_txq *
  1303. ath5k_txq_setup(struct ath5k_softc *sc,
  1304. int qtype, int subtype)
  1305. {
  1306. struct ath5k_hw *ah = sc->ah;
  1307. struct ath5k_txq *txq;
  1308. struct ath5k_txq_info qi = {
  1309. .tqi_subtype = subtype,
  1310. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1311. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1312. .tqi_cw_max = AR5K_TXQ_USEDEFAULT
  1313. };
  1314. int qnum;
  1315. /*
  1316. * Enable interrupts only for EOL and DESC conditions.
  1317. * We mark tx descriptors to receive a DESC interrupt
  1318. * when a tx queue gets deep; otherwise waiting for the
  1319. * EOL to reap descriptors. Note that this is done to
  1320. * reduce interrupt load and this only defers reaping
  1321. * descriptors, never transmitting frames. Aside from
  1322. * reducing interrupts this also permits more concurrency.
  1323. * The only potential downside is if the tx queue backs
  1324. * up in which case the top half of the kernel may backup
  1325. * due to a lack of tx descriptors.
  1326. */
  1327. qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
  1328. AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
  1329. qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
  1330. if (qnum < 0) {
  1331. /*
  1332. * NB: don't print a message, this happens
  1333. * normally on parts with too few tx queues
  1334. */
  1335. return ERR_PTR(qnum);
  1336. }
  1337. if (qnum >= ARRAY_SIZE(sc->txqs)) {
  1338. ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
  1339. qnum, ARRAY_SIZE(sc->txqs));
  1340. ath5k_hw_release_tx_queue(ah, qnum);
  1341. return ERR_PTR(-EINVAL);
  1342. }
  1343. txq = &sc->txqs[qnum];
  1344. if (!txq->setup) {
  1345. txq->qnum = qnum;
  1346. txq->link = NULL;
  1347. INIT_LIST_HEAD(&txq->q);
  1348. spin_lock_init(&txq->lock);
  1349. txq->setup = true;
  1350. }
  1351. return &sc->txqs[qnum];
  1352. }
  1353. static int
  1354. ath5k_beaconq_setup(struct ath5k_hw *ah)
  1355. {
  1356. struct ath5k_txq_info qi = {
  1357. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1358. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1359. .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
  1360. /* NB: for dynamic turbo, don't enable any other interrupts */
  1361. .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
  1362. };
  1363. return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
  1364. }
  1365. static int
  1366. ath5k_beaconq_config(struct ath5k_softc *sc)
  1367. {
  1368. struct ath5k_hw *ah = sc->ah;
  1369. struct ath5k_txq_info qi;
  1370. int ret;
  1371. ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
  1372. if (ret)
  1373. goto err;
  1374. if (sc->opmode == NL80211_IFTYPE_AP ||
  1375. sc->opmode == NL80211_IFTYPE_MESH_POINT) {
  1376. /*
  1377. * Always burst out beacon and CAB traffic
  1378. * (aifs = cwmin = cwmax = 0)
  1379. */
  1380. qi.tqi_aifs = 0;
  1381. qi.tqi_cw_min = 0;
  1382. qi.tqi_cw_max = 0;
  1383. } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  1384. /*
  1385. * Adhoc mode; backoff between 0 and (2 * cw_min).
  1386. */
  1387. qi.tqi_aifs = 0;
  1388. qi.tqi_cw_min = 0;
  1389. qi.tqi_cw_max = 2 * ah->ah_cw_min;
  1390. }
  1391. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1392. "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
  1393. qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
  1394. ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
  1395. if (ret) {
  1396. ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
  1397. "hardware queue!\n", __func__);
  1398. goto err;
  1399. }
  1400. ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
  1401. if (ret)
  1402. goto err;
  1403. /* reconfigure cabq with ready time to 80% of beacon_interval */
  1404. ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  1405. if (ret)
  1406. goto err;
  1407. qi.tqi_ready_time = (sc->bintval * 80) / 100;
  1408. ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  1409. if (ret)
  1410. goto err;
  1411. ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
  1412. err:
  1413. return ret;
  1414. }
  1415. static void
  1416. ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1417. {
  1418. struct ath5k_buf *bf, *bf0;
  1419. /*
  1420. * NB: this assumes output has been stopped and
  1421. * we do not need to block ath5k_tx_tasklet
  1422. */
  1423. spin_lock_bh(&txq->lock);
  1424. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1425. ath5k_debug_printtxbuf(sc, bf);
  1426. ath5k_txbuf_free_skb(sc, bf);
  1427. spin_lock_bh(&sc->txbuflock);
  1428. list_move_tail(&bf->list, &sc->txbuf);
  1429. sc->txbuf_len++;
  1430. spin_unlock_bh(&sc->txbuflock);
  1431. }
  1432. txq->link = NULL;
  1433. spin_unlock_bh(&txq->lock);
  1434. }
  1435. /*
  1436. * Drain the transmit queues and reclaim resources.
  1437. */
  1438. static void
  1439. ath5k_txq_cleanup(struct ath5k_softc *sc)
  1440. {
  1441. struct ath5k_hw *ah = sc->ah;
  1442. unsigned int i;
  1443. /* XXX return value */
  1444. if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
  1445. /* don't touch the hardware if marked invalid */
  1446. ath5k_hw_stop_tx_dma(ah, sc->bhalq);
  1447. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
  1448. ath5k_hw_get_txdp(ah, sc->bhalq));
  1449. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1450. if (sc->txqs[i].setup) {
  1451. ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
  1452. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
  1453. "link %p\n",
  1454. sc->txqs[i].qnum,
  1455. ath5k_hw_get_txdp(ah,
  1456. sc->txqs[i].qnum),
  1457. sc->txqs[i].link);
  1458. }
  1459. }
  1460. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1461. if (sc->txqs[i].setup)
  1462. ath5k_txq_drainq(sc, &sc->txqs[i]);
  1463. }
  1464. static void
  1465. ath5k_txq_release(struct ath5k_softc *sc)
  1466. {
  1467. struct ath5k_txq *txq = sc->txqs;
  1468. unsigned int i;
  1469. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
  1470. if (txq->setup) {
  1471. ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
  1472. txq->setup = false;
  1473. }
  1474. }
  1475. /*************\
  1476. * RX Handling *
  1477. \*************/
  1478. /*
  1479. * Enable the receive h/w following a reset.
  1480. */
  1481. static int
  1482. ath5k_rx_start(struct ath5k_softc *sc)
  1483. {
  1484. struct ath5k_hw *ah = sc->ah;
  1485. struct ath_common *common = ath5k_hw_common(ah);
  1486. struct ath5k_buf *bf;
  1487. int ret;
  1488. common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
  1489. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
  1490. common->cachelsz, common->rx_bufsize);
  1491. spin_lock_bh(&sc->rxbuflock);
  1492. sc->rxlink = NULL;
  1493. list_for_each_entry(bf, &sc->rxbuf, list) {
  1494. ret = ath5k_rxbuf_setup(sc, bf);
  1495. if (ret != 0) {
  1496. spin_unlock_bh(&sc->rxbuflock);
  1497. goto err;
  1498. }
  1499. }
  1500. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1501. ath5k_hw_set_rxdp(ah, bf->daddr);
  1502. spin_unlock_bh(&sc->rxbuflock);
  1503. ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
  1504. ath5k_mode_setup(sc); /* set filters, etc. */
  1505. ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
  1506. return 0;
  1507. err:
  1508. return ret;
  1509. }
  1510. /*
  1511. * Disable the receive h/w in preparation for a reset.
  1512. */
  1513. static void
  1514. ath5k_rx_stop(struct ath5k_softc *sc)
  1515. {
  1516. struct ath5k_hw *ah = sc->ah;
  1517. ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
  1518. ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
  1519. ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
  1520. ath5k_debug_printrxbuffs(sc, ah);
  1521. }
  1522. static unsigned int
  1523. ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
  1524. struct ath5k_rx_status *rs)
  1525. {
  1526. struct ath5k_hw *ah = sc->ah;
  1527. struct ath_common *common = ath5k_hw_common(ah);
  1528. struct ieee80211_hdr *hdr = (void *)skb->data;
  1529. unsigned int keyix, hlen;
  1530. if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1531. rs->rs_keyix != AR5K_RXKEYIX_INVALID)
  1532. return RX_FLAG_DECRYPTED;
  1533. /* Apparently when a default key is used to decrypt the packet
  1534. the hw does not set the index used to decrypt. In such cases
  1535. get the index from the packet. */
  1536. hlen = ieee80211_hdrlen(hdr->frame_control);
  1537. if (ieee80211_has_protected(hdr->frame_control) &&
  1538. !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1539. skb->len >= hlen + 4) {
  1540. keyix = skb->data[hlen + 3] >> 6;
  1541. if (test_bit(keyix, common->keymap))
  1542. return RX_FLAG_DECRYPTED;
  1543. }
  1544. return 0;
  1545. }
  1546. static void
  1547. ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
  1548. struct ieee80211_rx_status *rxs)
  1549. {
  1550. struct ath_common *common = ath5k_hw_common(sc->ah);
  1551. u64 tsf, bc_tstamp;
  1552. u32 hw_tu;
  1553. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1554. if (ieee80211_is_beacon(mgmt->frame_control) &&
  1555. le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
  1556. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
  1557. /*
  1558. * Received an IBSS beacon with the same BSSID. Hardware *must*
  1559. * have updated the local TSF. We have to work around various
  1560. * hardware bugs, though...
  1561. */
  1562. tsf = ath5k_hw_get_tsf64(sc->ah);
  1563. bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
  1564. hw_tu = TSF_TO_TU(tsf);
  1565. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1566. "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
  1567. (unsigned long long)bc_tstamp,
  1568. (unsigned long long)rxs->mactime,
  1569. (unsigned long long)(rxs->mactime - bc_tstamp),
  1570. (unsigned long long)tsf);
  1571. /*
  1572. * Sometimes the HW will give us a wrong tstamp in the rx
  1573. * status, causing the timestamp extension to go wrong.
  1574. * (This seems to happen especially with beacon frames bigger
  1575. * than 78 byte (incl. FCS))
  1576. * But we know that the receive timestamp must be later than the
  1577. * timestamp of the beacon since HW must have synced to that.
  1578. *
  1579. * NOTE: here we assume mactime to be after the frame was
  1580. * received, not like mac80211 which defines it at the start.
  1581. */
  1582. if (bc_tstamp > rxs->mactime) {
  1583. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1584. "fixing mactime from %llx to %llx\n",
  1585. (unsigned long long)rxs->mactime,
  1586. (unsigned long long)tsf);
  1587. rxs->mactime = tsf;
  1588. }
  1589. /*
  1590. * Local TSF might have moved higher than our beacon timers,
  1591. * in that case we have to update them to continue sending
  1592. * beacons. This also takes care of synchronizing beacon sending
  1593. * times with other stations.
  1594. */
  1595. if (hw_tu >= sc->nexttbtt)
  1596. ath5k_beacon_update_timers(sc, bc_tstamp);
  1597. }
  1598. }
  1599. static void
  1600. ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
  1601. {
  1602. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1603. struct ath5k_hw *ah = sc->ah;
  1604. struct ath_common *common = ath5k_hw_common(ah);
  1605. /* only beacons from our BSSID */
  1606. if (!ieee80211_is_beacon(mgmt->frame_control) ||
  1607. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
  1608. return;
  1609. ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
  1610. rssi);
  1611. /* in IBSS mode we should keep RSSI statistics per neighbour */
  1612. /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
  1613. }
  1614. /*
  1615. * Compute padding position. skb must contains an IEEE 802.11 frame
  1616. */
  1617. static int ath5k_common_padpos(struct sk_buff *skb)
  1618. {
  1619. struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
  1620. __le16 frame_control = hdr->frame_control;
  1621. int padpos = 24;
  1622. if (ieee80211_has_a4(frame_control)) {
  1623. padpos += ETH_ALEN;
  1624. }
  1625. if (ieee80211_is_data_qos(frame_control)) {
  1626. padpos += IEEE80211_QOS_CTL_LEN;
  1627. }
  1628. return padpos;
  1629. }
  1630. /*
  1631. * This function expects a 802.11 frame and returns the number of
  1632. * bytes added, or -1 if we don't have enought header room.
  1633. */
  1634. static int ath5k_add_padding(struct sk_buff *skb)
  1635. {
  1636. int padpos = ath5k_common_padpos(skb);
  1637. int padsize = padpos & 3;
  1638. if (padsize && skb->len>padpos) {
  1639. if (skb_headroom(skb) < padsize)
  1640. return -1;
  1641. skb_push(skb, padsize);
  1642. memmove(skb->data, skb->data+padsize, padpos);
  1643. return padsize;
  1644. }
  1645. return 0;
  1646. }
  1647. /*
  1648. * This function expects a 802.11 frame and returns the number of
  1649. * bytes removed
  1650. */
  1651. static int ath5k_remove_padding(struct sk_buff *skb)
  1652. {
  1653. int padpos = ath5k_common_padpos(skb);
  1654. int padsize = padpos & 3;
  1655. if (padsize && skb->len>=padpos+padsize) {
  1656. memmove(skb->data + padsize, skb->data, padpos);
  1657. skb_pull(skb, padsize);
  1658. return padsize;
  1659. }
  1660. return 0;
  1661. }
  1662. static void
  1663. ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
  1664. struct ath5k_rx_status *rs)
  1665. {
  1666. struct ieee80211_rx_status *rxs;
  1667. /* The MAC header is padded to have 32-bit boundary if the
  1668. * packet payload is non-zero. The general calculation for
  1669. * padsize would take into account odd header lengths:
  1670. * padsize = (4 - hdrlen % 4) % 4; However, since only
  1671. * even-length headers are used, padding can only be 0 or 2
  1672. * bytes and we can optimize this a bit. In addition, we must
  1673. * not try to remove padding from short control frames that do
  1674. * not have payload. */
  1675. ath5k_remove_padding(skb);
  1676. rxs = IEEE80211_SKB_RXCB(skb);
  1677. rxs->flag = 0;
  1678. if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
  1679. rxs->flag |= RX_FLAG_MMIC_ERROR;
  1680. /*
  1681. * always extend the mac timestamp, since this information is
  1682. * also needed for proper IBSS merging.
  1683. *
  1684. * XXX: it might be too late to do it here, since rs_tstamp is
  1685. * 15bit only. that means TSF extension has to be done within
  1686. * 32768usec (about 32ms). it might be necessary to move this to
  1687. * the interrupt handler, like it is done in madwifi.
  1688. *
  1689. * Unfortunately we don't know when the hardware takes the rx
  1690. * timestamp (beginning of phy frame, data frame, end of rx?).
  1691. * The only thing we know is that it is hardware specific...
  1692. * On AR5213 it seems the rx timestamp is at the end of the
  1693. * frame, but i'm not sure.
  1694. *
  1695. * NOTE: mac80211 defines mactime at the beginning of the first
  1696. * data symbol. Since we don't have any time references it's
  1697. * impossible to comply to that. This affects IBSS merge only
  1698. * right now, so it's not too bad...
  1699. */
  1700. rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
  1701. rxs->flag |= RX_FLAG_TSFT;
  1702. rxs->freq = sc->curchan->center_freq;
  1703. rxs->band = sc->curband->band;
  1704. rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
  1705. rxs->antenna = rs->rs_antenna;
  1706. if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
  1707. sc->stats.antenna_rx[rs->rs_antenna]++;
  1708. else
  1709. sc->stats.antenna_rx[0]++; /* invalid */
  1710. rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
  1711. rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
  1712. if (rxs->rate_idx >= 0 && rs->rs_rate ==
  1713. sc->curband->bitrates[rxs->rate_idx].hw_value_short)
  1714. rxs->flag |= RX_FLAG_SHORTPRE;
  1715. ath5k_debug_dump_skb(sc, skb, "RX ", 0);
  1716. ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
  1717. /* check beacons in IBSS mode */
  1718. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  1719. ath5k_check_ibss_tsf(sc, skb, rxs);
  1720. ieee80211_rx(sc->hw, skb);
  1721. }
  1722. /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
  1723. *
  1724. * Check if we want to further process this frame or not. Also update
  1725. * statistics. Return true if we want this frame, false if not.
  1726. */
  1727. static bool
  1728. ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
  1729. {
  1730. sc->stats.rx_all_count++;
  1731. if (unlikely(rs->rs_status)) {
  1732. if (rs->rs_status & AR5K_RXERR_CRC)
  1733. sc->stats.rxerr_crc++;
  1734. if (rs->rs_status & AR5K_RXERR_FIFO)
  1735. sc->stats.rxerr_fifo++;
  1736. if (rs->rs_status & AR5K_RXERR_PHY) {
  1737. sc->stats.rxerr_phy++;
  1738. if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
  1739. sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
  1740. return false;
  1741. }
  1742. if (rs->rs_status & AR5K_RXERR_DECRYPT) {
  1743. /*
  1744. * Decrypt error. If the error occurred
  1745. * because there was no hardware key, then
  1746. * let the frame through so the upper layers
  1747. * can process it. This is necessary for 5210
  1748. * parts which have no way to setup a ``clear''
  1749. * key cache entry.
  1750. *
  1751. * XXX do key cache faulting
  1752. */
  1753. sc->stats.rxerr_decrypt++;
  1754. if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
  1755. !(rs->rs_status & AR5K_RXERR_CRC))
  1756. return true;
  1757. }
  1758. if (rs->rs_status & AR5K_RXERR_MIC) {
  1759. sc->stats.rxerr_mic++;
  1760. return true;
  1761. }
  1762. /* let crypto-error packets fall through in MNTR */
  1763. if ((rs->rs_status & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
  1764. sc->opmode != NL80211_IFTYPE_MONITOR)
  1765. return false;
  1766. }
  1767. if (unlikely(rs->rs_more)) {
  1768. sc->stats.rxerr_jumbo++;
  1769. return false;
  1770. }
  1771. return true;
  1772. }
  1773. static void
  1774. ath5k_tasklet_rx(unsigned long data)
  1775. {
  1776. struct ath5k_rx_status rs = {};
  1777. struct sk_buff *skb, *next_skb;
  1778. dma_addr_t next_skb_addr;
  1779. struct ath5k_softc *sc = (void *)data;
  1780. struct ath5k_hw *ah = sc->ah;
  1781. struct ath_common *common = ath5k_hw_common(ah);
  1782. struct ath5k_buf *bf;
  1783. struct ath5k_desc *ds;
  1784. int ret;
  1785. spin_lock(&sc->rxbuflock);
  1786. if (list_empty(&sc->rxbuf)) {
  1787. ATH5K_WARN(sc, "empty rx buf pool\n");
  1788. goto unlock;
  1789. }
  1790. do {
  1791. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1792. BUG_ON(bf->skb == NULL);
  1793. skb = bf->skb;
  1794. ds = bf->desc;
  1795. /* bail if HW is still using self-linked descriptor */
  1796. if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
  1797. break;
  1798. ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
  1799. if (unlikely(ret == -EINPROGRESS))
  1800. break;
  1801. else if (unlikely(ret)) {
  1802. ATH5K_ERR(sc, "error in processing rx descriptor\n");
  1803. sc->stats.rxerr_proc++;
  1804. break;
  1805. }
  1806. if (ath5k_receive_frame_ok(sc, &rs)) {
  1807. next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
  1808. /*
  1809. * If we can't replace bf->skb with a new skb under
  1810. * memory pressure, just skip this packet
  1811. */
  1812. if (!next_skb)
  1813. goto next;
  1814. pci_unmap_single(sc->pdev, bf->skbaddr,
  1815. common->rx_bufsize,
  1816. PCI_DMA_FROMDEVICE);
  1817. skb_put(skb, rs.rs_datalen);
  1818. ath5k_receive_frame(sc, skb, &rs);
  1819. bf->skb = next_skb;
  1820. bf->skbaddr = next_skb_addr;
  1821. }
  1822. next:
  1823. list_move_tail(&bf->list, &sc->rxbuf);
  1824. } while (ath5k_rxbuf_setup(sc, bf) == 0);
  1825. unlock:
  1826. spin_unlock(&sc->rxbuflock);
  1827. }
  1828. /*************\
  1829. * TX Handling *
  1830. \*************/
  1831. static void
  1832. ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1833. {
  1834. struct ath5k_tx_status ts = {};
  1835. struct ath5k_buf *bf, *bf0;
  1836. struct ath5k_desc *ds;
  1837. struct sk_buff *skb;
  1838. struct ieee80211_tx_info *info;
  1839. int i, ret;
  1840. spin_lock(&txq->lock);
  1841. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1842. ds = bf->desc;
  1843. /*
  1844. * It's possible that the hardware can say the buffer is
  1845. * completed when it hasn't yet loaded the ds_link from
  1846. * host memory and moved on. If there are more TX
  1847. * descriptors in the queue, wait for TXDP to change
  1848. * before processing this one.
  1849. */
  1850. if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
  1851. !list_is_last(&bf->list, &txq->q))
  1852. break;
  1853. ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
  1854. if (unlikely(ret == -EINPROGRESS))
  1855. break;
  1856. else if (unlikely(ret)) {
  1857. ATH5K_ERR(sc, "error %d while processing queue %u\n",
  1858. ret, txq->qnum);
  1859. break;
  1860. }
  1861. sc->stats.tx_all_count++;
  1862. skb = bf->skb;
  1863. info = IEEE80211_SKB_CB(skb);
  1864. bf->skb = NULL;
  1865. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
  1866. PCI_DMA_TODEVICE);
  1867. ieee80211_tx_info_clear_status(info);
  1868. for (i = 0; i < 4; i++) {
  1869. struct ieee80211_tx_rate *r =
  1870. &info->status.rates[i];
  1871. if (ts.ts_rate[i]) {
  1872. r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
  1873. r->count = ts.ts_retry[i];
  1874. } else {
  1875. r->idx = -1;
  1876. r->count = 0;
  1877. }
  1878. }
  1879. /* count the successful attempt as well */
  1880. info->status.rates[ts.ts_final_idx].count++;
  1881. if (unlikely(ts.ts_status)) {
  1882. sc->stats.ack_fail++;
  1883. if (ts.ts_status & AR5K_TXERR_FILT) {
  1884. info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1885. sc->stats.txerr_filt++;
  1886. }
  1887. if (ts.ts_status & AR5K_TXERR_XRETRY)
  1888. sc->stats.txerr_retry++;
  1889. if (ts.ts_status & AR5K_TXERR_FIFO)
  1890. sc->stats.txerr_fifo++;
  1891. } else {
  1892. info->flags |= IEEE80211_TX_STAT_ACK;
  1893. info->status.ack_signal = ts.ts_rssi;
  1894. }
  1895. /*
  1896. * Remove MAC header padding before giving the frame
  1897. * back to mac80211.
  1898. */
  1899. ath5k_remove_padding(skb);
  1900. if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
  1901. sc->stats.antenna_tx[ts.ts_antenna]++;
  1902. else
  1903. sc->stats.antenna_tx[0]++; /* invalid */
  1904. ieee80211_tx_status(sc->hw, skb);
  1905. spin_lock(&sc->txbuflock);
  1906. list_move_tail(&bf->list, &sc->txbuf);
  1907. sc->txbuf_len++;
  1908. spin_unlock(&sc->txbuflock);
  1909. }
  1910. if (likely(list_empty(&txq->q)))
  1911. txq->link = NULL;
  1912. spin_unlock(&txq->lock);
  1913. if (sc->txbuf_len > ATH_TXBUF / 5)
  1914. ieee80211_wake_queues(sc->hw);
  1915. }
  1916. static void
  1917. ath5k_tasklet_tx(unsigned long data)
  1918. {
  1919. int i;
  1920. struct ath5k_softc *sc = (void *)data;
  1921. for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
  1922. if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
  1923. ath5k_tx_processq(sc, &sc->txqs[i]);
  1924. }
  1925. /*****************\
  1926. * Beacon handling *
  1927. \*****************/
  1928. /*
  1929. * Setup the beacon frame for transmit.
  1930. */
  1931. static int
  1932. ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1933. {
  1934. struct sk_buff *skb = bf->skb;
  1935. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1936. struct ath5k_hw *ah = sc->ah;
  1937. struct ath5k_desc *ds;
  1938. int ret = 0;
  1939. u8 antenna;
  1940. u32 flags;
  1941. const int padsize = 0;
  1942. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1943. PCI_DMA_TODEVICE);
  1944. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
  1945. "skbaddr %llx\n", skb, skb->data, skb->len,
  1946. (unsigned long long)bf->skbaddr);
  1947. if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
  1948. ATH5K_ERR(sc, "beacon DMA mapping failed\n");
  1949. return -EIO;
  1950. }
  1951. ds = bf->desc;
  1952. antenna = ah->ah_tx_ant;
  1953. flags = AR5K_TXDESC_NOACK;
  1954. if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
  1955. ds->ds_link = bf->daddr; /* self-linked */
  1956. flags |= AR5K_TXDESC_VEOL;
  1957. } else
  1958. ds->ds_link = 0;
  1959. /*
  1960. * If we use multiple antennas on AP and use
  1961. * the Sectored AP scenario, switch antenna every
  1962. * 4 beacons to make sure everybody hears our AP.
  1963. * When a client tries to associate, hw will keep
  1964. * track of the tx antenna to be used for this client
  1965. * automaticaly, based on ACKed packets.
  1966. *
  1967. * Note: AP still listens and transmits RTS on the
  1968. * default antenna which is supposed to be an omni.
  1969. *
  1970. * Note2: On sectored scenarios it's possible to have
  1971. * multiple antennas (1omni -the default- and 14 sectors)
  1972. * so if we choose to actually support this mode we need
  1973. * to allow user to set how many antennas we have and tweak
  1974. * the code below to send beacons on all of them.
  1975. */
  1976. if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
  1977. antenna = sc->bsent & 4 ? 2 : 1;
  1978. /* FIXME: If we are in g mode and rate is a CCK rate
  1979. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1980. * from tx power (value is in dB units already) */
  1981. ds->ds_data = bf->skbaddr;
  1982. ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
  1983. ieee80211_get_hdrlen_from_skb(skb), padsize,
  1984. AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
  1985. ieee80211_get_tx_rate(sc->hw, info)->hw_value,
  1986. 1, AR5K_TXKEYIX_INVALID,
  1987. antenna, flags, 0, 0);
  1988. if (ret)
  1989. goto err_unmap;
  1990. return 0;
  1991. err_unmap:
  1992. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1993. return ret;
  1994. }
  1995. /*
  1996. * Transmit a beacon frame at SWBA. Dynamic updates to the
  1997. * frame contents are done as needed and the slot time is
  1998. * also adjusted based on current state.
  1999. *
  2000. * This is called from software irq context (beacontq tasklets)
  2001. * or user context from ath5k_beacon_config.
  2002. */
  2003. static void
  2004. ath5k_beacon_send(struct ath5k_softc *sc)
  2005. {
  2006. struct ath5k_buf *bf = sc->bbuf;
  2007. struct ath5k_hw *ah = sc->ah;
  2008. struct sk_buff *skb;
  2009. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
  2010. if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
  2011. sc->opmode == NL80211_IFTYPE_MONITOR)) {
  2012. ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
  2013. return;
  2014. }
  2015. /*
  2016. * Check if the previous beacon has gone out. If
  2017. * not don't don't try to post another, skip this
  2018. * period and wait for the next. Missed beacons
  2019. * indicate a problem and should not occur. If we
  2020. * miss too many consecutive beacons reset the device.
  2021. */
  2022. if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
  2023. sc->bmisscount++;
  2024. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2025. "missed %u consecutive beacons\n", sc->bmisscount);
  2026. if (sc->bmisscount > 10) { /* NB: 10 is a guess */
  2027. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2028. "stuck beacon time (%u missed)\n",
  2029. sc->bmisscount);
  2030. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2031. "stuck beacon, resetting\n");
  2032. ieee80211_queue_work(sc->hw, &sc->reset_work);
  2033. }
  2034. return;
  2035. }
  2036. if (unlikely(sc->bmisscount != 0)) {
  2037. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2038. "resume beacon xmit after %u misses\n",
  2039. sc->bmisscount);
  2040. sc->bmisscount = 0;
  2041. }
  2042. /*
  2043. * Stop any current dma and put the new frame on the queue.
  2044. * This should never fail since we check above that no frames
  2045. * are still pending on the queue.
  2046. */
  2047. if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
  2048. ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
  2049. /* NB: hw still stops DMA, so proceed */
  2050. }
  2051. /* refresh the beacon for AP mode */
  2052. if (sc->opmode == NL80211_IFTYPE_AP)
  2053. ath5k_beacon_update(sc->hw, sc->vif);
  2054. ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
  2055. ath5k_hw_start_tx_dma(ah, sc->bhalq);
  2056. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
  2057. sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
  2058. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  2059. while (skb) {
  2060. ath5k_tx_queue(sc->hw, skb, sc->cabq);
  2061. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  2062. }
  2063. sc->bsent++;
  2064. }
  2065. /**
  2066. * ath5k_beacon_update_timers - update beacon timers
  2067. *
  2068. * @sc: struct ath5k_softc pointer we are operating on
  2069. * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
  2070. * beacon timer update based on the current HW TSF.
  2071. *
  2072. * Calculate the next target beacon transmit time (TBTT) based on the timestamp
  2073. * of a received beacon or the current local hardware TSF and write it to the
  2074. * beacon timer registers.
  2075. *
  2076. * This is called in a variety of situations, e.g. when a beacon is received,
  2077. * when a TSF update has been detected, but also when an new IBSS is created or
  2078. * when we otherwise know we have to update the timers, but we keep it in this
  2079. * function to have it all together in one place.
  2080. */
  2081. static void
  2082. ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
  2083. {
  2084. struct ath5k_hw *ah = sc->ah;
  2085. u32 nexttbtt, intval, hw_tu, bc_tu;
  2086. u64 hw_tsf;
  2087. intval = sc->bintval & AR5K_BEACON_PERIOD;
  2088. if (WARN_ON(!intval))
  2089. return;
  2090. /* beacon TSF converted to TU */
  2091. bc_tu = TSF_TO_TU(bc_tsf);
  2092. /* current TSF converted to TU */
  2093. hw_tsf = ath5k_hw_get_tsf64(ah);
  2094. hw_tu = TSF_TO_TU(hw_tsf);
  2095. #define FUDGE 3
  2096. /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
  2097. if (bc_tsf == -1) {
  2098. /*
  2099. * no beacons received, called internally.
  2100. * just need to refresh timers based on HW TSF.
  2101. */
  2102. nexttbtt = roundup(hw_tu + FUDGE, intval);
  2103. } else if (bc_tsf == 0) {
  2104. /*
  2105. * no beacon received, probably called by ath5k_reset_tsf().
  2106. * reset TSF to start with 0.
  2107. */
  2108. nexttbtt = intval;
  2109. intval |= AR5K_BEACON_RESET_TSF;
  2110. } else if (bc_tsf > hw_tsf) {
  2111. /*
  2112. * beacon received, SW merge happend but HW TSF not yet updated.
  2113. * not possible to reconfigure timers yet, but next time we
  2114. * receive a beacon with the same BSSID, the hardware will
  2115. * automatically update the TSF and then we need to reconfigure
  2116. * the timers.
  2117. */
  2118. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2119. "need to wait for HW TSF sync\n");
  2120. return;
  2121. } else {
  2122. /*
  2123. * most important case for beacon synchronization between STA.
  2124. *
  2125. * beacon received and HW TSF has been already updated by HW.
  2126. * update next TBTT based on the TSF of the beacon, but make
  2127. * sure it is ahead of our local TSF timer.
  2128. */
  2129. nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
  2130. }
  2131. #undef FUDGE
  2132. sc->nexttbtt = nexttbtt;
  2133. intval |= AR5K_BEACON_ENA;
  2134. ath5k_hw_init_beacon(ah, nexttbtt, intval);
  2135. /*
  2136. * debugging output last in order to preserve the time critical aspect
  2137. * of this function
  2138. */
  2139. if (bc_tsf == -1)
  2140. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2141. "reconfigured timers based on HW TSF\n");
  2142. else if (bc_tsf == 0)
  2143. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2144. "reset HW TSF and timers\n");
  2145. else
  2146. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2147. "updated timers based on beacon TSF\n");
  2148. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  2149. "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
  2150. (unsigned long long) bc_tsf,
  2151. (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
  2152. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
  2153. intval & AR5K_BEACON_PERIOD,
  2154. intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
  2155. intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
  2156. }
  2157. /**
  2158. * ath5k_beacon_config - Configure the beacon queues and interrupts
  2159. *
  2160. * @sc: struct ath5k_softc pointer we are operating on
  2161. *
  2162. * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  2163. * interrupts to detect TSF updates only.
  2164. */
  2165. static void
  2166. ath5k_beacon_config(struct ath5k_softc *sc)
  2167. {
  2168. struct ath5k_hw *ah = sc->ah;
  2169. unsigned long flags;
  2170. spin_lock_irqsave(&sc->block, flags);
  2171. sc->bmisscount = 0;
  2172. sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
  2173. if (sc->enable_beacon) {
  2174. /*
  2175. * In IBSS mode we use a self-linked tx descriptor and let the
  2176. * hardware send the beacons automatically. We have to load it
  2177. * only once here.
  2178. * We use the SWBA interrupt only to keep track of the beacon
  2179. * timers in order to detect automatic TSF updates.
  2180. */
  2181. ath5k_beaconq_config(sc);
  2182. sc->imask |= AR5K_INT_SWBA;
  2183. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  2184. if (ath5k_hw_hasveol(ah))
  2185. ath5k_beacon_send(sc);
  2186. } else
  2187. ath5k_beacon_update_timers(sc, -1);
  2188. } else {
  2189. ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
  2190. }
  2191. ath5k_hw_set_imr(ah, sc->imask);
  2192. mmiowb();
  2193. spin_unlock_irqrestore(&sc->block, flags);
  2194. }
  2195. static void ath5k_tasklet_beacon(unsigned long data)
  2196. {
  2197. struct ath5k_softc *sc = (struct ath5k_softc *) data;
  2198. /*
  2199. * Software beacon alert--time to send a beacon.
  2200. *
  2201. * In IBSS mode we use this interrupt just to
  2202. * keep track of the next TBTT (target beacon
  2203. * transmission time) in order to detect wether
  2204. * automatic TSF updates happened.
  2205. */
  2206. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  2207. /* XXX: only if VEOL suppported */
  2208. u64 tsf = ath5k_hw_get_tsf64(sc->ah);
  2209. sc->nexttbtt += sc->bintval;
  2210. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2211. "SWBA nexttbtt: %x hw_tu: %x "
  2212. "TSF: %llx\n",
  2213. sc->nexttbtt,
  2214. TSF_TO_TU(tsf),
  2215. (unsigned long long) tsf);
  2216. } else {
  2217. spin_lock(&sc->block);
  2218. ath5k_beacon_send(sc);
  2219. spin_unlock(&sc->block);
  2220. }
  2221. }
  2222. /********************\
  2223. * Interrupt handling *
  2224. \********************/
  2225. static int
  2226. ath5k_init(struct ath5k_softc *sc)
  2227. {
  2228. struct ath5k_hw *ah = sc->ah;
  2229. int ret, i;
  2230. mutex_lock(&sc->lock);
  2231. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
  2232. /*
  2233. * Stop anything previously setup. This is safe
  2234. * no matter this is the first time through or not.
  2235. */
  2236. ath5k_stop_locked(sc);
  2237. /*
  2238. * The basic interface to setting the hardware in a good
  2239. * state is ``reset''. On return the hardware is known to
  2240. * be powered up and with interrupts disabled. This must
  2241. * be followed by initialization of the appropriate bits
  2242. * and then setup of the interrupt mask.
  2243. */
  2244. sc->curchan = sc->hw->conf.channel;
  2245. sc->curband = &sc->sbands[sc->curchan->band];
  2246. sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
  2247. AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
  2248. AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
  2249. ret = ath5k_reset(sc, NULL);
  2250. if (ret)
  2251. goto done;
  2252. ath5k_rfkill_hw_start(ah);
  2253. /*
  2254. * Reset the key cache since some parts do not reset the
  2255. * contents on initial power up or resume from suspend.
  2256. */
  2257. for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
  2258. ath5k_hw_reset_key(ah, i);
  2259. ath5k_hw_set_ack_bitrate_high(ah, true);
  2260. ret = 0;
  2261. done:
  2262. mmiowb();
  2263. mutex_unlock(&sc->lock);
  2264. return ret;
  2265. }
  2266. static int
  2267. ath5k_stop_locked(struct ath5k_softc *sc)
  2268. {
  2269. struct ath5k_hw *ah = sc->ah;
  2270. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
  2271. test_bit(ATH_STAT_INVALID, sc->status));
  2272. /*
  2273. * Shutdown the hardware and driver:
  2274. * stop output from above
  2275. * disable interrupts
  2276. * turn off timers
  2277. * turn off the radio
  2278. * clear transmit machinery
  2279. * clear receive machinery
  2280. * drain and release tx queues
  2281. * reclaim beacon resources
  2282. * power down hardware
  2283. *
  2284. * Note that some of this work is not possible if the
  2285. * hardware is gone (invalid).
  2286. */
  2287. ieee80211_stop_queues(sc->hw);
  2288. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2289. ath5k_led_off(sc);
  2290. ath5k_hw_set_imr(ah, 0);
  2291. synchronize_irq(sc->pdev->irq);
  2292. }
  2293. ath5k_txq_cleanup(sc);
  2294. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2295. ath5k_rx_stop(sc);
  2296. ath5k_hw_phy_disable(ah);
  2297. }
  2298. return 0;
  2299. }
  2300. static void stop_tasklets(struct ath5k_softc *sc)
  2301. {
  2302. tasklet_kill(&sc->rxtq);
  2303. tasklet_kill(&sc->txtq);
  2304. tasklet_kill(&sc->calib);
  2305. tasklet_kill(&sc->beacontq);
  2306. tasklet_kill(&sc->ani_tasklet);
  2307. }
  2308. /*
  2309. * Stop the device, grabbing the top-level lock to protect
  2310. * against concurrent entry through ath5k_init (which can happen
  2311. * if another thread does a system call and the thread doing the
  2312. * stop is preempted).
  2313. */
  2314. static int
  2315. ath5k_stop_hw(struct ath5k_softc *sc)
  2316. {
  2317. int ret;
  2318. mutex_lock(&sc->lock);
  2319. ret = ath5k_stop_locked(sc);
  2320. if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
  2321. /*
  2322. * Don't set the card in full sleep mode!
  2323. *
  2324. * a) When the device is in this state it must be carefully
  2325. * woken up or references to registers in the PCI clock
  2326. * domain may freeze the bus (and system). This varies
  2327. * by chip and is mostly an issue with newer parts
  2328. * (madwifi sources mentioned srev >= 0x78) that go to
  2329. * sleep more quickly.
  2330. *
  2331. * b) On older chips full sleep results a weird behaviour
  2332. * during wakeup. I tested various cards with srev < 0x78
  2333. * and they don't wake up after module reload, a second
  2334. * module reload is needed to bring the card up again.
  2335. *
  2336. * Until we figure out what's going on don't enable
  2337. * full chip reset on any chip (this is what Legacy HAL
  2338. * and Sam's HAL do anyway). Instead Perform a full reset
  2339. * on the device (same as initial state after attach) and
  2340. * leave it idle (keep MAC/BB on warm reset) */
  2341. ret = ath5k_hw_on_hold(sc->ah);
  2342. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2343. "putting device to sleep\n");
  2344. }
  2345. ath5k_txbuf_free_skb(sc, sc->bbuf);
  2346. mmiowb();
  2347. mutex_unlock(&sc->lock);
  2348. stop_tasklets(sc);
  2349. ath5k_rfkill_hw_stop(sc->ah);
  2350. return ret;
  2351. }
  2352. static void
  2353. ath5k_intr_calibration_poll(struct ath5k_hw *ah)
  2354. {
  2355. if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
  2356. !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
  2357. /* run ANI only when full calibration is not active */
  2358. ah->ah_cal_next_ani = jiffies +
  2359. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
  2360. tasklet_schedule(&ah->ah_sc->ani_tasklet);
  2361. } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
  2362. ah->ah_cal_next_full = jiffies +
  2363. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
  2364. tasklet_schedule(&ah->ah_sc->calib);
  2365. }
  2366. /* we could use SWI to generate enough interrupts to meet our
  2367. * calibration interval requirements, if necessary:
  2368. * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
  2369. }
  2370. static irqreturn_t
  2371. ath5k_intr(int irq, void *dev_id)
  2372. {
  2373. struct ath5k_softc *sc = dev_id;
  2374. struct ath5k_hw *ah = sc->ah;
  2375. enum ath5k_int status;
  2376. unsigned int counter = 1000;
  2377. if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
  2378. !ath5k_hw_is_intr_pending(ah)))
  2379. return IRQ_NONE;
  2380. do {
  2381. ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
  2382. ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
  2383. status, sc->imask);
  2384. if (unlikely(status & AR5K_INT_FATAL)) {
  2385. /*
  2386. * Fatal errors are unrecoverable.
  2387. * Typically these are caused by DMA errors.
  2388. */
  2389. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2390. "fatal int, resetting\n");
  2391. ieee80211_queue_work(sc->hw, &sc->reset_work);
  2392. } else if (unlikely(status & AR5K_INT_RXORN)) {
  2393. /*
  2394. * Receive buffers are full. Either the bus is busy or
  2395. * the CPU is not fast enough to process all received
  2396. * frames.
  2397. * Older chipsets need a reset to come out of this
  2398. * condition, but we treat it as RX for newer chips.
  2399. * We don't know exactly which versions need a reset -
  2400. * this guess is copied from the HAL.
  2401. */
  2402. sc->stats.rxorn_intr++;
  2403. if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
  2404. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2405. "rx overrun, resetting\n");
  2406. ieee80211_queue_work(sc->hw, &sc->reset_work);
  2407. }
  2408. else
  2409. tasklet_schedule(&sc->rxtq);
  2410. } else {
  2411. if (status & AR5K_INT_SWBA) {
  2412. tasklet_hi_schedule(&sc->beacontq);
  2413. }
  2414. if (status & AR5K_INT_RXEOL) {
  2415. /*
  2416. * NB: the hardware should re-read the link when
  2417. * RXE bit is written, but it doesn't work at
  2418. * least on older hardware revs.
  2419. */
  2420. sc->stats.rxeol_intr++;
  2421. }
  2422. if (status & AR5K_INT_TXURN) {
  2423. /* bump tx trigger level */
  2424. ath5k_hw_update_tx_triglevel(ah, true);
  2425. }
  2426. if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
  2427. tasklet_schedule(&sc->rxtq);
  2428. if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
  2429. | AR5K_INT_TXERR | AR5K_INT_TXEOL))
  2430. tasklet_schedule(&sc->txtq);
  2431. if (status & AR5K_INT_BMISS) {
  2432. /* TODO */
  2433. }
  2434. if (status & AR5K_INT_MIB) {
  2435. sc->stats.mib_intr++;
  2436. ath5k_hw_update_mib_counters(ah);
  2437. ath5k_ani_mib_intr(ah);
  2438. }
  2439. if (status & AR5K_INT_GPIO)
  2440. tasklet_schedule(&sc->rf_kill.toggleq);
  2441. }
  2442. } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
  2443. if (unlikely(!counter))
  2444. ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
  2445. ath5k_intr_calibration_poll(ah);
  2446. return IRQ_HANDLED;
  2447. }
  2448. /*
  2449. * Periodically recalibrate the PHY to account
  2450. * for temperature/environment changes.
  2451. */
  2452. static void
  2453. ath5k_tasklet_calibrate(unsigned long data)
  2454. {
  2455. struct ath5k_softc *sc = (void *)data;
  2456. struct ath5k_hw *ah = sc->ah;
  2457. /* Only full calibration for now */
  2458. ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
  2459. ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
  2460. ieee80211_frequency_to_channel(sc->curchan->center_freq),
  2461. sc->curchan->hw_value);
  2462. if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
  2463. /*
  2464. * Rfgain is out of bounds, reset the chip
  2465. * to load new gain values.
  2466. */
  2467. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
  2468. ieee80211_queue_work(sc->hw, &sc->reset_work);
  2469. }
  2470. if (ath5k_hw_phy_calibrate(ah, sc->curchan))
  2471. ATH5K_ERR(sc, "calibration of channel %u failed\n",
  2472. ieee80211_frequency_to_channel(
  2473. sc->curchan->center_freq));
  2474. /* Noise floor calibration interrupts rx/tx path while I/Q calibration
  2475. * doesn't. We stop the queues so that calibration doesn't interfere
  2476. * with TX and don't run it as often */
  2477. if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
  2478. ah->ah_cal_next_nf = jiffies +
  2479. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
  2480. ieee80211_stop_queues(sc->hw);
  2481. ath5k_hw_update_noise_floor(ah);
  2482. ieee80211_wake_queues(sc->hw);
  2483. }
  2484. ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
  2485. }
  2486. static void
  2487. ath5k_tasklet_ani(unsigned long data)
  2488. {
  2489. struct ath5k_softc *sc = (void *)data;
  2490. struct ath5k_hw *ah = sc->ah;
  2491. ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
  2492. ath5k_ani_calibration(ah);
  2493. ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
  2494. }
  2495. /********************\
  2496. * Mac80211 functions *
  2497. \********************/
  2498. static int
  2499. ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2500. {
  2501. struct ath5k_softc *sc = hw->priv;
  2502. return ath5k_tx_queue(hw, skb, sc->txq);
  2503. }
  2504. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  2505. struct ath5k_txq *txq)
  2506. {
  2507. struct ath5k_softc *sc = hw->priv;
  2508. struct ath5k_buf *bf;
  2509. unsigned long flags;
  2510. int padsize;
  2511. ath5k_debug_dump_skb(sc, skb, "TX ", 1);
  2512. if (sc->opmode == NL80211_IFTYPE_MONITOR)
  2513. ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
  2514. /*
  2515. * the hardware expects the header padded to 4 byte boundaries
  2516. * if this is not the case we add the padding after the header
  2517. */
  2518. padsize = ath5k_add_padding(skb);
  2519. if (padsize < 0) {
  2520. ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
  2521. " headroom to pad");
  2522. goto drop_packet;
  2523. }
  2524. spin_lock_irqsave(&sc->txbuflock, flags);
  2525. if (list_empty(&sc->txbuf)) {
  2526. ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
  2527. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2528. ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
  2529. goto drop_packet;
  2530. }
  2531. bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
  2532. list_del(&bf->list);
  2533. sc->txbuf_len--;
  2534. if (list_empty(&sc->txbuf))
  2535. ieee80211_stop_queues(hw);
  2536. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2537. bf->skb = skb;
  2538. if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
  2539. bf->skb = NULL;
  2540. spin_lock_irqsave(&sc->txbuflock, flags);
  2541. list_add_tail(&bf->list, &sc->txbuf);
  2542. sc->txbuf_len++;
  2543. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2544. goto drop_packet;
  2545. }
  2546. return NETDEV_TX_OK;
  2547. drop_packet:
  2548. dev_kfree_skb_any(skb);
  2549. return NETDEV_TX_OK;
  2550. }
  2551. /*
  2552. * Reset the hardware. If chan is not NULL, then also pause rx/tx
  2553. * and change to the given channel.
  2554. *
  2555. * This should be called with sc->lock.
  2556. */
  2557. static int
  2558. ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  2559. {
  2560. struct ath5k_hw *ah = sc->ah;
  2561. int ret;
  2562. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
  2563. ath5k_hw_set_imr(ah, 0);
  2564. synchronize_irq(sc->pdev->irq);
  2565. stop_tasklets(sc);
  2566. if (chan) {
  2567. ath5k_txq_cleanup(sc);
  2568. ath5k_rx_stop(sc);
  2569. sc->curchan = chan;
  2570. sc->curband = &sc->sbands[chan->band];
  2571. }
  2572. ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
  2573. if (ret) {
  2574. ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
  2575. goto err;
  2576. }
  2577. ret = ath5k_rx_start(sc);
  2578. if (ret) {
  2579. ATH5K_ERR(sc, "can't start recv logic\n");
  2580. goto err;
  2581. }
  2582. ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
  2583. ah->ah_cal_next_full = jiffies;
  2584. ah->ah_cal_next_ani = jiffies;
  2585. ah->ah_cal_next_nf = jiffies;
  2586. /*
  2587. * Change channels and update the h/w rate map if we're switching;
  2588. * e.g. 11a to 11b/g.
  2589. *
  2590. * We may be doing a reset in response to an ioctl that changes the
  2591. * channel so update any state that might change as a result.
  2592. *
  2593. * XXX needed?
  2594. */
  2595. /* ath5k_chan_change(sc, c); */
  2596. ath5k_beacon_config(sc);
  2597. /* intrs are enabled by ath5k_beacon_config */
  2598. ieee80211_wake_queues(sc->hw);
  2599. return 0;
  2600. err:
  2601. return ret;
  2602. }
  2603. static void ath5k_reset_work(struct work_struct *work)
  2604. {
  2605. struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
  2606. reset_work);
  2607. mutex_lock(&sc->lock);
  2608. ath5k_reset(sc, sc->curchan);
  2609. mutex_unlock(&sc->lock);
  2610. }
  2611. static int ath5k_start(struct ieee80211_hw *hw)
  2612. {
  2613. return ath5k_init(hw->priv);
  2614. }
  2615. static void ath5k_stop(struct ieee80211_hw *hw)
  2616. {
  2617. ath5k_stop_hw(hw->priv);
  2618. }
  2619. static int ath5k_add_interface(struct ieee80211_hw *hw,
  2620. struct ieee80211_vif *vif)
  2621. {
  2622. struct ath5k_softc *sc = hw->priv;
  2623. int ret;
  2624. mutex_lock(&sc->lock);
  2625. if (sc->vif) {
  2626. ret = 0;
  2627. goto end;
  2628. }
  2629. sc->vif = vif;
  2630. switch (vif->type) {
  2631. case NL80211_IFTYPE_AP:
  2632. case NL80211_IFTYPE_STATION:
  2633. case NL80211_IFTYPE_ADHOC:
  2634. case NL80211_IFTYPE_MESH_POINT:
  2635. case NL80211_IFTYPE_MONITOR:
  2636. sc->opmode = vif->type;
  2637. break;
  2638. default:
  2639. ret = -EOPNOTSUPP;
  2640. goto end;
  2641. }
  2642. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
  2643. ath5k_hw_set_lladdr(sc->ah, vif->addr);
  2644. ath5k_mode_setup(sc);
  2645. ret = 0;
  2646. end:
  2647. mutex_unlock(&sc->lock);
  2648. return ret;
  2649. }
  2650. static void
  2651. ath5k_remove_interface(struct ieee80211_hw *hw,
  2652. struct ieee80211_vif *vif)
  2653. {
  2654. struct ath5k_softc *sc = hw->priv;
  2655. u8 mac[ETH_ALEN] = {};
  2656. mutex_lock(&sc->lock);
  2657. if (sc->vif != vif)
  2658. goto end;
  2659. ath5k_hw_set_lladdr(sc->ah, mac);
  2660. sc->vif = NULL;
  2661. end:
  2662. mutex_unlock(&sc->lock);
  2663. }
  2664. /*
  2665. * TODO: Phy disable/diversity etc
  2666. */
  2667. static int
  2668. ath5k_config(struct ieee80211_hw *hw, u32 changed)
  2669. {
  2670. struct ath5k_softc *sc = hw->priv;
  2671. struct ath5k_hw *ah = sc->ah;
  2672. struct ieee80211_conf *conf = &hw->conf;
  2673. int ret = 0;
  2674. mutex_lock(&sc->lock);
  2675. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  2676. ret = ath5k_chan_set(sc, conf->channel);
  2677. if (ret < 0)
  2678. goto unlock;
  2679. }
  2680. if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
  2681. (sc->power_level != conf->power_level)) {
  2682. sc->power_level = conf->power_level;
  2683. /* Half dB steps */
  2684. ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
  2685. }
  2686. /* TODO:
  2687. * 1) Move this on config_interface and handle each case
  2688. * separately eg. when we have only one STA vif, use
  2689. * AR5K_ANTMODE_SINGLE_AP
  2690. *
  2691. * 2) Allow the user to change antenna mode eg. when only
  2692. * one antenna is present
  2693. *
  2694. * 3) Allow the user to set default/tx antenna when possible
  2695. *
  2696. * 4) Default mode should handle 90% of the cases, together
  2697. * with fixed a/b and single AP modes we should be able to
  2698. * handle 99%. Sectored modes are extreme cases and i still
  2699. * haven't found a usage for them. If we decide to support them,
  2700. * then we must allow the user to set how many tx antennas we
  2701. * have available
  2702. */
  2703. ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
  2704. unlock:
  2705. mutex_unlock(&sc->lock);
  2706. return ret;
  2707. }
  2708. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  2709. struct netdev_hw_addr_list *mc_list)
  2710. {
  2711. u32 mfilt[2], val;
  2712. u8 pos;
  2713. struct netdev_hw_addr *ha;
  2714. mfilt[0] = 0;
  2715. mfilt[1] = 1;
  2716. netdev_hw_addr_list_for_each(ha, mc_list) {
  2717. /* calculate XOR of eight 6-bit values */
  2718. val = get_unaligned_le32(ha->addr + 0);
  2719. pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2720. val = get_unaligned_le32(ha->addr + 3);
  2721. pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2722. pos &= 0x3f;
  2723. mfilt[pos / 32] |= (1 << (pos % 32));
  2724. /* XXX: we might be able to just do this instead,
  2725. * but not sure, needs testing, if we do use this we'd
  2726. * neet to inform below to not reset the mcast */
  2727. /* ath5k_hw_set_mcast_filterindex(ah,
  2728. * ha->addr[5]); */
  2729. }
  2730. return ((u64)(mfilt[1]) << 32) | mfilt[0];
  2731. }
  2732. #define SUPPORTED_FIF_FLAGS \
  2733. FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
  2734. FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
  2735. FIF_BCN_PRBRESP_PROMISC
  2736. /*
  2737. * o always accept unicast, broadcast, and multicast traffic
  2738. * o multicast traffic for all BSSIDs will be enabled if mac80211
  2739. * says it should be
  2740. * o maintain current state of phy ofdm or phy cck error reception.
  2741. * If the hardware detects any of these type of errors then
  2742. * ath5k_hw_get_rx_filter() will pass to us the respective
  2743. * hardware filters to be able to receive these type of frames.
  2744. * o probe request frames are accepted only when operating in
  2745. * hostap, adhoc, or monitor modes
  2746. * o enable promiscuous mode according to the interface state
  2747. * o accept beacons:
  2748. * - when operating in adhoc mode so the 802.11 layer creates
  2749. * node table entries for peers,
  2750. * - when operating in station mode for collecting rssi data when
  2751. * the station is otherwise quiet, or
  2752. * - when scanning
  2753. */
  2754. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  2755. unsigned int changed_flags,
  2756. unsigned int *new_flags,
  2757. u64 multicast)
  2758. {
  2759. struct ath5k_softc *sc = hw->priv;
  2760. struct ath5k_hw *ah = sc->ah;
  2761. u32 mfilt[2], rfilt;
  2762. mutex_lock(&sc->lock);
  2763. mfilt[0] = multicast;
  2764. mfilt[1] = multicast >> 32;
  2765. /* Only deal with supported flags */
  2766. changed_flags &= SUPPORTED_FIF_FLAGS;
  2767. *new_flags &= SUPPORTED_FIF_FLAGS;
  2768. /* If HW detects any phy or radar errors, leave those filters on.
  2769. * Also, always enable Unicast, Broadcasts and Multicast
  2770. * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
  2771. rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
  2772. (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
  2773. AR5K_RX_FILTER_MCAST);
  2774. if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  2775. if (*new_flags & FIF_PROMISC_IN_BSS) {
  2776. __set_bit(ATH_STAT_PROMISC, sc->status);
  2777. } else {
  2778. __clear_bit(ATH_STAT_PROMISC, sc->status);
  2779. }
  2780. }
  2781. if (test_bit(ATH_STAT_PROMISC, sc->status))
  2782. rfilt |= AR5K_RX_FILTER_PROM;
  2783. /* Note, AR5K_RX_FILTER_MCAST is already enabled */
  2784. if (*new_flags & FIF_ALLMULTI) {
  2785. mfilt[0] = ~0;
  2786. mfilt[1] = ~0;
  2787. }
  2788. /* This is the best we can do */
  2789. if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
  2790. rfilt |= AR5K_RX_FILTER_PHYERR;
  2791. /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
  2792. * and probes for any BSSID, this needs testing */
  2793. if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
  2794. rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
  2795. /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
  2796. * set we should only pass on control frames for this
  2797. * station. This needs testing. I believe right now this
  2798. * enables *all* control frames, which is OK.. but
  2799. * but we should see if we can improve on granularity */
  2800. if (*new_flags & FIF_CONTROL)
  2801. rfilt |= AR5K_RX_FILTER_CONTROL;
  2802. /* Additional settings per mode -- this is per ath5k */
  2803. /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
  2804. switch (sc->opmode) {
  2805. case NL80211_IFTYPE_MESH_POINT:
  2806. case NL80211_IFTYPE_MONITOR:
  2807. rfilt |= AR5K_RX_FILTER_CONTROL |
  2808. AR5K_RX_FILTER_BEACON |
  2809. AR5K_RX_FILTER_PROBEREQ |
  2810. AR5K_RX_FILTER_PROM;
  2811. break;
  2812. case NL80211_IFTYPE_AP:
  2813. case NL80211_IFTYPE_ADHOC:
  2814. rfilt |= AR5K_RX_FILTER_PROBEREQ |
  2815. AR5K_RX_FILTER_BEACON;
  2816. break;
  2817. case NL80211_IFTYPE_STATION:
  2818. if (sc->assoc)
  2819. rfilt |= AR5K_RX_FILTER_BEACON;
  2820. default:
  2821. break;
  2822. }
  2823. /* Set filters */
  2824. ath5k_hw_set_rx_filter(ah, rfilt);
  2825. /* Set multicast bits */
  2826. ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
  2827. /* Set the cached hw filter flags, this will alter actually
  2828. * be set in HW */
  2829. sc->filter_flags = rfilt;
  2830. mutex_unlock(&sc->lock);
  2831. }
  2832. static int
  2833. ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2834. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  2835. struct ieee80211_key_conf *key)
  2836. {
  2837. struct ath5k_softc *sc = hw->priv;
  2838. struct ath5k_hw *ah = sc->ah;
  2839. struct ath_common *common = ath5k_hw_common(ah);
  2840. int ret = 0;
  2841. if (modparam_nohwcrypt)
  2842. return -EOPNOTSUPP;
  2843. if (sc->opmode == NL80211_IFTYPE_AP)
  2844. return -EOPNOTSUPP;
  2845. switch (key->alg) {
  2846. case ALG_WEP:
  2847. case ALG_TKIP:
  2848. break;
  2849. case ALG_CCMP:
  2850. if (sc->ah->ah_aes_support)
  2851. break;
  2852. return -EOPNOTSUPP;
  2853. default:
  2854. WARN_ON(1);
  2855. return -EINVAL;
  2856. }
  2857. mutex_lock(&sc->lock);
  2858. switch (cmd) {
  2859. case SET_KEY:
  2860. ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
  2861. sta ? sta->addr : NULL);
  2862. if (ret) {
  2863. ATH5K_ERR(sc, "can't set the key\n");
  2864. goto unlock;
  2865. }
  2866. __set_bit(key->keyidx, common->keymap);
  2867. key->hw_key_idx = key->keyidx;
  2868. key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
  2869. IEEE80211_KEY_FLAG_GENERATE_MMIC);
  2870. break;
  2871. case DISABLE_KEY:
  2872. ath5k_hw_reset_key(sc->ah, key->keyidx);
  2873. __clear_bit(key->keyidx, common->keymap);
  2874. break;
  2875. default:
  2876. ret = -EINVAL;
  2877. goto unlock;
  2878. }
  2879. unlock:
  2880. mmiowb();
  2881. mutex_unlock(&sc->lock);
  2882. return ret;
  2883. }
  2884. static int
  2885. ath5k_get_stats(struct ieee80211_hw *hw,
  2886. struct ieee80211_low_level_stats *stats)
  2887. {
  2888. struct ath5k_softc *sc = hw->priv;
  2889. /* Force update */
  2890. ath5k_hw_update_mib_counters(sc->ah);
  2891. stats->dot11ACKFailureCount = sc->stats.ack_fail;
  2892. stats->dot11RTSFailureCount = sc->stats.rts_fail;
  2893. stats->dot11RTSSuccessCount = sc->stats.rts_ok;
  2894. stats->dot11FCSErrorCount = sc->stats.fcs_error;
  2895. return 0;
  2896. }
  2897. static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
  2898. struct survey_info *survey)
  2899. {
  2900. struct ath5k_softc *sc = hw->priv;
  2901. struct ieee80211_conf *conf = &hw->conf;
  2902. if (idx != 0)
  2903. return -ENOENT;
  2904. survey->channel = conf->channel;
  2905. survey->filled = SURVEY_INFO_NOISE_DBM;
  2906. survey->noise = sc->ah->ah_noise_floor;
  2907. return 0;
  2908. }
  2909. static u64
  2910. ath5k_get_tsf(struct ieee80211_hw *hw)
  2911. {
  2912. struct ath5k_softc *sc = hw->priv;
  2913. return ath5k_hw_get_tsf64(sc->ah);
  2914. }
  2915. static void
  2916. ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  2917. {
  2918. struct ath5k_softc *sc = hw->priv;
  2919. ath5k_hw_set_tsf64(sc->ah, tsf);
  2920. }
  2921. static void
  2922. ath5k_reset_tsf(struct ieee80211_hw *hw)
  2923. {
  2924. struct ath5k_softc *sc = hw->priv;
  2925. /*
  2926. * in IBSS mode we need to update the beacon timers too.
  2927. * this will also reset the TSF if we call it with 0
  2928. */
  2929. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  2930. ath5k_beacon_update_timers(sc, 0);
  2931. else
  2932. ath5k_hw_reset_tsf(sc->ah);
  2933. }
  2934. /*
  2935. * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
  2936. * this is called only once at config_bss time, for AP we do it every
  2937. * SWBA interrupt so that the TIM will reflect buffered frames.
  2938. *
  2939. * Called with the beacon lock.
  2940. */
  2941. static int
  2942. ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  2943. {
  2944. int ret;
  2945. struct ath5k_softc *sc = hw->priv;
  2946. struct sk_buff *skb;
  2947. if (WARN_ON(!vif)) {
  2948. ret = -EINVAL;
  2949. goto out;
  2950. }
  2951. skb = ieee80211_beacon_get(hw, vif);
  2952. if (!skb) {
  2953. ret = -ENOMEM;
  2954. goto out;
  2955. }
  2956. ath5k_debug_dump_skb(sc, skb, "BC ", 1);
  2957. ath5k_txbuf_free_skb(sc, sc->bbuf);
  2958. sc->bbuf->skb = skb;
  2959. ret = ath5k_beacon_setup(sc, sc->bbuf);
  2960. if (ret)
  2961. sc->bbuf->skb = NULL;
  2962. out:
  2963. return ret;
  2964. }
  2965. static void
  2966. set_beacon_filter(struct ieee80211_hw *hw, bool enable)
  2967. {
  2968. struct ath5k_softc *sc = hw->priv;
  2969. struct ath5k_hw *ah = sc->ah;
  2970. u32 rfilt;
  2971. rfilt = ath5k_hw_get_rx_filter(ah);
  2972. if (enable)
  2973. rfilt |= AR5K_RX_FILTER_BEACON;
  2974. else
  2975. rfilt &= ~AR5K_RX_FILTER_BEACON;
  2976. ath5k_hw_set_rx_filter(ah, rfilt);
  2977. sc->filter_flags = rfilt;
  2978. }
  2979. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  2980. struct ieee80211_vif *vif,
  2981. struct ieee80211_bss_conf *bss_conf,
  2982. u32 changes)
  2983. {
  2984. struct ath5k_softc *sc = hw->priv;
  2985. struct ath5k_hw *ah = sc->ah;
  2986. struct ath_common *common = ath5k_hw_common(ah);
  2987. unsigned long flags;
  2988. mutex_lock(&sc->lock);
  2989. if (WARN_ON(sc->vif != vif))
  2990. goto unlock;
  2991. if (changes & BSS_CHANGED_BSSID) {
  2992. /* Cache for later use during resets */
  2993. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  2994. common->curaid = 0;
  2995. ath5k_hw_set_associd(ah);
  2996. mmiowb();
  2997. }
  2998. if (changes & BSS_CHANGED_BEACON_INT)
  2999. sc->bintval = bss_conf->beacon_int;
  3000. if (changes & BSS_CHANGED_ASSOC) {
  3001. sc->assoc = bss_conf->assoc;
  3002. if (sc->opmode == NL80211_IFTYPE_STATION)
  3003. set_beacon_filter(hw, sc->assoc);
  3004. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  3005. AR5K_LED_ASSOC : AR5K_LED_INIT);
  3006. if (bss_conf->assoc) {
  3007. ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
  3008. "Bss Info ASSOC %d, bssid: %pM\n",
  3009. bss_conf->aid, common->curbssid);
  3010. common->curaid = bss_conf->aid;
  3011. ath5k_hw_set_associd(ah);
  3012. /* Once ANI is available you would start it here */
  3013. }
  3014. }
  3015. if (changes & BSS_CHANGED_BEACON) {
  3016. spin_lock_irqsave(&sc->block, flags);
  3017. ath5k_beacon_update(hw, vif);
  3018. spin_unlock_irqrestore(&sc->block, flags);
  3019. }
  3020. if (changes & BSS_CHANGED_BEACON_ENABLED)
  3021. sc->enable_beacon = bss_conf->enable_beacon;
  3022. if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
  3023. BSS_CHANGED_BEACON_INT))
  3024. ath5k_beacon_config(sc);
  3025. unlock:
  3026. mutex_unlock(&sc->lock);
  3027. }
  3028. static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
  3029. {
  3030. struct ath5k_softc *sc = hw->priv;
  3031. if (!sc->assoc)
  3032. ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
  3033. }
  3034. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
  3035. {
  3036. struct ath5k_softc *sc = hw->priv;
  3037. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  3038. AR5K_LED_ASSOC : AR5K_LED_INIT);
  3039. }
  3040. /**
  3041. * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
  3042. *
  3043. * @hw: struct ieee80211_hw pointer
  3044. * @coverage_class: IEEE 802.11 coverage class number
  3045. *
  3046. * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
  3047. * coverage class. The values are persistent, they are restored after device
  3048. * reset.
  3049. */
  3050. static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  3051. {
  3052. struct ath5k_softc *sc = hw->priv;
  3053. mutex_lock(&sc->lock);
  3054. ath5k_hw_set_coverage_class(sc->ah, coverage_class);
  3055. mutex_unlock(&sc->lock);
  3056. }