tg3.h 111 KB

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  1. /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
  2. * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2007-2010 Broadcom Corporation.
  8. */
  9. #ifndef _T3_H
  10. #define _T3_H
  11. #define TG3_64BIT_REG_HIGH 0x00UL
  12. #define TG3_64BIT_REG_LOW 0x04UL
  13. /* Descriptor block info. */
  14. #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
  15. #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
  16. #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
  17. #define BDINFO_FLAGS_DISABLED 0x00000002
  18. #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
  19. #define BDINFO_FLAGS_MAXLEN_SHIFT 16
  20. #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
  21. #define TG3_BDINFO_SIZE 0x10UL
  22. #define TG3_RX_INTERNAL_RING_SZ_5906 32
  23. #define RX_STD_MAX_SIZE_5705 512
  24. #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
  25. /* First 256 bytes are a mirror of PCI config space. */
  26. #define TG3PCI_VENDOR 0x00000000
  27. #define TG3PCI_VENDOR_BROADCOM 0x14e4
  28. #define TG3PCI_DEVICE 0x00000002
  29. #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
  30. #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
  31. #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
  32. #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
  33. #define TG3PCI_DEVICE_TIGON3_5761S 0x1688
  34. #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
  35. #define TG3PCI_DEVICE_TIGON3_57780 0x1692
  36. #define TG3PCI_DEVICE_TIGON3_57760 0x1690
  37. #define TG3PCI_DEVICE_TIGON3_57790 0x1694
  38. #define TG3PCI_DEVICE_TIGON3_57788 0x1691
  39. #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
  40. #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
  41. #define TG3PCI_DEVICE_TIGON3_5717 0x1655
  42. #define TG3PCI_DEVICE_TIGON3_5718 0x1656
  43. #define TG3PCI_DEVICE_TIGON3_5724 0x165c
  44. #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
  45. #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
  46. #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
  47. #define TG3PCI_DEVICE_TIGON3_57765 0x16b4
  48. #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
  49. #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
  50. #define TG3PCI_DEVICE_TIGON3_5719 0x1657
  51. /* 0x04 --> 0x2c unused */
  52. #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
  53. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
  54. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
  55. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
  56. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
  57. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
  58. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
  59. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
  60. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
  61. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
  62. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
  63. #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
  64. #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
  65. #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
  66. #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
  67. #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
  68. #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
  69. #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
  70. #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
  71. #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
  72. #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
  73. #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
  74. #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
  75. #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
  76. #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
  77. #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
  78. #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
  79. #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
  80. #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
  81. #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
  82. #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
  83. /* 0x30 --> 0x64 unused */
  84. #define TG3PCI_MSI_DATA 0x00000064
  85. /* 0x66 --> 0x68 unused */
  86. #define TG3PCI_MISC_HOST_CTRL 0x00000068
  87. #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
  88. #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
  89. #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
  90. #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
  91. #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
  92. #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
  93. #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
  94. #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
  95. #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
  96. #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
  97. #define MISC_HOST_CTRL_CHIPREV 0xffff0000
  98. #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
  99. #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
  100. (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
  101. MISC_HOST_CTRL_CHIPREV_SHIFT)
  102. #define CHIPREV_ID_5700_A0 0x7000
  103. #define CHIPREV_ID_5700_A1 0x7001
  104. #define CHIPREV_ID_5700_B0 0x7100
  105. #define CHIPREV_ID_5700_B1 0x7101
  106. #define CHIPREV_ID_5700_B3 0x7102
  107. #define CHIPREV_ID_5700_ALTIMA 0x7104
  108. #define CHIPREV_ID_5700_C0 0x7200
  109. #define CHIPREV_ID_5701_A0 0x0000
  110. #define CHIPREV_ID_5701_B0 0x0100
  111. #define CHIPREV_ID_5701_B2 0x0102
  112. #define CHIPREV_ID_5701_B5 0x0105
  113. #define CHIPREV_ID_5703_A0 0x1000
  114. #define CHIPREV_ID_5703_A1 0x1001
  115. #define CHIPREV_ID_5703_A2 0x1002
  116. #define CHIPREV_ID_5703_A3 0x1003
  117. #define CHIPREV_ID_5704_A0 0x2000
  118. #define CHIPREV_ID_5704_A1 0x2001
  119. #define CHIPREV_ID_5704_A2 0x2002
  120. #define CHIPREV_ID_5704_A3 0x2003
  121. #define CHIPREV_ID_5705_A0 0x3000
  122. #define CHIPREV_ID_5705_A1 0x3001
  123. #define CHIPREV_ID_5705_A2 0x3002
  124. #define CHIPREV_ID_5705_A3 0x3003
  125. #define CHIPREV_ID_5750_A0 0x4000
  126. #define CHIPREV_ID_5750_A1 0x4001
  127. #define CHIPREV_ID_5750_A3 0x4003
  128. #define CHIPREV_ID_5750_C2 0x4202
  129. #define CHIPREV_ID_5752_A0_HW 0x5000
  130. #define CHIPREV_ID_5752_A0 0x6000
  131. #define CHIPREV_ID_5752_A1 0x6001
  132. #define CHIPREV_ID_5714_A2 0x9002
  133. #define CHIPREV_ID_5906_A1 0xc001
  134. #define CHIPREV_ID_57780_A0 0x57780000
  135. #define CHIPREV_ID_57780_A1 0x57780001
  136. #define CHIPREV_ID_5717_A0 0x05717000
  137. #define CHIPREV_ID_57765_A0 0x57785000
  138. #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
  139. #define ASIC_REV_5700 0x07
  140. #define ASIC_REV_5701 0x00
  141. #define ASIC_REV_5703 0x01
  142. #define ASIC_REV_5704 0x02
  143. #define ASIC_REV_5705 0x03
  144. #define ASIC_REV_5750 0x04
  145. #define ASIC_REV_5752 0x06
  146. #define ASIC_REV_5780 0x08
  147. #define ASIC_REV_5714 0x09
  148. #define ASIC_REV_5755 0x0a
  149. #define ASIC_REV_5787 0x0b
  150. #define ASIC_REV_5906 0x0c
  151. #define ASIC_REV_USE_PROD_ID_REG 0x0f
  152. #define ASIC_REV_5784 0x5784
  153. #define ASIC_REV_5761 0x5761
  154. #define ASIC_REV_5785 0x5785
  155. #define ASIC_REV_57780 0x57780
  156. #define ASIC_REV_5717 0x5717
  157. #define ASIC_REV_57765 0x57785
  158. #define ASIC_REV_5719 0x5719
  159. #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
  160. #define CHIPREV_5700_AX 0x70
  161. #define CHIPREV_5700_BX 0x71
  162. #define CHIPREV_5700_CX 0x72
  163. #define CHIPREV_5701_AX 0x00
  164. #define CHIPREV_5703_AX 0x10
  165. #define CHIPREV_5704_AX 0x20
  166. #define CHIPREV_5704_BX 0x21
  167. #define CHIPREV_5750_AX 0x40
  168. #define CHIPREV_5750_BX 0x41
  169. #define CHIPREV_5784_AX 0x57840
  170. #define CHIPREV_5761_AX 0x57610
  171. #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
  172. #define METAL_REV_A0 0x00
  173. #define METAL_REV_A1 0x01
  174. #define METAL_REV_B0 0x00
  175. #define METAL_REV_B1 0x01
  176. #define METAL_REV_B2 0x02
  177. #define TG3PCI_DMA_RW_CTRL 0x0000006c
  178. #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
  179. #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
  180. #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
  181. #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
  182. #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
  183. #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
  184. #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
  185. #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
  186. #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
  187. #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
  188. #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
  189. #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
  190. #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
  191. #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
  192. #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
  193. #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
  194. #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
  195. #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
  196. #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
  197. #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
  198. #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
  199. #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
  200. #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
  201. #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
  202. #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
  203. #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
  204. #define DMA_RWCTRL_ONE_DMA 0x00004000
  205. #define DMA_RWCTRL_READ_WATER 0x00070000
  206. #define DMA_RWCTRL_READ_WATER_SHIFT 16
  207. #define DMA_RWCTRL_WRITE_WATER 0x00380000
  208. #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
  209. #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
  210. #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
  211. #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
  212. #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
  213. #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
  214. #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
  215. #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
  216. #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
  217. #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
  218. #define TG3PCI_PCISTATE 0x00000070
  219. #define PCISTATE_FORCE_RESET 0x00000001
  220. #define PCISTATE_INT_NOT_ACTIVE 0x00000002
  221. #define PCISTATE_CONV_PCI_MODE 0x00000004
  222. #define PCISTATE_BUS_SPEED_HIGH 0x00000008
  223. #define PCISTATE_BUS_32BIT 0x00000010
  224. #define PCISTATE_ROM_ENABLE 0x00000020
  225. #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
  226. #define PCISTATE_FLAT_VIEW 0x00000100
  227. #define PCISTATE_RETRY_SAME_DMA 0x00002000
  228. #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
  229. #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
  230. #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
  231. #define TG3PCI_CLOCK_CTRL 0x00000074
  232. #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
  233. #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
  234. #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
  235. #define CLOCK_CTRL_ALTCLK 0x00001000
  236. #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
  237. #define CLOCK_CTRL_44MHZ_CORE 0x00040000
  238. #define CLOCK_CTRL_625_CORE 0x00100000
  239. #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
  240. #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
  241. #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
  242. #define TG3PCI_REG_BASE_ADDR 0x00000078
  243. #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
  244. #define TG3PCI_REG_DATA 0x00000080
  245. #define TG3PCI_MEM_WIN_DATA 0x00000084
  246. #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
  247. /* 0x94 --> 0x98 unused */
  248. #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
  249. #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
  250. /* 0xa8 --> 0xb8 unused */
  251. #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
  252. #define DUAL_MAC_CTRL_CH_MASK 0x00000003
  253. #define DUAL_MAC_CTRL_ID 0x00000004
  254. #define TG3PCI_PRODID_ASICREV 0x000000bc
  255. #define PROD_ID_ASIC_REV_MASK 0x0fffffff
  256. /* 0xc0 --> 0xf4 unused */
  257. #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
  258. #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
  259. /* 0xf8 --> 0x200 unused */
  260. #define TG3_CORR_ERR_STAT 0x00000110
  261. #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
  262. /* 0x114 --> 0x200 unused */
  263. /* Mailbox registers */
  264. #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
  265. #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
  266. #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
  267. #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
  268. #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
  269. #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
  270. #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
  271. #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
  272. #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
  273. #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
  274. #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
  275. #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
  276. #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
  277. #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
  278. #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
  279. TG3_64BIT_REG_LOW)
  280. #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
  281. #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
  282. TG3_64BIT_REG_LOW)
  283. #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
  284. #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
  285. #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
  286. #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
  287. #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
  288. #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
  289. #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
  290. #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
  291. #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
  292. #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
  293. #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
  294. #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
  295. #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
  296. #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
  297. #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
  298. #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
  299. #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
  300. #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
  301. #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
  302. #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
  303. #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
  304. #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
  305. #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
  306. #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
  307. #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
  308. #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
  309. #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
  310. #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
  311. #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
  312. #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
  313. #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
  314. #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
  315. #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
  316. #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
  317. #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
  318. #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
  319. #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
  320. #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
  321. #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
  322. #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
  323. #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
  324. #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
  325. #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
  326. #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
  327. #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
  328. #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
  329. #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
  330. #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
  331. #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
  332. /* MAC control registers */
  333. #define MAC_MODE 0x00000400
  334. #define MAC_MODE_RESET 0x00000001
  335. #define MAC_MODE_HALF_DUPLEX 0x00000002
  336. #define MAC_MODE_PORT_MODE_MASK 0x0000000c
  337. #define MAC_MODE_PORT_MODE_TBI 0x0000000c
  338. #define MAC_MODE_PORT_MODE_GMII 0x00000008
  339. #define MAC_MODE_PORT_MODE_MII 0x00000004
  340. #define MAC_MODE_PORT_MODE_NONE 0x00000000
  341. #define MAC_MODE_PORT_INT_LPBACK 0x00000010
  342. #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
  343. #define MAC_MODE_TX_BURSTING 0x00000100
  344. #define MAC_MODE_MAX_DEFER 0x00000200
  345. #define MAC_MODE_LINK_POLARITY 0x00000400
  346. #define MAC_MODE_RXSTAT_ENABLE 0x00000800
  347. #define MAC_MODE_RXSTAT_CLEAR 0x00001000
  348. #define MAC_MODE_RXSTAT_FLUSH 0x00002000
  349. #define MAC_MODE_TXSTAT_ENABLE 0x00004000
  350. #define MAC_MODE_TXSTAT_CLEAR 0x00008000
  351. #define MAC_MODE_TXSTAT_FLUSH 0x00010000
  352. #define MAC_MODE_SEND_CONFIGS 0x00020000
  353. #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
  354. #define MAC_MODE_ACPI_ENABLE 0x00080000
  355. #define MAC_MODE_MIP_ENABLE 0x00100000
  356. #define MAC_MODE_TDE_ENABLE 0x00200000
  357. #define MAC_MODE_RDE_ENABLE 0x00400000
  358. #define MAC_MODE_FHDE_ENABLE 0x00800000
  359. #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
  360. #define MAC_MODE_APE_RX_EN 0x08000000
  361. #define MAC_MODE_APE_TX_EN 0x10000000
  362. #define MAC_STATUS 0x00000404
  363. #define MAC_STATUS_PCS_SYNCED 0x00000001
  364. #define MAC_STATUS_SIGNAL_DET 0x00000002
  365. #define MAC_STATUS_RCVD_CFG 0x00000004
  366. #define MAC_STATUS_CFG_CHANGED 0x00000008
  367. #define MAC_STATUS_SYNC_CHANGED 0x00000010
  368. #define MAC_STATUS_PORT_DEC_ERR 0x00000400
  369. #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
  370. #define MAC_STATUS_MI_COMPLETION 0x00400000
  371. #define MAC_STATUS_MI_INTERRUPT 0x00800000
  372. #define MAC_STATUS_AP_ERROR 0x01000000
  373. #define MAC_STATUS_ODI_ERROR 0x02000000
  374. #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
  375. #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
  376. #define MAC_EVENT 0x00000408
  377. #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
  378. #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
  379. #define MAC_EVENT_MI_COMPLETION 0x00400000
  380. #define MAC_EVENT_MI_INTERRUPT 0x00800000
  381. #define MAC_EVENT_AP_ERROR 0x01000000
  382. #define MAC_EVENT_ODI_ERROR 0x02000000
  383. #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
  384. #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
  385. #define MAC_LED_CTRL 0x0000040c
  386. #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
  387. #define LED_CTRL_1000MBPS_ON 0x00000002
  388. #define LED_CTRL_100MBPS_ON 0x00000004
  389. #define LED_CTRL_10MBPS_ON 0x00000008
  390. #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
  391. #define LED_CTRL_TRAFFIC_BLINK 0x00000020
  392. #define LED_CTRL_TRAFFIC_LED 0x00000040
  393. #define LED_CTRL_1000MBPS_STATUS 0x00000080
  394. #define LED_CTRL_100MBPS_STATUS 0x00000100
  395. #define LED_CTRL_10MBPS_STATUS 0x00000200
  396. #define LED_CTRL_TRAFFIC_STATUS 0x00000400
  397. #define LED_CTRL_MODE_MAC 0x00000000
  398. #define LED_CTRL_MODE_PHY_1 0x00000800
  399. #define LED_CTRL_MODE_PHY_2 0x00001000
  400. #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
  401. #define LED_CTRL_MODE_SHARED 0x00004000
  402. #define LED_CTRL_MODE_COMBO 0x00008000
  403. #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
  404. #define LED_CTRL_BLINK_RATE_SHIFT 19
  405. #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
  406. #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
  407. #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
  408. #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
  409. #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
  410. #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
  411. #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
  412. #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
  413. #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
  414. #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
  415. #define MAC_ACPI_MBUF_PTR 0x00000430
  416. #define MAC_ACPI_LEN_OFFSET 0x00000434
  417. #define ACPI_LENOFF_LEN_MASK 0x0000ffff
  418. #define ACPI_LENOFF_LEN_SHIFT 0
  419. #define ACPI_LENOFF_OFF_MASK 0x0fff0000
  420. #define ACPI_LENOFF_OFF_SHIFT 16
  421. #define MAC_TX_BACKOFF_SEED 0x00000438
  422. #define TX_BACKOFF_SEED_MASK 0x000003ff
  423. #define MAC_RX_MTU_SIZE 0x0000043c
  424. #define RX_MTU_SIZE_MASK 0x0000ffff
  425. #define MAC_PCS_TEST 0x00000440
  426. #define PCS_TEST_PATTERN_MASK 0x000fffff
  427. #define PCS_TEST_PATTERN_SHIFT 0
  428. #define PCS_TEST_ENABLE 0x00100000
  429. #define MAC_TX_AUTO_NEG 0x00000444
  430. #define TX_AUTO_NEG_MASK 0x0000ffff
  431. #define TX_AUTO_NEG_SHIFT 0
  432. #define MAC_RX_AUTO_NEG 0x00000448
  433. #define RX_AUTO_NEG_MASK 0x0000ffff
  434. #define RX_AUTO_NEG_SHIFT 0
  435. #define MAC_MI_COM 0x0000044c
  436. #define MI_COM_CMD_MASK 0x0c000000
  437. #define MI_COM_CMD_WRITE 0x04000000
  438. #define MI_COM_CMD_READ 0x08000000
  439. #define MI_COM_READ_FAILED 0x10000000
  440. #define MI_COM_START 0x20000000
  441. #define MI_COM_BUSY 0x20000000
  442. #define MI_COM_PHY_ADDR_MASK 0x03e00000
  443. #define MI_COM_PHY_ADDR_SHIFT 21
  444. #define MI_COM_REG_ADDR_MASK 0x001f0000
  445. #define MI_COM_REG_ADDR_SHIFT 16
  446. #define MI_COM_DATA_MASK 0x0000ffff
  447. #define MAC_MI_STAT 0x00000450
  448. #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
  449. #define MAC_MI_STAT_10MBPS_MODE 0x00000002
  450. #define MAC_MI_MODE 0x00000454
  451. #define MAC_MI_MODE_CLK_10MHZ 0x00000001
  452. #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
  453. #define MAC_MI_MODE_AUTO_POLL 0x00000010
  454. #define MAC_MI_MODE_500KHZ_CONST 0x00008000
  455. #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
  456. #define MAC_AUTO_POLL_STATUS 0x00000458
  457. #define MAC_AUTO_POLL_ERROR 0x00000001
  458. #define MAC_TX_MODE 0x0000045c
  459. #define TX_MODE_RESET 0x00000001
  460. #define TX_MODE_ENABLE 0x00000002
  461. #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
  462. #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
  463. #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
  464. #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
  465. #define MAC_TX_STATUS 0x00000460
  466. #define TX_STATUS_XOFFED 0x00000001
  467. #define TX_STATUS_SENT_XOFF 0x00000002
  468. #define TX_STATUS_SENT_XON 0x00000004
  469. #define TX_STATUS_LINK_UP 0x00000008
  470. #define TX_STATUS_ODI_UNDERRUN 0x00000010
  471. #define TX_STATUS_ODI_OVERRUN 0x00000020
  472. #define MAC_TX_LENGTHS 0x00000464
  473. #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
  474. #define TX_LENGTHS_SLOT_TIME_SHIFT 0
  475. #define TX_LENGTHS_IPG_MASK 0x00000f00
  476. #define TX_LENGTHS_IPG_SHIFT 8
  477. #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
  478. #define TX_LENGTHS_IPG_CRS_SHIFT 12
  479. #define MAC_RX_MODE 0x00000468
  480. #define RX_MODE_RESET 0x00000001
  481. #define RX_MODE_ENABLE 0x00000002
  482. #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
  483. #define RX_MODE_KEEP_MAC_CTRL 0x00000008
  484. #define RX_MODE_KEEP_PAUSE 0x00000010
  485. #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
  486. #define RX_MODE_ACCEPT_RUNTS 0x00000040
  487. #define RX_MODE_LEN_CHECK 0x00000080
  488. #define RX_MODE_PROMISC 0x00000100
  489. #define RX_MODE_NO_CRC_CHECK 0x00000200
  490. #define RX_MODE_KEEP_VLAN_TAG 0x00000400
  491. #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
  492. #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
  493. #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
  494. #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
  495. #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
  496. #define RX_MODE_RSS_ENABLE 0x00800000
  497. #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
  498. #define MAC_RX_STATUS 0x0000046c
  499. #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
  500. #define RX_STATUS_XOFF_RCVD 0x00000002
  501. #define RX_STATUS_XON_RCVD 0x00000004
  502. #define MAC_HASH_REG_0 0x00000470
  503. #define MAC_HASH_REG_1 0x00000474
  504. #define MAC_HASH_REG_2 0x00000478
  505. #define MAC_HASH_REG_3 0x0000047c
  506. #define MAC_RCV_RULE_0 0x00000480
  507. #define MAC_RCV_VALUE_0 0x00000484
  508. #define MAC_RCV_RULE_1 0x00000488
  509. #define MAC_RCV_VALUE_1 0x0000048c
  510. #define MAC_RCV_RULE_2 0x00000490
  511. #define MAC_RCV_VALUE_2 0x00000494
  512. #define MAC_RCV_RULE_3 0x00000498
  513. #define MAC_RCV_VALUE_3 0x0000049c
  514. #define MAC_RCV_RULE_4 0x000004a0
  515. #define MAC_RCV_VALUE_4 0x000004a4
  516. #define MAC_RCV_RULE_5 0x000004a8
  517. #define MAC_RCV_VALUE_5 0x000004ac
  518. #define MAC_RCV_RULE_6 0x000004b0
  519. #define MAC_RCV_VALUE_6 0x000004b4
  520. #define MAC_RCV_RULE_7 0x000004b8
  521. #define MAC_RCV_VALUE_7 0x000004bc
  522. #define MAC_RCV_RULE_8 0x000004c0
  523. #define MAC_RCV_VALUE_8 0x000004c4
  524. #define MAC_RCV_RULE_9 0x000004c8
  525. #define MAC_RCV_VALUE_9 0x000004cc
  526. #define MAC_RCV_RULE_10 0x000004d0
  527. #define MAC_RCV_VALUE_10 0x000004d4
  528. #define MAC_RCV_RULE_11 0x000004d8
  529. #define MAC_RCV_VALUE_11 0x000004dc
  530. #define MAC_RCV_RULE_12 0x000004e0
  531. #define MAC_RCV_VALUE_12 0x000004e4
  532. #define MAC_RCV_RULE_13 0x000004e8
  533. #define MAC_RCV_VALUE_13 0x000004ec
  534. #define MAC_RCV_RULE_14 0x000004f0
  535. #define MAC_RCV_VALUE_14 0x000004f4
  536. #define MAC_RCV_RULE_15 0x000004f8
  537. #define MAC_RCV_VALUE_15 0x000004fc
  538. #define RCV_RULE_DISABLE_MASK 0x7fffffff
  539. #define MAC_RCV_RULE_CFG 0x00000500
  540. #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
  541. #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
  542. /* 0x508 --> 0x520 unused */
  543. #define MAC_HASHREGU_0 0x00000520
  544. #define MAC_HASHREGU_1 0x00000524
  545. #define MAC_HASHREGU_2 0x00000528
  546. #define MAC_HASHREGU_3 0x0000052c
  547. #define MAC_EXTADDR_0_HIGH 0x00000530
  548. #define MAC_EXTADDR_0_LOW 0x00000534
  549. #define MAC_EXTADDR_1_HIGH 0x00000538
  550. #define MAC_EXTADDR_1_LOW 0x0000053c
  551. #define MAC_EXTADDR_2_HIGH 0x00000540
  552. #define MAC_EXTADDR_2_LOW 0x00000544
  553. #define MAC_EXTADDR_3_HIGH 0x00000548
  554. #define MAC_EXTADDR_3_LOW 0x0000054c
  555. #define MAC_EXTADDR_4_HIGH 0x00000550
  556. #define MAC_EXTADDR_4_LOW 0x00000554
  557. #define MAC_EXTADDR_5_HIGH 0x00000558
  558. #define MAC_EXTADDR_5_LOW 0x0000055c
  559. #define MAC_EXTADDR_6_HIGH 0x00000560
  560. #define MAC_EXTADDR_6_LOW 0x00000564
  561. #define MAC_EXTADDR_7_HIGH 0x00000568
  562. #define MAC_EXTADDR_7_LOW 0x0000056c
  563. #define MAC_EXTADDR_8_HIGH 0x00000570
  564. #define MAC_EXTADDR_8_LOW 0x00000574
  565. #define MAC_EXTADDR_9_HIGH 0x00000578
  566. #define MAC_EXTADDR_9_LOW 0x0000057c
  567. #define MAC_EXTADDR_10_HIGH 0x00000580
  568. #define MAC_EXTADDR_10_LOW 0x00000584
  569. #define MAC_EXTADDR_11_HIGH 0x00000588
  570. #define MAC_EXTADDR_11_LOW 0x0000058c
  571. #define MAC_SERDES_CFG 0x00000590
  572. #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
  573. #define MAC_SERDES_STAT 0x00000594
  574. /* 0x598 --> 0x5a0 unused */
  575. #define MAC_PHYCFG1 0x000005a0
  576. #define MAC_PHYCFG1_RGMII_INT 0x00000001
  577. #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
  578. #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
  579. #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
  580. #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
  581. #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
  582. #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
  583. #define MAC_PHYCFG1_TXC_DRV 0x20000000
  584. #define MAC_PHYCFG2 0x000005a4
  585. #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
  586. #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
  587. #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
  588. #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
  589. #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
  590. #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
  591. #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
  592. #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
  593. #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
  594. #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
  595. #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
  596. #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
  597. #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
  598. #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
  599. #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
  600. #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
  601. #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
  602. #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
  603. #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
  604. #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
  605. #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
  606. #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
  607. #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
  608. #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
  609. #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
  610. #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
  611. #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
  612. #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
  613. #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
  614. #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
  615. #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
  616. #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
  617. #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
  618. #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
  619. #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
  620. #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
  621. #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
  622. #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
  623. #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
  624. #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
  625. #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
  626. #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
  627. #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
  628. #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
  629. #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
  630. #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
  631. #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
  632. #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
  633. #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
  634. #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
  635. #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
  636. #define MAC_PHYCFG2_50610_LED_MODES \
  637. (MAC_PHYCFG2_EMODE_MASK_50610 | \
  638. MAC_PHYCFG2_EMODE_COMP_50610 | \
  639. MAC_PHYCFG2_FMODE_MASK_50610 | \
  640. MAC_PHYCFG2_FMODE_COMP_50610 | \
  641. MAC_PHYCFG2_GMODE_MASK_50610 | \
  642. MAC_PHYCFG2_GMODE_COMP_50610 | \
  643. MAC_PHYCFG2_ACT_MASK_50610 | \
  644. MAC_PHYCFG2_ACT_COMP_50610 | \
  645. MAC_PHYCFG2_QUAL_MASK_50610 | \
  646. MAC_PHYCFG2_QUAL_COMP_50610)
  647. #define MAC_PHYCFG2_AC131_LED_MODES \
  648. (MAC_PHYCFG2_EMODE_MASK_AC131 | \
  649. MAC_PHYCFG2_EMODE_COMP_AC131 | \
  650. MAC_PHYCFG2_FMODE_MASK_AC131 | \
  651. MAC_PHYCFG2_FMODE_COMP_AC131 | \
  652. MAC_PHYCFG2_GMODE_MASK_AC131 | \
  653. MAC_PHYCFG2_GMODE_COMP_AC131 | \
  654. MAC_PHYCFG2_ACT_MASK_AC131 | \
  655. MAC_PHYCFG2_ACT_COMP_AC131 | \
  656. MAC_PHYCFG2_QUAL_MASK_AC131 | \
  657. MAC_PHYCFG2_QUAL_COMP_AC131)
  658. #define MAC_PHYCFG2_RTL8211C_LED_MODES \
  659. (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
  660. MAC_PHYCFG2_EMODE_COMP_RT8211 | \
  661. MAC_PHYCFG2_FMODE_MASK_RT8211 | \
  662. MAC_PHYCFG2_FMODE_COMP_RT8211 | \
  663. MAC_PHYCFG2_GMODE_MASK_RT8211 | \
  664. MAC_PHYCFG2_GMODE_COMP_RT8211 | \
  665. MAC_PHYCFG2_ACT_MASK_RT8211 | \
  666. MAC_PHYCFG2_ACT_COMP_RT8211 | \
  667. MAC_PHYCFG2_QUAL_MASK_RT8211 | \
  668. MAC_PHYCFG2_QUAL_COMP_RT8211)
  669. #define MAC_PHYCFG2_RTL8201E_LED_MODES \
  670. (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
  671. MAC_PHYCFG2_EMODE_COMP_RT8201 | \
  672. MAC_PHYCFG2_FMODE_MASK_RT8201 | \
  673. MAC_PHYCFG2_FMODE_COMP_RT8201 | \
  674. MAC_PHYCFG2_GMODE_MASK_RT8201 | \
  675. MAC_PHYCFG2_GMODE_COMP_RT8201 | \
  676. MAC_PHYCFG2_ACT_MASK_RT8201 | \
  677. MAC_PHYCFG2_ACT_COMP_RT8201 | \
  678. MAC_PHYCFG2_QUAL_MASK_RT8201 | \
  679. MAC_PHYCFG2_QUAL_COMP_RT8201)
  680. #define MAC_EXT_RGMII_MODE 0x000005a8
  681. #define MAC_RGMII_MODE_TX_ENABLE 0x00000001
  682. #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
  683. #define MAC_RGMII_MODE_TX_RESET 0x00000004
  684. #define MAC_RGMII_MODE_RX_INT_B 0x00000100
  685. #define MAC_RGMII_MODE_RX_QUALITY 0x00000200
  686. #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
  687. #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
  688. /* 0x5ac --> 0x5b0 unused */
  689. #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
  690. #define SERDES_RX_SIG_DETECT 0x00000400
  691. #define SG_DIG_CTRL 0x000005b0
  692. #define SG_DIG_USING_HW_AUTONEG 0x80000000
  693. #define SG_DIG_SOFT_RESET 0x40000000
  694. #define SG_DIG_DISABLE_LINKRDY 0x20000000
  695. #define SG_DIG_CRC16_CLEAR_N 0x01000000
  696. #define SG_DIG_EN10B 0x00800000
  697. #define SG_DIG_CLEAR_STATUS 0x00400000
  698. #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
  699. #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
  700. #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
  701. #define SG_DIG_SPEED_STATUS_SHIFT 18
  702. #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
  703. #define SG_DIG_RESTART_AUTONEG 0x00010000
  704. #define SG_DIG_FIBER_MODE 0x00008000
  705. #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
  706. #define SG_DIG_PAUSE_MASK 0x00001800
  707. #define SG_DIG_PAUSE_CAP 0x00000800
  708. #define SG_DIG_ASYM_PAUSE 0x00001000
  709. #define SG_DIG_GBIC_ENABLE 0x00000400
  710. #define SG_DIG_CHECK_END_ENABLE 0x00000200
  711. #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
  712. #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
  713. #define SG_DIG_GMII_INPUT_SELECT 0x00000040
  714. #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
  715. #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
  716. #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
  717. #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
  718. #define SG_DIG_REMOTE_LOOPBACK 0x00000002
  719. #define SG_DIG_LOOPBACK 0x00000001
  720. #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
  721. SG_DIG_LOCAL_DUPLEX_STATUS | \
  722. SG_DIG_LOCAL_LINK_STATUS | \
  723. (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
  724. SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
  725. #define SG_DIG_STATUS 0x000005b4
  726. #define SG_DIG_CRC16_BUS_MASK 0xffff0000
  727. #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
  728. #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
  729. #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
  730. #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
  731. #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
  732. #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
  733. #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
  734. #define SG_DIG_IS_SERDES 0x00000100
  735. #define SG_DIG_COMMA_DETECTOR 0x00000008
  736. #define SG_DIG_MAC_ACK_STATUS 0x00000004
  737. #define SG_DIG_AUTONEG_COMPLETE 0x00000002
  738. #define SG_DIG_AUTONEG_ERROR 0x00000001
  739. /* 0x5b8 --> 0x600 unused */
  740. #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
  741. #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
  742. /* 0x624 --> 0x670 unused */
  743. #define MAC_RSS_INDIR_TBL_0 0x00000630
  744. #define MAC_RSS_HASH_KEY_0 0x00000670
  745. #define MAC_RSS_HASH_KEY_1 0x00000674
  746. #define MAC_RSS_HASH_KEY_2 0x00000678
  747. #define MAC_RSS_HASH_KEY_3 0x0000067c
  748. #define MAC_RSS_HASH_KEY_4 0x00000680
  749. #define MAC_RSS_HASH_KEY_5 0x00000684
  750. #define MAC_RSS_HASH_KEY_6 0x00000688
  751. #define MAC_RSS_HASH_KEY_7 0x0000068c
  752. #define MAC_RSS_HASH_KEY_8 0x00000690
  753. #define MAC_RSS_HASH_KEY_9 0x00000694
  754. /* 0x698 --> 0x800 unused */
  755. #define MAC_TX_STATS_OCTETS 0x00000800
  756. #define MAC_TX_STATS_RESV1 0x00000804
  757. #define MAC_TX_STATS_COLLISIONS 0x00000808
  758. #define MAC_TX_STATS_XON_SENT 0x0000080c
  759. #define MAC_TX_STATS_XOFF_SENT 0x00000810
  760. #define MAC_TX_STATS_RESV2 0x00000814
  761. #define MAC_TX_STATS_MAC_ERRORS 0x00000818
  762. #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
  763. #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
  764. #define MAC_TX_STATS_DEFERRED 0x00000824
  765. #define MAC_TX_STATS_RESV3 0x00000828
  766. #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
  767. #define MAC_TX_STATS_LATE_COL 0x00000830
  768. #define MAC_TX_STATS_RESV4_1 0x00000834
  769. #define MAC_TX_STATS_RESV4_2 0x00000838
  770. #define MAC_TX_STATS_RESV4_3 0x0000083c
  771. #define MAC_TX_STATS_RESV4_4 0x00000840
  772. #define MAC_TX_STATS_RESV4_5 0x00000844
  773. #define MAC_TX_STATS_RESV4_6 0x00000848
  774. #define MAC_TX_STATS_RESV4_7 0x0000084c
  775. #define MAC_TX_STATS_RESV4_8 0x00000850
  776. #define MAC_TX_STATS_RESV4_9 0x00000854
  777. #define MAC_TX_STATS_RESV4_10 0x00000858
  778. #define MAC_TX_STATS_RESV4_11 0x0000085c
  779. #define MAC_TX_STATS_RESV4_12 0x00000860
  780. #define MAC_TX_STATS_RESV4_13 0x00000864
  781. #define MAC_TX_STATS_RESV4_14 0x00000868
  782. #define MAC_TX_STATS_UCAST 0x0000086c
  783. #define MAC_TX_STATS_MCAST 0x00000870
  784. #define MAC_TX_STATS_BCAST 0x00000874
  785. #define MAC_TX_STATS_RESV5_1 0x00000878
  786. #define MAC_TX_STATS_RESV5_2 0x0000087c
  787. #define MAC_RX_STATS_OCTETS 0x00000880
  788. #define MAC_RX_STATS_RESV1 0x00000884
  789. #define MAC_RX_STATS_FRAGMENTS 0x00000888
  790. #define MAC_RX_STATS_UCAST 0x0000088c
  791. #define MAC_RX_STATS_MCAST 0x00000890
  792. #define MAC_RX_STATS_BCAST 0x00000894
  793. #define MAC_RX_STATS_FCS_ERRORS 0x00000898
  794. #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
  795. #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
  796. #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
  797. #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
  798. #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
  799. #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
  800. #define MAC_RX_STATS_JABBERS 0x000008b4
  801. #define MAC_RX_STATS_UNDERSIZE 0x000008b8
  802. /* 0x8bc --> 0xc00 unused */
  803. /* Send data initiator control registers */
  804. #define SNDDATAI_MODE 0x00000c00
  805. #define SNDDATAI_MODE_RESET 0x00000001
  806. #define SNDDATAI_MODE_ENABLE 0x00000002
  807. #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
  808. #define SNDDATAI_STATUS 0x00000c04
  809. #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
  810. #define SNDDATAI_STATSCTRL 0x00000c08
  811. #define SNDDATAI_SCTRL_ENABLE 0x00000001
  812. #define SNDDATAI_SCTRL_FASTUPD 0x00000002
  813. #define SNDDATAI_SCTRL_CLEAR 0x00000004
  814. #define SNDDATAI_SCTRL_FLUSH 0x00000008
  815. #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
  816. #define SNDDATAI_STATSENAB 0x00000c0c
  817. #define SNDDATAI_STATSINCMASK 0x00000c10
  818. #define ISO_PKT_TX 0x00000c20
  819. /* 0xc24 --> 0xc80 unused */
  820. #define SNDDATAI_COS_CNT_0 0x00000c80
  821. #define SNDDATAI_COS_CNT_1 0x00000c84
  822. #define SNDDATAI_COS_CNT_2 0x00000c88
  823. #define SNDDATAI_COS_CNT_3 0x00000c8c
  824. #define SNDDATAI_COS_CNT_4 0x00000c90
  825. #define SNDDATAI_COS_CNT_5 0x00000c94
  826. #define SNDDATAI_COS_CNT_6 0x00000c98
  827. #define SNDDATAI_COS_CNT_7 0x00000c9c
  828. #define SNDDATAI_COS_CNT_8 0x00000ca0
  829. #define SNDDATAI_COS_CNT_9 0x00000ca4
  830. #define SNDDATAI_COS_CNT_10 0x00000ca8
  831. #define SNDDATAI_COS_CNT_11 0x00000cac
  832. #define SNDDATAI_COS_CNT_12 0x00000cb0
  833. #define SNDDATAI_COS_CNT_13 0x00000cb4
  834. #define SNDDATAI_COS_CNT_14 0x00000cb8
  835. #define SNDDATAI_COS_CNT_15 0x00000cbc
  836. #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
  837. #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
  838. #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
  839. #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
  840. #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
  841. #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
  842. #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
  843. #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
  844. /* 0xce0 --> 0x1000 unused */
  845. /* Send data completion control registers */
  846. #define SNDDATAC_MODE 0x00001000
  847. #define SNDDATAC_MODE_RESET 0x00000001
  848. #define SNDDATAC_MODE_ENABLE 0x00000002
  849. #define SNDDATAC_MODE_CDELAY 0x00000010
  850. /* 0x1004 --> 0x1400 unused */
  851. /* Send BD ring selector */
  852. #define SNDBDS_MODE 0x00001400
  853. #define SNDBDS_MODE_RESET 0x00000001
  854. #define SNDBDS_MODE_ENABLE 0x00000002
  855. #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
  856. #define SNDBDS_STATUS 0x00001404
  857. #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
  858. #define SNDBDS_HWDIAG 0x00001408
  859. /* 0x140c --> 0x1440 */
  860. #define SNDBDS_SEL_CON_IDX_0 0x00001440
  861. #define SNDBDS_SEL_CON_IDX_1 0x00001444
  862. #define SNDBDS_SEL_CON_IDX_2 0x00001448
  863. #define SNDBDS_SEL_CON_IDX_3 0x0000144c
  864. #define SNDBDS_SEL_CON_IDX_4 0x00001450
  865. #define SNDBDS_SEL_CON_IDX_5 0x00001454
  866. #define SNDBDS_SEL_CON_IDX_6 0x00001458
  867. #define SNDBDS_SEL_CON_IDX_7 0x0000145c
  868. #define SNDBDS_SEL_CON_IDX_8 0x00001460
  869. #define SNDBDS_SEL_CON_IDX_9 0x00001464
  870. #define SNDBDS_SEL_CON_IDX_10 0x00001468
  871. #define SNDBDS_SEL_CON_IDX_11 0x0000146c
  872. #define SNDBDS_SEL_CON_IDX_12 0x00001470
  873. #define SNDBDS_SEL_CON_IDX_13 0x00001474
  874. #define SNDBDS_SEL_CON_IDX_14 0x00001478
  875. #define SNDBDS_SEL_CON_IDX_15 0x0000147c
  876. /* 0x1480 --> 0x1800 unused */
  877. /* Send BD initiator control registers */
  878. #define SNDBDI_MODE 0x00001800
  879. #define SNDBDI_MODE_RESET 0x00000001
  880. #define SNDBDI_MODE_ENABLE 0x00000002
  881. #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
  882. #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
  883. #define SNDBDI_STATUS 0x00001804
  884. #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
  885. #define SNDBDI_IN_PROD_IDX_0 0x00001808
  886. #define SNDBDI_IN_PROD_IDX_1 0x0000180c
  887. #define SNDBDI_IN_PROD_IDX_2 0x00001810
  888. #define SNDBDI_IN_PROD_IDX_3 0x00001814
  889. #define SNDBDI_IN_PROD_IDX_4 0x00001818
  890. #define SNDBDI_IN_PROD_IDX_5 0x0000181c
  891. #define SNDBDI_IN_PROD_IDX_6 0x00001820
  892. #define SNDBDI_IN_PROD_IDX_7 0x00001824
  893. #define SNDBDI_IN_PROD_IDX_8 0x00001828
  894. #define SNDBDI_IN_PROD_IDX_9 0x0000182c
  895. #define SNDBDI_IN_PROD_IDX_10 0x00001830
  896. #define SNDBDI_IN_PROD_IDX_11 0x00001834
  897. #define SNDBDI_IN_PROD_IDX_12 0x00001838
  898. #define SNDBDI_IN_PROD_IDX_13 0x0000183c
  899. #define SNDBDI_IN_PROD_IDX_14 0x00001840
  900. #define SNDBDI_IN_PROD_IDX_15 0x00001844
  901. /* 0x1848 --> 0x1c00 unused */
  902. /* Send BD completion control registers */
  903. #define SNDBDC_MODE 0x00001c00
  904. #define SNDBDC_MODE_RESET 0x00000001
  905. #define SNDBDC_MODE_ENABLE 0x00000002
  906. #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
  907. /* 0x1c04 --> 0x2000 unused */
  908. /* Receive list placement control registers */
  909. #define RCVLPC_MODE 0x00002000
  910. #define RCVLPC_MODE_RESET 0x00000001
  911. #define RCVLPC_MODE_ENABLE 0x00000002
  912. #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
  913. #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
  914. #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
  915. #define RCVLPC_STATUS 0x00002004
  916. #define RCVLPC_STATUS_CLASS0 0x00000004
  917. #define RCVLPC_STATUS_MAPOOR 0x00000008
  918. #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
  919. #define RCVLPC_LOCK 0x00002008
  920. #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
  921. #define RCVLPC_LOCK_REQ_SHIFT 0
  922. #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
  923. #define RCVLPC_LOCK_GRANT_SHIFT 16
  924. #define RCVLPC_NON_EMPTY_BITS 0x0000200c
  925. #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
  926. #define RCVLPC_CONFIG 0x00002010
  927. #define RCVLPC_STATSCTRL 0x00002014
  928. #define RCVLPC_STATSCTRL_ENABLE 0x00000001
  929. #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
  930. #define RCVLPC_STATS_ENABLE 0x00002018
  931. #define RCVLPC_STATSENAB_ASF_FIX 0x00000002
  932. #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
  933. #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
  934. #define RCVLPC_STATS_INCMASK 0x0000201c
  935. /* 0x2020 --> 0x2100 unused */
  936. #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
  937. #define SELLST_TAIL 0x00000004
  938. #define SELLST_CONT 0x00000008
  939. #define SELLST_UNUSED 0x0000000c
  940. #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
  941. #define RCVLPC_DROP_FILTER_CNT 0x00002240
  942. #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
  943. #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
  944. #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
  945. #define RCVLPC_IN_DISCARDS_CNT 0x00002250
  946. #define RCVLPC_IN_ERRORS_CNT 0x00002254
  947. #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
  948. /* 0x225c --> 0x2400 unused */
  949. /* Receive Data and Receive BD Initiator Control */
  950. #define RCVDBDI_MODE 0x00002400
  951. #define RCVDBDI_MODE_RESET 0x00000001
  952. #define RCVDBDI_MODE_ENABLE 0x00000002
  953. #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
  954. #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
  955. #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
  956. #define RCVDBDI_STATUS 0x00002404
  957. #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
  958. #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
  959. #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
  960. #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
  961. /* 0x240c --> 0x2440 unused */
  962. #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
  963. #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
  964. #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
  965. #define RCVDBDI_JUMBO_CON_IDX 0x00002470
  966. #define RCVDBDI_STD_CON_IDX 0x00002474
  967. #define RCVDBDI_MINI_CON_IDX 0x00002478
  968. /* 0x247c --> 0x2480 unused */
  969. #define RCVDBDI_BD_PROD_IDX_0 0x00002480
  970. #define RCVDBDI_BD_PROD_IDX_1 0x00002484
  971. #define RCVDBDI_BD_PROD_IDX_2 0x00002488
  972. #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
  973. #define RCVDBDI_BD_PROD_IDX_4 0x00002490
  974. #define RCVDBDI_BD_PROD_IDX_5 0x00002494
  975. #define RCVDBDI_BD_PROD_IDX_6 0x00002498
  976. #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
  977. #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
  978. #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
  979. #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
  980. #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
  981. #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
  982. #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
  983. #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
  984. #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
  985. #define RCVDBDI_HWDIAG 0x000024c0
  986. /* 0x24c4 --> 0x2800 unused */
  987. /* Receive Data Completion Control */
  988. #define RCVDCC_MODE 0x00002800
  989. #define RCVDCC_MODE_RESET 0x00000001
  990. #define RCVDCC_MODE_ENABLE 0x00000002
  991. #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
  992. /* 0x2804 --> 0x2c00 unused */
  993. /* Receive BD Initiator Control Registers */
  994. #define RCVBDI_MODE 0x00002c00
  995. #define RCVBDI_MODE_RESET 0x00000001
  996. #define RCVBDI_MODE_ENABLE 0x00000002
  997. #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
  998. #define RCVBDI_STATUS 0x00002c04
  999. #define RCVBDI_STATUS_RCB_ATTN 0x00000004
  1000. #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
  1001. #define RCVBDI_STD_PROD_IDX 0x00002c0c
  1002. #define RCVBDI_MINI_PROD_IDX 0x00002c10
  1003. #define RCVBDI_MINI_THRESH 0x00002c14
  1004. #define RCVBDI_STD_THRESH 0x00002c18
  1005. #define RCVBDI_JUMBO_THRESH 0x00002c1c
  1006. /* 0x2c20 --> 0x2d00 unused */
  1007. #define STD_REPLENISH_LWM 0x00002d00
  1008. #define JMB_REPLENISH_LWM 0x00002d04
  1009. /* 0x2d08 --> 0x3000 unused */
  1010. /* Receive BD Completion Control Registers */
  1011. #define RCVCC_MODE 0x00003000
  1012. #define RCVCC_MODE_RESET 0x00000001
  1013. #define RCVCC_MODE_ENABLE 0x00000002
  1014. #define RCVCC_MODE_ATTN_ENABLE 0x00000004
  1015. #define RCVCC_STATUS 0x00003004
  1016. #define RCVCC_STATUS_ERROR_ATTN 0x00000004
  1017. #define RCVCC_JUMP_PROD_IDX 0x00003008
  1018. #define RCVCC_STD_PROD_IDX 0x0000300c
  1019. #define RCVCC_MINI_PROD_IDX 0x00003010
  1020. /* 0x3014 --> 0x3400 unused */
  1021. /* Receive list selector control registers */
  1022. #define RCVLSC_MODE 0x00003400
  1023. #define RCVLSC_MODE_RESET 0x00000001
  1024. #define RCVLSC_MODE_ENABLE 0x00000002
  1025. #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
  1026. #define RCVLSC_STATUS 0x00003404
  1027. #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
  1028. /* 0x3408 --> 0x3600 unused */
  1029. /* CPMU registers */
  1030. #define TG3_CPMU_CTRL 0x00003600
  1031. #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
  1032. #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
  1033. #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
  1034. #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
  1035. #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
  1036. #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
  1037. #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
  1038. /* 0x3608 --> 0x360c unused */
  1039. #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
  1040. #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
  1041. #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
  1042. #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
  1043. #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
  1044. #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
  1045. #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
  1046. /* 0x3614 --> 0x361c unused */
  1047. #define TG3_CPMU_HST_ACC 0x0000361c
  1048. #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
  1049. #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
  1050. /* 0x3620 --> 0x3630 unused */
  1051. #define TG3_CPMU_CLCK_STAT 0x00003630
  1052. #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
  1053. #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
  1054. #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
  1055. #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
  1056. /* 0x3634 --> 0x365c unused */
  1057. #define TG3_CPMU_MUTEX_REQ 0x0000365c
  1058. #define CPMU_MUTEX_REQ_DRIVER 0x00001000
  1059. #define TG3_CPMU_MUTEX_GNT 0x00003660
  1060. #define CPMU_MUTEX_GNT_DRIVER 0x00001000
  1061. #define TG3_CPMU_PHY_STRAP 0x00003664
  1062. #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
  1063. /* 0x3664 --> 0x3800 unused */
  1064. /* Mbuf cluster free registers */
  1065. #define MBFREE_MODE 0x00003800
  1066. #define MBFREE_MODE_RESET 0x00000001
  1067. #define MBFREE_MODE_ENABLE 0x00000002
  1068. #define MBFREE_STATUS 0x00003804
  1069. /* 0x3808 --> 0x3c00 unused */
  1070. /* Host coalescing control registers */
  1071. #define HOSTCC_MODE 0x00003c00
  1072. #define HOSTCC_MODE_RESET 0x00000001
  1073. #define HOSTCC_MODE_ENABLE 0x00000002
  1074. #define HOSTCC_MODE_ATTN 0x00000004
  1075. #define HOSTCC_MODE_NOW 0x00000008
  1076. #define HOSTCC_MODE_FULL_STATUS 0x00000000
  1077. #define HOSTCC_MODE_64BYTE 0x00000080
  1078. #define HOSTCC_MODE_32BYTE 0x00000100
  1079. #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
  1080. #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
  1081. #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
  1082. #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
  1083. #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
  1084. #define HOSTCC_STATUS 0x00003c04
  1085. #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
  1086. #define HOSTCC_RXCOL_TICKS 0x00003c08
  1087. #define LOW_RXCOL_TICKS 0x00000032
  1088. #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
  1089. #define DEFAULT_RXCOL_TICKS 0x00000048
  1090. #define HIGH_RXCOL_TICKS 0x00000096
  1091. #define MAX_RXCOL_TICKS 0x000003ff
  1092. #define HOSTCC_TXCOL_TICKS 0x00003c0c
  1093. #define LOW_TXCOL_TICKS 0x00000096
  1094. #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
  1095. #define DEFAULT_TXCOL_TICKS 0x0000012c
  1096. #define HIGH_TXCOL_TICKS 0x00000145
  1097. #define MAX_TXCOL_TICKS 0x000003ff
  1098. #define HOSTCC_RXMAX_FRAMES 0x00003c10
  1099. #define LOW_RXMAX_FRAMES 0x00000005
  1100. #define DEFAULT_RXMAX_FRAMES 0x00000008
  1101. #define HIGH_RXMAX_FRAMES 0x00000012
  1102. #define MAX_RXMAX_FRAMES 0x000000ff
  1103. #define HOSTCC_TXMAX_FRAMES 0x00003c14
  1104. #define LOW_TXMAX_FRAMES 0x00000035
  1105. #define DEFAULT_TXMAX_FRAMES 0x0000004b
  1106. #define HIGH_TXMAX_FRAMES 0x00000052
  1107. #define MAX_TXMAX_FRAMES 0x000000ff
  1108. #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
  1109. #define DEFAULT_RXCOAL_TICK_INT 0x00000019
  1110. #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
  1111. #define MAX_RXCOAL_TICK_INT 0x000003ff
  1112. #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
  1113. #define DEFAULT_TXCOAL_TICK_INT 0x00000019
  1114. #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
  1115. #define MAX_TXCOAL_TICK_INT 0x000003ff
  1116. #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
  1117. #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
  1118. #define MAX_RXCOAL_MAXF_INT 0x000000ff
  1119. #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
  1120. #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
  1121. #define MAX_TXCOAL_MAXF_INT 0x000000ff
  1122. #define HOSTCC_STAT_COAL_TICKS 0x00003c28
  1123. #define DEFAULT_STAT_COAL_TICKS 0x000f4240
  1124. #define MAX_STAT_COAL_TICKS 0xd693d400
  1125. #define MIN_STAT_COAL_TICKS 0x00000064
  1126. /* 0x3c2c --> 0x3c30 unused */
  1127. #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
  1128. #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
  1129. #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
  1130. #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
  1131. #define HOSTCC_FLOW_ATTN 0x00003c48
  1132. /* 0x3c4c --> 0x3c50 unused */
  1133. #define HOSTCC_JUMBO_CON_IDX 0x00003c50
  1134. #define HOSTCC_STD_CON_IDX 0x00003c54
  1135. #define HOSTCC_MINI_CON_IDX 0x00003c58
  1136. /* 0x3c5c --> 0x3c80 unused */
  1137. #define HOSTCC_RET_PROD_IDX_0 0x00003c80
  1138. #define HOSTCC_RET_PROD_IDX_1 0x00003c84
  1139. #define HOSTCC_RET_PROD_IDX_2 0x00003c88
  1140. #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
  1141. #define HOSTCC_RET_PROD_IDX_4 0x00003c90
  1142. #define HOSTCC_RET_PROD_IDX_5 0x00003c94
  1143. #define HOSTCC_RET_PROD_IDX_6 0x00003c98
  1144. #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
  1145. #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
  1146. #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
  1147. #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
  1148. #define HOSTCC_RET_PROD_IDX_11 0x00003cac
  1149. #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
  1150. #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
  1151. #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
  1152. #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
  1153. #define HOSTCC_SND_CON_IDX_0 0x00003cc0
  1154. #define HOSTCC_SND_CON_IDX_1 0x00003cc4
  1155. #define HOSTCC_SND_CON_IDX_2 0x00003cc8
  1156. #define HOSTCC_SND_CON_IDX_3 0x00003ccc
  1157. #define HOSTCC_SND_CON_IDX_4 0x00003cd0
  1158. #define HOSTCC_SND_CON_IDX_5 0x00003cd4
  1159. #define HOSTCC_SND_CON_IDX_6 0x00003cd8
  1160. #define HOSTCC_SND_CON_IDX_7 0x00003cdc
  1161. #define HOSTCC_SND_CON_IDX_8 0x00003ce0
  1162. #define HOSTCC_SND_CON_IDX_9 0x00003ce4
  1163. #define HOSTCC_SND_CON_IDX_10 0x00003ce8
  1164. #define HOSTCC_SND_CON_IDX_11 0x00003cec
  1165. #define HOSTCC_SND_CON_IDX_12 0x00003cf0
  1166. #define HOSTCC_SND_CON_IDX_13 0x00003cf4
  1167. #define HOSTCC_SND_CON_IDX_14 0x00003cf8
  1168. #define HOSTCC_SND_CON_IDX_15 0x00003cfc
  1169. #define HOSTCC_STATBLCK_RING1 0x00003d00
  1170. /* 0x3d00 --> 0x3d80 unused */
  1171. #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
  1172. #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
  1173. #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
  1174. #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
  1175. #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
  1176. #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
  1177. /* 0x3d98 --> 0x4000 unused */
  1178. /* Memory arbiter control registers */
  1179. #define MEMARB_MODE 0x00004000
  1180. #define MEMARB_MODE_RESET 0x00000001
  1181. #define MEMARB_MODE_ENABLE 0x00000002
  1182. #define MEMARB_STATUS 0x00004004
  1183. #define MEMARB_TRAP_ADDR_LOW 0x00004008
  1184. #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
  1185. /* 0x4010 --> 0x4400 unused */
  1186. /* Buffer manager control registers */
  1187. #define BUFMGR_MODE 0x00004400
  1188. #define BUFMGR_MODE_RESET 0x00000001
  1189. #define BUFMGR_MODE_ENABLE 0x00000002
  1190. #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
  1191. #define BUFMGR_MODE_BM_TEST 0x00000008
  1192. #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
  1193. #define BUFMGR_STATUS 0x00004404
  1194. #define BUFMGR_STATUS_ERROR 0x00000004
  1195. #define BUFMGR_STATUS_MBLOW 0x00000010
  1196. #define BUFMGR_MB_POOL_ADDR 0x00004408
  1197. #define BUFMGR_MB_POOL_SIZE 0x0000440c
  1198. #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
  1199. #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
  1200. #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
  1201. #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
  1202. #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
  1203. #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
  1204. #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
  1205. #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
  1206. #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
  1207. #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
  1208. #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
  1209. #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
  1210. #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
  1211. #define BUFMGR_MB_HIGH_WATER 0x00004418
  1212. #define DEFAULT_MB_HIGH_WATER 0x00000060
  1213. #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
  1214. #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
  1215. #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
  1216. #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
  1217. #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
  1218. #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
  1219. #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
  1220. #define BUFMGR_MB_ALLOC_BIT 0x10000000
  1221. #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
  1222. #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
  1223. #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
  1224. #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
  1225. #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
  1226. #define BUFMGR_DMA_LOW_WATER 0x00004434
  1227. #define DEFAULT_DMA_LOW_WATER 0x00000005
  1228. #define BUFMGR_DMA_HIGH_WATER 0x00004438
  1229. #define DEFAULT_DMA_HIGH_WATER 0x0000000a
  1230. #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
  1231. #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
  1232. #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
  1233. #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
  1234. #define BUFMGR_HWDIAG_0 0x0000444c
  1235. #define BUFMGR_HWDIAG_1 0x00004450
  1236. #define BUFMGR_HWDIAG_2 0x00004454
  1237. /* 0x4458 --> 0x4800 unused */
  1238. /* Read DMA control registers */
  1239. #define RDMAC_MODE 0x00004800
  1240. #define RDMAC_MODE_RESET 0x00000001
  1241. #define RDMAC_MODE_ENABLE 0x00000002
  1242. #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
  1243. #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
  1244. #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
  1245. #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
  1246. #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
  1247. #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
  1248. #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
  1249. #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
  1250. #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
  1251. #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
  1252. #define RDMAC_MODE_SPLIT_RESET 0x00001000
  1253. #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
  1254. #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
  1255. #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
  1256. #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
  1257. #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
  1258. #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
  1259. #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
  1260. #define RDMAC_STATUS 0x00004804
  1261. #define RDMAC_STATUS_TGTABORT 0x00000004
  1262. #define RDMAC_STATUS_MSTABORT 0x00000008
  1263. #define RDMAC_STATUS_PARITYERR 0x00000010
  1264. #define RDMAC_STATUS_ADDROFLOW 0x00000020
  1265. #define RDMAC_STATUS_FIFOOFLOW 0x00000040
  1266. #define RDMAC_STATUS_FIFOURUN 0x00000080
  1267. #define RDMAC_STATUS_FIFOOREAD 0x00000100
  1268. #define RDMAC_STATUS_LNGREAD 0x00000200
  1269. /* 0x4808 --> 0x4c00 unused */
  1270. /* Write DMA control registers */
  1271. #define WDMAC_MODE 0x00004c00
  1272. #define WDMAC_MODE_RESET 0x00000001
  1273. #define WDMAC_MODE_ENABLE 0x00000002
  1274. #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
  1275. #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
  1276. #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
  1277. #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
  1278. #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
  1279. #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
  1280. #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
  1281. #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
  1282. #define WDMAC_MODE_RX_ACCEL 0x00000400
  1283. #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
  1284. #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
  1285. #define WDMAC_STATUS 0x00004c04
  1286. #define WDMAC_STATUS_TGTABORT 0x00000004
  1287. #define WDMAC_STATUS_MSTABORT 0x00000008
  1288. #define WDMAC_STATUS_PARITYERR 0x00000010
  1289. #define WDMAC_STATUS_ADDROFLOW 0x00000020
  1290. #define WDMAC_STATUS_FIFOOFLOW 0x00000040
  1291. #define WDMAC_STATUS_FIFOURUN 0x00000080
  1292. #define WDMAC_STATUS_FIFOOREAD 0x00000100
  1293. #define WDMAC_STATUS_LNGREAD 0x00000200
  1294. /* 0x4c08 --> 0x5000 unused */
  1295. /* Per-cpu register offsets (arm9) */
  1296. #define CPU_MODE 0x00000000
  1297. #define CPU_MODE_RESET 0x00000001
  1298. #define CPU_MODE_HALT 0x00000400
  1299. #define CPU_STATE 0x00000004
  1300. #define CPU_EVTMASK 0x00000008
  1301. /* 0xc --> 0x1c reserved */
  1302. #define CPU_PC 0x0000001c
  1303. #define CPU_INSN 0x00000020
  1304. #define CPU_SPAD_UFLOW 0x00000024
  1305. #define CPU_WDOG_CLEAR 0x00000028
  1306. #define CPU_WDOG_VECTOR 0x0000002c
  1307. #define CPU_WDOG_PC 0x00000030
  1308. #define CPU_HW_BP 0x00000034
  1309. /* 0x38 --> 0x44 unused */
  1310. #define CPU_WDOG_SAVED_STATE 0x00000044
  1311. #define CPU_LAST_BRANCH_ADDR 0x00000048
  1312. #define CPU_SPAD_UFLOW_SET 0x0000004c
  1313. /* 0x50 --> 0x200 unused */
  1314. #define CPU_R0 0x00000200
  1315. #define CPU_R1 0x00000204
  1316. #define CPU_R2 0x00000208
  1317. #define CPU_R3 0x0000020c
  1318. #define CPU_R4 0x00000210
  1319. #define CPU_R5 0x00000214
  1320. #define CPU_R6 0x00000218
  1321. #define CPU_R7 0x0000021c
  1322. #define CPU_R8 0x00000220
  1323. #define CPU_R9 0x00000224
  1324. #define CPU_R10 0x00000228
  1325. #define CPU_R11 0x0000022c
  1326. #define CPU_R12 0x00000230
  1327. #define CPU_R13 0x00000234
  1328. #define CPU_R14 0x00000238
  1329. #define CPU_R15 0x0000023c
  1330. #define CPU_R16 0x00000240
  1331. #define CPU_R17 0x00000244
  1332. #define CPU_R18 0x00000248
  1333. #define CPU_R19 0x0000024c
  1334. #define CPU_R20 0x00000250
  1335. #define CPU_R21 0x00000254
  1336. #define CPU_R22 0x00000258
  1337. #define CPU_R23 0x0000025c
  1338. #define CPU_R24 0x00000260
  1339. #define CPU_R25 0x00000264
  1340. #define CPU_R26 0x00000268
  1341. #define CPU_R27 0x0000026c
  1342. #define CPU_R28 0x00000270
  1343. #define CPU_R29 0x00000274
  1344. #define CPU_R30 0x00000278
  1345. #define CPU_R31 0x0000027c
  1346. /* 0x280 --> 0x400 unused */
  1347. #define RX_CPU_BASE 0x00005000
  1348. #define RX_CPU_MODE 0x00005000
  1349. #define RX_CPU_STATE 0x00005004
  1350. #define RX_CPU_PGMCTR 0x0000501c
  1351. #define RX_CPU_HWBKPT 0x00005034
  1352. #define TX_CPU_BASE 0x00005400
  1353. #define TX_CPU_MODE 0x00005400
  1354. #define TX_CPU_STATE 0x00005404
  1355. #define TX_CPU_PGMCTR 0x0000541c
  1356. #define VCPU_STATUS 0x00005100
  1357. #define VCPU_STATUS_INIT_DONE 0x04000000
  1358. #define VCPU_STATUS_DRV_RESET 0x08000000
  1359. #define VCPU_CFGSHDW 0x00005104
  1360. #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
  1361. #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
  1362. #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
  1363. /* Mailboxes */
  1364. #define GRCMBOX_BASE 0x00005600
  1365. #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
  1366. #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
  1367. #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
  1368. #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
  1369. #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
  1370. #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
  1371. #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
  1372. #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
  1373. #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
  1374. #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
  1375. #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
  1376. #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
  1377. #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
  1378. #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
  1379. #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
  1380. #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
  1381. #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
  1382. #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
  1383. #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
  1384. #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
  1385. #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
  1386. #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
  1387. #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
  1388. #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
  1389. #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
  1390. #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
  1391. #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
  1392. #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
  1393. #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
  1394. #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
  1395. #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
  1396. #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
  1397. #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
  1398. #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
  1399. #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
  1400. #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
  1401. #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
  1402. #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
  1403. #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
  1404. #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
  1405. #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
  1406. #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
  1407. #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
  1408. #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
  1409. #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
  1410. #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
  1411. #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
  1412. #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
  1413. #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
  1414. #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
  1415. #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
  1416. #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
  1417. #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
  1418. #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
  1419. #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
  1420. #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
  1421. #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
  1422. #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
  1423. #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
  1424. #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
  1425. #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
  1426. #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
  1427. #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
  1428. #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
  1429. #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
  1430. #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
  1431. #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
  1432. #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
  1433. /* 0x5a10 --> 0x5c00 */
  1434. /* Flow Through queues */
  1435. #define FTQ_RESET 0x00005c00
  1436. /* 0x5c04 --> 0x5c10 unused */
  1437. #define FTQ_DMA_NORM_READ_CTL 0x00005c10
  1438. #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
  1439. #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
  1440. #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
  1441. #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
  1442. #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
  1443. #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
  1444. #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
  1445. #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
  1446. #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
  1447. #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
  1448. #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
  1449. #define FTQ_SEND_BD_COMP_CTL 0x00005c40
  1450. #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
  1451. #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
  1452. #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
  1453. #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
  1454. #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
  1455. #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
  1456. #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
  1457. #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
  1458. #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
  1459. #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
  1460. #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
  1461. #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
  1462. #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
  1463. #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
  1464. #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
  1465. #define FTQ_SWTYPE1_CTL 0x00005c80
  1466. #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
  1467. #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
  1468. #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
  1469. #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
  1470. #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
  1471. #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
  1472. #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
  1473. #define FTQ_HOST_COAL_CTL 0x00005ca0
  1474. #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
  1475. #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
  1476. #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
  1477. #define FTQ_MAC_TX_CTL 0x00005cb0
  1478. #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
  1479. #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
  1480. #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
  1481. #define FTQ_MB_FREE_CTL 0x00005cc0
  1482. #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
  1483. #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
  1484. #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
  1485. #define FTQ_RCVBD_COMP_CTL 0x00005cd0
  1486. #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
  1487. #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
  1488. #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
  1489. #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
  1490. #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
  1491. #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
  1492. #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
  1493. #define FTQ_RCVDATA_INI_CTL 0x00005cf0
  1494. #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
  1495. #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
  1496. #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
  1497. #define FTQ_RCVDATA_COMP_CTL 0x00005d00
  1498. #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
  1499. #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
  1500. #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
  1501. #define FTQ_SWTYPE2_CTL 0x00005d10
  1502. #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
  1503. #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
  1504. #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
  1505. /* 0x5d20 --> 0x6000 unused */
  1506. /* Message signaled interrupt registers */
  1507. #define MSGINT_MODE 0x00006000
  1508. #define MSGINT_MODE_RESET 0x00000001
  1509. #define MSGINT_MODE_ENABLE 0x00000002
  1510. #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
  1511. #define MSGINT_MODE_MULTIVEC_EN 0x00000080
  1512. #define MSGINT_STATUS 0x00006004
  1513. #define MSGINT_FIFO 0x00006008
  1514. /* 0x600c --> 0x6400 unused */
  1515. /* DMA completion registers */
  1516. #define DMAC_MODE 0x00006400
  1517. #define DMAC_MODE_RESET 0x00000001
  1518. #define DMAC_MODE_ENABLE 0x00000002
  1519. /* 0x6404 --> 0x6800 unused */
  1520. /* GRC registers */
  1521. #define GRC_MODE 0x00006800
  1522. #define GRC_MODE_UPD_ON_COAL 0x00000001
  1523. #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
  1524. #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
  1525. #define GRC_MODE_BSWAP_DATA 0x00000010
  1526. #define GRC_MODE_WSWAP_DATA 0x00000020
  1527. #define GRC_MODE_SPLITHDR 0x00000100
  1528. #define GRC_MODE_NOFRM_CRACKING 0x00000200
  1529. #define GRC_MODE_INCL_CRC 0x00000400
  1530. #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
  1531. #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
  1532. #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
  1533. #define GRC_MODE_FORCE_PCI32BIT 0x00008000
  1534. #define GRC_MODE_HOST_STACKUP 0x00010000
  1535. #define GRC_MODE_HOST_SENDBDS 0x00020000
  1536. #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
  1537. #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
  1538. #define GRC_MODE_PCIE_TL_SEL 0x00000000
  1539. #define GRC_MODE_PCIE_PL_SEL 0x00400000
  1540. #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
  1541. #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
  1542. #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
  1543. #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
  1544. #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
  1545. #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
  1546. #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
  1547. #define GRC_MODE_PCIE_DL_SEL 0x20000000
  1548. #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
  1549. #define GRC_MODE_PCIE_HI_1K_EN 0x80000000
  1550. #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
  1551. GRC_MODE_PCIE_PL_SEL | \
  1552. GRC_MODE_PCIE_DL_SEL | \
  1553. GRC_MODE_PCIE_HI_1K_EN)
  1554. #define GRC_MISC_CFG 0x00006804
  1555. #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
  1556. #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
  1557. #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
  1558. #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
  1559. #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
  1560. #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
  1561. #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
  1562. #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
  1563. #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
  1564. #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
  1565. #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
  1566. #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
  1567. #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
  1568. #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
  1569. #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
  1570. #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
  1571. #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
  1572. #define GRC_LOCAL_CTRL 0x00006808
  1573. #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
  1574. #define GRC_LCLCTRL_CLEARINT 0x00000002
  1575. #define GRC_LCLCTRL_SETINT 0x00000004
  1576. #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
  1577. #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
  1578. #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
  1579. #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
  1580. #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
  1581. #define GRC_LCLCTRL_GPIO_OE3 0x00000040
  1582. #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
  1583. #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
  1584. #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
  1585. #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
  1586. #define GRC_LCLCTRL_GPIO_OE0 0x00000800
  1587. #define GRC_LCLCTRL_GPIO_OE1 0x00001000
  1588. #define GRC_LCLCTRL_GPIO_OE2 0x00002000
  1589. #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
  1590. #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
  1591. #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
  1592. #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
  1593. #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
  1594. #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
  1595. #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
  1596. #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
  1597. #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
  1598. #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
  1599. #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
  1600. #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
  1601. #define GRC_LCLCTRL_BANK_SELECT 0x00200000
  1602. #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
  1603. #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
  1604. #define GRC_TIMER 0x0000680c
  1605. #define GRC_RX_CPU_EVENT 0x00006810
  1606. #define GRC_RX_CPU_DRIVER_EVENT 0x00004000
  1607. #define GRC_RX_TIMER_REF 0x00006814
  1608. #define GRC_RX_CPU_SEM 0x00006818
  1609. #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
  1610. #define GRC_TX_CPU_EVENT 0x00006820
  1611. #define GRC_TX_TIMER_REF 0x00006824
  1612. #define GRC_TX_CPU_SEM 0x00006828
  1613. #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
  1614. #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
  1615. #define GRC_EEPROM_ADDR 0x00006838
  1616. #define EEPROM_ADDR_WRITE 0x00000000
  1617. #define EEPROM_ADDR_READ 0x80000000
  1618. #define EEPROM_ADDR_COMPLETE 0x40000000
  1619. #define EEPROM_ADDR_FSM_RESET 0x20000000
  1620. #define EEPROM_ADDR_DEVID_MASK 0x1c000000
  1621. #define EEPROM_ADDR_DEVID_SHIFT 26
  1622. #define EEPROM_ADDR_START 0x02000000
  1623. #define EEPROM_ADDR_CLKPERD_SHIFT 16
  1624. #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
  1625. #define EEPROM_ADDR_ADDR_SHIFT 0
  1626. #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
  1627. #define EEPROM_CHIP_SIZE (64 * 1024)
  1628. #define GRC_EEPROM_DATA 0x0000683c
  1629. #define GRC_EEPROM_CTRL 0x00006840
  1630. #define GRC_MDI_CTRL 0x00006844
  1631. #define GRC_SEEPROM_DELAY 0x00006848
  1632. /* 0x684c --> 0x6890 unused */
  1633. #define GRC_VCPU_EXT_CTRL 0x00006890
  1634. #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
  1635. #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
  1636. #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
  1637. /* 0x6c00 --> 0x7000 unused */
  1638. /* NVRAM Control registers */
  1639. #define NVRAM_CMD 0x00007000
  1640. #define NVRAM_CMD_RESET 0x00000001
  1641. #define NVRAM_CMD_DONE 0x00000008
  1642. #define NVRAM_CMD_GO 0x00000010
  1643. #define NVRAM_CMD_WR 0x00000020
  1644. #define NVRAM_CMD_RD 0x00000000
  1645. #define NVRAM_CMD_ERASE 0x00000040
  1646. #define NVRAM_CMD_FIRST 0x00000080
  1647. #define NVRAM_CMD_LAST 0x00000100
  1648. #define NVRAM_CMD_WREN 0x00010000
  1649. #define NVRAM_CMD_WRDI 0x00020000
  1650. #define NVRAM_STAT 0x00007004
  1651. #define NVRAM_WRDATA 0x00007008
  1652. #define NVRAM_ADDR 0x0000700c
  1653. #define NVRAM_ADDR_MSK 0x00ffffff
  1654. #define NVRAM_RDDATA 0x00007010
  1655. #define NVRAM_CFG1 0x00007014
  1656. #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
  1657. #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
  1658. #define NVRAM_CFG1_PASS_THRU 0x00000004
  1659. #define NVRAM_CFG1_STATUS_BITS 0x00000070
  1660. #define NVRAM_CFG1_BIT_BANG 0x00000008
  1661. #define NVRAM_CFG1_FLASH_SIZE 0x02000000
  1662. #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
  1663. #define NVRAM_CFG1_VENDOR_MASK 0x03000003
  1664. #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
  1665. #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
  1666. #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
  1667. #define FLASH_VENDOR_ST 0x03000001
  1668. #define FLASH_VENDOR_SAIFUN 0x01000003
  1669. #define FLASH_VENDOR_SST_SMALL 0x00000001
  1670. #define FLASH_VENDOR_SST_LARGE 0x02000001
  1671. #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
  1672. #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
  1673. #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
  1674. #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
  1675. #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
  1676. #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
  1677. #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
  1678. #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
  1679. #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
  1680. #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
  1681. #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
  1682. #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
  1683. #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
  1684. #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
  1685. #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
  1686. #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
  1687. #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
  1688. #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
  1689. #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
  1690. #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
  1691. #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
  1692. #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
  1693. #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
  1694. #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
  1695. #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
  1696. #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
  1697. #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
  1698. #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
  1699. #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
  1700. #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
  1701. #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
  1702. #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
  1703. #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
  1704. #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
  1705. #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
  1706. #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
  1707. #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
  1708. #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
  1709. #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
  1710. #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
  1711. #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
  1712. #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
  1713. #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
  1714. #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
  1715. #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
  1716. #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
  1717. #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
  1718. #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
  1719. #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
  1720. #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
  1721. #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
  1722. #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
  1723. #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
  1724. #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
  1725. #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
  1726. #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
  1727. #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
  1728. #define FLASH_5717VENDOR_ST_25USPT 0x03400002
  1729. #define FLASH_5717VENDOR_ST_45USPT 0x03400001
  1730. #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
  1731. #define FLASH_5752PAGE_SIZE_256 0x00000000
  1732. #define FLASH_5752PAGE_SIZE_512 0x10000000
  1733. #define FLASH_5752PAGE_SIZE_1K 0x20000000
  1734. #define FLASH_5752PAGE_SIZE_2K 0x30000000
  1735. #define FLASH_5752PAGE_SIZE_4K 0x40000000
  1736. #define FLASH_5752PAGE_SIZE_264 0x50000000
  1737. #define FLASH_5752PAGE_SIZE_528 0x60000000
  1738. #define NVRAM_CFG2 0x00007018
  1739. #define NVRAM_CFG3 0x0000701c
  1740. #define NVRAM_SWARB 0x00007020
  1741. #define SWARB_REQ_SET0 0x00000001
  1742. #define SWARB_REQ_SET1 0x00000002
  1743. #define SWARB_REQ_SET2 0x00000004
  1744. #define SWARB_REQ_SET3 0x00000008
  1745. #define SWARB_REQ_CLR0 0x00000010
  1746. #define SWARB_REQ_CLR1 0x00000020
  1747. #define SWARB_REQ_CLR2 0x00000040
  1748. #define SWARB_REQ_CLR3 0x00000080
  1749. #define SWARB_GNT0 0x00000100
  1750. #define SWARB_GNT1 0x00000200
  1751. #define SWARB_GNT2 0x00000400
  1752. #define SWARB_GNT3 0x00000800
  1753. #define SWARB_REQ0 0x00001000
  1754. #define SWARB_REQ1 0x00002000
  1755. #define SWARB_REQ2 0x00004000
  1756. #define SWARB_REQ3 0x00008000
  1757. #define NVRAM_ACCESS 0x00007024
  1758. #define ACCESS_ENABLE 0x00000001
  1759. #define ACCESS_WR_ENABLE 0x00000002
  1760. #define NVRAM_WRITE1 0x00007028
  1761. /* 0x702c unused */
  1762. #define NVRAM_ADDR_LOCKOUT 0x00007030
  1763. /* 0x7034 --> 0x7500 unused */
  1764. #define OTP_MODE 0x00007500
  1765. #define OTP_MODE_OTP_THRU_GRC 0x00000001
  1766. #define OTP_CTRL 0x00007504
  1767. #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
  1768. #define OTP_CTRL_OTP_CMD_READ 0x00000000
  1769. #define OTP_CTRL_OTP_CMD_INIT 0x00000008
  1770. #define OTP_CTRL_OTP_CMD_START 0x00000001
  1771. #define OTP_STATUS 0x00007508
  1772. #define OTP_STATUS_CMD_DONE 0x00000001
  1773. #define OTP_ADDRESS 0x0000750c
  1774. #define OTP_ADDRESS_MAGIC1 0x000000a0
  1775. #define OTP_ADDRESS_MAGIC2 0x00000080
  1776. /* 0x7510 unused */
  1777. #define OTP_READ_DATA 0x00007514
  1778. /* 0x7518 --> 0x7c04 unused */
  1779. #define PCIE_TRANSACTION_CFG 0x00007c04
  1780. #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
  1781. #define PCIE_TRANS_CFG_LOM 0x00000020
  1782. /* 0x7c08 --> 0x7d28 unused */
  1783. #define PCIE_PWR_MGMT_THRESH 0x00007d28
  1784. #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
  1785. #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
  1786. #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
  1787. /* 0x7d2c --> 0x7d54 unused */
  1788. #define TG3_PCIE_LNKCTL 0x00007d54
  1789. #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
  1790. #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
  1791. /* 0x7d58 --> 0x7e70 unused */
  1792. #define TG3_PCIE_PHY_TSTCTL 0x00007e2c
  1793. #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
  1794. #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
  1795. #define TG3_PCIE_EIDLE_DELAY 0x00007e70
  1796. #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
  1797. #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
  1798. /* 0x7e74 --> 0x8000 unused */
  1799. /* Alternate PCIE definitions */
  1800. #define TG3_PCIE_TLDLPL_PORT 0x00007c00
  1801. #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
  1802. #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
  1803. #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
  1804. #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
  1805. /* OTP bit definitions */
  1806. #define TG3_OTP_AGCTGT_MASK 0x000000e0
  1807. #define TG3_OTP_AGCTGT_SHIFT 1
  1808. #define TG3_OTP_HPFFLTR_MASK 0x00000300
  1809. #define TG3_OTP_HPFFLTR_SHIFT 1
  1810. #define TG3_OTP_HPFOVER_MASK 0x00000400
  1811. #define TG3_OTP_HPFOVER_SHIFT 1
  1812. #define TG3_OTP_LPFDIS_MASK 0x00000800
  1813. #define TG3_OTP_LPFDIS_SHIFT 11
  1814. #define TG3_OTP_VDAC_MASK 0xff000000
  1815. #define TG3_OTP_VDAC_SHIFT 24
  1816. #define TG3_OTP_10BTAMP_MASK 0x0000f000
  1817. #define TG3_OTP_10BTAMP_SHIFT 8
  1818. #define TG3_OTP_ROFF_MASK 0x00e00000
  1819. #define TG3_OTP_ROFF_SHIFT 11
  1820. #define TG3_OTP_RCOFF_MASK 0x001c0000
  1821. #define TG3_OTP_RCOFF_SHIFT 16
  1822. #define TG3_OTP_DEFAULT 0x286c1640
  1823. /* Hardware Legacy NVRAM layout */
  1824. #define TG3_NVM_VPD_OFF 0x100
  1825. #define TG3_NVM_VPD_LEN 256
  1826. /* Hardware Selfboot NVRAM layout */
  1827. #define TG3_NVM_HWSB_CFG1 0x00000004
  1828. #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
  1829. #define TG3_NVM_HWSB_CFG1_MAJSFT 27
  1830. #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
  1831. #define TG3_NVM_HWSB_CFG1_MINSFT 22
  1832. #define TG3_EEPROM_MAGIC 0x669955aa
  1833. #define TG3_EEPROM_MAGIC_FW 0xa5000000
  1834. #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
  1835. #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
  1836. #define TG3_EEPROM_SB_FORMAT_1 0x00200000
  1837. #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
  1838. #define TG3_EEPROM_SB_REVISION_0 0x00000000
  1839. #define TG3_EEPROM_SB_REVISION_2 0x00020000
  1840. #define TG3_EEPROM_SB_REVISION_3 0x00030000
  1841. #define TG3_EEPROM_SB_REVISION_4 0x00040000
  1842. #define TG3_EEPROM_SB_REVISION_5 0x00050000
  1843. #define TG3_EEPROM_MAGIC_HW 0xabcd
  1844. #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
  1845. #define TG3_NVM_DIR_START 0x18
  1846. #define TG3_NVM_DIR_END 0x78
  1847. #define TG3_NVM_DIRENT_SIZE 0xc
  1848. #define TG3_NVM_DIRTYPE_SHIFT 24
  1849. #define TG3_NVM_DIRTYPE_ASFINI 1
  1850. #define TG3_NVM_PTREV_BCVER 0x94
  1851. #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
  1852. #define TG3_NVM_BCVER_MAJSFT 8
  1853. #define TG3_NVM_BCVER_MINMSK 0x000000ff
  1854. #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
  1855. #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
  1856. #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
  1857. #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
  1858. #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
  1859. #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
  1860. #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
  1861. #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
  1862. #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
  1863. #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
  1864. #define TG3_EEPROM_SB_EDH_BLD_SHFT 11
  1865. /* 32K Window into NIC internal memory */
  1866. #define NIC_SRAM_WIN_BASE 0x00008000
  1867. /* Offsets into first 32k of NIC internal memory. */
  1868. #define NIC_SRAM_PAGE_ZERO 0x00000000
  1869. #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
  1870. #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
  1871. #define NIC_SRAM_STATS_BLK 0x00000300
  1872. #define NIC_SRAM_STATUS_BLK 0x00000b00
  1873. #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
  1874. #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
  1875. #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
  1876. #define NIC_SRAM_DATA_SIG 0x00000b54
  1877. #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
  1878. #define NIC_SRAM_DATA_CFG 0x00000b58
  1879. #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
  1880. #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
  1881. #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
  1882. #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
  1883. #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
  1884. #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
  1885. #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
  1886. #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
  1887. #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
  1888. #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
  1889. #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
  1890. #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
  1891. #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
  1892. #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
  1893. #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
  1894. #define NIC_SRAM_DATA_VER 0x00000b5c
  1895. #define NIC_SRAM_DATA_VER_SHIFT 16
  1896. #define NIC_SRAM_DATA_PHY_ID 0x00000b74
  1897. #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
  1898. #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
  1899. #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
  1900. #define FWCMD_NICDRV_ALIVE 0x00000001
  1901. #define FWCMD_NICDRV_PAUSE_FW 0x00000002
  1902. #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
  1903. #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
  1904. #define FWCMD_NICDRV_FIX_DMAR 0x00000005
  1905. #define FWCMD_NICDRV_FIX_DMAW 0x00000006
  1906. #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
  1907. #define FWCMD_NICDRV_ALIVE2 0x0000000d
  1908. #define FWCMD_NICDRV_ALIVE3 0x0000000e
  1909. #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
  1910. #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
  1911. #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
  1912. #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
  1913. #define DRV_STATE_START 0x00000001
  1914. #define DRV_STATE_START_DONE 0x80000001
  1915. #define DRV_STATE_UNLOAD 0x00000002
  1916. #define DRV_STATE_UNLOAD_DONE 0x80000002
  1917. #define DRV_STATE_WOL 0x00000003
  1918. #define DRV_STATE_SUSPEND 0x00000004
  1919. #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
  1920. #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
  1921. #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
  1922. #define NIC_SRAM_WOL_MBOX 0x00000d30
  1923. #define WOL_SIGNATURE 0x474c0000
  1924. #define WOL_DRV_STATE_SHUTDOWN 0x00000001
  1925. #define WOL_DRV_WOL 0x00000002
  1926. #define WOL_SET_MAGIC_PKT 0x00000004
  1927. #define NIC_SRAM_DATA_CFG_2 0x00000d38
  1928. #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
  1929. #define SHASTA_EXT_LED_MODE_MASK 0x00018000
  1930. #define SHASTA_EXT_LED_LEGACY 0x00000000
  1931. #define SHASTA_EXT_LED_SHARED 0x00008000
  1932. #define SHASTA_EXT_LED_MAC 0x00010000
  1933. #define SHASTA_EXT_LED_COMBO 0x00018000
  1934. #define NIC_SRAM_DATA_CFG_3 0x00000d3c
  1935. #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
  1936. #define NIC_SRAM_DATA_CFG_4 0x00000d60
  1937. #define NIC_SRAM_GMII_MODE 0x00000002
  1938. #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
  1939. #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
  1940. #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
  1941. #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
  1942. #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
  1943. #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
  1944. #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
  1945. #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
  1946. #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
  1947. #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
  1948. #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
  1949. #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
  1950. #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
  1951. #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
  1952. /* Currently this is fixed. */
  1953. #define TG3_PHY_MII_ADDR 0x01
  1954. /*** Tigon3 specific PHY MII registers. ***/
  1955. #define TG3_BMCR_SPEED1000 0x0040
  1956. #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
  1957. #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
  1958. #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
  1959. #define MII_TG3_CTRL_AS_MASTER 0x0800
  1960. #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
  1961. #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
  1962. #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
  1963. #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
  1964. #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
  1965. #define MII_TG3_EXT_CTRL_TBI 0x8000
  1966. #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
  1967. #define MII_TG3_EXT_STAT_LPASS 0x0100
  1968. #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
  1969. #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
  1970. #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
  1971. #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
  1972. #define MII_TG3_DSP_TAP1 0x0001
  1973. #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
  1974. #define MII_TG3_DSP_AADJ1CH0 0x001f
  1975. #define MII_TG3_DSP_AADJ1CH3 0x601f
  1976. #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
  1977. #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
  1978. #define MII_TG3_DSP_EXP8 0x0f08
  1979. #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
  1980. #define MII_TG3_DSP_EXP8_AEDW 0x0200
  1981. #define MII_TG3_DSP_EXP75 0x0f75
  1982. #define MII_TG3_DSP_EXP96 0x0f96
  1983. #define MII_TG3_DSP_EXP97 0x0f97
  1984. #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
  1985. #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
  1986. #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
  1987. #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
  1988. #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
  1989. #define MII_TG3_AUXCTL_MISC_WREN 0x8000
  1990. #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
  1991. #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
  1992. #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
  1993. #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
  1994. #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
  1995. #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
  1996. #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
  1997. #define MII_TG3_AUX_STAT_LPASS 0x0004
  1998. #define MII_TG3_AUX_STAT_SPDMASK 0x0700
  1999. #define MII_TG3_AUX_STAT_10HALF 0x0100
  2000. #define MII_TG3_AUX_STAT_10FULL 0x0200
  2001. #define MII_TG3_AUX_STAT_100HALF 0x0300
  2002. #define MII_TG3_AUX_STAT_100_4 0x0400
  2003. #define MII_TG3_AUX_STAT_100FULL 0x0500
  2004. #define MII_TG3_AUX_STAT_1000HALF 0x0600
  2005. #define MII_TG3_AUX_STAT_1000FULL 0x0700
  2006. #define MII_TG3_AUX_STAT_100 0x0008
  2007. #define MII_TG3_AUX_STAT_FULL 0x0001
  2008. #define MII_TG3_ISTAT 0x1a /* IRQ status register */
  2009. #define MII_TG3_IMASK 0x1b /* IRQ mask register */
  2010. /* ISTAT/IMASK event bits */
  2011. #define MII_TG3_INT_LINKCHG 0x0002
  2012. #define MII_TG3_INT_SPEEDCHG 0x0004
  2013. #define MII_TG3_INT_DUPLEXCHG 0x0008
  2014. #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
  2015. #define MII_TG3_MISC_SHDW 0x1c
  2016. #define MII_TG3_MISC_SHDW_WREN 0x8000
  2017. #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
  2018. #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
  2019. #define MII_TG3_MISC_SHDW_APD_SEL 0x2800
  2020. #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
  2021. #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
  2022. #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
  2023. #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
  2024. #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
  2025. #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
  2026. #define MII_TG3_TEST1 0x1e
  2027. #define MII_TG3_TEST1_TRIM_EN 0x0010
  2028. #define MII_TG3_TEST1_CRC_EN 0x8000
  2029. /* Fast Ethernet Tranceiver definitions */
  2030. #define MII_TG3_FET_PTEST 0x17
  2031. #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
  2032. #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
  2033. #define MII_TG3_FET_TEST 0x1f
  2034. #define MII_TG3_FET_SHADOW_EN 0x0080
  2035. #define MII_TG3_FET_SHDW_MISCCTRL 0x10
  2036. #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
  2037. #define MII_TG3_FET_SHDW_AUXMODE4 0x1a
  2038. #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
  2039. #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
  2040. #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
  2041. /* APE registers. Accessible through BAR1 */
  2042. #define TG3_APE_EVENT 0x000c
  2043. #define APE_EVENT_1 0x00000001
  2044. #define TG3_APE_LOCK_REQ 0x002c
  2045. #define APE_LOCK_REQ_DRIVER 0x00001000
  2046. #define TG3_APE_LOCK_GRANT 0x004c
  2047. #define APE_LOCK_GRANT_DRIVER 0x00001000
  2048. #define TG3_APE_SEG_SIG 0x4000
  2049. #define APE_SEG_SIG_MAGIC 0x41504521
  2050. /* APE shared memory. Accessible through BAR1 */
  2051. #define TG3_APE_FW_STATUS 0x400c
  2052. #define APE_FW_STATUS_READY 0x00000100
  2053. #define TG3_APE_FW_FEATURES 0x4010
  2054. #define TG3_APE_FW_FEATURE_NCSI 0x00000002
  2055. #define TG3_APE_FW_VERSION 0x4018
  2056. #define APE_FW_VERSION_MAJMSK 0xff000000
  2057. #define APE_FW_VERSION_MAJSFT 24
  2058. #define APE_FW_VERSION_MINMSK 0x00ff0000
  2059. #define APE_FW_VERSION_MINSFT 16
  2060. #define APE_FW_VERSION_REVMSK 0x0000ff00
  2061. #define APE_FW_VERSION_REVSFT 8
  2062. #define APE_FW_VERSION_BLDMSK 0x000000ff
  2063. #define TG3_APE_HOST_SEG_SIG 0x4200
  2064. #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
  2065. #define TG3_APE_HOST_SEG_LEN 0x4204
  2066. #define APE_HOST_SEG_LEN_MAGIC 0x0000001c
  2067. #define TG3_APE_HOST_INIT_COUNT 0x4208
  2068. #define TG3_APE_HOST_DRIVER_ID 0x420c
  2069. #define APE_HOST_DRIVER_ID_LINUX 0xf0000000
  2070. #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
  2071. (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
  2072. #define TG3_APE_HOST_BEHAVIOR 0x4210
  2073. #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
  2074. #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
  2075. #define APE_HOST_HEARTBEAT_INT_DISABLE 0
  2076. #define APE_HOST_HEARTBEAT_INT_5SEC 5000
  2077. #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
  2078. #define TG3_APE_EVENT_STATUS 0x4300
  2079. #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
  2080. #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
  2081. #define APE_EVENT_STATUS_STATE_START 0x00010000
  2082. #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
  2083. #define APE_EVENT_STATUS_STATE_WOL 0x00030000
  2084. #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
  2085. #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
  2086. #define TG3_APE_PER_LOCK_REQ 0x8400
  2087. #define APE_LOCK_PER_REQ_DRIVER 0x00001000
  2088. #define TG3_APE_PER_LOCK_GRANT 0x8420
  2089. #define APE_PER_LOCK_GRANT_DRIVER 0x00001000
  2090. /* APE convenience enumerations. */
  2091. #define TG3_APE_LOCK_GRC 1
  2092. #define TG3_APE_LOCK_MEM 4
  2093. #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
  2094. /* There are two ways to manage the TX descriptors on the tigon3.
  2095. * Either the descriptors are in host DMA'able memory, or they
  2096. * exist only in the cards on-chip SRAM. All 16 send bds are under
  2097. * the same mode, they may not be configured individually.
  2098. *
  2099. * This driver always uses host memory TX descriptors.
  2100. *
  2101. * To use host memory TX descriptors:
  2102. * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
  2103. * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
  2104. * 2) Allocate DMA'able memory.
  2105. * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  2106. * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
  2107. * obtained in step 2
  2108. * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
  2109. * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
  2110. * of TX descriptors. Leave flags field clear.
  2111. * 4) Access TX descriptors via host memory. The chip
  2112. * will refetch into local SRAM as needed when producer
  2113. * index mailboxes are updated.
  2114. *
  2115. * To use on-chip TX descriptors:
  2116. * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
  2117. * Make sure GRC_MODE_HOST_SENDBDS is clear.
  2118. * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  2119. * a) Set TG3_BDINFO_HOST_ADDR to zero.
  2120. * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
  2121. * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
  2122. * 3) Access TX descriptors directly in on-chip SRAM
  2123. * using normal {read,write}l(). (and not using
  2124. * pointer dereferencing of ioremap()'d memory like
  2125. * the broken Broadcom driver does)
  2126. *
  2127. * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
  2128. * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
  2129. */
  2130. struct tg3_tx_buffer_desc {
  2131. u32 addr_hi;
  2132. u32 addr_lo;
  2133. u32 len_flags;
  2134. #define TXD_FLAG_TCPUDP_CSUM 0x0001
  2135. #define TXD_FLAG_IP_CSUM 0x0002
  2136. #define TXD_FLAG_END 0x0004
  2137. #define TXD_FLAG_IP_FRAG 0x0008
  2138. #define TXD_FLAG_JMB_PKT 0x0008
  2139. #define TXD_FLAG_IP_FRAG_END 0x0010
  2140. #define TXD_FLAG_VLAN 0x0040
  2141. #define TXD_FLAG_COAL_NOW 0x0080
  2142. #define TXD_FLAG_CPU_PRE_DMA 0x0100
  2143. #define TXD_FLAG_CPU_POST_DMA 0x0200
  2144. #define TXD_FLAG_ADD_SRC_ADDR 0x1000
  2145. #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
  2146. #define TXD_FLAG_NO_CRC 0x8000
  2147. #define TXD_LEN_SHIFT 16
  2148. u32 vlan_tag;
  2149. #define TXD_VLAN_TAG_SHIFT 0
  2150. #define TXD_MSS_SHIFT 16
  2151. };
  2152. #define TXD_ADDR 0x00UL /* 64-bit */
  2153. #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
  2154. #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
  2155. #define TXD_SIZE 0x10UL
  2156. struct tg3_rx_buffer_desc {
  2157. u32 addr_hi;
  2158. u32 addr_lo;
  2159. u32 idx_len;
  2160. #define RXD_IDX_MASK 0xffff0000
  2161. #define RXD_IDX_SHIFT 16
  2162. #define RXD_LEN_MASK 0x0000ffff
  2163. #define RXD_LEN_SHIFT 0
  2164. u32 type_flags;
  2165. #define RXD_TYPE_SHIFT 16
  2166. #define RXD_FLAGS_SHIFT 0
  2167. #define RXD_FLAG_END 0x0004
  2168. #define RXD_FLAG_MINI 0x0800
  2169. #define RXD_FLAG_JUMBO 0x0020
  2170. #define RXD_FLAG_VLAN 0x0040
  2171. #define RXD_FLAG_ERROR 0x0400
  2172. #define RXD_FLAG_IP_CSUM 0x1000
  2173. #define RXD_FLAG_TCPUDP_CSUM 0x2000
  2174. #define RXD_FLAG_IS_TCP 0x4000
  2175. u32 ip_tcp_csum;
  2176. #define RXD_IPCSUM_MASK 0xffff0000
  2177. #define RXD_IPCSUM_SHIFT 16
  2178. #define RXD_TCPCSUM_MASK 0x0000ffff
  2179. #define RXD_TCPCSUM_SHIFT 0
  2180. u32 err_vlan;
  2181. #define RXD_VLAN_MASK 0x0000ffff
  2182. #define RXD_ERR_BAD_CRC 0x00010000
  2183. #define RXD_ERR_COLLISION 0x00020000
  2184. #define RXD_ERR_LINK_LOST 0x00040000
  2185. #define RXD_ERR_PHY_DECODE 0x00080000
  2186. #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
  2187. #define RXD_ERR_MAC_ABRT 0x00200000
  2188. #define RXD_ERR_TOO_SMALL 0x00400000
  2189. #define RXD_ERR_NO_RESOURCES 0x00800000
  2190. #define RXD_ERR_HUGE_FRAME 0x01000000
  2191. #define RXD_ERR_MASK 0xffff0000
  2192. u32 reserved;
  2193. u32 opaque;
  2194. #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
  2195. #define RXD_OPAQUE_INDEX_SHIFT 0
  2196. #define RXD_OPAQUE_RING_STD 0x00010000
  2197. #define RXD_OPAQUE_RING_JUMBO 0x00020000
  2198. #define RXD_OPAQUE_RING_MINI 0x00040000
  2199. #define RXD_OPAQUE_RING_MASK 0x00070000
  2200. };
  2201. struct tg3_ext_rx_buffer_desc {
  2202. struct {
  2203. u32 addr_hi;
  2204. u32 addr_lo;
  2205. } addrlist[3];
  2206. u32 len2_len1;
  2207. u32 resv_len3;
  2208. struct tg3_rx_buffer_desc std;
  2209. };
  2210. /* We only use this when testing out the DMA engine
  2211. * at probe time. This is the internal format of buffer
  2212. * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
  2213. */
  2214. struct tg3_internal_buffer_desc {
  2215. u32 addr_hi;
  2216. u32 addr_lo;
  2217. u32 nic_mbuf;
  2218. /* XXX FIX THIS */
  2219. #ifdef __BIG_ENDIAN
  2220. u16 cqid_sqid;
  2221. u16 len;
  2222. #else
  2223. u16 len;
  2224. u16 cqid_sqid;
  2225. #endif
  2226. u32 flags;
  2227. u32 __cookie1;
  2228. u32 __cookie2;
  2229. u32 __cookie3;
  2230. };
  2231. #define TG3_HW_STATUS_SIZE 0x50
  2232. struct tg3_hw_status {
  2233. u32 status;
  2234. #define SD_STATUS_UPDATED 0x00000001
  2235. #define SD_STATUS_LINK_CHG 0x00000002
  2236. #define SD_STATUS_ERROR 0x00000004
  2237. u32 status_tag;
  2238. #ifdef __BIG_ENDIAN
  2239. u16 rx_consumer;
  2240. u16 rx_jumbo_consumer;
  2241. #else
  2242. u16 rx_jumbo_consumer;
  2243. u16 rx_consumer;
  2244. #endif
  2245. #ifdef __BIG_ENDIAN
  2246. u16 reserved;
  2247. u16 rx_mini_consumer;
  2248. #else
  2249. u16 rx_mini_consumer;
  2250. u16 reserved;
  2251. #endif
  2252. struct {
  2253. #ifdef __BIG_ENDIAN
  2254. u16 tx_consumer;
  2255. u16 rx_producer;
  2256. #else
  2257. u16 rx_producer;
  2258. u16 tx_consumer;
  2259. #endif
  2260. } idx[16];
  2261. };
  2262. typedef struct {
  2263. u32 high, low;
  2264. } tg3_stat64_t;
  2265. struct tg3_hw_stats {
  2266. u8 __reserved0[0x400-0x300];
  2267. /* Statistics maintained by Receive MAC. */
  2268. tg3_stat64_t rx_octets;
  2269. u64 __reserved1;
  2270. tg3_stat64_t rx_fragments;
  2271. tg3_stat64_t rx_ucast_packets;
  2272. tg3_stat64_t rx_mcast_packets;
  2273. tg3_stat64_t rx_bcast_packets;
  2274. tg3_stat64_t rx_fcs_errors;
  2275. tg3_stat64_t rx_align_errors;
  2276. tg3_stat64_t rx_xon_pause_rcvd;
  2277. tg3_stat64_t rx_xoff_pause_rcvd;
  2278. tg3_stat64_t rx_mac_ctrl_rcvd;
  2279. tg3_stat64_t rx_xoff_entered;
  2280. tg3_stat64_t rx_frame_too_long_errors;
  2281. tg3_stat64_t rx_jabbers;
  2282. tg3_stat64_t rx_undersize_packets;
  2283. tg3_stat64_t rx_in_length_errors;
  2284. tg3_stat64_t rx_out_length_errors;
  2285. tg3_stat64_t rx_64_or_less_octet_packets;
  2286. tg3_stat64_t rx_65_to_127_octet_packets;
  2287. tg3_stat64_t rx_128_to_255_octet_packets;
  2288. tg3_stat64_t rx_256_to_511_octet_packets;
  2289. tg3_stat64_t rx_512_to_1023_octet_packets;
  2290. tg3_stat64_t rx_1024_to_1522_octet_packets;
  2291. tg3_stat64_t rx_1523_to_2047_octet_packets;
  2292. tg3_stat64_t rx_2048_to_4095_octet_packets;
  2293. tg3_stat64_t rx_4096_to_8191_octet_packets;
  2294. tg3_stat64_t rx_8192_to_9022_octet_packets;
  2295. u64 __unused0[37];
  2296. /* Statistics maintained by Transmit MAC. */
  2297. tg3_stat64_t tx_octets;
  2298. u64 __reserved2;
  2299. tg3_stat64_t tx_collisions;
  2300. tg3_stat64_t tx_xon_sent;
  2301. tg3_stat64_t tx_xoff_sent;
  2302. tg3_stat64_t tx_flow_control;
  2303. tg3_stat64_t tx_mac_errors;
  2304. tg3_stat64_t tx_single_collisions;
  2305. tg3_stat64_t tx_mult_collisions;
  2306. tg3_stat64_t tx_deferred;
  2307. u64 __reserved3;
  2308. tg3_stat64_t tx_excessive_collisions;
  2309. tg3_stat64_t tx_late_collisions;
  2310. tg3_stat64_t tx_collide_2times;
  2311. tg3_stat64_t tx_collide_3times;
  2312. tg3_stat64_t tx_collide_4times;
  2313. tg3_stat64_t tx_collide_5times;
  2314. tg3_stat64_t tx_collide_6times;
  2315. tg3_stat64_t tx_collide_7times;
  2316. tg3_stat64_t tx_collide_8times;
  2317. tg3_stat64_t tx_collide_9times;
  2318. tg3_stat64_t tx_collide_10times;
  2319. tg3_stat64_t tx_collide_11times;
  2320. tg3_stat64_t tx_collide_12times;
  2321. tg3_stat64_t tx_collide_13times;
  2322. tg3_stat64_t tx_collide_14times;
  2323. tg3_stat64_t tx_collide_15times;
  2324. tg3_stat64_t tx_ucast_packets;
  2325. tg3_stat64_t tx_mcast_packets;
  2326. tg3_stat64_t tx_bcast_packets;
  2327. tg3_stat64_t tx_carrier_sense_errors;
  2328. tg3_stat64_t tx_discards;
  2329. tg3_stat64_t tx_errors;
  2330. u64 __unused1[31];
  2331. /* Statistics maintained by Receive List Placement. */
  2332. tg3_stat64_t COS_rx_packets[16];
  2333. tg3_stat64_t COS_rx_filter_dropped;
  2334. tg3_stat64_t dma_writeq_full;
  2335. tg3_stat64_t dma_write_prioq_full;
  2336. tg3_stat64_t rxbds_empty;
  2337. tg3_stat64_t rx_discards;
  2338. tg3_stat64_t rx_errors;
  2339. tg3_stat64_t rx_threshold_hit;
  2340. u64 __unused2[9];
  2341. /* Statistics maintained by Send Data Initiator. */
  2342. tg3_stat64_t COS_out_packets[16];
  2343. tg3_stat64_t dma_readq_full;
  2344. tg3_stat64_t dma_read_prioq_full;
  2345. tg3_stat64_t tx_comp_queue_full;
  2346. /* Statistics maintained by Host Coalescing. */
  2347. tg3_stat64_t ring_set_send_prod_index;
  2348. tg3_stat64_t ring_status_update;
  2349. tg3_stat64_t nic_irqs;
  2350. tg3_stat64_t nic_avoided_irqs;
  2351. tg3_stat64_t nic_tx_threshold_hit;
  2352. u8 __reserved4[0xb00-0x9c0];
  2353. };
  2354. /* 'mapping' is superfluous as the chip does not write into
  2355. * the tx/rx post rings so we could just fetch it from there.
  2356. * But the cache behavior is better how we are doing it now.
  2357. */
  2358. struct ring_info {
  2359. struct sk_buff *skb;
  2360. DEFINE_DMA_UNMAP_ADDR(mapping);
  2361. };
  2362. struct tg3_config_info {
  2363. u32 flags;
  2364. };
  2365. struct tg3_link_config {
  2366. /* Describes what we're trying to get. */
  2367. u32 advertising;
  2368. u16 speed;
  2369. u8 duplex;
  2370. u8 autoneg;
  2371. u8 flowctrl;
  2372. /* Describes what we actually have. */
  2373. u8 active_flowctrl;
  2374. u8 active_duplex;
  2375. #define SPEED_INVALID 0xffff
  2376. #define DUPLEX_INVALID 0xff
  2377. #define AUTONEG_INVALID 0xff
  2378. u16 active_speed;
  2379. /* When we go in and out of low power mode we need
  2380. * to swap with this state.
  2381. */
  2382. u16 orig_speed;
  2383. u8 orig_duplex;
  2384. u8 orig_autoneg;
  2385. u32 orig_advertising;
  2386. };
  2387. struct tg3_bufmgr_config {
  2388. u32 mbuf_read_dma_low_water;
  2389. u32 mbuf_mac_rx_low_water;
  2390. u32 mbuf_high_water;
  2391. u32 mbuf_read_dma_low_water_jumbo;
  2392. u32 mbuf_mac_rx_low_water_jumbo;
  2393. u32 mbuf_high_water_jumbo;
  2394. u32 dma_low_water;
  2395. u32 dma_high_water;
  2396. };
  2397. struct tg3_ethtool_stats {
  2398. /* Statistics maintained by Receive MAC. */
  2399. u64 rx_octets;
  2400. u64 rx_fragments;
  2401. u64 rx_ucast_packets;
  2402. u64 rx_mcast_packets;
  2403. u64 rx_bcast_packets;
  2404. u64 rx_fcs_errors;
  2405. u64 rx_align_errors;
  2406. u64 rx_xon_pause_rcvd;
  2407. u64 rx_xoff_pause_rcvd;
  2408. u64 rx_mac_ctrl_rcvd;
  2409. u64 rx_xoff_entered;
  2410. u64 rx_frame_too_long_errors;
  2411. u64 rx_jabbers;
  2412. u64 rx_undersize_packets;
  2413. u64 rx_in_length_errors;
  2414. u64 rx_out_length_errors;
  2415. u64 rx_64_or_less_octet_packets;
  2416. u64 rx_65_to_127_octet_packets;
  2417. u64 rx_128_to_255_octet_packets;
  2418. u64 rx_256_to_511_octet_packets;
  2419. u64 rx_512_to_1023_octet_packets;
  2420. u64 rx_1024_to_1522_octet_packets;
  2421. u64 rx_1523_to_2047_octet_packets;
  2422. u64 rx_2048_to_4095_octet_packets;
  2423. u64 rx_4096_to_8191_octet_packets;
  2424. u64 rx_8192_to_9022_octet_packets;
  2425. /* Statistics maintained by Transmit MAC. */
  2426. u64 tx_octets;
  2427. u64 tx_collisions;
  2428. u64 tx_xon_sent;
  2429. u64 tx_xoff_sent;
  2430. u64 tx_flow_control;
  2431. u64 tx_mac_errors;
  2432. u64 tx_single_collisions;
  2433. u64 tx_mult_collisions;
  2434. u64 tx_deferred;
  2435. u64 tx_excessive_collisions;
  2436. u64 tx_late_collisions;
  2437. u64 tx_collide_2times;
  2438. u64 tx_collide_3times;
  2439. u64 tx_collide_4times;
  2440. u64 tx_collide_5times;
  2441. u64 tx_collide_6times;
  2442. u64 tx_collide_7times;
  2443. u64 tx_collide_8times;
  2444. u64 tx_collide_9times;
  2445. u64 tx_collide_10times;
  2446. u64 tx_collide_11times;
  2447. u64 tx_collide_12times;
  2448. u64 tx_collide_13times;
  2449. u64 tx_collide_14times;
  2450. u64 tx_collide_15times;
  2451. u64 tx_ucast_packets;
  2452. u64 tx_mcast_packets;
  2453. u64 tx_bcast_packets;
  2454. u64 tx_carrier_sense_errors;
  2455. u64 tx_discards;
  2456. u64 tx_errors;
  2457. /* Statistics maintained by Receive List Placement. */
  2458. u64 dma_writeq_full;
  2459. u64 dma_write_prioq_full;
  2460. u64 rxbds_empty;
  2461. u64 rx_discards;
  2462. u64 rx_errors;
  2463. u64 rx_threshold_hit;
  2464. /* Statistics maintained by Send Data Initiator. */
  2465. u64 dma_readq_full;
  2466. u64 dma_read_prioq_full;
  2467. u64 tx_comp_queue_full;
  2468. /* Statistics maintained by Host Coalescing. */
  2469. u64 ring_set_send_prod_index;
  2470. u64 ring_status_update;
  2471. u64 nic_irqs;
  2472. u64 nic_avoided_irqs;
  2473. u64 nic_tx_threshold_hit;
  2474. };
  2475. struct tg3_rx_prodring_set {
  2476. u32 rx_std_prod_idx;
  2477. u32 rx_std_cons_idx;
  2478. u32 rx_jmb_prod_idx;
  2479. u32 rx_jmb_cons_idx;
  2480. struct tg3_rx_buffer_desc *rx_std;
  2481. struct tg3_ext_rx_buffer_desc *rx_jmb;
  2482. struct ring_info *rx_std_buffers;
  2483. struct ring_info *rx_jmb_buffers;
  2484. dma_addr_t rx_std_mapping;
  2485. dma_addr_t rx_jmb_mapping;
  2486. };
  2487. #define TG3_IRQ_MAX_VECS 5
  2488. struct tg3_napi {
  2489. struct napi_struct napi ____cacheline_aligned;
  2490. struct tg3 *tp;
  2491. struct tg3_hw_status *hw_status;
  2492. u32 last_tag;
  2493. u32 last_irq_tag;
  2494. u32 int_mbox;
  2495. u32 coal_now;
  2496. u32 tx_prod;
  2497. u32 tx_cons;
  2498. u32 tx_pending;
  2499. u32 prodmbox;
  2500. u32 consmbox;
  2501. u32 rx_rcb_ptr;
  2502. u16 *rx_rcb_prod_idx;
  2503. struct tg3_rx_prodring_set *prodring;
  2504. struct tg3_rx_buffer_desc *rx_rcb;
  2505. struct tg3_tx_buffer_desc *tx_ring;
  2506. struct ring_info *tx_buffers;
  2507. dma_addr_t status_mapping;
  2508. dma_addr_t rx_rcb_mapping;
  2509. dma_addr_t tx_desc_mapping;
  2510. char irq_lbl[IFNAMSIZ];
  2511. unsigned int irq_vec;
  2512. };
  2513. struct tg3 {
  2514. /* begin "general, frequently-used members" cacheline section */
  2515. /* If the IRQ handler (which runs lockless) needs to be
  2516. * quiesced, the following bitmask state is used. The
  2517. * SYNC flag is set by non-IRQ context code to initiate
  2518. * the quiescence.
  2519. *
  2520. * When the IRQ handler notices that SYNC is set, it
  2521. * disables interrupts and returns.
  2522. *
  2523. * When all outstanding IRQ handlers have returned after
  2524. * the SYNC flag has been set, the setter can be assured
  2525. * that interrupts will no longer get run.
  2526. *
  2527. * In this way all SMP driver locks are never acquired
  2528. * in hw IRQ context, only sw IRQ context or lower.
  2529. */
  2530. unsigned int irq_sync;
  2531. /* SMP locking strategy:
  2532. *
  2533. * lock: Held during reset, PHY access, timer, and when
  2534. * updating tg3_flags and tg3_flags2.
  2535. *
  2536. * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
  2537. * netif_tx_lock when it needs to call
  2538. * netif_wake_queue.
  2539. *
  2540. * Both of these locks are to be held with BH safety.
  2541. *
  2542. * Because the IRQ handler, tg3_poll, and tg3_start_xmit
  2543. * are running lockless, it is necessary to completely
  2544. * quiesce the chip with tg3_netif_stop and tg3_full_lock
  2545. * before reconfiguring the device.
  2546. *
  2547. * indirect_lock: Held when accessing registers indirectly
  2548. * with IRQ disabling.
  2549. */
  2550. spinlock_t lock;
  2551. spinlock_t indirect_lock;
  2552. u32 (*read32) (struct tg3 *, u32);
  2553. void (*write32) (struct tg3 *, u32, u32);
  2554. u32 (*read32_mbox) (struct tg3 *, u32);
  2555. void (*write32_mbox) (struct tg3 *, u32,
  2556. u32);
  2557. void __iomem *regs;
  2558. void __iomem *aperegs;
  2559. struct net_device *dev;
  2560. struct pci_dev *pdev;
  2561. u32 coal_now;
  2562. u32 msg_enable;
  2563. /* begin "tx thread" cacheline section */
  2564. void (*write32_tx_mbox) (struct tg3 *, u32,
  2565. u32);
  2566. /* begin "rx thread" cacheline section */
  2567. struct tg3_napi napi[TG3_IRQ_MAX_VECS];
  2568. void (*write32_rx_mbox) (struct tg3 *, u32,
  2569. u32);
  2570. u32 rx_copy_thresh;
  2571. u32 rx_pending;
  2572. u32 rx_jumbo_pending;
  2573. u32 rx_std_max_post;
  2574. u32 rx_offset;
  2575. u32 rx_pkt_map_sz;
  2576. #if TG3_VLAN_TAG_USED
  2577. struct vlan_group *vlgrp;
  2578. #endif
  2579. struct tg3_rx_prodring_set prodring[TG3_IRQ_MAX_VECS];
  2580. /* begin "everything else" cacheline(s) section */
  2581. struct rtnl_link_stats64 net_stats;
  2582. struct rtnl_link_stats64 net_stats_prev;
  2583. struct tg3_ethtool_stats estats;
  2584. struct tg3_ethtool_stats estats_prev;
  2585. union {
  2586. unsigned long phy_crc_errors;
  2587. unsigned long last_event_jiffies;
  2588. };
  2589. u32 tg3_flags;
  2590. #define TG3_FLAG_TAGGED_STATUS 0x00000001
  2591. #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
  2592. #define TG3_FLAG_RX_CHECKSUMS 0x00000004
  2593. #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
  2594. #define TG3_FLAG_ENABLE_ASF 0x00000020
  2595. #define TG3_FLAG_ASPM_WORKAROUND 0x00000040
  2596. #define TG3_FLAG_POLL_SERDES 0x00000080
  2597. #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
  2598. #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
  2599. #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
  2600. #define TG3_FLAG_WOL_ENABLE 0x00000800
  2601. #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
  2602. #define TG3_FLAG_NVRAM 0x00002000
  2603. #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
  2604. #define TG3_FLAG_SUPPORT_MSI 0x00008000
  2605. #define TG3_FLAG_SUPPORT_MSIX 0x00010000
  2606. #define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
  2607. TG3_FLAG_SUPPORT_MSIX)
  2608. #define TG3_FLAG_PCIX_MODE 0x00020000
  2609. #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
  2610. #define TG3_FLAG_PCI_32BIT 0x00080000
  2611. #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
  2612. #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
  2613. #define TG3_FLAG_WOL_CAP 0x00400000
  2614. #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
  2615. #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
  2616. #define TG3_FLAG_CPMU_PRESENT 0x04000000
  2617. #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
  2618. #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
  2619. #define TG3_FLAG_JUMBO_CAPABLE 0x20000000
  2620. #define TG3_FLAG_CHIP_RESETTING 0x40000000
  2621. #define TG3_FLAG_INIT_COMPLETE 0x80000000
  2622. u32 tg3_flags2;
  2623. #define TG3_FLG2_RESTART_TIMER 0x00000001
  2624. #define TG3_FLG2_TSO_BUG 0x00000002
  2625. #define TG3_FLG2_IS_5788 0x00000008
  2626. #define TG3_FLG2_MAX_RXPEND_64 0x00000010
  2627. #define TG3_FLG2_TSO_CAPABLE 0x00000020
  2628. #define TG3_FLG2_PCI_EXPRESS 0x00000200
  2629. #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
  2630. #define TG3_FLG2_HW_AUTONEG 0x00000800
  2631. #define TG3_FLG2_IS_NIC 0x00001000
  2632. #define TG3_FLG2_FLASH 0x00008000
  2633. #define TG3_FLG2_HW_TSO_1 0x00010000
  2634. #define TG3_FLG2_5705_PLUS 0x00040000
  2635. #define TG3_FLG2_5750_PLUS 0x00080000
  2636. #define TG3_FLG2_HW_TSO_3 0x00100000
  2637. #define TG3_FLG2_USING_MSI 0x00200000
  2638. #define TG3_FLG2_USING_MSIX 0x00400000
  2639. #define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
  2640. TG3_FLG2_USING_MSIX)
  2641. #define TG3_FLG2_ICH_WORKAROUND 0x02000000
  2642. #define TG3_FLG2_5780_CLASS 0x04000000
  2643. #define TG3_FLG2_HW_TSO_2 0x08000000
  2644. #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
  2645. TG3_FLG2_HW_TSO_2 | \
  2646. TG3_FLG2_HW_TSO_3)
  2647. #define TG3_FLG2_1SHOT_MSI 0x10000000
  2648. #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
  2649. u32 tg3_flags3;
  2650. #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
  2651. #define TG3_FLG3_ENABLE_APE 0x00000002
  2652. #define TG3_FLG3_PROTECTED_NVRAM 0x00000004
  2653. #define TG3_FLG3_5701_DMA_BUG 0x00000008
  2654. #define TG3_FLG3_USE_PHYLIB 0x00000010
  2655. #define TG3_FLG3_MDIOBUS_INITED 0x00000020
  2656. #define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
  2657. #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
  2658. #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
  2659. #define TG3_FLG3_CLKREQ_BUG 0x00000800
  2660. #define TG3_FLG3_5755_PLUS 0x00002000
  2661. #define TG3_FLG3_NO_NVRAM 0x00004000
  2662. #define TG3_FLG3_ENABLE_RSS 0x00020000
  2663. #define TG3_FLG3_ENABLE_TSS 0x00040000
  2664. #define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
  2665. #define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
  2666. #define TG3_FLG3_SHORT_DMA_BUG 0x00200000
  2667. #define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
  2668. #define TG3_FLG3_L1PLLPD_EN 0x00800000
  2669. #define TG3_FLG3_5717_PLUS 0x01000000
  2670. struct timer_list timer;
  2671. u16 timer_counter;
  2672. u16 timer_multiplier;
  2673. u32 timer_offset;
  2674. u16 asf_counter;
  2675. u16 asf_multiplier;
  2676. /* 1 second counter for transient serdes link events */
  2677. u32 serdes_counter;
  2678. #define SERDES_AN_TIMEOUT_5704S 2
  2679. #define SERDES_PARALLEL_DET_TIMEOUT 1
  2680. #define SERDES_AN_TIMEOUT_5714S 1
  2681. struct tg3_link_config link_config;
  2682. struct tg3_bufmgr_config bufmgr_config;
  2683. /* cache h/w values, often passed straight to h/w */
  2684. u32 rx_mode;
  2685. u32 tx_mode;
  2686. u32 mac_mode;
  2687. u32 mi_mode;
  2688. u32 misc_host_ctrl;
  2689. u32 grc_mode;
  2690. u32 grc_local_ctrl;
  2691. u32 dma_rwctrl;
  2692. u32 coalesce_mode;
  2693. u32 pwrmgmt_thresh;
  2694. /* PCI block */
  2695. u32 pci_chip_rev_id;
  2696. u16 pci_cmd;
  2697. u8 pci_cacheline_sz;
  2698. u8 pci_lat_timer;
  2699. int pm_cap;
  2700. int msi_cap;
  2701. union {
  2702. int pcix_cap;
  2703. int pcie_cap;
  2704. };
  2705. struct mii_bus *mdio_bus;
  2706. int mdio_irq[PHY_MAX_ADDR];
  2707. u8 phy_addr;
  2708. /* PHY info */
  2709. u32 phy_id;
  2710. #define TG3_PHY_ID_MASK 0xfffffff0
  2711. #define TG3_PHY_ID_BCM5400 0x60008040
  2712. #define TG3_PHY_ID_BCM5401 0x60008050
  2713. #define TG3_PHY_ID_BCM5411 0x60008070
  2714. #define TG3_PHY_ID_BCM5701 0x60008110
  2715. #define TG3_PHY_ID_BCM5703 0x60008160
  2716. #define TG3_PHY_ID_BCM5704 0x60008190
  2717. #define TG3_PHY_ID_BCM5705 0x600081a0
  2718. #define TG3_PHY_ID_BCM5750 0x60008180
  2719. #define TG3_PHY_ID_BCM5752 0x60008100
  2720. #define TG3_PHY_ID_BCM5714 0x60008340
  2721. #define TG3_PHY_ID_BCM5780 0x60008350
  2722. #define TG3_PHY_ID_BCM5755 0xbc050cc0
  2723. #define TG3_PHY_ID_BCM5787 0xbc050ce0
  2724. #define TG3_PHY_ID_BCM5756 0xbc050ed0
  2725. #define TG3_PHY_ID_BCM5784 0xbc050fa0
  2726. #define TG3_PHY_ID_BCM5761 0xbc050fd0
  2727. #define TG3_PHY_ID_BCM5718C 0x5c0d8a00
  2728. #define TG3_PHY_ID_BCM5718S 0xbc050ff0
  2729. #define TG3_PHY_ID_BCM57765 0x5c0d8a40
  2730. #define TG3_PHY_ID_BCM5719C 0x5c0d8a20
  2731. #define TG3_PHY_ID_BCM5906 0xdc00ac40
  2732. #define TG3_PHY_ID_BCM8002 0x60010140
  2733. #define TG3_PHY_ID_INVALID 0xffffffff
  2734. #define PHY_ID_RTL8211C 0x001cc910
  2735. #define PHY_ID_RTL8201E 0x00008200
  2736. #define TG3_PHY_ID_REV_MASK 0x0000000f
  2737. #define TG3_PHY_REV_BCM5401_B0 0x1
  2738. /* This macro assumes the passed PHY ID is
  2739. * already masked with TG3_PHY_ID_MASK.
  2740. */
  2741. #define TG3_KNOWN_PHY_ID(X) \
  2742. ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
  2743. (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
  2744. (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
  2745. (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
  2746. (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
  2747. (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
  2748. (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
  2749. (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
  2750. (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
  2751. (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
  2752. (X) == TG3_PHY_ID_BCM8002)
  2753. u32 phy_flags;
  2754. #define TG3_PHYFLG_IS_LOW_POWER 0x00000001
  2755. #define TG3_PHYFLG_IS_CONNECTED 0x00000002
  2756. #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
  2757. #define TG3_PHYFLG_PHY_SERDES 0x00000010
  2758. #define TG3_PHYFLG_MII_SERDES 0x00000020
  2759. #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
  2760. TG3_PHYFLG_MII_SERDES)
  2761. #define TG3_PHYFLG_IS_FET 0x00000040
  2762. #define TG3_PHYFLG_10_100_ONLY 0x00000080
  2763. #define TG3_PHYFLG_ENABLE_APD 0x00000100
  2764. #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
  2765. #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
  2766. #define TG3_PHYFLG_JITTER_BUG 0x00000800
  2767. #define TG3_PHYFLG_ADJUST_TRIM 0x00001000
  2768. #define TG3_PHYFLG_ADC_BUG 0x00002000
  2769. #define TG3_PHYFLG_5704_A0_BUG 0x00004000
  2770. #define TG3_PHYFLG_BER_BUG 0x00008000
  2771. #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
  2772. #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
  2773. u32 led_ctrl;
  2774. u32 phy_otp;
  2775. #define TG3_BPN_SIZE 24
  2776. char board_part_number[TG3_BPN_SIZE];
  2777. #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
  2778. char fw_ver[TG3_VER_SIZE];
  2779. u32 nic_sram_data_cfg;
  2780. u32 pci_clock_ctrl;
  2781. struct pci_dev *pdev_peer;
  2782. struct tg3_hw_stats *hw_stats;
  2783. dma_addr_t stats_mapping;
  2784. struct work_struct reset_task;
  2785. int nvram_lock_cnt;
  2786. u32 nvram_size;
  2787. #define TG3_NVRAM_SIZE_64KB 0x00010000
  2788. #define TG3_NVRAM_SIZE_128KB 0x00020000
  2789. #define TG3_NVRAM_SIZE_256KB 0x00040000
  2790. #define TG3_NVRAM_SIZE_512KB 0x00080000
  2791. #define TG3_NVRAM_SIZE_1MB 0x00100000
  2792. #define TG3_NVRAM_SIZE_2MB 0x00200000
  2793. u32 nvram_pagesize;
  2794. u32 nvram_jedecnum;
  2795. #define JEDEC_ATMEL 0x1f
  2796. #define JEDEC_ST 0x20
  2797. #define JEDEC_SAIFUN 0x4f
  2798. #define JEDEC_SST 0xbf
  2799. #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
  2800. #define ATMEL_AT24C64_PAGE_SIZE (32)
  2801. #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
  2802. #define ATMEL_AT24C512_PAGE_SIZE (128)
  2803. #define ATMEL_AT45DB0X1B_PAGE_POS 9
  2804. #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
  2805. #define ATMEL_AT25F512_PAGE_SIZE 256
  2806. #define ST_M45PEX0_PAGE_SIZE 256
  2807. #define SAIFUN_SA25F0XX_PAGE_SIZE 256
  2808. #define SST_25VF0X0_PAGE_SIZE 4098
  2809. unsigned int irq_max;
  2810. unsigned int irq_cnt;
  2811. struct ethtool_coalesce coal;
  2812. /* firmware info */
  2813. const char *fw_needed;
  2814. const struct firmware *fw;
  2815. u32 fw_len; /* includes BSS */
  2816. };
  2817. #endif /* !(_T3_H) */