tg3.c 395 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261726272637264726572667267726872697270727172727273727472757276727772787279728072817282728372847285728672877288728972907291729272937294729572967297729872997300730173027303730473057306730773087309731073117312731373147315731673177318731973207321732273237324732573267327732873297330733173327333733473357336733773387339734073417342734373447345734673477348734973507351735273537354735573567357735873597360736173627363736473657366736773687369737073717372737373747375737673777378737973807381738273837384738573867387738873897390739173927393739473957396739773987399740074017402740374047405740674077408740974107411741274137414741574167417741874197420742174227423742474257426742774287429743074317432743374347435743674377438743974407441744274437444744574467447744874497450745174527453745474557456745774587459746074617462746374647465746674677468746974707471747274737474747574767477747874797480748174827483748474857486748774887489749074917492749374947495749674977498749975007501750275037504750575067507750875097510751175127513751475157516751775187519752075217522752375247525752675277528752975307531753275337534753575367537753875397540754175427543754475457546754775487549755075517552755375547555755675577558755975607561756275637564756575667567756875697570757175727573757475757576757775787579758075817582758375847585758675877588758975907591759275937594759575967597759875997600760176027603760476057606760776087609761076117612761376147615761676177618761976207621762276237624762576267627762876297630763176327633763476357636763776387639764076417642764376447645764676477648764976507651765276537654765576567657765876597660766176627663766476657666766776687669767076717672767376747675767676777678767976807681768276837684768576867687768876897690769176927693769476957696769776987699770077017702770377047705770677077708770977107711771277137714771577167717771877197720772177227723772477257726772777287729773077317732773377347735773677377738773977407741774277437744774577467747774877497750775177527753775477557756775777587759776077617762776377647765776677677768776977707771777277737774777577767777777877797780778177827783778477857786778777887789779077917792779377947795779677977798779978007801780278037804780578067807780878097810781178127813781478157816781778187819782078217822782378247825782678277828782978307831783278337834783578367837783878397840784178427843784478457846784778487849785078517852785378547855785678577858785978607861786278637864786578667867786878697870787178727873787478757876787778787879788078817882788378847885788678877888788978907891789278937894789578967897789878997900790179027903790479057906790779087909791079117912791379147915791679177918791979207921792279237924792579267927792879297930793179327933793479357936793779387939794079417942794379447945794679477948794979507951795279537954795579567957795879597960796179627963796479657966796779687969797079717972797379747975797679777978797979807981798279837984798579867987798879897990799179927993799479957996799779987999800080018002800380048005800680078008800980108011801280138014801580168017801880198020802180228023802480258026802780288029803080318032803380348035803680378038803980408041804280438044804580468047804880498050805180528053805480558056805780588059806080618062806380648065806680678068806980708071807280738074807580768077807880798080808180828083808480858086808780888089809080918092809380948095809680978098809981008101810281038104810581068107810881098110811181128113811481158116811781188119812081218122812381248125812681278128812981308131813281338134813581368137813881398140814181428143814481458146814781488149815081518152815381548155815681578158815981608161816281638164816581668167816881698170817181728173817481758176817781788179818081818182818381848185818681878188818981908191819281938194819581968197819881998200820182028203820482058206820782088209821082118212821382148215821682178218821982208221822282238224822582268227822882298230823182328233823482358236823782388239824082418242824382448245824682478248824982508251825282538254825582568257825882598260826182628263826482658266826782688269827082718272827382748275827682778278827982808281828282838284828582868287828882898290829182928293829482958296829782988299830083018302830383048305830683078308830983108311831283138314831583168317831883198320832183228323832483258326832783288329833083318332833383348335833683378338833983408341834283438344834583468347834883498350835183528353835483558356835783588359836083618362836383648365836683678368836983708371837283738374837583768377837883798380838183828383838483858386838783888389839083918392839383948395839683978398839984008401840284038404840584068407840884098410841184128413841484158416841784188419842084218422842384248425842684278428842984308431843284338434843584368437843884398440844184428443844484458446844784488449845084518452845384548455845684578458845984608461846284638464846584668467846884698470847184728473847484758476847784788479848084818482848384848485848684878488848984908491849284938494849584968497849884998500850185028503850485058506850785088509851085118512851385148515851685178518851985208521852285238524852585268527852885298530853185328533853485358536853785388539854085418542854385448545854685478548854985508551855285538554855585568557855885598560856185628563856485658566856785688569857085718572857385748575857685778578857985808581858285838584858585868587858885898590859185928593859485958596859785988599860086018602860386048605860686078608860986108611861286138614861586168617861886198620862186228623862486258626862786288629863086318632863386348635863686378638863986408641864286438644864586468647864886498650865186528653865486558656865786588659866086618662866386648665866686678668866986708671867286738674867586768677867886798680868186828683868486858686868786888689869086918692869386948695869686978698869987008701870287038704870587068707870887098710871187128713871487158716871787188719872087218722872387248725872687278728872987308731873287338734873587368737873887398740874187428743874487458746874787488749875087518752875387548755875687578758875987608761876287638764876587668767876887698770877187728773877487758776877787788779878087818782878387848785878687878788878987908791879287938794879587968797879887998800880188028803880488058806880788088809881088118812881388148815881688178818881988208821882288238824882588268827882888298830883188328833883488358836883788388839884088418842884388448845884688478848884988508851885288538854885588568857885888598860886188628863886488658866886788688869887088718872887388748875887688778878887988808881888288838884888588868887888888898890889188928893889488958896889788988899890089018902890389048905890689078908890989108911891289138914891589168917891889198920892189228923892489258926892789288929893089318932893389348935893689378938893989408941894289438944894589468947894889498950895189528953895489558956895789588959896089618962896389648965896689678968896989708971897289738974897589768977897889798980898189828983898489858986898789888989899089918992899389948995899689978998899990009001900290039004900590069007900890099010901190129013901490159016901790189019902090219022902390249025902690279028902990309031903290339034903590369037903890399040904190429043904490459046904790489049905090519052905390549055905690579058905990609061906290639064906590669067906890699070907190729073907490759076907790789079908090819082908390849085908690879088908990909091909290939094909590969097909890999100910191029103910491059106910791089109911091119112911391149115911691179118911991209121912291239124912591269127912891299130913191329133913491359136913791389139914091419142914391449145914691479148914991509151915291539154915591569157915891599160916191629163916491659166916791689169917091719172917391749175917691779178917991809181918291839184918591869187918891899190919191929193919491959196919791989199920092019202920392049205920692079208920992109211921292139214921592169217921892199220922192229223922492259226922792289229923092319232923392349235923692379238923992409241924292439244924592469247924892499250925192529253925492559256925792589259926092619262926392649265926692679268926992709271927292739274927592769277927892799280928192829283928492859286928792889289929092919292929392949295929692979298929993009301930293039304930593069307930893099310931193129313931493159316931793189319932093219322932393249325932693279328932993309331933293339334933593369337933893399340934193429343934493459346934793489349935093519352935393549355935693579358935993609361936293639364936593669367936893699370937193729373937493759376937793789379938093819382938393849385938693879388938993909391939293939394939593969397939893999400940194029403940494059406940794089409941094119412941394149415941694179418941994209421942294239424942594269427942894299430943194329433943494359436943794389439944094419442944394449445944694479448944994509451945294539454945594569457945894599460946194629463946494659466946794689469947094719472947394749475947694779478947994809481948294839484948594869487948894899490949194929493949494959496949794989499950095019502950395049505950695079508950995109511951295139514951595169517951895199520952195229523952495259526952795289529953095319532953395349535953695379538953995409541954295439544954595469547954895499550955195529553955495559556955795589559956095619562956395649565956695679568956995709571957295739574957595769577957895799580958195829583958495859586958795889589959095919592959395949595959695979598959996009601960296039604960596069607960896099610961196129613961496159616961796189619962096219622962396249625962696279628962996309631963296339634963596369637963896399640964196429643964496459646964796489649965096519652965396549655965696579658965996609661966296639664966596669667966896699670967196729673967496759676967796789679968096819682968396849685968696879688968996909691969296939694969596969697969896999700970197029703970497059706970797089709971097119712971397149715971697179718971997209721972297239724972597269727972897299730973197329733973497359736973797389739974097419742974397449745974697479748974997509751975297539754975597569757975897599760976197629763976497659766976797689769977097719772977397749775977697779778977997809781978297839784978597869787978897899790979197929793979497959796979797989799980098019802980398049805980698079808980998109811981298139814981598169817981898199820982198229823982498259826982798289829983098319832983398349835983698379838983998409841984298439844984598469847984898499850985198529853985498559856985798589859986098619862986398649865986698679868986998709871987298739874987598769877987898799880988198829883988498859886988798889889989098919892989398949895989698979898989999009901990299039904990599069907990899099910991199129913991499159916991799189919992099219922992399249925992699279928992999309931993299339934993599369937993899399940994199429943994499459946994799489949995099519952995399549955995699579958995999609961996299639964996599669967996899699970997199729973997499759976997799789979998099819982998399849985998699879988998999909991999299939994999599969997999899991000010001100021000310004100051000610007100081000910010100111001210013100141001510016100171001810019100201002110022100231002410025100261002710028100291003010031100321003310034100351003610037100381003910040100411004210043100441004510046100471004810049100501005110052100531005410055100561005710058100591006010061100621006310064100651006610067100681006910070100711007210073100741007510076100771007810079100801008110082100831008410085100861008710088100891009010091100921009310094100951009610097100981009910100101011010210103101041010510106101071010810109101101011110112101131011410115101161011710118101191012010121101221012310124101251012610127101281012910130101311013210133101341013510136101371013810139101401014110142101431014410145101461014710148101491015010151101521015310154101551015610157101581015910160101611016210163101641016510166101671016810169101701017110172101731017410175101761017710178101791018010181101821018310184101851018610187101881018910190101911019210193101941019510196101971019810199102001020110202102031020410205102061020710208102091021010211102121021310214102151021610217102181021910220102211022210223102241022510226102271022810229102301023110232102331023410235102361023710238102391024010241102421024310244102451024610247102481024910250102511025210253102541025510256102571025810259102601026110262102631026410265102661026710268102691027010271102721027310274102751027610277102781027910280102811028210283102841028510286102871028810289102901029110292102931029410295102961029710298102991030010301103021030310304103051030610307103081030910310103111031210313103141031510316103171031810319103201032110322103231032410325103261032710328103291033010331103321033310334103351033610337103381033910340103411034210343103441034510346103471034810349103501035110352103531035410355103561035710358103591036010361103621036310364103651036610367103681036910370103711037210373103741037510376103771037810379103801038110382103831038410385103861038710388103891039010391103921039310394103951039610397103981039910400104011040210403104041040510406104071040810409104101041110412104131041410415104161041710418104191042010421104221042310424104251042610427104281042910430104311043210433104341043510436104371043810439104401044110442104431044410445104461044710448104491045010451104521045310454104551045610457104581045910460104611046210463104641046510466104671046810469104701047110472104731047410475104761047710478104791048010481104821048310484104851048610487104881048910490104911049210493104941049510496104971049810499105001050110502105031050410505105061050710508105091051010511105121051310514105151051610517105181051910520105211052210523105241052510526105271052810529105301053110532105331053410535105361053710538105391054010541105421054310544105451054610547105481054910550105511055210553105541055510556105571055810559105601056110562105631056410565105661056710568105691057010571105721057310574105751057610577105781057910580105811058210583105841058510586105871058810589105901059110592105931059410595105961059710598105991060010601106021060310604106051060610607106081060910610106111061210613106141061510616106171061810619106201062110622106231062410625106261062710628106291063010631106321063310634106351063610637106381063910640106411064210643106441064510646106471064810649106501065110652106531065410655106561065710658106591066010661106621066310664106651066610667106681066910670106711067210673106741067510676106771067810679106801068110682106831068410685106861068710688106891069010691106921069310694106951069610697106981069910700107011070210703107041070510706107071070810709107101071110712107131071410715107161071710718107191072010721107221072310724107251072610727107281072910730107311073210733107341073510736107371073810739107401074110742107431074410745107461074710748107491075010751107521075310754107551075610757107581075910760107611076210763107641076510766107671076810769107701077110772107731077410775107761077710778107791078010781107821078310784107851078610787107881078910790107911079210793107941079510796107971079810799108001080110802108031080410805108061080710808108091081010811108121081310814108151081610817108181081910820108211082210823108241082510826108271082810829108301083110832108331083410835108361083710838108391084010841108421084310844108451084610847108481084910850108511085210853108541085510856108571085810859108601086110862108631086410865108661086710868108691087010871108721087310874108751087610877108781087910880108811088210883108841088510886108871088810889108901089110892108931089410895108961089710898108991090010901109021090310904109051090610907109081090910910109111091210913109141091510916109171091810919109201092110922109231092410925109261092710928109291093010931109321093310934109351093610937109381093910940109411094210943109441094510946109471094810949109501095110952109531095410955109561095710958109591096010961109621096310964109651096610967109681096910970109711097210973109741097510976109771097810979109801098110982109831098410985109861098710988109891099010991109921099310994109951099610997109981099911000110011100211003110041100511006110071100811009110101101111012110131101411015110161101711018110191102011021110221102311024110251102611027110281102911030110311103211033110341103511036110371103811039110401104111042110431104411045110461104711048110491105011051110521105311054110551105611057110581105911060110611106211063110641106511066110671106811069110701107111072110731107411075110761107711078110791108011081110821108311084110851108611087110881108911090110911109211093110941109511096110971109811099111001110111102111031110411105111061110711108111091111011111111121111311114111151111611117111181111911120111211112211123111241112511126111271112811129111301113111132111331113411135111361113711138111391114011141111421114311144111451114611147111481114911150111511115211153111541115511156111571115811159111601116111162111631116411165111661116711168111691117011171111721117311174111751117611177111781117911180111811118211183111841118511186111871118811189111901119111192111931119411195111961119711198111991120011201112021120311204112051120611207112081120911210112111121211213112141121511216112171121811219112201122111222112231122411225112261122711228112291123011231112321123311234112351123611237112381123911240112411124211243112441124511246112471124811249112501125111252112531125411255112561125711258112591126011261112621126311264112651126611267112681126911270112711127211273112741127511276112771127811279112801128111282112831128411285112861128711288112891129011291112921129311294112951129611297112981129911300113011130211303113041130511306113071130811309113101131111312113131131411315113161131711318113191132011321113221132311324113251132611327113281132911330113311133211333113341133511336113371133811339113401134111342113431134411345113461134711348113491135011351113521135311354113551135611357113581135911360113611136211363113641136511366113671136811369113701137111372113731137411375113761137711378113791138011381113821138311384113851138611387113881138911390113911139211393113941139511396113971139811399114001140111402114031140411405114061140711408114091141011411114121141311414114151141611417114181141911420114211142211423114241142511426114271142811429114301143111432114331143411435114361143711438114391144011441114421144311444114451144611447114481144911450114511145211453114541145511456114571145811459114601146111462114631146411465114661146711468114691147011471114721147311474114751147611477114781147911480114811148211483114841148511486114871148811489114901149111492114931149411495114961149711498114991150011501115021150311504115051150611507115081150911510115111151211513115141151511516115171151811519115201152111522115231152411525115261152711528115291153011531115321153311534115351153611537115381153911540115411154211543115441154511546115471154811549115501155111552115531155411555115561155711558115591156011561115621156311564115651156611567115681156911570115711157211573115741157511576115771157811579115801158111582115831158411585115861158711588115891159011591115921159311594115951159611597115981159911600116011160211603116041160511606116071160811609116101161111612116131161411615116161161711618116191162011621116221162311624116251162611627116281162911630116311163211633116341163511636116371163811639116401164111642116431164411645116461164711648116491165011651116521165311654116551165611657116581165911660116611166211663116641166511666116671166811669116701167111672116731167411675116761167711678116791168011681116821168311684116851168611687116881168911690116911169211693116941169511696116971169811699117001170111702117031170411705117061170711708117091171011711117121171311714117151171611717117181171911720117211172211723117241172511726117271172811729117301173111732117331173411735117361173711738117391174011741117421174311744117451174611747117481174911750117511175211753117541175511756117571175811759117601176111762117631176411765117661176711768117691177011771117721177311774117751177611777117781177911780117811178211783117841178511786117871178811789117901179111792117931179411795117961179711798117991180011801118021180311804118051180611807118081180911810118111181211813118141181511816118171181811819118201182111822118231182411825118261182711828118291183011831118321183311834118351183611837118381183911840118411184211843118441184511846118471184811849118501185111852118531185411855118561185711858118591186011861118621186311864118651186611867118681186911870118711187211873118741187511876118771187811879118801188111882118831188411885118861188711888118891189011891118921189311894118951189611897118981189911900119011190211903119041190511906119071190811909119101191111912119131191411915119161191711918119191192011921119221192311924119251192611927119281192911930119311193211933119341193511936119371193811939119401194111942119431194411945119461194711948119491195011951119521195311954119551195611957119581195911960119611196211963119641196511966119671196811969119701197111972119731197411975119761197711978119791198011981119821198311984119851198611987119881198911990119911199211993119941199511996119971199811999120001200112002120031200412005120061200712008120091201012011120121201312014120151201612017120181201912020120211202212023120241202512026120271202812029120301203112032120331203412035120361203712038120391204012041120421204312044120451204612047120481204912050120511205212053120541205512056120571205812059120601206112062120631206412065120661206712068120691207012071120721207312074120751207612077120781207912080120811208212083120841208512086120871208812089120901209112092120931209412095120961209712098120991210012101121021210312104121051210612107121081210912110121111211212113121141211512116121171211812119121201212112122121231212412125121261212712128121291213012131121321213312134121351213612137121381213912140121411214212143121441214512146121471214812149121501215112152121531215412155121561215712158121591216012161121621216312164121651216612167121681216912170121711217212173121741217512176121771217812179121801218112182121831218412185121861218712188121891219012191121921219312194121951219612197121981219912200122011220212203122041220512206122071220812209122101221112212122131221412215122161221712218122191222012221122221222312224122251222612227122281222912230122311223212233122341223512236122371223812239122401224112242122431224412245122461224712248122491225012251122521225312254122551225612257122581225912260122611226212263122641226512266122671226812269122701227112272122731227412275122761227712278122791228012281122821228312284122851228612287122881228912290122911229212293122941229512296122971229812299123001230112302123031230412305123061230712308123091231012311123121231312314123151231612317123181231912320123211232212323123241232512326123271232812329123301233112332123331233412335123361233712338123391234012341123421234312344123451234612347123481234912350123511235212353123541235512356123571235812359123601236112362123631236412365123661236712368123691237012371123721237312374123751237612377123781237912380123811238212383123841238512386123871238812389123901239112392123931239412395123961239712398123991240012401124021240312404124051240612407124081240912410124111241212413124141241512416124171241812419124201242112422124231242412425124261242712428124291243012431124321243312434124351243612437124381243912440124411244212443124441244512446124471244812449124501245112452124531245412455124561245712458124591246012461124621246312464124651246612467124681246912470124711247212473124741247512476124771247812479124801248112482124831248412485124861248712488124891249012491124921249312494124951249612497124981249912500125011250212503125041250512506125071250812509125101251112512125131251412515125161251712518125191252012521125221252312524125251252612527125281252912530125311253212533125341253512536125371253812539125401254112542125431254412545125461254712548125491255012551125521255312554125551255612557125581255912560125611256212563125641256512566125671256812569125701257112572125731257412575125761257712578125791258012581125821258312584125851258612587125881258912590125911259212593125941259512596125971259812599126001260112602126031260412605126061260712608126091261012611126121261312614126151261612617126181261912620126211262212623126241262512626126271262812629126301263112632126331263412635126361263712638126391264012641126421264312644126451264612647126481264912650126511265212653126541265512656126571265812659126601266112662126631266412665126661266712668126691267012671126721267312674126751267612677126781267912680126811268212683126841268512686126871268812689126901269112692126931269412695126961269712698126991270012701127021270312704127051270612707127081270912710127111271212713127141271512716127171271812719127201272112722127231272412725127261272712728127291273012731127321273312734127351273612737127381273912740127411274212743127441274512746127471274812749127501275112752127531275412755127561275712758127591276012761127621276312764127651276612767127681276912770127711277212773127741277512776127771277812779127801278112782127831278412785127861278712788127891279012791127921279312794127951279612797127981279912800128011280212803128041280512806128071280812809128101281112812128131281412815128161281712818128191282012821128221282312824128251282612827128281282912830128311283212833128341283512836128371283812839128401284112842128431284412845128461284712848128491285012851128521285312854128551285612857128581285912860128611286212863128641286512866128671286812869128701287112872128731287412875128761287712878128791288012881128821288312884128851288612887128881288912890128911289212893128941289512896128971289812899129001290112902129031290412905129061290712908129091291012911129121291312914129151291612917129181291912920129211292212923129241292512926129271292812929129301293112932129331293412935129361293712938129391294012941129421294312944129451294612947129481294912950129511295212953129541295512956129571295812959129601296112962129631296412965129661296712968129691297012971129721297312974129751297612977129781297912980129811298212983129841298512986129871298812989129901299112992129931299412995129961299712998129991300013001130021300313004130051300613007130081300913010130111301213013130141301513016130171301813019130201302113022130231302413025130261302713028130291303013031130321303313034130351303613037130381303913040130411304213043130441304513046130471304813049130501305113052130531305413055130561305713058130591306013061130621306313064130651306613067130681306913070130711307213073130741307513076130771307813079130801308113082130831308413085130861308713088130891309013091130921309313094130951309613097130981309913100131011310213103131041310513106131071310813109131101311113112131131311413115131161311713118131191312013121131221312313124131251312613127131281312913130131311313213133131341313513136131371313813139131401314113142131431314413145131461314713148131491315013151131521315313154131551315613157131581315913160131611316213163131641316513166131671316813169131701317113172131731317413175131761317713178131791318013181131821318313184131851318613187131881318913190131911319213193131941319513196131971319813199132001320113202132031320413205132061320713208132091321013211132121321313214132151321613217132181321913220132211322213223132241322513226132271322813229132301323113232132331323413235132361323713238132391324013241132421324313244132451324613247132481324913250132511325213253132541325513256132571325813259132601326113262132631326413265132661326713268132691327013271132721327313274132751327613277132781327913280132811328213283132841328513286132871328813289132901329113292132931329413295132961329713298132991330013301133021330313304133051330613307133081330913310133111331213313133141331513316133171331813319133201332113322133231332413325133261332713328133291333013331133321333313334133351333613337133381333913340133411334213343133441334513346133471334813349133501335113352133531335413355133561335713358133591336013361133621336313364133651336613367133681336913370133711337213373133741337513376133771337813379133801338113382133831338413385133861338713388133891339013391133921339313394133951339613397133981339913400134011340213403134041340513406134071340813409134101341113412134131341413415134161341713418134191342013421134221342313424134251342613427134281342913430134311343213433134341343513436134371343813439134401344113442134431344413445134461344713448134491345013451134521345313454134551345613457134581345913460134611346213463134641346513466134671346813469134701347113472134731347413475134761347713478134791348013481134821348313484134851348613487134881348913490134911349213493134941349513496134971349813499135001350113502135031350413505135061350713508135091351013511135121351313514135151351613517135181351913520135211352213523135241352513526135271352813529135301353113532135331353413535135361353713538135391354013541135421354313544135451354613547135481354913550135511355213553135541355513556135571355813559135601356113562135631356413565135661356713568135691357013571135721357313574135751357613577135781357913580135811358213583135841358513586135871358813589135901359113592135931359413595135961359713598135991360013601136021360313604136051360613607136081360913610136111361213613136141361513616136171361813619136201362113622136231362413625136261362713628136291363013631136321363313634136351363613637136381363913640136411364213643136441364513646136471364813649136501365113652136531365413655136561365713658136591366013661136621366313664136651366613667136681366913670136711367213673136741367513676136771367813679136801368113682136831368413685136861368713688136891369013691136921369313694136951369613697136981369913700137011370213703137041370513706137071370813709137101371113712137131371413715137161371713718137191372013721137221372313724137251372613727137281372913730137311373213733137341373513736137371373813739137401374113742137431374413745137461374713748137491375013751137521375313754137551375613757137581375913760137611376213763137641376513766137671376813769137701377113772137731377413775137761377713778137791378013781137821378313784137851378613787137881378913790137911379213793137941379513796137971379813799138001380113802138031380413805138061380713808138091381013811138121381313814138151381613817138181381913820138211382213823138241382513826138271382813829138301383113832138331383413835138361383713838138391384013841138421384313844138451384613847138481384913850138511385213853138541385513856138571385813859138601386113862138631386413865138661386713868138691387013871138721387313874138751387613877138781387913880138811388213883138841388513886138871388813889138901389113892138931389413895138961389713898138991390013901139021390313904139051390613907139081390913910139111391213913139141391513916139171391813919139201392113922139231392413925139261392713928139291393013931139321393313934139351393613937139381393913940139411394213943139441394513946139471394813949139501395113952139531395413955139561395713958139591396013961139621396313964139651396613967139681396913970139711397213973139741397513976139771397813979139801398113982139831398413985139861398713988139891399013991139921399313994139951399613997139981399914000140011400214003140041400514006140071400814009140101401114012140131401414015140161401714018140191402014021140221402314024140251402614027140281402914030140311403214033140341403514036140371403814039140401404114042140431404414045140461404714048140491405014051140521405314054140551405614057140581405914060140611406214063140641406514066140671406814069140701407114072140731407414075140761407714078140791408014081140821408314084140851408614087140881408914090140911409214093140941409514096140971409814099141001410114102141031410414105141061410714108141091411014111141121411314114141151411614117141181411914120141211412214123141241412514126141271412814129141301413114132141331413414135141361413714138141391414014141141421414314144141451414614147141481414914150141511415214153141541415514156141571415814159141601416114162141631416414165141661416714168141691417014171141721417314174141751417614177141781417914180141811418214183141841418514186141871418814189141901419114192141931419414195141961419714198141991420014201142021420314204142051420614207142081420914210142111421214213142141421514216142171421814219142201422114222142231422414225142261422714228142291423014231142321423314234142351423614237142381423914240142411424214243142441424514246142471424814249142501425114252142531425414255142561425714258142591426014261142621426314264142651426614267142681426914270142711427214273142741427514276142771427814279142801428114282142831428414285142861428714288142891429014291142921429314294142951429614297142981429914300143011430214303143041430514306143071430814309143101431114312143131431414315143161431714318143191432014321143221432314324143251432614327143281432914330143311433214333143341433514336143371433814339143401434114342143431434414345143461434714348143491435014351143521435314354143551435614357143581435914360143611436214363143641436514366143671436814369143701437114372143731437414375143761437714378143791438014381143821438314384143851438614387143881438914390143911439214393143941439514396143971439814399144001440114402144031440414405144061440714408144091441014411144121441314414144151441614417144181441914420144211442214423144241442514426144271442814429144301443114432144331443414435144361443714438144391444014441144421444314444144451444614447144481444914450144511445214453144541445514456144571445814459144601446114462144631446414465144661446714468144691447014471144721447314474144751447614477144781447914480144811448214483144841448514486144871448814489144901449114492144931449414495144961449714498144991450014501145021450314504145051450614507145081450914510145111451214513145141451514516145171451814519145201452114522145231452414525145261452714528145291453014531145321453314534145351453614537145381453914540145411454214543145441454514546145471454814549145501455114552145531455414555145561455714558145591456014561145621456314564145651456614567145681456914570145711457214573145741457514576145771457814579145801458114582145831458414585145861458714588145891459014591145921459314594145951459614597145981459914600146011460214603146041460514606146071460814609146101461114612146131461414615146161461714618146191462014621146221462314624146251462614627146281462914630146311463214633146341463514636146371463814639146401464114642146431464414645146461464714648146491465014651146521465314654146551465614657146581465914660146611466214663146641466514666146671466814669146701467114672146731467414675146761467714678146791468014681146821468314684146851468614687146881468914690146911469214693146941469514696146971469814699147001470114702147031470414705147061470714708147091471014711147121471314714147151471614717147181471914720147211472214723147241472514726147271472814729147301473114732147331473414735147361473714738147391474014741147421474314744147451474614747147481474914750147511475214753147541475514756147571475814759147601476114762147631476414765147661476714768147691477014771147721477314774147751477614777147781477914780147811478214783147841478514786147871478814789147901479114792147931479414795147961479714798147991480014801148021480314804148051480614807148081480914810148111481214813148141481514816148171481814819148201482114822148231482414825148261482714828148291483014831148321483314834148351483614837148381483914840148411484214843148441484514846148471484814849148501485114852148531485414855
  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2010 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/stringify.h>
  20. #include <linux/kernel.h>
  21. #include <linux/types.h>
  22. #include <linux/compiler.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/in.h>
  26. #include <linux/init.h>
  27. #include <linux/ioport.h>
  28. #include <linux/pci.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/mii.h>
  34. #include <linux/phy.h>
  35. #include <linux/brcmphy.h>
  36. #include <linux/if_vlan.h>
  37. #include <linux/ip.h>
  38. #include <linux/tcp.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/prefetch.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/firmware.h>
  43. #include <net/checksum.h>
  44. #include <net/ip.h>
  45. #include <asm/system.h>
  46. #include <asm/io.h>
  47. #include <asm/byteorder.h>
  48. #include <asm/uaccess.h>
  49. #ifdef CONFIG_SPARC
  50. #include <asm/idprom.h>
  51. #include <asm/prom.h>
  52. #endif
  53. #define BAR_0 0
  54. #define BAR_2 2
  55. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56. #define TG3_VLAN_TAG_USED 1
  57. #else
  58. #define TG3_VLAN_TAG_USED 0
  59. #endif
  60. #include "tg3.h"
  61. #define DRV_MODULE_NAME "tg3"
  62. #define TG3_MAJ_NUM 3
  63. #define TG3_MIN_NUM 113
  64. #define DRV_MODULE_VERSION \
  65. __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  66. #define DRV_MODULE_RELDATE "August 2, 2010"
  67. #define TG3_DEF_MAC_MODE 0
  68. #define TG3_DEF_RX_MODE 0
  69. #define TG3_DEF_TX_MODE 0
  70. #define TG3_DEF_MSG_ENABLE \
  71. (NETIF_MSG_DRV | \
  72. NETIF_MSG_PROBE | \
  73. NETIF_MSG_LINK | \
  74. NETIF_MSG_TIMER | \
  75. NETIF_MSG_IFDOWN | \
  76. NETIF_MSG_IFUP | \
  77. NETIF_MSG_RX_ERR | \
  78. NETIF_MSG_TX_ERR)
  79. /* length of time before we decide the hardware is borked,
  80. * and dev->tx_timeout() should be called to fix the problem
  81. */
  82. #define TG3_TX_TIMEOUT (5 * HZ)
  83. /* hardware minimum and maximum for a single frame's data payload */
  84. #define TG3_MIN_MTU 60
  85. #define TG3_MAX_MTU(tp) \
  86. ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  87. /* These numbers seem to be hard coded in the NIC firmware somehow.
  88. * You can't change the ring sizes, but you can change where you place
  89. * them in the NIC onboard memory.
  90. */
  91. #define TG3_RX_RING_SIZE 512
  92. #define TG3_DEF_RX_RING_PENDING 200
  93. #define TG3_RX_JUMBO_RING_SIZE 256
  94. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  95. #define TG3_RSS_INDIR_TBL_SIZE 128
  96. /* Do not place this n-ring entries value into the tp struct itself,
  97. * we really want to expose these constants to GCC so that modulo et
  98. * al. operations are done with shifts and masks instead of with
  99. * hw multiply/modulo instructions. Another solution would be to
  100. * replace things like '% foo' with '& (foo - 1)'.
  101. */
  102. #define TG3_RX_RCB_RING_SIZE(tp) \
  103. (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
  104. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
  105. #define TG3_TX_RING_SIZE 512
  106. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  107. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  108. TG3_RX_RING_SIZE)
  109. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
  110. TG3_RX_JUMBO_RING_SIZE)
  111. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  112. TG3_RX_RCB_RING_SIZE(tp))
  113. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  114. TG3_TX_RING_SIZE)
  115. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  116. #define TG3_RX_DMA_ALIGN 16
  117. #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
  118. #define TG3_DMA_BYTE_ENAB 64
  119. #define TG3_RX_STD_DMA_SZ 1536
  120. #define TG3_RX_JMB_DMA_SZ 9046
  121. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  122. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  123. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  124. #define TG3_RX_STD_BUFF_RING_SIZE \
  125. (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
  126. #define TG3_RX_JMB_BUFF_RING_SIZE \
  127. (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
  128. /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  129. * that are at least dword aligned when used in PCIX mode. The driver
  130. * works around this bug by double copying the packet. This workaround
  131. * is built into the normal double copy length check for efficiency.
  132. *
  133. * However, the double copy is only necessary on those architectures
  134. * where unaligned memory accesses are inefficient. For those architectures
  135. * where unaligned memory accesses incur little penalty, we can reintegrate
  136. * the 5701 in the normal rx path. Doing so saves a device structure
  137. * dereference by hardcoding the double copy threshold in place.
  138. */
  139. #define TG3_RX_COPY_THRESHOLD 256
  140. #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  141. #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
  142. #else
  143. #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
  144. #endif
  145. /* minimum number of free TX descriptors required to wake up TX process */
  146. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  147. #define TG3_RAW_IP_ALIGN 2
  148. /* number of ETHTOOL_GSTATS u64's */
  149. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  150. #define TG3_NUM_TEST 6
  151. #define TG3_FW_UPDATE_TIMEOUT_SEC 5
  152. #define FIRMWARE_TG3 "tigon/tg3.bin"
  153. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  154. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  155. static char version[] __devinitdata =
  156. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
  157. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  158. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  159. MODULE_LICENSE("GPL");
  160. MODULE_VERSION(DRV_MODULE_VERSION);
  161. MODULE_FIRMWARE(FIRMWARE_TG3);
  162. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  163. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  164. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  165. module_param(tg3_debug, int, 0);
  166. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  167. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  184. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  185. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  186. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  187. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  188. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  189. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  190. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  191. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  192. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  193. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  194. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  195. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  196. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  215. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  216. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  217. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  218. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  219. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  220. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  221. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  222. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  223. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  224. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  225. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  228. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  229. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
  230. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  231. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  232. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  233. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
  234. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  235. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  236. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  237. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  238. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
  239. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
  240. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  241. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  242. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  243. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  244. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  245. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  246. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  247. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  248. {}
  249. };
  250. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  251. static const struct {
  252. const char string[ETH_GSTRING_LEN];
  253. } ethtool_stats_keys[TG3_NUM_STATS] = {
  254. { "rx_octets" },
  255. { "rx_fragments" },
  256. { "rx_ucast_packets" },
  257. { "rx_mcast_packets" },
  258. { "rx_bcast_packets" },
  259. { "rx_fcs_errors" },
  260. { "rx_align_errors" },
  261. { "rx_xon_pause_rcvd" },
  262. { "rx_xoff_pause_rcvd" },
  263. { "rx_mac_ctrl_rcvd" },
  264. { "rx_xoff_entered" },
  265. { "rx_frame_too_long_errors" },
  266. { "rx_jabbers" },
  267. { "rx_undersize_packets" },
  268. { "rx_in_length_errors" },
  269. { "rx_out_length_errors" },
  270. { "rx_64_or_less_octet_packets" },
  271. { "rx_65_to_127_octet_packets" },
  272. { "rx_128_to_255_octet_packets" },
  273. { "rx_256_to_511_octet_packets" },
  274. { "rx_512_to_1023_octet_packets" },
  275. { "rx_1024_to_1522_octet_packets" },
  276. { "rx_1523_to_2047_octet_packets" },
  277. { "rx_2048_to_4095_octet_packets" },
  278. { "rx_4096_to_8191_octet_packets" },
  279. { "rx_8192_to_9022_octet_packets" },
  280. { "tx_octets" },
  281. { "tx_collisions" },
  282. { "tx_xon_sent" },
  283. { "tx_xoff_sent" },
  284. { "tx_flow_control" },
  285. { "tx_mac_errors" },
  286. { "tx_single_collisions" },
  287. { "tx_mult_collisions" },
  288. { "tx_deferred" },
  289. { "tx_excessive_collisions" },
  290. { "tx_late_collisions" },
  291. { "tx_collide_2times" },
  292. { "tx_collide_3times" },
  293. { "tx_collide_4times" },
  294. { "tx_collide_5times" },
  295. { "tx_collide_6times" },
  296. { "tx_collide_7times" },
  297. { "tx_collide_8times" },
  298. { "tx_collide_9times" },
  299. { "tx_collide_10times" },
  300. { "tx_collide_11times" },
  301. { "tx_collide_12times" },
  302. { "tx_collide_13times" },
  303. { "tx_collide_14times" },
  304. { "tx_collide_15times" },
  305. { "tx_ucast_packets" },
  306. { "tx_mcast_packets" },
  307. { "tx_bcast_packets" },
  308. { "tx_carrier_sense_errors" },
  309. { "tx_discards" },
  310. { "tx_errors" },
  311. { "dma_writeq_full" },
  312. { "dma_write_prioq_full" },
  313. { "rxbds_empty" },
  314. { "rx_discards" },
  315. { "rx_errors" },
  316. { "rx_threshold_hit" },
  317. { "dma_readq_full" },
  318. { "dma_read_prioq_full" },
  319. { "tx_comp_queue_full" },
  320. { "ring_set_send_prod_index" },
  321. { "ring_status_update" },
  322. { "nic_irqs" },
  323. { "nic_avoided_irqs" },
  324. { "nic_tx_threshold_hit" }
  325. };
  326. static const struct {
  327. const char string[ETH_GSTRING_LEN];
  328. } ethtool_test_keys[TG3_NUM_TEST] = {
  329. { "nvram test (online) " },
  330. { "link test (online) " },
  331. { "register test (offline)" },
  332. { "memory test (offline)" },
  333. { "loopback test (offline)" },
  334. { "interrupt test (offline)" },
  335. };
  336. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  337. {
  338. writel(val, tp->regs + off);
  339. }
  340. static u32 tg3_read32(struct tg3 *tp, u32 off)
  341. {
  342. return readl(tp->regs + off);
  343. }
  344. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  345. {
  346. writel(val, tp->aperegs + off);
  347. }
  348. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  349. {
  350. return readl(tp->aperegs + off);
  351. }
  352. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  353. {
  354. unsigned long flags;
  355. spin_lock_irqsave(&tp->indirect_lock, flags);
  356. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  357. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  358. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  359. }
  360. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  361. {
  362. writel(val, tp->regs + off);
  363. readl(tp->regs + off);
  364. }
  365. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  366. {
  367. unsigned long flags;
  368. u32 val;
  369. spin_lock_irqsave(&tp->indirect_lock, flags);
  370. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  371. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  372. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  373. return val;
  374. }
  375. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  376. {
  377. unsigned long flags;
  378. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  379. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  380. TG3_64BIT_REG_LOW, val);
  381. return;
  382. }
  383. if (off == TG3_RX_STD_PROD_IDX_REG) {
  384. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  385. TG3_64BIT_REG_LOW, val);
  386. return;
  387. }
  388. spin_lock_irqsave(&tp->indirect_lock, flags);
  389. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  390. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  391. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  392. /* In indirect mode when disabling interrupts, we also need
  393. * to clear the interrupt bit in the GRC local ctrl register.
  394. */
  395. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  396. (val == 0x1)) {
  397. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  398. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  399. }
  400. }
  401. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  402. {
  403. unsigned long flags;
  404. u32 val;
  405. spin_lock_irqsave(&tp->indirect_lock, flags);
  406. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  407. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  408. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  409. return val;
  410. }
  411. /* usec_wait specifies the wait time in usec when writing to certain registers
  412. * where it is unsafe to read back the register without some delay.
  413. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  414. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  415. */
  416. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  417. {
  418. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  419. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  420. /* Non-posted methods */
  421. tp->write32(tp, off, val);
  422. else {
  423. /* Posted method */
  424. tg3_write32(tp, off, val);
  425. if (usec_wait)
  426. udelay(usec_wait);
  427. tp->read32(tp, off);
  428. }
  429. /* Wait again after the read for the posted method to guarantee that
  430. * the wait time is met.
  431. */
  432. if (usec_wait)
  433. udelay(usec_wait);
  434. }
  435. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  436. {
  437. tp->write32_mbox(tp, off, val);
  438. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  439. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  440. tp->read32_mbox(tp, off);
  441. }
  442. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  443. {
  444. void __iomem *mbox = tp->regs + off;
  445. writel(val, mbox);
  446. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  447. writel(val, mbox);
  448. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  449. readl(mbox);
  450. }
  451. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  452. {
  453. return readl(tp->regs + off + GRCMBOX_BASE);
  454. }
  455. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  456. {
  457. writel(val, tp->regs + off + GRCMBOX_BASE);
  458. }
  459. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  460. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  461. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  462. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  463. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  464. #define tw32(reg, val) tp->write32(tp, reg, val)
  465. #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
  466. #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
  467. #define tr32(reg) tp->read32(tp, reg)
  468. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  469. {
  470. unsigned long flags;
  471. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  472. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  473. return;
  474. spin_lock_irqsave(&tp->indirect_lock, flags);
  475. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  476. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  477. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  478. /* Always leave this as zero. */
  479. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  480. } else {
  481. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  482. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  483. /* Always leave this as zero. */
  484. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  485. }
  486. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  487. }
  488. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  489. {
  490. unsigned long flags;
  491. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  492. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  493. *val = 0;
  494. return;
  495. }
  496. spin_lock_irqsave(&tp->indirect_lock, flags);
  497. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  498. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  499. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  500. /* Always leave this as zero. */
  501. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  502. } else {
  503. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  504. *val = tr32(TG3PCI_MEM_WIN_DATA);
  505. /* Always leave this as zero. */
  506. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  507. }
  508. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  509. }
  510. static void tg3_ape_lock_init(struct tg3 *tp)
  511. {
  512. int i;
  513. u32 regbase;
  514. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  515. regbase = TG3_APE_LOCK_GRANT;
  516. else
  517. regbase = TG3_APE_PER_LOCK_GRANT;
  518. /* Make sure the driver hasn't any stale locks. */
  519. for (i = 0; i < 8; i++)
  520. tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
  521. }
  522. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  523. {
  524. int i, off;
  525. int ret = 0;
  526. u32 status, req, gnt;
  527. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  528. return 0;
  529. switch (locknum) {
  530. case TG3_APE_LOCK_GRC:
  531. case TG3_APE_LOCK_MEM:
  532. break;
  533. default:
  534. return -EINVAL;
  535. }
  536. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  537. req = TG3_APE_LOCK_REQ;
  538. gnt = TG3_APE_LOCK_GRANT;
  539. } else {
  540. req = TG3_APE_PER_LOCK_REQ;
  541. gnt = TG3_APE_PER_LOCK_GRANT;
  542. }
  543. off = 4 * locknum;
  544. tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
  545. /* Wait for up to 1 millisecond to acquire lock. */
  546. for (i = 0; i < 100; i++) {
  547. status = tg3_ape_read32(tp, gnt + off);
  548. if (status == APE_LOCK_GRANT_DRIVER)
  549. break;
  550. udelay(10);
  551. }
  552. if (status != APE_LOCK_GRANT_DRIVER) {
  553. /* Revoke the lock request. */
  554. tg3_ape_write32(tp, gnt + off,
  555. APE_LOCK_GRANT_DRIVER);
  556. ret = -EBUSY;
  557. }
  558. return ret;
  559. }
  560. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  561. {
  562. u32 gnt;
  563. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  564. return;
  565. switch (locknum) {
  566. case TG3_APE_LOCK_GRC:
  567. case TG3_APE_LOCK_MEM:
  568. break;
  569. default:
  570. return;
  571. }
  572. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  573. gnt = TG3_APE_LOCK_GRANT;
  574. else
  575. gnt = TG3_APE_PER_LOCK_GRANT;
  576. tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
  577. }
  578. static void tg3_disable_ints(struct tg3 *tp)
  579. {
  580. int i;
  581. tw32(TG3PCI_MISC_HOST_CTRL,
  582. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  583. for (i = 0; i < tp->irq_max; i++)
  584. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  585. }
  586. static void tg3_enable_ints(struct tg3 *tp)
  587. {
  588. int i;
  589. tp->irq_sync = 0;
  590. wmb();
  591. tw32(TG3PCI_MISC_HOST_CTRL,
  592. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  593. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  594. for (i = 0; i < tp->irq_cnt; i++) {
  595. struct tg3_napi *tnapi = &tp->napi[i];
  596. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  597. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  598. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  599. tp->coal_now |= tnapi->coal_now;
  600. }
  601. /* Force an initial interrupt */
  602. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  603. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  604. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  605. else
  606. tw32(HOSTCC_MODE, tp->coal_now);
  607. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  608. }
  609. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  610. {
  611. struct tg3 *tp = tnapi->tp;
  612. struct tg3_hw_status *sblk = tnapi->hw_status;
  613. unsigned int work_exists = 0;
  614. /* check for phy events */
  615. if (!(tp->tg3_flags &
  616. (TG3_FLAG_USE_LINKCHG_REG |
  617. TG3_FLAG_POLL_SERDES))) {
  618. if (sblk->status & SD_STATUS_LINK_CHG)
  619. work_exists = 1;
  620. }
  621. /* check for RX/TX work to do */
  622. if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
  623. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  624. work_exists = 1;
  625. return work_exists;
  626. }
  627. /* tg3_int_reenable
  628. * similar to tg3_enable_ints, but it accurately determines whether there
  629. * is new work pending and can return without flushing the PIO write
  630. * which reenables interrupts
  631. */
  632. static void tg3_int_reenable(struct tg3_napi *tnapi)
  633. {
  634. struct tg3 *tp = tnapi->tp;
  635. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  636. mmiowb();
  637. /* When doing tagged status, this work check is unnecessary.
  638. * The last_tag we write above tells the chip which piece of
  639. * work we've completed.
  640. */
  641. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  642. tg3_has_work(tnapi))
  643. tw32(HOSTCC_MODE, tp->coalesce_mode |
  644. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  645. }
  646. static void tg3_napi_disable(struct tg3 *tp)
  647. {
  648. int i;
  649. for (i = tp->irq_cnt - 1; i >= 0; i--)
  650. napi_disable(&tp->napi[i].napi);
  651. }
  652. static void tg3_napi_enable(struct tg3 *tp)
  653. {
  654. int i;
  655. for (i = 0; i < tp->irq_cnt; i++)
  656. napi_enable(&tp->napi[i].napi);
  657. }
  658. static inline void tg3_netif_stop(struct tg3 *tp)
  659. {
  660. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  661. tg3_napi_disable(tp);
  662. netif_tx_disable(tp->dev);
  663. }
  664. static inline void tg3_netif_start(struct tg3 *tp)
  665. {
  666. /* NOTE: unconditional netif_tx_wake_all_queues is only
  667. * appropriate so long as all callers are assured to
  668. * have free tx slots (such as after tg3_init_hw)
  669. */
  670. netif_tx_wake_all_queues(tp->dev);
  671. tg3_napi_enable(tp);
  672. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  673. tg3_enable_ints(tp);
  674. }
  675. static void tg3_switch_clocks(struct tg3 *tp)
  676. {
  677. u32 clock_ctrl;
  678. u32 orig_clock_ctrl;
  679. if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  680. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  681. return;
  682. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  683. orig_clock_ctrl = clock_ctrl;
  684. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  685. CLOCK_CTRL_CLKRUN_OENABLE |
  686. 0x1f);
  687. tp->pci_clock_ctrl = clock_ctrl;
  688. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  689. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  690. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  691. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  692. }
  693. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  694. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  695. clock_ctrl |
  696. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  697. 40);
  698. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  699. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  700. 40);
  701. }
  702. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  703. }
  704. #define PHY_BUSY_LOOPS 5000
  705. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  706. {
  707. u32 frame_val;
  708. unsigned int loops;
  709. int ret;
  710. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  711. tw32_f(MAC_MI_MODE,
  712. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  713. udelay(80);
  714. }
  715. *val = 0x0;
  716. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  717. MI_COM_PHY_ADDR_MASK);
  718. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  719. MI_COM_REG_ADDR_MASK);
  720. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  721. tw32_f(MAC_MI_COM, frame_val);
  722. loops = PHY_BUSY_LOOPS;
  723. while (loops != 0) {
  724. udelay(10);
  725. frame_val = tr32(MAC_MI_COM);
  726. if ((frame_val & MI_COM_BUSY) == 0) {
  727. udelay(5);
  728. frame_val = tr32(MAC_MI_COM);
  729. break;
  730. }
  731. loops -= 1;
  732. }
  733. ret = -EBUSY;
  734. if (loops != 0) {
  735. *val = frame_val & MI_COM_DATA_MASK;
  736. ret = 0;
  737. }
  738. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  739. tw32_f(MAC_MI_MODE, tp->mi_mode);
  740. udelay(80);
  741. }
  742. return ret;
  743. }
  744. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  745. {
  746. u32 frame_val;
  747. unsigned int loops;
  748. int ret;
  749. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  750. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  751. return 0;
  752. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  753. tw32_f(MAC_MI_MODE,
  754. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  755. udelay(80);
  756. }
  757. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  758. MI_COM_PHY_ADDR_MASK);
  759. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  760. MI_COM_REG_ADDR_MASK);
  761. frame_val |= (val & MI_COM_DATA_MASK);
  762. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  763. tw32_f(MAC_MI_COM, frame_val);
  764. loops = PHY_BUSY_LOOPS;
  765. while (loops != 0) {
  766. udelay(10);
  767. frame_val = tr32(MAC_MI_COM);
  768. if ((frame_val & MI_COM_BUSY) == 0) {
  769. udelay(5);
  770. frame_val = tr32(MAC_MI_COM);
  771. break;
  772. }
  773. loops -= 1;
  774. }
  775. ret = -EBUSY;
  776. if (loops != 0)
  777. ret = 0;
  778. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  779. tw32_f(MAC_MI_MODE, tp->mi_mode);
  780. udelay(80);
  781. }
  782. return ret;
  783. }
  784. static int tg3_bmcr_reset(struct tg3 *tp)
  785. {
  786. u32 phy_control;
  787. int limit, err;
  788. /* OK, reset it, and poll the BMCR_RESET bit until it
  789. * clears or we time out.
  790. */
  791. phy_control = BMCR_RESET;
  792. err = tg3_writephy(tp, MII_BMCR, phy_control);
  793. if (err != 0)
  794. return -EBUSY;
  795. limit = 5000;
  796. while (limit--) {
  797. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  798. if (err != 0)
  799. return -EBUSY;
  800. if ((phy_control & BMCR_RESET) == 0) {
  801. udelay(40);
  802. break;
  803. }
  804. udelay(10);
  805. }
  806. if (limit < 0)
  807. return -EBUSY;
  808. return 0;
  809. }
  810. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  811. {
  812. struct tg3 *tp = bp->priv;
  813. u32 val;
  814. spin_lock_bh(&tp->lock);
  815. if (tg3_readphy(tp, reg, &val))
  816. val = -EIO;
  817. spin_unlock_bh(&tp->lock);
  818. return val;
  819. }
  820. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  821. {
  822. struct tg3 *tp = bp->priv;
  823. u32 ret = 0;
  824. spin_lock_bh(&tp->lock);
  825. if (tg3_writephy(tp, reg, val))
  826. ret = -EIO;
  827. spin_unlock_bh(&tp->lock);
  828. return ret;
  829. }
  830. static int tg3_mdio_reset(struct mii_bus *bp)
  831. {
  832. return 0;
  833. }
  834. static void tg3_mdio_config_5785(struct tg3 *tp)
  835. {
  836. u32 val;
  837. struct phy_device *phydev;
  838. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  839. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  840. case PHY_ID_BCM50610:
  841. case PHY_ID_BCM50610M:
  842. val = MAC_PHYCFG2_50610_LED_MODES;
  843. break;
  844. case PHY_ID_BCMAC131:
  845. val = MAC_PHYCFG2_AC131_LED_MODES;
  846. break;
  847. case PHY_ID_RTL8211C:
  848. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  849. break;
  850. case PHY_ID_RTL8201E:
  851. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  852. break;
  853. default:
  854. return;
  855. }
  856. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  857. tw32(MAC_PHYCFG2, val);
  858. val = tr32(MAC_PHYCFG1);
  859. val &= ~(MAC_PHYCFG1_RGMII_INT |
  860. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  861. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  862. tw32(MAC_PHYCFG1, val);
  863. return;
  864. }
  865. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
  866. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  867. MAC_PHYCFG2_FMODE_MASK_MASK |
  868. MAC_PHYCFG2_GMODE_MASK_MASK |
  869. MAC_PHYCFG2_ACT_MASK_MASK |
  870. MAC_PHYCFG2_QUAL_MASK_MASK |
  871. MAC_PHYCFG2_INBAND_ENABLE;
  872. tw32(MAC_PHYCFG2, val);
  873. val = tr32(MAC_PHYCFG1);
  874. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  875. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  876. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
  877. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  878. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  879. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  880. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  881. }
  882. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  883. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  884. tw32(MAC_PHYCFG1, val);
  885. val = tr32(MAC_EXT_RGMII_MODE);
  886. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  887. MAC_RGMII_MODE_RX_QUALITY |
  888. MAC_RGMII_MODE_RX_ACTIVITY |
  889. MAC_RGMII_MODE_RX_ENG_DET |
  890. MAC_RGMII_MODE_TX_ENABLE |
  891. MAC_RGMII_MODE_TX_LOWPWR |
  892. MAC_RGMII_MODE_TX_RESET);
  893. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
  894. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  895. val |= MAC_RGMII_MODE_RX_INT_B |
  896. MAC_RGMII_MODE_RX_QUALITY |
  897. MAC_RGMII_MODE_RX_ACTIVITY |
  898. MAC_RGMII_MODE_RX_ENG_DET;
  899. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  900. val |= MAC_RGMII_MODE_TX_ENABLE |
  901. MAC_RGMII_MODE_TX_LOWPWR |
  902. MAC_RGMII_MODE_TX_RESET;
  903. }
  904. tw32(MAC_EXT_RGMII_MODE, val);
  905. }
  906. static void tg3_mdio_start(struct tg3 *tp)
  907. {
  908. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  909. tw32_f(MAC_MI_MODE, tp->mi_mode);
  910. udelay(80);
  911. if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
  912. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  913. tg3_mdio_config_5785(tp);
  914. }
  915. static int tg3_mdio_init(struct tg3 *tp)
  916. {
  917. int i;
  918. u32 reg;
  919. struct phy_device *phydev;
  920. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  921. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
  922. u32 is_serdes;
  923. tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
  924. if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  925. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  926. else
  927. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  928. TG3_CPMU_PHY_STRAP_IS_SERDES;
  929. if (is_serdes)
  930. tp->phy_addr += 7;
  931. } else
  932. tp->phy_addr = TG3_PHY_MII_ADDR;
  933. tg3_mdio_start(tp);
  934. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
  935. (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
  936. return 0;
  937. tp->mdio_bus = mdiobus_alloc();
  938. if (tp->mdio_bus == NULL)
  939. return -ENOMEM;
  940. tp->mdio_bus->name = "tg3 mdio bus";
  941. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  942. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  943. tp->mdio_bus->priv = tp;
  944. tp->mdio_bus->parent = &tp->pdev->dev;
  945. tp->mdio_bus->read = &tg3_mdio_read;
  946. tp->mdio_bus->write = &tg3_mdio_write;
  947. tp->mdio_bus->reset = &tg3_mdio_reset;
  948. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  949. tp->mdio_bus->irq = &tp->mdio_irq[0];
  950. for (i = 0; i < PHY_MAX_ADDR; i++)
  951. tp->mdio_bus->irq[i] = PHY_POLL;
  952. /* The bus registration will look for all the PHYs on the mdio bus.
  953. * Unfortunately, it does not ensure the PHY is powered up before
  954. * accessing the PHY ID registers. A chip reset is the
  955. * quickest way to bring the device back to an operational state..
  956. */
  957. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  958. tg3_bmcr_reset(tp);
  959. i = mdiobus_register(tp->mdio_bus);
  960. if (i) {
  961. dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
  962. mdiobus_free(tp->mdio_bus);
  963. return i;
  964. }
  965. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  966. if (!phydev || !phydev->drv) {
  967. dev_warn(&tp->pdev->dev, "No PHY devices\n");
  968. mdiobus_unregister(tp->mdio_bus);
  969. mdiobus_free(tp->mdio_bus);
  970. return -ENODEV;
  971. }
  972. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  973. case PHY_ID_BCM57780:
  974. phydev->interface = PHY_INTERFACE_MODE_GMII;
  975. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  976. break;
  977. case PHY_ID_BCM50610:
  978. case PHY_ID_BCM50610M:
  979. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  980. PHY_BRCM_RX_REFCLK_UNUSED |
  981. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  982. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  983. if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
  984. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  985. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  986. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  987. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  988. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  989. /* fallthru */
  990. case PHY_ID_RTL8211C:
  991. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  992. break;
  993. case PHY_ID_RTL8201E:
  994. case PHY_ID_BCMAC131:
  995. phydev->interface = PHY_INTERFACE_MODE_MII;
  996. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  997. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  998. break;
  999. }
  1000. tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
  1001. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  1002. tg3_mdio_config_5785(tp);
  1003. return 0;
  1004. }
  1005. static void tg3_mdio_fini(struct tg3 *tp)
  1006. {
  1007. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
  1008. tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
  1009. mdiobus_unregister(tp->mdio_bus);
  1010. mdiobus_free(tp->mdio_bus);
  1011. }
  1012. }
  1013. /* tp->lock is held. */
  1014. static inline void tg3_generate_fw_event(struct tg3 *tp)
  1015. {
  1016. u32 val;
  1017. val = tr32(GRC_RX_CPU_EVENT);
  1018. val |= GRC_RX_CPU_DRIVER_EVENT;
  1019. tw32_f(GRC_RX_CPU_EVENT, val);
  1020. tp->last_event_jiffies = jiffies;
  1021. }
  1022. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  1023. /* tp->lock is held. */
  1024. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1025. {
  1026. int i;
  1027. unsigned int delay_cnt;
  1028. long time_remain;
  1029. /* If enough time has passed, no wait is necessary. */
  1030. time_remain = (long)(tp->last_event_jiffies + 1 +
  1031. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1032. (long)jiffies;
  1033. if (time_remain < 0)
  1034. return;
  1035. /* Check if we can shorten the wait time. */
  1036. delay_cnt = jiffies_to_usecs(time_remain);
  1037. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1038. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1039. delay_cnt = (delay_cnt >> 3) + 1;
  1040. for (i = 0; i < delay_cnt; i++) {
  1041. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1042. break;
  1043. udelay(8);
  1044. }
  1045. }
  1046. /* tp->lock is held. */
  1047. static void tg3_ump_link_report(struct tg3 *tp)
  1048. {
  1049. u32 reg;
  1050. u32 val;
  1051. if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1052. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1053. return;
  1054. tg3_wait_for_event_ack(tp);
  1055. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1056. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1057. val = 0;
  1058. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1059. val = reg << 16;
  1060. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1061. val |= (reg & 0xffff);
  1062. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
  1063. val = 0;
  1064. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1065. val = reg << 16;
  1066. if (!tg3_readphy(tp, MII_LPA, &reg))
  1067. val |= (reg & 0xffff);
  1068. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
  1069. val = 0;
  1070. if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
  1071. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1072. val = reg << 16;
  1073. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1074. val |= (reg & 0xffff);
  1075. }
  1076. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
  1077. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1078. val = reg << 16;
  1079. else
  1080. val = 0;
  1081. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
  1082. tg3_generate_fw_event(tp);
  1083. }
  1084. static void tg3_link_report(struct tg3 *tp)
  1085. {
  1086. if (!netif_carrier_ok(tp->dev)) {
  1087. netif_info(tp, link, tp->dev, "Link is down\n");
  1088. tg3_ump_link_report(tp);
  1089. } else if (netif_msg_link(tp)) {
  1090. netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
  1091. (tp->link_config.active_speed == SPEED_1000 ?
  1092. 1000 :
  1093. (tp->link_config.active_speed == SPEED_100 ?
  1094. 100 : 10)),
  1095. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1096. "full" : "half"));
  1097. netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
  1098. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1099. "on" : "off",
  1100. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1101. "on" : "off");
  1102. tg3_ump_link_report(tp);
  1103. }
  1104. }
  1105. static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
  1106. {
  1107. u16 miireg;
  1108. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1109. miireg = ADVERTISE_PAUSE_CAP;
  1110. else if (flow_ctrl & FLOW_CTRL_TX)
  1111. miireg = ADVERTISE_PAUSE_ASYM;
  1112. else if (flow_ctrl & FLOW_CTRL_RX)
  1113. miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1114. else
  1115. miireg = 0;
  1116. return miireg;
  1117. }
  1118. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1119. {
  1120. u16 miireg;
  1121. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1122. miireg = ADVERTISE_1000XPAUSE;
  1123. else if (flow_ctrl & FLOW_CTRL_TX)
  1124. miireg = ADVERTISE_1000XPSE_ASYM;
  1125. else if (flow_ctrl & FLOW_CTRL_RX)
  1126. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1127. else
  1128. miireg = 0;
  1129. return miireg;
  1130. }
  1131. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1132. {
  1133. u8 cap = 0;
  1134. if (lcladv & ADVERTISE_1000XPAUSE) {
  1135. if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1136. if (rmtadv & LPA_1000XPAUSE)
  1137. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1138. else if (rmtadv & LPA_1000XPAUSE_ASYM)
  1139. cap = FLOW_CTRL_RX;
  1140. } else {
  1141. if (rmtadv & LPA_1000XPAUSE)
  1142. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1143. }
  1144. } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1145. if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
  1146. cap = FLOW_CTRL_TX;
  1147. }
  1148. return cap;
  1149. }
  1150. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1151. {
  1152. u8 autoneg;
  1153. u8 flowctrl = 0;
  1154. u32 old_rx_mode = tp->rx_mode;
  1155. u32 old_tx_mode = tp->tx_mode;
  1156. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  1157. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1158. else
  1159. autoneg = tp->link_config.autoneg;
  1160. if (autoneg == AUTONEG_ENABLE &&
  1161. (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
  1162. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  1163. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1164. else
  1165. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1166. } else
  1167. flowctrl = tp->link_config.flowctrl;
  1168. tp->link_config.active_flowctrl = flowctrl;
  1169. if (flowctrl & FLOW_CTRL_RX)
  1170. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1171. else
  1172. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1173. if (old_rx_mode != tp->rx_mode)
  1174. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1175. if (flowctrl & FLOW_CTRL_TX)
  1176. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1177. else
  1178. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1179. if (old_tx_mode != tp->tx_mode)
  1180. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1181. }
  1182. static void tg3_adjust_link(struct net_device *dev)
  1183. {
  1184. u8 oldflowctrl, linkmesg = 0;
  1185. u32 mac_mode, lcl_adv, rmt_adv;
  1186. struct tg3 *tp = netdev_priv(dev);
  1187. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1188. spin_lock_bh(&tp->lock);
  1189. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1190. MAC_MODE_HALF_DUPLEX);
  1191. oldflowctrl = tp->link_config.active_flowctrl;
  1192. if (phydev->link) {
  1193. lcl_adv = 0;
  1194. rmt_adv = 0;
  1195. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1196. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1197. else if (phydev->speed == SPEED_1000 ||
  1198. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
  1199. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1200. else
  1201. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1202. if (phydev->duplex == DUPLEX_HALF)
  1203. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1204. else {
  1205. lcl_adv = tg3_advert_flowctrl_1000T(
  1206. tp->link_config.flowctrl);
  1207. if (phydev->pause)
  1208. rmt_adv = LPA_PAUSE_CAP;
  1209. if (phydev->asym_pause)
  1210. rmt_adv |= LPA_PAUSE_ASYM;
  1211. }
  1212. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1213. } else
  1214. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1215. if (mac_mode != tp->mac_mode) {
  1216. tp->mac_mode = mac_mode;
  1217. tw32_f(MAC_MODE, tp->mac_mode);
  1218. udelay(40);
  1219. }
  1220. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  1221. if (phydev->speed == SPEED_10)
  1222. tw32(MAC_MI_STAT,
  1223. MAC_MI_STAT_10MBPS_MODE |
  1224. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1225. else
  1226. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1227. }
  1228. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1229. tw32(MAC_TX_LENGTHS,
  1230. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1231. (6 << TX_LENGTHS_IPG_SHIFT) |
  1232. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1233. else
  1234. tw32(MAC_TX_LENGTHS,
  1235. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1236. (6 << TX_LENGTHS_IPG_SHIFT) |
  1237. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1238. if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
  1239. (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
  1240. phydev->speed != tp->link_config.active_speed ||
  1241. phydev->duplex != tp->link_config.active_duplex ||
  1242. oldflowctrl != tp->link_config.active_flowctrl)
  1243. linkmesg = 1;
  1244. tp->link_config.active_speed = phydev->speed;
  1245. tp->link_config.active_duplex = phydev->duplex;
  1246. spin_unlock_bh(&tp->lock);
  1247. if (linkmesg)
  1248. tg3_link_report(tp);
  1249. }
  1250. static int tg3_phy_init(struct tg3 *tp)
  1251. {
  1252. struct phy_device *phydev;
  1253. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
  1254. return 0;
  1255. /* Bring the PHY back to a known state. */
  1256. tg3_bmcr_reset(tp);
  1257. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1258. /* Attach the MAC to the PHY. */
  1259. phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
  1260. phydev->dev_flags, phydev->interface);
  1261. if (IS_ERR(phydev)) {
  1262. dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
  1263. return PTR_ERR(phydev);
  1264. }
  1265. /* Mask with MAC supported features. */
  1266. switch (phydev->interface) {
  1267. case PHY_INTERFACE_MODE_GMII:
  1268. case PHY_INTERFACE_MODE_RGMII:
  1269. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  1270. phydev->supported &= (PHY_GBIT_FEATURES |
  1271. SUPPORTED_Pause |
  1272. SUPPORTED_Asym_Pause);
  1273. break;
  1274. }
  1275. /* fallthru */
  1276. case PHY_INTERFACE_MODE_MII:
  1277. phydev->supported &= (PHY_BASIC_FEATURES |
  1278. SUPPORTED_Pause |
  1279. SUPPORTED_Asym_Pause);
  1280. break;
  1281. default:
  1282. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1283. return -EINVAL;
  1284. }
  1285. tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
  1286. phydev->advertising = phydev->supported;
  1287. return 0;
  1288. }
  1289. static void tg3_phy_start(struct tg3 *tp)
  1290. {
  1291. struct phy_device *phydev;
  1292. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1293. return;
  1294. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1295. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  1296. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  1297. phydev->speed = tp->link_config.orig_speed;
  1298. phydev->duplex = tp->link_config.orig_duplex;
  1299. phydev->autoneg = tp->link_config.orig_autoneg;
  1300. phydev->advertising = tp->link_config.orig_advertising;
  1301. }
  1302. phy_start(phydev);
  1303. phy_start_aneg(phydev);
  1304. }
  1305. static void tg3_phy_stop(struct tg3 *tp)
  1306. {
  1307. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1308. return;
  1309. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1310. }
  1311. static void tg3_phy_fini(struct tg3 *tp)
  1312. {
  1313. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  1314. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1315. tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
  1316. }
  1317. }
  1318. static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1319. {
  1320. int err;
  1321. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1322. if (!err)
  1323. err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1324. return err;
  1325. }
  1326. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1327. {
  1328. u32 phytest;
  1329. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1330. u32 phy;
  1331. tg3_writephy(tp, MII_TG3_FET_TEST,
  1332. phytest | MII_TG3_FET_SHADOW_EN);
  1333. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1334. if (enable)
  1335. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1336. else
  1337. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1338. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1339. }
  1340. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1341. }
  1342. }
  1343. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1344. {
  1345. u32 reg;
  1346. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  1347. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  1348. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
  1349. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1350. return;
  1351. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1352. tg3_phy_fet_toggle_apd(tp, enable);
  1353. return;
  1354. }
  1355. reg = MII_TG3_MISC_SHDW_WREN |
  1356. MII_TG3_MISC_SHDW_SCR5_SEL |
  1357. MII_TG3_MISC_SHDW_SCR5_LPED |
  1358. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1359. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1360. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1361. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
  1362. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1363. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1364. reg = MII_TG3_MISC_SHDW_WREN |
  1365. MII_TG3_MISC_SHDW_APD_SEL |
  1366. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1367. if (enable)
  1368. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1369. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1370. }
  1371. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  1372. {
  1373. u32 phy;
  1374. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  1375. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  1376. return;
  1377. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1378. u32 ephy;
  1379. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1380. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1381. tg3_writephy(tp, MII_TG3_FET_TEST,
  1382. ephy | MII_TG3_FET_SHADOW_EN);
  1383. if (!tg3_readphy(tp, reg, &phy)) {
  1384. if (enable)
  1385. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1386. else
  1387. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1388. tg3_writephy(tp, reg, phy);
  1389. }
  1390. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1391. }
  1392. } else {
  1393. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  1394. MII_TG3_AUXCTL_SHDWSEL_MISC;
  1395. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  1396. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  1397. if (enable)
  1398. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1399. else
  1400. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1401. phy |= MII_TG3_AUXCTL_MISC_WREN;
  1402. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1403. }
  1404. }
  1405. }
  1406. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1407. {
  1408. u32 val;
  1409. if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
  1410. return;
  1411. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  1412. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  1413. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1414. (val | (1 << 15) | (1 << 4)));
  1415. }
  1416. static void tg3_phy_apply_otp(struct tg3 *tp)
  1417. {
  1418. u32 otp, phy;
  1419. if (!tp->phy_otp)
  1420. return;
  1421. otp = tp->phy_otp;
  1422. /* Enable SM_DSP clock and tx 6dB coding. */
  1423. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1424. MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
  1425. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1426. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1427. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1428. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1429. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1430. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1431. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1432. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1433. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1434. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1435. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1436. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1437. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1438. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1439. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1440. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1441. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1442. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1443. /* Turn off SM_DSP clock. */
  1444. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1445. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1446. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1447. }
  1448. static int tg3_wait_macro_done(struct tg3 *tp)
  1449. {
  1450. int limit = 100;
  1451. while (limit--) {
  1452. u32 tmp32;
  1453. if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
  1454. if ((tmp32 & 0x1000) == 0)
  1455. break;
  1456. }
  1457. }
  1458. if (limit < 0)
  1459. return -EBUSY;
  1460. return 0;
  1461. }
  1462. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1463. {
  1464. static const u32 test_pat[4][6] = {
  1465. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  1466. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  1467. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  1468. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  1469. };
  1470. int chan;
  1471. for (chan = 0; chan < 4; chan++) {
  1472. int i;
  1473. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1474. (chan * 0x2000) | 0x0200);
  1475. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  1476. for (i = 0; i < 6; i++)
  1477. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  1478. test_pat[chan][i]);
  1479. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  1480. if (tg3_wait_macro_done(tp)) {
  1481. *resetp = 1;
  1482. return -EBUSY;
  1483. }
  1484. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1485. (chan * 0x2000) | 0x0200);
  1486. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
  1487. if (tg3_wait_macro_done(tp)) {
  1488. *resetp = 1;
  1489. return -EBUSY;
  1490. }
  1491. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
  1492. if (tg3_wait_macro_done(tp)) {
  1493. *resetp = 1;
  1494. return -EBUSY;
  1495. }
  1496. for (i = 0; i < 6; i += 2) {
  1497. u32 low, high;
  1498. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  1499. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  1500. tg3_wait_macro_done(tp)) {
  1501. *resetp = 1;
  1502. return -EBUSY;
  1503. }
  1504. low &= 0x7fff;
  1505. high &= 0x000f;
  1506. if (low != test_pat[chan][i] ||
  1507. high != test_pat[chan][i+1]) {
  1508. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  1509. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  1510. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  1511. return -EBUSY;
  1512. }
  1513. }
  1514. }
  1515. return 0;
  1516. }
  1517. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  1518. {
  1519. int chan;
  1520. for (chan = 0; chan < 4; chan++) {
  1521. int i;
  1522. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1523. (chan * 0x2000) | 0x0200);
  1524. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  1525. for (i = 0; i < 6; i++)
  1526. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  1527. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  1528. if (tg3_wait_macro_done(tp))
  1529. return -EBUSY;
  1530. }
  1531. return 0;
  1532. }
  1533. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  1534. {
  1535. u32 reg32, phy9_orig;
  1536. int retries, do_phy_reset, err;
  1537. retries = 10;
  1538. do_phy_reset = 1;
  1539. do {
  1540. if (do_phy_reset) {
  1541. err = tg3_bmcr_reset(tp);
  1542. if (err)
  1543. return err;
  1544. do_phy_reset = 0;
  1545. }
  1546. /* Disable transmitter and interrupt. */
  1547. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  1548. continue;
  1549. reg32 |= 0x3000;
  1550. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1551. /* Set full-duplex, 1000 mbps. */
  1552. tg3_writephy(tp, MII_BMCR,
  1553. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  1554. /* Set to master mode. */
  1555. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  1556. continue;
  1557. tg3_writephy(tp, MII_TG3_CTRL,
  1558. (MII_TG3_CTRL_AS_MASTER |
  1559. MII_TG3_CTRL_ENABLE_AS_MASTER));
  1560. /* Enable SM_DSP_CLOCK and 6dB. */
  1561. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1562. /* Block the PHY control access. */
  1563. tg3_phydsp_write(tp, 0x8005, 0x0800);
  1564. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  1565. if (!err)
  1566. break;
  1567. } while (--retries);
  1568. err = tg3_phy_reset_chanpat(tp);
  1569. if (err)
  1570. return err;
  1571. tg3_phydsp_write(tp, 0x8005, 0x0000);
  1572. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  1573. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
  1574. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1575. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1576. /* Set Extended packet length bit for jumbo frames */
  1577. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  1578. } else {
  1579. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1580. }
  1581. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  1582. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  1583. reg32 &= ~0x3000;
  1584. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1585. } else if (!err)
  1586. err = -EBUSY;
  1587. return err;
  1588. }
  1589. /* This will reset the tigon3 PHY if there is no valid
  1590. * link unless the FORCE argument is non-zero.
  1591. */
  1592. static int tg3_phy_reset(struct tg3 *tp)
  1593. {
  1594. u32 cpmuctrl;
  1595. u32 phy_status;
  1596. int err;
  1597. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1598. u32 val;
  1599. val = tr32(GRC_MISC_CFG);
  1600. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  1601. udelay(40);
  1602. }
  1603. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  1604. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  1605. if (err != 0)
  1606. return -EBUSY;
  1607. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  1608. netif_carrier_off(tp->dev);
  1609. tg3_link_report(tp);
  1610. }
  1611. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1612. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1613. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  1614. err = tg3_phy_reset_5703_4_5(tp);
  1615. if (err)
  1616. return err;
  1617. goto out;
  1618. }
  1619. cpmuctrl = 0;
  1620. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  1621. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  1622. cpmuctrl = tr32(TG3_CPMU_CTRL);
  1623. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  1624. tw32(TG3_CPMU_CTRL,
  1625. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  1626. }
  1627. err = tg3_bmcr_reset(tp);
  1628. if (err)
  1629. return err;
  1630. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  1631. u32 phy;
  1632. phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  1633. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
  1634. tw32(TG3_CPMU_CTRL, cpmuctrl);
  1635. }
  1636. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  1637. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  1638. u32 val;
  1639. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1640. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  1641. CPMU_LSPD_1000MB_MACCLK_12_5) {
  1642. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1643. udelay(40);
  1644. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1645. }
  1646. }
  1647. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  1648. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
  1649. (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  1650. return 0;
  1651. tg3_phy_apply_otp(tp);
  1652. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  1653. tg3_phy_toggle_apd(tp, true);
  1654. else
  1655. tg3_phy_toggle_apd(tp, false);
  1656. out:
  1657. if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
  1658. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1659. tg3_phydsp_write(tp, 0x201f, 0x2aaa);
  1660. tg3_phydsp_write(tp, 0x000a, 0x0323);
  1661. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1662. }
  1663. if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
  1664. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  1665. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  1666. }
  1667. if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
  1668. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1669. tg3_phydsp_write(tp, 0x000a, 0x310b);
  1670. tg3_phydsp_write(tp, 0x201f, 0x9506);
  1671. tg3_phydsp_write(tp, 0x401f, 0x14e2);
  1672. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1673. } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
  1674. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1675. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1676. if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
  1677. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  1678. tg3_writephy(tp, MII_TG3_TEST1,
  1679. MII_TG3_TEST1_TRIM_EN | 0x4);
  1680. } else
  1681. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  1682. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1683. }
  1684. /* Set Extended packet length bit (bit 14) on all chips that */
  1685. /* support jumbo frames */
  1686. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  1687. /* Cannot do read-modify-write on 5401 */
  1688. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1689. } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  1690. u32 phy_reg;
  1691. /* Set bit 14 with read-modify-write to preserve other bits */
  1692. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  1693. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  1694. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  1695. }
  1696. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  1697. * jumbo frames transmission.
  1698. */
  1699. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  1700. u32 phy_reg;
  1701. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  1702. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1703. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  1704. }
  1705. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1706. /* adjust output voltage */
  1707. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  1708. }
  1709. tg3_phy_toggle_automdix(tp, 1);
  1710. tg3_phy_set_wirespeed(tp);
  1711. return 0;
  1712. }
  1713. static void tg3_frob_aux_power(struct tg3 *tp)
  1714. {
  1715. struct tg3 *tp_peer = tp;
  1716. /* The GPIOs do something completely different on 57765. */
  1717. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
  1718. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  1719. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  1720. return;
  1721. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1722. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
  1723. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  1724. struct net_device *dev_peer;
  1725. dev_peer = pci_get_drvdata(tp->pdev_peer);
  1726. /* remove_one() may have been run on the peer. */
  1727. if (!dev_peer)
  1728. tp_peer = tp;
  1729. else
  1730. tp_peer = netdev_priv(dev_peer);
  1731. }
  1732. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1733. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  1734. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1735. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  1736. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1737. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1738. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1739. (GRC_LCLCTRL_GPIO_OE0 |
  1740. GRC_LCLCTRL_GPIO_OE1 |
  1741. GRC_LCLCTRL_GPIO_OE2 |
  1742. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1743. GRC_LCLCTRL_GPIO_OUTPUT1),
  1744. 100);
  1745. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  1746. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  1747. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  1748. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  1749. GRC_LCLCTRL_GPIO_OE1 |
  1750. GRC_LCLCTRL_GPIO_OE2 |
  1751. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1752. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1753. tp->grc_local_ctrl;
  1754. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1755. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  1756. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1757. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  1758. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1759. } else {
  1760. u32 no_gpio2;
  1761. u32 grc_local_ctrl = 0;
  1762. if (tp_peer != tp &&
  1763. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1764. return;
  1765. /* Workaround to prevent overdrawing Amps. */
  1766. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1767. ASIC_REV_5714) {
  1768. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  1769. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1770. grc_local_ctrl, 100);
  1771. }
  1772. /* On 5753 and variants, GPIO2 cannot be used. */
  1773. no_gpio2 = tp->nic_sram_data_cfg &
  1774. NIC_SRAM_DATA_CFG_NO_GPIO2;
  1775. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  1776. GRC_LCLCTRL_GPIO_OE1 |
  1777. GRC_LCLCTRL_GPIO_OE2 |
  1778. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1779. GRC_LCLCTRL_GPIO_OUTPUT2;
  1780. if (no_gpio2) {
  1781. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  1782. GRC_LCLCTRL_GPIO_OUTPUT2);
  1783. }
  1784. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1785. grc_local_ctrl, 100);
  1786. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  1787. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1788. grc_local_ctrl, 100);
  1789. if (!no_gpio2) {
  1790. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  1791. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1792. grc_local_ctrl, 100);
  1793. }
  1794. }
  1795. } else {
  1796. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1797. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1798. if (tp_peer != tp &&
  1799. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1800. return;
  1801. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1802. (GRC_LCLCTRL_GPIO_OE1 |
  1803. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1804. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1805. GRC_LCLCTRL_GPIO_OE1, 100);
  1806. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1807. (GRC_LCLCTRL_GPIO_OE1 |
  1808. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1809. }
  1810. }
  1811. }
  1812. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1813. {
  1814. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1815. return 1;
  1816. else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
  1817. if (speed != SPEED_10)
  1818. return 1;
  1819. } else if (speed == SPEED_10)
  1820. return 1;
  1821. return 0;
  1822. }
  1823. static int tg3_setup_phy(struct tg3 *, int);
  1824. #define RESET_KIND_SHUTDOWN 0
  1825. #define RESET_KIND_INIT 1
  1826. #define RESET_KIND_SUSPEND 2
  1827. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1828. static int tg3_halt_cpu(struct tg3 *, u32);
  1829. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  1830. {
  1831. u32 val;
  1832. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  1833. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1834. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1835. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1836. sg_dig_ctrl |=
  1837. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1838. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1839. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1840. }
  1841. return;
  1842. }
  1843. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1844. tg3_bmcr_reset(tp);
  1845. val = tr32(GRC_MISC_CFG);
  1846. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1847. udelay(40);
  1848. return;
  1849. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1850. u32 phytest;
  1851. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1852. u32 phy;
  1853. tg3_writephy(tp, MII_ADVERTISE, 0);
  1854. tg3_writephy(tp, MII_BMCR,
  1855. BMCR_ANENABLE | BMCR_ANRESTART);
  1856. tg3_writephy(tp, MII_TG3_FET_TEST,
  1857. phytest | MII_TG3_FET_SHADOW_EN);
  1858. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  1859. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  1860. tg3_writephy(tp,
  1861. MII_TG3_FET_SHDW_AUXMODE4,
  1862. phy);
  1863. }
  1864. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1865. }
  1866. return;
  1867. } else if (do_low_power) {
  1868. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1869. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1870. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1871. MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
  1872. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  1873. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  1874. MII_TG3_AUXCTL_PCTL_VREG_11V);
  1875. }
  1876. /* The PHY should not be powered down on some chips because
  1877. * of bugs.
  1878. */
  1879. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1880. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1881. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1882. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1883. return;
  1884. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  1885. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  1886. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1887. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1888. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  1889. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1890. }
  1891. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1892. }
  1893. /* tp->lock is held. */
  1894. static int tg3_nvram_lock(struct tg3 *tp)
  1895. {
  1896. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  1897. int i;
  1898. if (tp->nvram_lock_cnt == 0) {
  1899. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  1900. for (i = 0; i < 8000; i++) {
  1901. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  1902. break;
  1903. udelay(20);
  1904. }
  1905. if (i == 8000) {
  1906. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  1907. return -ENODEV;
  1908. }
  1909. }
  1910. tp->nvram_lock_cnt++;
  1911. }
  1912. return 0;
  1913. }
  1914. /* tp->lock is held. */
  1915. static void tg3_nvram_unlock(struct tg3 *tp)
  1916. {
  1917. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  1918. if (tp->nvram_lock_cnt > 0)
  1919. tp->nvram_lock_cnt--;
  1920. if (tp->nvram_lock_cnt == 0)
  1921. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  1922. }
  1923. }
  1924. /* tp->lock is held. */
  1925. static void tg3_enable_nvram_access(struct tg3 *tp)
  1926. {
  1927. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1928. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
  1929. u32 nvaccess = tr32(NVRAM_ACCESS);
  1930. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  1931. }
  1932. }
  1933. /* tp->lock is held. */
  1934. static void tg3_disable_nvram_access(struct tg3 *tp)
  1935. {
  1936. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1937. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
  1938. u32 nvaccess = tr32(NVRAM_ACCESS);
  1939. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  1940. }
  1941. }
  1942. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  1943. u32 offset, u32 *val)
  1944. {
  1945. u32 tmp;
  1946. int i;
  1947. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  1948. return -EINVAL;
  1949. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  1950. EEPROM_ADDR_DEVID_MASK |
  1951. EEPROM_ADDR_READ);
  1952. tw32(GRC_EEPROM_ADDR,
  1953. tmp |
  1954. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  1955. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  1956. EEPROM_ADDR_ADDR_MASK) |
  1957. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  1958. for (i = 0; i < 1000; i++) {
  1959. tmp = tr32(GRC_EEPROM_ADDR);
  1960. if (tmp & EEPROM_ADDR_COMPLETE)
  1961. break;
  1962. msleep(1);
  1963. }
  1964. if (!(tmp & EEPROM_ADDR_COMPLETE))
  1965. return -EBUSY;
  1966. tmp = tr32(GRC_EEPROM_DATA);
  1967. /*
  1968. * The data will always be opposite the native endian
  1969. * format. Perform a blind byteswap to compensate.
  1970. */
  1971. *val = swab32(tmp);
  1972. return 0;
  1973. }
  1974. #define NVRAM_CMD_TIMEOUT 10000
  1975. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  1976. {
  1977. int i;
  1978. tw32(NVRAM_CMD, nvram_cmd);
  1979. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  1980. udelay(10);
  1981. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  1982. udelay(10);
  1983. break;
  1984. }
  1985. }
  1986. if (i == NVRAM_CMD_TIMEOUT)
  1987. return -EBUSY;
  1988. return 0;
  1989. }
  1990. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  1991. {
  1992. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  1993. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  1994. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  1995. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  1996. (tp->nvram_jedecnum == JEDEC_ATMEL))
  1997. addr = ((addr / tp->nvram_pagesize) <<
  1998. ATMEL_AT45DB0X1B_PAGE_POS) +
  1999. (addr % tp->nvram_pagesize);
  2000. return addr;
  2001. }
  2002. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  2003. {
  2004. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  2005. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  2006. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  2007. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  2008. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2009. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  2010. tp->nvram_pagesize) +
  2011. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  2012. return addr;
  2013. }
  2014. /* NOTE: Data read in from NVRAM is byteswapped according to
  2015. * the byteswapping settings for all other register accesses.
  2016. * tg3 devices are BE devices, so on a BE machine, the data
  2017. * returned will be exactly as it is seen in NVRAM. On a LE
  2018. * machine, the 32-bit value will be byteswapped.
  2019. */
  2020. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  2021. {
  2022. int ret;
  2023. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  2024. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2025. offset = tg3_nvram_phys_addr(tp, offset);
  2026. if (offset > NVRAM_ADDR_MSK)
  2027. return -EINVAL;
  2028. ret = tg3_nvram_lock(tp);
  2029. if (ret)
  2030. return ret;
  2031. tg3_enable_nvram_access(tp);
  2032. tw32(NVRAM_ADDR, offset);
  2033. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2034. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2035. if (ret == 0)
  2036. *val = tr32(NVRAM_RDDATA);
  2037. tg3_disable_nvram_access(tp);
  2038. tg3_nvram_unlock(tp);
  2039. return ret;
  2040. }
  2041. /* Ensures NVRAM data is in bytestream format. */
  2042. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2043. {
  2044. u32 v;
  2045. int res = tg3_nvram_read(tp, offset, &v);
  2046. if (!res)
  2047. *val = cpu_to_be32(v);
  2048. return res;
  2049. }
  2050. /* tp->lock is held. */
  2051. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  2052. {
  2053. u32 addr_high, addr_low;
  2054. int i;
  2055. addr_high = ((tp->dev->dev_addr[0] << 8) |
  2056. tp->dev->dev_addr[1]);
  2057. addr_low = ((tp->dev->dev_addr[2] << 24) |
  2058. (tp->dev->dev_addr[3] << 16) |
  2059. (tp->dev->dev_addr[4] << 8) |
  2060. (tp->dev->dev_addr[5] << 0));
  2061. for (i = 0; i < 4; i++) {
  2062. if (i == 1 && skip_mac_1)
  2063. continue;
  2064. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  2065. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  2066. }
  2067. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2068. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  2069. for (i = 0; i < 12; i++) {
  2070. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  2071. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  2072. }
  2073. }
  2074. addr_high = (tp->dev->dev_addr[0] +
  2075. tp->dev->dev_addr[1] +
  2076. tp->dev->dev_addr[2] +
  2077. tp->dev->dev_addr[3] +
  2078. tp->dev->dev_addr[4] +
  2079. tp->dev->dev_addr[5]) &
  2080. TX_BACKOFF_SEED_MASK;
  2081. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  2082. }
  2083. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  2084. {
  2085. u32 misc_host_ctrl;
  2086. bool device_should_wake, do_low_power;
  2087. /* Make sure register accesses (indirect or otherwise)
  2088. * will function correctly.
  2089. */
  2090. pci_write_config_dword(tp->pdev,
  2091. TG3PCI_MISC_HOST_CTRL,
  2092. tp->misc_host_ctrl);
  2093. switch (state) {
  2094. case PCI_D0:
  2095. pci_enable_wake(tp->pdev, state, false);
  2096. pci_set_power_state(tp->pdev, PCI_D0);
  2097. /* Switch out of Vaux if it is a NIC */
  2098. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  2099. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  2100. return 0;
  2101. case PCI_D1:
  2102. case PCI_D2:
  2103. case PCI_D3hot:
  2104. break;
  2105. default:
  2106. netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
  2107. state);
  2108. return -EINVAL;
  2109. }
  2110. /* Restore the CLKREQ setting. */
  2111. if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
  2112. u16 lnkctl;
  2113. pci_read_config_word(tp->pdev,
  2114. tp->pcie_cap + PCI_EXP_LNKCTL,
  2115. &lnkctl);
  2116. lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
  2117. pci_write_config_word(tp->pdev,
  2118. tp->pcie_cap + PCI_EXP_LNKCTL,
  2119. lnkctl);
  2120. }
  2121. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  2122. tw32(TG3PCI_MISC_HOST_CTRL,
  2123. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  2124. device_should_wake = pci_pme_capable(tp->pdev, state) &&
  2125. device_may_wakeup(&tp->pdev->dev) &&
  2126. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
  2127. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  2128. do_low_power = false;
  2129. if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
  2130. !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  2131. struct phy_device *phydev;
  2132. u32 phyid, advertising;
  2133. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  2134. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  2135. tp->link_config.orig_speed = phydev->speed;
  2136. tp->link_config.orig_duplex = phydev->duplex;
  2137. tp->link_config.orig_autoneg = phydev->autoneg;
  2138. tp->link_config.orig_advertising = phydev->advertising;
  2139. advertising = ADVERTISED_TP |
  2140. ADVERTISED_Pause |
  2141. ADVERTISED_Autoneg |
  2142. ADVERTISED_10baseT_Half;
  2143. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  2144. device_should_wake) {
  2145. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  2146. advertising |=
  2147. ADVERTISED_100baseT_Half |
  2148. ADVERTISED_100baseT_Full |
  2149. ADVERTISED_10baseT_Full;
  2150. else
  2151. advertising |= ADVERTISED_10baseT_Full;
  2152. }
  2153. phydev->advertising = advertising;
  2154. phy_start_aneg(phydev);
  2155. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  2156. if (phyid != PHY_ID_BCMAC131) {
  2157. phyid &= PHY_BCM_OUI_MASK;
  2158. if (phyid == PHY_BCM_OUI_1 ||
  2159. phyid == PHY_BCM_OUI_2 ||
  2160. phyid == PHY_BCM_OUI_3)
  2161. do_low_power = true;
  2162. }
  2163. }
  2164. } else {
  2165. do_low_power = true;
  2166. if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  2167. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  2168. tp->link_config.orig_speed = tp->link_config.speed;
  2169. tp->link_config.orig_duplex = tp->link_config.duplex;
  2170. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  2171. }
  2172. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  2173. tp->link_config.speed = SPEED_10;
  2174. tp->link_config.duplex = DUPLEX_HALF;
  2175. tp->link_config.autoneg = AUTONEG_ENABLE;
  2176. tg3_setup_phy(tp, 0);
  2177. }
  2178. }
  2179. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2180. u32 val;
  2181. val = tr32(GRC_VCPU_EXT_CTRL);
  2182. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  2183. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  2184. int i;
  2185. u32 val;
  2186. for (i = 0; i < 200; i++) {
  2187. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  2188. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  2189. break;
  2190. msleep(1);
  2191. }
  2192. }
  2193. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  2194. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  2195. WOL_DRV_STATE_SHUTDOWN |
  2196. WOL_DRV_WOL |
  2197. WOL_SET_MAGIC_PKT);
  2198. if (device_should_wake) {
  2199. u32 mac_mode;
  2200. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  2201. if (do_low_power) {
  2202. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  2203. udelay(40);
  2204. }
  2205. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  2206. mac_mode = MAC_MODE_PORT_MODE_GMII;
  2207. else
  2208. mac_mode = MAC_MODE_PORT_MODE_MII;
  2209. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  2210. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2211. ASIC_REV_5700) {
  2212. u32 speed = (tp->tg3_flags &
  2213. TG3_FLAG_WOL_SPEED_100MB) ?
  2214. SPEED_100 : SPEED_10;
  2215. if (tg3_5700_link_polarity(tp, speed))
  2216. mac_mode |= MAC_MODE_LINK_POLARITY;
  2217. else
  2218. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2219. }
  2220. } else {
  2221. mac_mode = MAC_MODE_PORT_MODE_TBI;
  2222. }
  2223. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  2224. tw32(MAC_LED_CTRL, tp->led_ctrl);
  2225. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  2226. if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  2227. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
  2228. ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  2229. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
  2230. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  2231. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  2232. mac_mode |= tp->mac_mode &
  2233. (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  2234. if (mac_mode & MAC_MODE_APE_TX_EN)
  2235. mac_mode |= MAC_MODE_TDE_ENABLE;
  2236. }
  2237. tw32_f(MAC_MODE, mac_mode);
  2238. udelay(100);
  2239. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  2240. udelay(10);
  2241. }
  2242. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  2243. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2244. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  2245. u32 base_val;
  2246. base_val = tp->pci_clock_ctrl;
  2247. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  2248. CLOCK_CTRL_TXCLK_DISABLE);
  2249. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  2250. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  2251. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  2252. (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  2253. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  2254. /* do nothing */
  2255. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  2256. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  2257. u32 newbits1, newbits2;
  2258. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2259. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2260. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  2261. CLOCK_CTRL_TXCLK_DISABLE |
  2262. CLOCK_CTRL_ALTCLK);
  2263. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2264. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  2265. newbits1 = CLOCK_CTRL_625_CORE;
  2266. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  2267. } else {
  2268. newbits1 = CLOCK_CTRL_ALTCLK;
  2269. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2270. }
  2271. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  2272. 40);
  2273. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  2274. 40);
  2275. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2276. u32 newbits3;
  2277. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2278. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2279. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  2280. CLOCK_CTRL_TXCLK_DISABLE |
  2281. CLOCK_CTRL_44MHZ_CORE);
  2282. } else {
  2283. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  2284. }
  2285. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  2286. tp->pci_clock_ctrl | newbits3, 40);
  2287. }
  2288. }
  2289. if (!(device_should_wake) &&
  2290. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  2291. tg3_power_down_phy(tp, do_low_power);
  2292. tg3_frob_aux_power(tp);
  2293. /* Workaround for unstable PLL clock */
  2294. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  2295. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  2296. u32 val = tr32(0x7d00);
  2297. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  2298. tw32(0x7d00, val);
  2299. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  2300. int err;
  2301. err = tg3_nvram_lock(tp);
  2302. tg3_halt_cpu(tp, RX_CPU_BASE);
  2303. if (!err)
  2304. tg3_nvram_unlock(tp);
  2305. }
  2306. }
  2307. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  2308. if (device_should_wake)
  2309. pci_enable_wake(tp->pdev, state, true);
  2310. /* Finally, set the new power state. */
  2311. pci_set_power_state(tp->pdev, state);
  2312. return 0;
  2313. }
  2314. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  2315. {
  2316. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  2317. case MII_TG3_AUX_STAT_10HALF:
  2318. *speed = SPEED_10;
  2319. *duplex = DUPLEX_HALF;
  2320. break;
  2321. case MII_TG3_AUX_STAT_10FULL:
  2322. *speed = SPEED_10;
  2323. *duplex = DUPLEX_FULL;
  2324. break;
  2325. case MII_TG3_AUX_STAT_100HALF:
  2326. *speed = SPEED_100;
  2327. *duplex = DUPLEX_HALF;
  2328. break;
  2329. case MII_TG3_AUX_STAT_100FULL:
  2330. *speed = SPEED_100;
  2331. *duplex = DUPLEX_FULL;
  2332. break;
  2333. case MII_TG3_AUX_STAT_1000HALF:
  2334. *speed = SPEED_1000;
  2335. *duplex = DUPLEX_HALF;
  2336. break;
  2337. case MII_TG3_AUX_STAT_1000FULL:
  2338. *speed = SPEED_1000;
  2339. *duplex = DUPLEX_FULL;
  2340. break;
  2341. default:
  2342. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2343. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  2344. SPEED_10;
  2345. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  2346. DUPLEX_HALF;
  2347. break;
  2348. }
  2349. *speed = SPEED_INVALID;
  2350. *duplex = DUPLEX_INVALID;
  2351. break;
  2352. }
  2353. }
  2354. static void tg3_phy_copper_begin(struct tg3 *tp)
  2355. {
  2356. u32 new_adv;
  2357. int i;
  2358. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  2359. /* Entering low power mode. Disable gigabit and
  2360. * 100baseT advertisements.
  2361. */
  2362. tg3_writephy(tp, MII_TG3_CTRL, 0);
  2363. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  2364. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  2365. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  2366. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  2367. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2368. } else if (tp->link_config.speed == SPEED_INVALID) {
  2369. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  2370. tp->link_config.advertising &=
  2371. ~(ADVERTISED_1000baseT_Half |
  2372. ADVERTISED_1000baseT_Full);
  2373. new_adv = ADVERTISE_CSMA;
  2374. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  2375. new_adv |= ADVERTISE_10HALF;
  2376. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  2377. new_adv |= ADVERTISE_10FULL;
  2378. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  2379. new_adv |= ADVERTISE_100HALF;
  2380. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  2381. new_adv |= ADVERTISE_100FULL;
  2382. new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2383. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2384. if (tp->link_config.advertising &
  2385. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  2386. new_adv = 0;
  2387. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2388. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  2389. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2390. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  2391. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
  2392. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2393. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  2394. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  2395. MII_TG3_CTRL_ENABLE_AS_MASTER);
  2396. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  2397. } else {
  2398. tg3_writephy(tp, MII_TG3_CTRL, 0);
  2399. }
  2400. } else {
  2401. new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2402. new_adv |= ADVERTISE_CSMA;
  2403. /* Asking for a specific link mode. */
  2404. if (tp->link_config.speed == SPEED_1000) {
  2405. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2406. if (tp->link_config.duplex == DUPLEX_FULL)
  2407. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  2408. else
  2409. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  2410. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2411. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  2412. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  2413. MII_TG3_CTRL_ENABLE_AS_MASTER);
  2414. } else {
  2415. if (tp->link_config.speed == SPEED_100) {
  2416. if (tp->link_config.duplex == DUPLEX_FULL)
  2417. new_adv |= ADVERTISE_100FULL;
  2418. else
  2419. new_adv |= ADVERTISE_100HALF;
  2420. } else {
  2421. if (tp->link_config.duplex == DUPLEX_FULL)
  2422. new_adv |= ADVERTISE_10FULL;
  2423. else
  2424. new_adv |= ADVERTISE_10HALF;
  2425. }
  2426. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2427. new_adv = 0;
  2428. }
  2429. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  2430. }
  2431. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  2432. tp->link_config.speed != SPEED_INVALID) {
  2433. u32 bmcr, orig_bmcr;
  2434. tp->link_config.active_speed = tp->link_config.speed;
  2435. tp->link_config.active_duplex = tp->link_config.duplex;
  2436. bmcr = 0;
  2437. switch (tp->link_config.speed) {
  2438. default:
  2439. case SPEED_10:
  2440. break;
  2441. case SPEED_100:
  2442. bmcr |= BMCR_SPEED100;
  2443. break;
  2444. case SPEED_1000:
  2445. bmcr |= TG3_BMCR_SPEED1000;
  2446. break;
  2447. }
  2448. if (tp->link_config.duplex == DUPLEX_FULL)
  2449. bmcr |= BMCR_FULLDPLX;
  2450. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  2451. (bmcr != orig_bmcr)) {
  2452. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  2453. for (i = 0; i < 1500; i++) {
  2454. u32 tmp;
  2455. udelay(10);
  2456. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  2457. tg3_readphy(tp, MII_BMSR, &tmp))
  2458. continue;
  2459. if (!(tmp & BMSR_LSTATUS)) {
  2460. udelay(40);
  2461. break;
  2462. }
  2463. }
  2464. tg3_writephy(tp, MII_BMCR, bmcr);
  2465. udelay(40);
  2466. }
  2467. } else {
  2468. tg3_writephy(tp, MII_BMCR,
  2469. BMCR_ANENABLE | BMCR_ANRESTART);
  2470. }
  2471. }
  2472. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  2473. {
  2474. int err;
  2475. /* Turn off tap power management. */
  2476. /* Set Extended packet length bit */
  2477. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  2478. err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
  2479. err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
  2480. err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
  2481. err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
  2482. err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
  2483. udelay(40);
  2484. return err;
  2485. }
  2486. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  2487. {
  2488. u32 adv_reg, all_mask = 0;
  2489. if (mask & ADVERTISED_10baseT_Half)
  2490. all_mask |= ADVERTISE_10HALF;
  2491. if (mask & ADVERTISED_10baseT_Full)
  2492. all_mask |= ADVERTISE_10FULL;
  2493. if (mask & ADVERTISED_100baseT_Half)
  2494. all_mask |= ADVERTISE_100HALF;
  2495. if (mask & ADVERTISED_100baseT_Full)
  2496. all_mask |= ADVERTISE_100FULL;
  2497. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  2498. return 0;
  2499. if ((adv_reg & all_mask) != all_mask)
  2500. return 0;
  2501. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  2502. u32 tg3_ctrl;
  2503. all_mask = 0;
  2504. if (mask & ADVERTISED_1000baseT_Half)
  2505. all_mask |= ADVERTISE_1000HALF;
  2506. if (mask & ADVERTISED_1000baseT_Full)
  2507. all_mask |= ADVERTISE_1000FULL;
  2508. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  2509. return 0;
  2510. if ((tg3_ctrl & all_mask) != all_mask)
  2511. return 0;
  2512. }
  2513. return 1;
  2514. }
  2515. static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
  2516. {
  2517. u32 curadv, reqadv;
  2518. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  2519. return 1;
  2520. curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2521. reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2522. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  2523. if (curadv != reqadv)
  2524. return 0;
  2525. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
  2526. tg3_readphy(tp, MII_LPA, rmtadv);
  2527. } else {
  2528. /* Reprogram the advertisement register, even if it
  2529. * does not affect the current link. If the link
  2530. * gets renegotiated in the future, we can save an
  2531. * additional renegotiation cycle by advertising
  2532. * it correctly in the first place.
  2533. */
  2534. if (curadv != reqadv) {
  2535. *lcladv &= ~(ADVERTISE_PAUSE_CAP |
  2536. ADVERTISE_PAUSE_ASYM);
  2537. tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
  2538. }
  2539. }
  2540. return 1;
  2541. }
  2542. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  2543. {
  2544. int current_link_up;
  2545. u32 bmsr, dummy;
  2546. u32 lcl_adv, rmt_adv;
  2547. u16 current_speed;
  2548. u8 current_duplex;
  2549. int i, err;
  2550. tw32(MAC_EVENT, 0);
  2551. tw32_f(MAC_STATUS,
  2552. (MAC_STATUS_SYNC_CHANGED |
  2553. MAC_STATUS_CFG_CHANGED |
  2554. MAC_STATUS_MI_COMPLETION |
  2555. MAC_STATUS_LNKSTATE_CHANGED));
  2556. udelay(40);
  2557. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  2558. tw32_f(MAC_MI_MODE,
  2559. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  2560. udelay(80);
  2561. }
  2562. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  2563. /* Some third-party PHYs need to be reset on link going
  2564. * down.
  2565. */
  2566. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2567. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  2568. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  2569. netif_carrier_ok(tp->dev)) {
  2570. tg3_readphy(tp, MII_BMSR, &bmsr);
  2571. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2572. !(bmsr & BMSR_LSTATUS))
  2573. force_reset = 1;
  2574. }
  2575. if (force_reset)
  2576. tg3_phy_reset(tp);
  2577. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  2578. tg3_readphy(tp, MII_BMSR, &bmsr);
  2579. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  2580. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  2581. bmsr = 0;
  2582. if (!(bmsr & BMSR_LSTATUS)) {
  2583. err = tg3_init_5401phy_dsp(tp);
  2584. if (err)
  2585. return err;
  2586. tg3_readphy(tp, MII_BMSR, &bmsr);
  2587. for (i = 0; i < 1000; i++) {
  2588. udelay(10);
  2589. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2590. (bmsr & BMSR_LSTATUS)) {
  2591. udelay(40);
  2592. break;
  2593. }
  2594. }
  2595. if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
  2596. TG3_PHY_REV_BCM5401_B0 &&
  2597. !(bmsr & BMSR_LSTATUS) &&
  2598. tp->link_config.active_speed == SPEED_1000) {
  2599. err = tg3_phy_reset(tp);
  2600. if (!err)
  2601. err = tg3_init_5401phy_dsp(tp);
  2602. if (err)
  2603. return err;
  2604. }
  2605. }
  2606. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2607. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  2608. /* 5701 {A0,B0} CRC bug workaround */
  2609. tg3_writephy(tp, 0x15, 0x0a75);
  2610. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  2611. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2612. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  2613. }
  2614. /* Clear pending interrupts... */
  2615. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2616. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2617. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
  2618. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  2619. else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
  2620. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  2621. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2622. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2623. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  2624. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2625. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  2626. else
  2627. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  2628. }
  2629. current_link_up = 0;
  2630. current_speed = SPEED_INVALID;
  2631. current_duplex = DUPLEX_INVALID;
  2632. if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
  2633. u32 val;
  2634. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  2635. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  2636. if (!(val & (1 << 10))) {
  2637. val |= (1 << 10);
  2638. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  2639. goto relink;
  2640. }
  2641. }
  2642. bmsr = 0;
  2643. for (i = 0; i < 100; i++) {
  2644. tg3_readphy(tp, MII_BMSR, &bmsr);
  2645. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2646. (bmsr & BMSR_LSTATUS))
  2647. break;
  2648. udelay(40);
  2649. }
  2650. if (bmsr & BMSR_LSTATUS) {
  2651. u32 aux_stat, bmcr;
  2652. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  2653. for (i = 0; i < 2000; i++) {
  2654. udelay(10);
  2655. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  2656. aux_stat)
  2657. break;
  2658. }
  2659. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  2660. &current_speed,
  2661. &current_duplex);
  2662. bmcr = 0;
  2663. for (i = 0; i < 200; i++) {
  2664. tg3_readphy(tp, MII_BMCR, &bmcr);
  2665. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  2666. continue;
  2667. if (bmcr && bmcr != 0x7fff)
  2668. break;
  2669. udelay(10);
  2670. }
  2671. lcl_adv = 0;
  2672. rmt_adv = 0;
  2673. tp->link_config.active_speed = current_speed;
  2674. tp->link_config.active_duplex = current_duplex;
  2675. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2676. if ((bmcr & BMCR_ANENABLE) &&
  2677. tg3_copper_is_advertising_all(tp,
  2678. tp->link_config.advertising)) {
  2679. if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
  2680. &rmt_adv))
  2681. current_link_up = 1;
  2682. }
  2683. } else {
  2684. if (!(bmcr & BMCR_ANENABLE) &&
  2685. tp->link_config.speed == current_speed &&
  2686. tp->link_config.duplex == current_duplex &&
  2687. tp->link_config.flowctrl ==
  2688. tp->link_config.active_flowctrl) {
  2689. current_link_up = 1;
  2690. }
  2691. }
  2692. if (current_link_up == 1 &&
  2693. tp->link_config.active_duplex == DUPLEX_FULL)
  2694. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  2695. }
  2696. relink:
  2697. if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  2698. u32 tmp;
  2699. tg3_phy_copper_begin(tp);
  2700. tg3_readphy(tp, MII_BMSR, &tmp);
  2701. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  2702. (tmp & BMSR_LSTATUS))
  2703. current_link_up = 1;
  2704. }
  2705. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  2706. if (current_link_up == 1) {
  2707. if (tp->link_config.active_speed == SPEED_100 ||
  2708. tp->link_config.active_speed == SPEED_10)
  2709. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2710. else
  2711. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2712. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  2713. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2714. else
  2715. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2716. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2717. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2718. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2719. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  2720. if (current_link_up == 1 &&
  2721. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  2722. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  2723. else
  2724. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2725. }
  2726. /* ??? Without this setting Netgear GA302T PHY does not
  2727. * ??? send/receive packets...
  2728. */
  2729. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
  2730. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  2731. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  2732. tw32_f(MAC_MI_MODE, tp->mi_mode);
  2733. udelay(80);
  2734. }
  2735. tw32_f(MAC_MODE, tp->mac_mode);
  2736. udelay(40);
  2737. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  2738. /* Polled via timer. */
  2739. tw32_f(MAC_EVENT, 0);
  2740. } else {
  2741. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2742. }
  2743. udelay(40);
  2744. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  2745. current_link_up == 1 &&
  2746. tp->link_config.active_speed == SPEED_1000 &&
  2747. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  2748. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  2749. udelay(120);
  2750. tw32_f(MAC_STATUS,
  2751. (MAC_STATUS_SYNC_CHANGED |
  2752. MAC_STATUS_CFG_CHANGED));
  2753. udelay(40);
  2754. tg3_write_mem(tp,
  2755. NIC_SRAM_FIRMWARE_MBOX,
  2756. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  2757. }
  2758. /* Prevent send BD corruption. */
  2759. if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
  2760. u16 oldlnkctl, newlnkctl;
  2761. pci_read_config_word(tp->pdev,
  2762. tp->pcie_cap + PCI_EXP_LNKCTL,
  2763. &oldlnkctl);
  2764. if (tp->link_config.active_speed == SPEED_100 ||
  2765. tp->link_config.active_speed == SPEED_10)
  2766. newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
  2767. else
  2768. newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
  2769. if (newlnkctl != oldlnkctl)
  2770. pci_write_config_word(tp->pdev,
  2771. tp->pcie_cap + PCI_EXP_LNKCTL,
  2772. newlnkctl);
  2773. }
  2774. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2775. if (current_link_up)
  2776. netif_carrier_on(tp->dev);
  2777. else
  2778. netif_carrier_off(tp->dev);
  2779. tg3_link_report(tp);
  2780. }
  2781. return 0;
  2782. }
  2783. struct tg3_fiber_aneginfo {
  2784. int state;
  2785. #define ANEG_STATE_UNKNOWN 0
  2786. #define ANEG_STATE_AN_ENABLE 1
  2787. #define ANEG_STATE_RESTART_INIT 2
  2788. #define ANEG_STATE_RESTART 3
  2789. #define ANEG_STATE_DISABLE_LINK_OK 4
  2790. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  2791. #define ANEG_STATE_ABILITY_DETECT 6
  2792. #define ANEG_STATE_ACK_DETECT_INIT 7
  2793. #define ANEG_STATE_ACK_DETECT 8
  2794. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  2795. #define ANEG_STATE_COMPLETE_ACK 10
  2796. #define ANEG_STATE_IDLE_DETECT_INIT 11
  2797. #define ANEG_STATE_IDLE_DETECT 12
  2798. #define ANEG_STATE_LINK_OK 13
  2799. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  2800. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  2801. u32 flags;
  2802. #define MR_AN_ENABLE 0x00000001
  2803. #define MR_RESTART_AN 0x00000002
  2804. #define MR_AN_COMPLETE 0x00000004
  2805. #define MR_PAGE_RX 0x00000008
  2806. #define MR_NP_LOADED 0x00000010
  2807. #define MR_TOGGLE_TX 0x00000020
  2808. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  2809. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  2810. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  2811. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  2812. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  2813. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  2814. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  2815. #define MR_TOGGLE_RX 0x00002000
  2816. #define MR_NP_RX 0x00004000
  2817. #define MR_LINK_OK 0x80000000
  2818. unsigned long link_time, cur_time;
  2819. u32 ability_match_cfg;
  2820. int ability_match_count;
  2821. char ability_match, idle_match, ack_match;
  2822. u32 txconfig, rxconfig;
  2823. #define ANEG_CFG_NP 0x00000080
  2824. #define ANEG_CFG_ACK 0x00000040
  2825. #define ANEG_CFG_RF2 0x00000020
  2826. #define ANEG_CFG_RF1 0x00000010
  2827. #define ANEG_CFG_PS2 0x00000001
  2828. #define ANEG_CFG_PS1 0x00008000
  2829. #define ANEG_CFG_HD 0x00004000
  2830. #define ANEG_CFG_FD 0x00002000
  2831. #define ANEG_CFG_INVAL 0x00001f06
  2832. };
  2833. #define ANEG_OK 0
  2834. #define ANEG_DONE 1
  2835. #define ANEG_TIMER_ENAB 2
  2836. #define ANEG_FAILED -1
  2837. #define ANEG_STATE_SETTLE_TIME 10000
  2838. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  2839. struct tg3_fiber_aneginfo *ap)
  2840. {
  2841. u16 flowctrl;
  2842. unsigned long delta;
  2843. u32 rx_cfg_reg;
  2844. int ret;
  2845. if (ap->state == ANEG_STATE_UNKNOWN) {
  2846. ap->rxconfig = 0;
  2847. ap->link_time = 0;
  2848. ap->cur_time = 0;
  2849. ap->ability_match_cfg = 0;
  2850. ap->ability_match_count = 0;
  2851. ap->ability_match = 0;
  2852. ap->idle_match = 0;
  2853. ap->ack_match = 0;
  2854. }
  2855. ap->cur_time++;
  2856. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  2857. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  2858. if (rx_cfg_reg != ap->ability_match_cfg) {
  2859. ap->ability_match_cfg = rx_cfg_reg;
  2860. ap->ability_match = 0;
  2861. ap->ability_match_count = 0;
  2862. } else {
  2863. if (++ap->ability_match_count > 1) {
  2864. ap->ability_match = 1;
  2865. ap->ability_match_cfg = rx_cfg_reg;
  2866. }
  2867. }
  2868. if (rx_cfg_reg & ANEG_CFG_ACK)
  2869. ap->ack_match = 1;
  2870. else
  2871. ap->ack_match = 0;
  2872. ap->idle_match = 0;
  2873. } else {
  2874. ap->idle_match = 1;
  2875. ap->ability_match_cfg = 0;
  2876. ap->ability_match_count = 0;
  2877. ap->ability_match = 0;
  2878. ap->ack_match = 0;
  2879. rx_cfg_reg = 0;
  2880. }
  2881. ap->rxconfig = rx_cfg_reg;
  2882. ret = ANEG_OK;
  2883. switch (ap->state) {
  2884. case ANEG_STATE_UNKNOWN:
  2885. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  2886. ap->state = ANEG_STATE_AN_ENABLE;
  2887. /* fallthru */
  2888. case ANEG_STATE_AN_ENABLE:
  2889. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  2890. if (ap->flags & MR_AN_ENABLE) {
  2891. ap->link_time = 0;
  2892. ap->cur_time = 0;
  2893. ap->ability_match_cfg = 0;
  2894. ap->ability_match_count = 0;
  2895. ap->ability_match = 0;
  2896. ap->idle_match = 0;
  2897. ap->ack_match = 0;
  2898. ap->state = ANEG_STATE_RESTART_INIT;
  2899. } else {
  2900. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  2901. }
  2902. break;
  2903. case ANEG_STATE_RESTART_INIT:
  2904. ap->link_time = ap->cur_time;
  2905. ap->flags &= ~(MR_NP_LOADED);
  2906. ap->txconfig = 0;
  2907. tw32(MAC_TX_AUTO_NEG, 0);
  2908. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2909. tw32_f(MAC_MODE, tp->mac_mode);
  2910. udelay(40);
  2911. ret = ANEG_TIMER_ENAB;
  2912. ap->state = ANEG_STATE_RESTART;
  2913. /* fallthru */
  2914. case ANEG_STATE_RESTART:
  2915. delta = ap->cur_time - ap->link_time;
  2916. if (delta > ANEG_STATE_SETTLE_TIME)
  2917. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  2918. else
  2919. ret = ANEG_TIMER_ENAB;
  2920. break;
  2921. case ANEG_STATE_DISABLE_LINK_OK:
  2922. ret = ANEG_DONE;
  2923. break;
  2924. case ANEG_STATE_ABILITY_DETECT_INIT:
  2925. ap->flags &= ~(MR_TOGGLE_TX);
  2926. ap->txconfig = ANEG_CFG_FD;
  2927. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2928. if (flowctrl & ADVERTISE_1000XPAUSE)
  2929. ap->txconfig |= ANEG_CFG_PS1;
  2930. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2931. ap->txconfig |= ANEG_CFG_PS2;
  2932. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2933. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2934. tw32_f(MAC_MODE, tp->mac_mode);
  2935. udelay(40);
  2936. ap->state = ANEG_STATE_ABILITY_DETECT;
  2937. break;
  2938. case ANEG_STATE_ABILITY_DETECT:
  2939. if (ap->ability_match != 0 && ap->rxconfig != 0)
  2940. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  2941. break;
  2942. case ANEG_STATE_ACK_DETECT_INIT:
  2943. ap->txconfig |= ANEG_CFG_ACK;
  2944. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2945. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2946. tw32_f(MAC_MODE, tp->mac_mode);
  2947. udelay(40);
  2948. ap->state = ANEG_STATE_ACK_DETECT;
  2949. /* fallthru */
  2950. case ANEG_STATE_ACK_DETECT:
  2951. if (ap->ack_match != 0) {
  2952. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  2953. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  2954. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  2955. } else {
  2956. ap->state = ANEG_STATE_AN_ENABLE;
  2957. }
  2958. } else if (ap->ability_match != 0 &&
  2959. ap->rxconfig == 0) {
  2960. ap->state = ANEG_STATE_AN_ENABLE;
  2961. }
  2962. break;
  2963. case ANEG_STATE_COMPLETE_ACK_INIT:
  2964. if (ap->rxconfig & ANEG_CFG_INVAL) {
  2965. ret = ANEG_FAILED;
  2966. break;
  2967. }
  2968. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  2969. MR_LP_ADV_HALF_DUPLEX |
  2970. MR_LP_ADV_SYM_PAUSE |
  2971. MR_LP_ADV_ASYM_PAUSE |
  2972. MR_LP_ADV_REMOTE_FAULT1 |
  2973. MR_LP_ADV_REMOTE_FAULT2 |
  2974. MR_LP_ADV_NEXT_PAGE |
  2975. MR_TOGGLE_RX |
  2976. MR_NP_RX);
  2977. if (ap->rxconfig & ANEG_CFG_FD)
  2978. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  2979. if (ap->rxconfig & ANEG_CFG_HD)
  2980. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  2981. if (ap->rxconfig & ANEG_CFG_PS1)
  2982. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  2983. if (ap->rxconfig & ANEG_CFG_PS2)
  2984. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  2985. if (ap->rxconfig & ANEG_CFG_RF1)
  2986. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  2987. if (ap->rxconfig & ANEG_CFG_RF2)
  2988. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  2989. if (ap->rxconfig & ANEG_CFG_NP)
  2990. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  2991. ap->link_time = ap->cur_time;
  2992. ap->flags ^= (MR_TOGGLE_TX);
  2993. if (ap->rxconfig & 0x0008)
  2994. ap->flags |= MR_TOGGLE_RX;
  2995. if (ap->rxconfig & ANEG_CFG_NP)
  2996. ap->flags |= MR_NP_RX;
  2997. ap->flags |= MR_PAGE_RX;
  2998. ap->state = ANEG_STATE_COMPLETE_ACK;
  2999. ret = ANEG_TIMER_ENAB;
  3000. break;
  3001. case ANEG_STATE_COMPLETE_ACK:
  3002. if (ap->ability_match != 0 &&
  3003. ap->rxconfig == 0) {
  3004. ap->state = ANEG_STATE_AN_ENABLE;
  3005. break;
  3006. }
  3007. delta = ap->cur_time - ap->link_time;
  3008. if (delta > ANEG_STATE_SETTLE_TIME) {
  3009. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  3010. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3011. } else {
  3012. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  3013. !(ap->flags & MR_NP_RX)) {
  3014. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3015. } else {
  3016. ret = ANEG_FAILED;
  3017. }
  3018. }
  3019. }
  3020. break;
  3021. case ANEG_STATE_IDLE_DETECT_INIT:
  3022. ap->link_time = ap->cur_time;
  3023. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3024. tw32_f(MAC_MODE, tp->mac_mode);
  3025. udelay(40);
  3026. ap->state = ANEG_STATE_IDLE_DETECT;
  3027. ret = ANEG_TIMER_ENAB;
  3028. break;
  3029. case ANEG_STATE_IDLE_DETECT:
  3030. if (ap->ability_match != 0 &&
  3031. ap->rxconfig == 0) {
  3032. ap->state = ANEG_STATE_AN_ENABLE;
  3033. break;
  3034. }
  3035. delta = ap->cur_time - ap->link_time;
  3036. if (delta > ANEG_STATE_SETTLE_TIME) {
  3037. /* XXX another gem from the Broadcom driver :( */
  3038. ap->state = ANEG_STATE_LINK_OK;
  3039. }
  3040. break;
  3041. case ANEG_STATE_LINK_OK:
  3042. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  3043. ret = ANEG_DONE;
  3044. break;
  3045. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  3046. /* ??? unimplemented */
  3047. break;
  3048. case ANEG_STATE_NEXT_PAGE_WAIT:
  3049. /* ??? unimplemented */
  3050. break;
  3051. default:
  3052. ret = ANEG_FAILED;
  3053. break;
  3054. }
  3055. return ret;
  3056. }
  3057. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  3058. {
  3059. int res = 0;
  3060. struct tg3_fiber_aneginfo aninfo;
  3061. int status = ANEG_FAILED;
  3062. unsigned int tick;
  3063. u32 tmp;
  3064. tw32_f(MAC_TX_AUTO_NEG, 0);
  3065. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  3066. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  3067. udelay(40);
  3068. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  3069. udelay(40);
  3070. memset(&aninfo, 0, sizeof(aninfo));
  3071. aninfo.flags |= MR_AN_ENABLE;
  3072. aninfo.state = ANEG_STATE_UNKNOWN;
  3073. aninfo.cur_time = 0;
  3074. tick = 0;
  3075. while (++tick < 195000) {
  3076. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  3077. if (status == ANEG_DONE || status == ANEG_FAILED)
  3078. break;
  3079. udelay(1);
  3080. }
  3081. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3082. tw32_f(MAC_MODE, tp->mac_mode);
  3083. udelay(40);
  3084. *txflags = aninfo.txconfig;
  3085. *rxflags = aninfo.flags;
  3086. if (status == ANEG_DONE &&
  3087. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  3088. MR_LP_ADV_FULL_DUPLEX)))
  3089. res = 1;
  3090. return res;
  3091. }
  3092. static void tg3_init_bcm8002(struct tg3 *tp)
  3093. {
  3094. u32 mac_status = tr32(MAC_STATUS);
  3095. int i;
  3096. /* Reset when initting first time or we have a link. */
  3097. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  3098. !(mac_status & MAC_STATUS_PCS_SYNCED))
  3099. return;
  3100. /* Set PLL lock range. */
  3101. tg3_writephy(tp, 0x16, 0x8007);
  3102. /* SW reset */
  3103. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  3104. /* Wait for reset to complete. */
  3105. /* XXX schedule_timeout() ... */
  3106. for (i = 0; i < 500; i++)
  3107. udelay(10);
  3108. /* Config mode; select PMA/Ch 1 regs. */
  3109. tg3_writephy(tp, 0x10, 0x8411);
  3110. /* Enable auto-lock and comdet, select txclk for tx. */
  3111. tg3_writephy(tp, 0x11, 0x0a10);
  3112. tg3_writephy(tp, 0x18, 0x00a0);
  3113. tg3_writephy(tp, 0x16, 0x41ff);
  3114. /* Assert and deassert POR. */
  3115. tg3_writephy(tp, 0x13, 0x0400);
  3116. udelay(40);
  3117. tg3_writephy(tp, 0x13, 0x0000);
  3118. tg3_writephy(tp, 0x11, 0x0a50);
  3119. udelay(40);
  3120. tg3_writephy(tp, 0x11, 0x0a10);
  3121. /* Wait for signal to stabilize */
  3122. /* XXX schedule_timeout() ... */
  3123. for (i = 0; i < 15000; i++)
  3124. udelay(10);
  3125. /* Deselect the channel register so we can read the PHYID
  3126. * later.
  3127. */
  3128. tg3_writephy(tp, 0x10, 0x8011);
  3129. }
  3130. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  3131. {
  3132. u16 flowctrl;
  3133. u32 sg_dig_ctrl, sg_dig_status;
  3134. u32 serdes_cfg, expected_sg_dig_ctrl;
  3135. int workaround, port_a;
  3136. int current_link_up;
  3137. serdes_cfg = 0;
  3138. expected_sg_dig_ctrl = 0;
  3139. workaround = 0;
  3140. port_a = 1;
  3141. current_link_up = 0;
  3142. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  3143. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  3144. workaround = 1;
  3145. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  3146. port_a = 0;
  3147. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  3148. /* preserve bits 20-23 for voltage regulator */
  3149. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  3150. }
  3151. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  3152. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  3153. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  3154. if (workaround) {
  3155. u32 val = serdes_cfg;
  3156. if (port_a)
  3157. val |= 0xc010000;
  3158. else
  3159. val |= 0x4010000;
  3160. tw32_f(MAC_SERDES_CFG, val);
  3161. }
  3162. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3163. }
  3164. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  3165. tg3_setup_flow_control(tp, 0, 0);
  3166. current_link_up = 1;
  3167. }
  3168. goto out;
  3169. }
  3170. /* Want auto-negotiation. */
  3171. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  3172. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3173. if (flowctrl & ADVERTISE_1000XPAUSE)
  3174. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  3175. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  3176. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  3177. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  3178. if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
  3179. tp->serdes_counter &&
  3180. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  3181. MAC_STATUS_RCVD_CFG)) ==
  3182. MAC_STATUS_PCS_SYNCED)) {
  3183. tp->serdes_counter--;
  3184. current_link_up = 1;
  3185. goto out;
  3186. }
  3187. restart_autoneg:
  3188. if (workaround)
  3189. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  3190. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  3191. udelay(5);
  3192. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  3193. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3194. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3195. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  3196. MAC_STATUS_SIGNAL_DET)) {
  3197. sg_dig_status = tr32(SG_DIG_STATUS);
  3198. mac_status = tr32(MAC_STATUS);
  3199. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  3200. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  3201. u32 local_adv = 0, remote_adv = 0;
  3202. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  3203. local_adv |= ADVERTISE_1000XPAUSE;
  3204. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  3205. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3206. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  3207. remote_adv |= LPA_1000XPAUSE;
  3208. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  3209. remote_adv |= LPA_1000XPAUSE_ASYM;
  3210. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3211. current_link_up = 1;
  3212. tp->serdes_counter = 0;
  3213. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3214. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  3215. if (tp->serdes_counter)
  3216. tp->serdes_counter--;
  3217. else {
  3218. if (workaround) {
  3219. u32 val = serdes_cfg;
  3220. if (port_a)
  3221. val |= 0xc010000;
  3222. else
  3223. val |= 0x4010000;
  3224. tw32_f(MAC_SERDES_CFG, val);
  3225. }
  3226. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3227. udelay(40);
  3228. /* Link parallel detection - link is up */
  3229. /* only if we have PCS_SYNC and not */
  3230. /* receiving config code words */
  3231. mac_status = tr32(MAC_STATUS);
  3232. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  3233. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  3234. tg3_setup_flow_control(tp, 0, 0);
  3235. current_link_up = 1;
  3236. tp->phy_flags |=
  3237. TG3_PHYFLG_PARALLEL_DETECT;
  3238. tp->serdes_counter =
  3239. SERDES_PARALLEL_DET_TIMEOUT;
  3240. } else
  3241. goto restart_autoneg;
  3242. }
  3243. }
  3244. } else {
  3245. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3246. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3247. }
  3248. out:
  3249. return current_link_up;
  3250. }
  3251. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  3252. {
  3253. int current_link_up = 0;
  3254. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  3255. goto out;
  3256. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3257. u32 txflags, rxflags;
  3258. int i;
  3259. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  3260. u32 local_adv = 0, remote_adv = 0;
  3261. if (txflags & ANEG_CFG_PS1)
  3262. local_adv |= ADVERTISE_1000XPAUSE;
  3263. if (txflags & ANEG_CFG_PS2)
  3264. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3265. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  3266. remote_adv |= LPA_1000XPAUSE;
  3267. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  3268. remote_adv |= LPA_1000XPAUSE_ASYM;
  3269. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3270. current_link_up = 1;
  3271. }
  3272. for (i = 0; i < 30; i++) {
  3273. udelay(20);
  3274. tw32_f(MAC_STATUS,
  3275. (MAC_STATUS_SYNC_CHANGED |
  3276. MAC_STATUS_CFG_CHANGED));
  3277. udelay(40);
  3278. if ((tr32(MAC_STATUS) &
  3279. (MAC_STATUS_SYNC_CHANGED |
  3280. MAC_STATUS_CFG_CHANGED)) == 0)
  3281. break;
  3282. }
  3283. mac_status = tr32(MAC_STATUS);
  3284. if (current_link_up == 0 &&
  3285. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  3286. !(mac_status & MAC_STATUS_RCVD_CFG))
  3287. current_link_up = 1;
  3288. } else {
  3289. tg3_setup_flow_control(tp, 0, 0);
  3290. /* Forcing 1000FD link up. */
  3291. current_link_up = 1;
  3292. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  3293. udelay(40);
  3294. tw32_f(MAC_MODE, tp->mac_mode);
  3295. udelay(40);
  3296. }
  3297. out:
  3298. return current_link_up;
  3299. }
  3300. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  3301. {
  3302. u32 orig_pause_cfg;
  3303. u16 orig_active_speed;
  3304. u8 orig_active_duplex;
  3305. u32 mac_status;
  3306. int current_link_up;
  3307. int i;
  3308. orig_pause_cfg = tp->link_config.active_flowctrl;
  3309. orig_active_speed = tp->link_config.active_speed;
  3310. orig_active_duplex = tp->link_config.active_duplex;
  3311. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  3312. netif_carrier_ok(tp->dev) &&
  3313. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  3314. mac_status = tr32(MAC_STATUS);
  3315. mac_status &= (MAC_STATUS_PCS_SYNCED |
  3316. MAC_STATUS_SIGNAL_DET |
  3317. MAC_STATUS_CFG_CHANGED |
  3318. MAC_STATUS_RCVD_CFG);
  3319. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  3320. MAC_STATUS_SIGNAL_DET)) {
  3321. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3322. MAC_STATUS_CFG_CHANGED));
  3323. return 0;
  3324. }
  3325. }
  3326. tw32_f(MAC_TX_AUTO_NEG, 0);
  3327. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  3328. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  3329. tw32_f(MAC_MODE, tp->mac_mode);
  3330. udelay(40);
  3331. if (tp->phy_id == TG3_PHY_ID_BCM8002)
  3332. tg3_init_bcm8002(tp);
  3333. /* Enable link change event even when serdes polling. */
  3334. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3335. udelay(40);
  3336. current_link_up = 0;
  3337. mac_status = tr32(MAC_STATUS);
  3338. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  3339. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  3340. else
  3341. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  3342. tp->napi[0].hw_status->status =
  3343. (SD_STATUS_UPDATED |
  3344. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  3345. for (i = 0; i < 100; i++) {
  3346. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3347. MAC_STATUS_CFG_CHANGED));
  3348. udelay(5);
  3349. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  3350. MAC_STATUS_CFG_CHANGED |
  3351. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  3352. break;
  3353. }
  3354. mac_status = tr32(MAC_STATUS);
  3355. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  3356. current_link_up = 0;
  3357. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  3358. tp->serdes_counter == 0) {
  3359. tw32_f(MAC_MODE, (tp->mac_mode |
  3360. MAC_MODE_SEND_CONFIGS));
  3361. udelay(1);
  3362. tw32_f(MAC_MODE, tp->mac_mode);
  3363. }
  3364. }
  3365. if (current_link_up == 1) {
  3366. tp->link_config.active_speed = SPEED_1000;
  3367. tp->link_config.active_duplex = DUPLEX_FULL;
  3368. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3369. LED_CTRL_LNKLED_OVERRIDE |
  3370. LED_CTRL_1000MBPS_ON));
  3371. } else {
  3372. tp->link_config.active_speed = SPEED_INVALID;
  3373. tp->link_config.active_duplex = DUPLEX_INVALID;
  3374. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3375. LED_CTRL_LNKLED_OVERRIDE |
  3376. LED_CTRL_TRAFFIC_OVERRIDE));
  3377. }
  3378. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3379. if (current_link_up)
  3380. netif_carrier_on(tp->dev);
  3381. else
  3382. netif_carrier_off(tp->dev);
  3383. tg3_link_report(tp);
  3384. } else {
  3385. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  3386. if (orig_pause_cfg != now_pause_cfg ||
  3387. orig_active_speed != tp->link_config.active_speed ||
  3388. orig_active_duplex != tp->link_config.active_duplex)
  3389. tg3_link_report(tp);
  3390. }
  3391. return 0;
  3392. }
  3393. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  3394. {
  3395. int current_link_up, err = 0;
  3396. u32 bmsr, bmcr;
  3397. u16 current_speed;
  3398. u8 current_duplex;
  3399. u32 local_adv, remote_adv;
  3400. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3401. tw32_f(MAC_MODE, tp->mac_mode);
  3402. udelay(40);
  3403. tw32(MAC_EVENT, 0);
  3404. tw32_f(MAC_STATUS,
  3405. (MAC_STATUS_SYNC_CHANGED |
  3406. MAC_STATUS_CFG_CHANGED |
  3407. MAC_STATUS_MI_COMPLETION |
  3408. MAC_STATUS_LNKSTATE_CHANGED));
  3409. udelay(40);
  3410. if (force_reset)
  3411. tg3_phy_reset(tp);
  3412. current_link_up = 0;
  3413. current_speed = SPEED_INVALID;
  3414. current_duplex = DUPLEX_INVALID;
  3415. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3416. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3417. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  3418. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  3419. bmsr |= BMSR_LSTATUS;
  3420. else
  3421. bmsr &= ~BMSR_LSTATUS;
  3422. }
  3423. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  3424. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  3425. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  3426. /* do nothing, just check for link up at the end */
  3427. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3428. u32 adv, new_adv;
  3429. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  3430. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  3431. ADVERTISE_1000XPAUSE |
  3432. ADVERTISE_1000XPSE_ASYM |
  3433. ADVERTISE_SLCT);
  3434. new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3435. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  3436. new_adv |= ADVERTISE_1000XHALF;
  3437. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  3438. new_adv |= ADVERTISE_1000XFULL;
  3439. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  3440. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  3441. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  3442. tg3_writephy(tp, MII_BMCR, bmcr);
  3443. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3444. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  3445. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3446. return err;
  3447. }
  3448. } else {
  3449. u32 new_bmcr;
  3450. bmcr &= ~BMCR_SPEED1000;
  3451. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  3452. if (tp->link_config.duplex == DUPLEX_FULL)
  3453. new_bmcr |= BMCR_FULLDPLX;
  3454. if (new_bmcr != bmcr) {
  3455. /* BMCR_SPEED1000 is a reserved bit that needs
  3456. * to be set on write.
  3457. */
  3458. new_bmcr |= BMCR_SPEED1000;
  3459. /* Force a linkdown */
  3460. if (netif_carrier_ok(tp->dev)) {
  3461. u32 adv;
  3462. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  3463. adv &= ~(ADVERTISE_1000XFULL |
  3464. ADVERTISE_1000XHALF |
  3465. ADVERTISE_SLCT);
  3466. tg3_writephy(tp, MII_ADVERTISE, adv);
  3467. tg3_writephy(tp, MII_BMCR, bmcr |
  3468. BMCR_ANRESTART |
  3469. BMCR_ANENABLE);
  3470. udelay(10);
  3471. netif_carrier_off(tp->dev);
  3472. }
  3473. tg3_writephy(tp, MII_BMCR, new_bmcr);
  3474. bmcr = new_bmcr;
  3475. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3476. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3477. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  3478. ASIC_REV_5714) {
  3479. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  3480. bmsr |= BMSR_LSTATUS;
  3481. else
  3482. bmsr &= ~BMSR_LSTATUS;
  3483. }
  3484. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3485. }
  3486. }
  3487. if (bmsr & BMSR_LSTATUS) {
  3488. current_speed = SPEED_1000;
  3489. current_link_up = 1;
  3490. if (bmcr & BMCR_FULLDPLX)
  3491. current_duplex = DUPLEX_FULL;
  3492. else
  3493. current_duplex = DUPLEX_HALF;
  3494. local_adv = 0;
  3495. remote_adv = 0;
  3496. if (bmcr & BMCR_ANENABLE) {
  3497. u32 common;
  3498. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  3499. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  3500. common = local_adv & remote_adv;
  3501. if (common & (ADVERTISE_1000XHALF |
  3502. ADVERTISE_1000XFULL)) {
  3503. if (common & ADVERTISE_1000XFULL)
  3504. current_duplex = DUPLEX_FULL;
  3505. else
  3506. current_duplex = DUPLEX_HALF;
  3507. } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  3508. /* Link is up via parallel detect */
  3509. } else {
  3510. current_link_up = 0;
  3511. }
  3512. }
  3513. }
  3514. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  3515. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3516. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  3517. if (tp->link_config.active_duplex == DUPLEX_HALF)
  3518. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  3519. tw32_f(MAC_MODE, tp->mac_mode);
  3520. udelay(40);
  3521. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3522. tp->link_config.active_speed = current_speed;
  3523. tp->link_config.active_duplex = current_duplex;
  3524. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3525. if (current_link_up)
  3526. netif_carrier_on(tp->dev);
  3527. else {
  3528. netif_carrier_off(tp->dev);
  3529. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3530. }
  3531. tg3_link_report(tp);
  3532. }
  3533. return err;
  3534. }
  3535. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  3536. {
  3537. if (tp->serdes_counter) {
  3538. /* Give autoneg time to complete. */
  3539. tp->serdes_counter--;
  3540. return;
  3541. }
  3542. if (!netif_carrier_ok(tp->dev) &&
  3543. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  3544. u32 bmcr;
  3545. tg3_readphy(tp, MII_BMCR, &bmcr);
  3546. if (bmcr & BMCR_ANENABLE) {
  3547. u32 phy1, phy2;
  3548. /* Select shadow register 0x1f */
  3549. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
  3550. tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
  3551. /* Select expansion interrupt status register */
  3552. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  3553. MII_TG3_DSP_EXP1_INT_STAT);
  3554. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  3555. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  3556. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  3557. /* We have signal detect and not receiving
  3558. * config code words, link is up by parallel
  3559. * detection.
  3560. */
  3561. bmcr &= ~BMCR_ANENABLE;
  3562. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  3563. tg3_writephy(tp, MII_BMCR, bmcr);
  3564. tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
  3565. }
  3566. }
  3567. } else if (netif_carrier_ok(tp->dev) &&
  3568. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  3569. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  3570. u32 phy2;
  3571. /* Select expansion interrupt status register */
  3572. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  3573. MII_TG3_DSP_EXP1_INT_STAT);
  3574. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  3575. if (phy2 & 0x20) {
  3576. u32 bmcr;
  3577. /* Config code words received, turn on autoneg. */
  3578. tg3_readphy(tp, MII_BMCR, &bmcr);
  3579. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  3580. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3581. }
  3582. }
  3583. }
  3584. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  3585. {
  3586. int err;
  3587. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  3588. err = tg3_setup_fiber_phy(tp, force_reset);
  3589. else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3590. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  3591. else
  3592. err = tg3_setup_copper_phy(tp, force_reset);
  3593. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  3594. u32 val, scale;
  3595. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  3596. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  3597. scale = 65;
  3598. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  3599. scale = 6;
  3600. else
  3601. scale = 12;
  3602. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  3603. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  3604. tw32(GRC_MISC_CFG, val);
  3605. }
  3606. if (tp->link_config.active_speed == SPEED_1000 &&
  3607. tp->link_config.active_duplex == DUPLEX_HALF)
  3608. tw32(MAC_TX_LENGTHS,
  3609. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3610. (6 << TX_LENGTHS_IPG_SHIFT) |
  3611. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3612. else
  3613. tw32(MAC_TX_LENGTHS,
  3614. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3615. (6 << TX_LENGTHS_IPG_SHIFT) |
  3616. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3617. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  3618. if (netif_carrier_ok(tp->dev)) {
  3619. tw32(HOSTCC_STAT_COAL_TICKS,
  3620. tp->coal.stats_block_coalesce_usecs);
  3621. } else {
  3622. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  3623. }
  3624. }
  3625. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  3626. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  3627. if (!netif_carrier_ok(tp->dev))
  3628. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  3629. tp->pwrmgmt_thresh;
  3630. else
  3631. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  3632. tw32(PCIE_PWR_MGMT_THRESH, val);
  3633. }
  3634. return err;
  3635. }
  3636. /* This is called whenever we suspect that the system chipset is re-
  3637. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  3638. * is bogus tx completions. We try to recover by setting the
  3639. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  3640. * in the workqueue.
  3641. */
  3642. static void tg3_tx_recover(struct tg3 *tp)
  3643. {
  3644. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  3645. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  3646. netdev_warn(tp->dev,
  3647. "The system may be re-ordering memory-mapped I/O "
  3648. "cycles to the network device, attempting to recover. "
  3649. "Please report the problem to the driver maintainer "
  3650. "and include system chipset information.\n");
  3651. spin_lock(&tp->lock);
  3652. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  3653. spin_unlock(&tp->lock);
  3654. }
  3655. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  3656. {
  3657. /* Tell compiler to fetch tx indices from memory. */
  3658. barrier();
  3659. return tnapi->tx_pending -
  3660. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  3661. }
  3662. /* Tigon3 never reports partial packet sends. So we do not
  3663. * need special logic to handle SKBs that have not had all
  3664. * of their frags sent yet, like SunGEM does.
  3665. */
  3666. static void tg3_tx(struct tg3_napi *tnapi)
  3667. {
  3668. struct tg3 *tp = tnapi->tp;
  3669. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  3670. u32 sw_idx = tnapi->tx_cons;
  3671. struct netdev_queue *txq;
  3672. int index = tnapi - tp->napi;
  3673. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  3674. index--;
  3675. txq = netdev_get_tx_queue(tp->dev, index);
  3676. while (sw_idx != hw_idx) {
  3677. struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
  3678. struct sk_buff *skb = ri->skb;
  3679. int i, tx_bug = 0;
  3680. if (unlikely(skb == NULL)) {
  3681. tg3_tx_recover(tp);
  3682. return;
  3683. }
  3684. pci_unmap_single(tp->pdev,
  3685. dma_unmap_addr(ri, mapping),
  3686. skb_headlen(skb),
  3687. PCI_DMA_TODEVICE);
  3688. ri->skb = NULL;
  3689. sw_idx = NEXT_TX(sw_idx);
  3690. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  3691. ri = &tnapi->tx_buffers[sw_idx];
  3692. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  3693. tx_bug = 1;
  3694. pci_unmap_page(tp->pdev,
  3695. dma_unmap_addr(ri, mapping),
  3696. skb_shinfo(skb)->frags[i].size,
  3697. PCI_DMA_TODEVICE);
  3698. sw_idx = NEXT_TX(sw_idx);
  3699. }
  3700. dev_kfree_skb(skb);
  3701. if (unlikely(tx_bug)) {
  3702. tg3_tx_recover(tp);
  3703. return;
  3704. }
  3705. }
  3706. tnapi->tx_cons = sw_idx;
  3707. /* Need to make the tx_cons update visible to tg3_start_xmit()
  3708. * before checking for netif_queue_stopped(). Without the
  3709. * memory barrier, there is a small possibility that tg3_start_xmit()
  3710. * will miss it and cause the queue to be stopped forever.
  3711. */
  3712. smp_mb();
  3713. if (unlikely(netif_tx_queue_stopped(txq) &&
  3714. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  3715. __netif_tx_lock(txq, smp_processor_id());
  3716. if (netif_tx_queue_stopped(txq) &&
  3717. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  3718. netif_tx_wake_queue(txq);
  3719. __netif_tx_unlock(txq);
  3720. }
  3721. }
  3722. static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  3723. {
  3724. if (!ri->skb)
  3725. return;
  3726. pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
  3727. map_sz, PCI_DMA_FROMDEVICE);
  3728. dev_kfree_skb_any(ri->skb);
  3729. ri->skb = NULL;
  3730. }
  3731. /* Returns size of skb allocated or < 0 on error.
  3732. *
  3733. * We only need to fill in the address because the other members
  3734. * of the RX descriptor are invariant, see tg3_init_rings.
  3735. *
  3736. * Note the purposeful assymetry of cpu vs. chip accesses. For
  3737. * posting buffers we only dirty the first cache line of the RX
  3738. * descriptor (containing the address). Whereas for the RX status
  3739. * buffers the cpu only reads the last cacheline of the RX descriptor
  3740. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  3741. */
  3742. static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  3743. u32 opaque_key, u32 dest_idx_unmasked)
  3744. {
  3745. struct tg3_rx_buffer_desc *desc;
  3746. struct ring_info *map, *src_map;
  3747. struct sk_buff *skb;
  3748. dma_addr_t mapping;
  3749. int skb_size, dest_idx;
  3750. src_map = NULL;
  3751. switch (opaque_key) {
  3752. case RXD_OPAQUE_RING_STD:
  3753. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3754. desc = &tpr->rx_std[dest_idx];
  3755. map = &tpr->rx_std_buffers[dest_idx];
  3756. skb_size = tp->rx_pkt_map_sz;
  3757. break;
  3758. case RXD_OPAQUE_RING_JUMBO:
  3759. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3760. desc = &tpr->rx_jmb[dest_idx].std;
  3761. map = &tpr->rx_jmb_buffers[dest_idx];
  3762. skb_size = TG3_RX_JMB_MAP_SZ;
  3763. break;
  3764. default:
  3765. return -EINVAL;
  3766. }
  3767. /* Do not overwrite any of the map or rp information
  3768. * until we are sure we can commit to a new buffer.
  3769. *
  3770. * Callers depend upon this behavior and assume that
  3771. * we leave everything unchanged if we fail.
  3772. */
  3773. skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
  3774. if (skb == NULL)
  3775. return -ENOMEM;
  3776. skb_reserve(skb, tp->rx_offset);
  3777. mapping = pci_map_single(tp->pdev, skb->data, skb_size,
  3778. PCI_DMA_FROMDEVICE);
  3779. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  3780. dev_kfree_skb(skb);
  3781. return -EIO;
  3782. }
  3783. map->skb = skb;
  3784. dma_unmap_addr_set(map, mapping, mapping);
  3785. desc->addr_hi = ((u64)mapping >> 32);
  3786. desc->addr_lo = ((u64)mapping & 0xffffffff);
  3787. return skb_size;
  3788. }
  3789. /* We only need to move over in the address because the other
  3790. * members of the RX descriptor are invariant. See notes above
  3791. * tg3_alloc_rx_skb for full details.
  3792. */
  3793. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  3794. struct tg3_rx_prodring_set *dpr,
  3795. u32 opaque_key, int src_idx,
  3796. u32 dest_idx_unmasked)
  3797. {
  3798. struct tg3 *tp = tnapi->tp;
  3799. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  3800. struct ring_info *src_map, *dest_map;
  3801. struct tg3_rx_prodring_set *spr = &tp->prodring[0];
  3802. int dest_idx;
  3803. switch (opaque_key) {
  3804. case RXD_OPAQUE_RING_STD:
  3805. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3806. dest_desc = &dpr->rx_std[dest_idx];
  3807. dest_map = &dpr->rx_std_buffers[dest_idx];
  3808. src_desc = &spr->rx_std[src_idx];
  3809. src_map = &spr->rx_std_buffers[src_idx];
  3810. break;
  3811. case RXD_OPAQUE_RING_JUMBO:
  3812. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3813. dest_desc = &dpr->rx_jmb[dest_idx].std;
  3814. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  3815. src_desc = &spr->rx_jmb[src_idx].std;
  3816. src_map = &spr->rx_jmb_buffers[src_idx];
  3817. break;
  3818. default:
  3819. return;
  3820. }
  3821. dest_map->skb = src_map->skb;
  3822. dma_unmap_addr_set(dest_map, mapping,
  3823. dma_unmap_addr(src_map, mapping));
  3824. dest_desc->addr_hi = src_desc->addr_hi;
  3825. dest_desc->addr_lo = src_desc->addr_lo;
  3826. /* Ensure that the update to the skb happens after the physical
  3827. * addresses have been transferred to the new BD location.
  3828. */
  3829. smp_wmb();
  3830. src_map->skb = NULL;
  3831. }
  3832. /* The RX ring scheme is composed of multiple rings which post fresh
  3833. * buffers to the chip, and one special ring the chip uses to report
  3834. * status back to the host.
  3835. *
  3836. * The special ring reports the status of received packets to the
  3837. * host. The chip does not write into the original descriptor the
  3838. * RX buffer was obtained from. The chip simply takes the original
  3839. * descriptor as provided by the host, updates the status and length
  3840. * field, then writes this into the next status ring entry.
  3841. *
  3842. * Each ring the host uses to post buffers to the chip is described
  3843. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  3844. * it is first placed into the on-chip ram. When the packet's length
  3845. * is known, it walks down the TG3_BDINFO entries to select the ring.
  3846. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  3847. * which is within the range of the new packet's length is chosen.
  3848. *
  3849. * The "separate ring for rx status" scheme may sound queer, but it makes
  3850. * sense from a cache coherency perspective. If only the host writes
  3851. * to the buffer post rings, and only the chip writes to the rx status
  3852. * rings, then cache lines never move beyond shared-modified state.
  3853. * If both the host and chip were to write into the same ring, cache line
  3854. * eviction could occur since both entities want it in an exclusive state.
  3855. */
  3856. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  3857. {
  3858. struct tg3 *tp = tnapi->tp;
  3859. u32 work_mask, rx_std_posted = 0;
  3860. u32 std_prod_idx, jmb_prod_idx;
  3861. u32 sw_idx = tnapi->rx_rcb_ptr;
  3862. u16 hw_idx;
  3863. int received;
  3864. struct tg3_rx_prodring_set *tpr = tnapi->prodring;
  3865. hw_idx = *(tnapi->rx_rcb_prod_idx);
  3866. /*
  3867. * We need to order the read of hw_idx and the read of
  3868. * the opaque cookie.
  3869. */
  3870. rmb();
  3871. work_mask = 0;
  3872. received = 0;
  3873. std_prod_idx = tpr->rx_std_prod_idx;
  3874. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  3875. while (sw_idx != hw_idx && budget > 0) {
  3876. struct ring_info *ri;
  3877. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  3878. unsigned int len;
  3879. struct sk_buff *skb;
  3880. dma_addr_t dma_addr;
  3881. u32 opaque_key, desc_idx, *post_ptr;
  3882. bool hw_vlan __maybe_unused = false;
  3883. u16 vtag __maybe_unused = 0;
  3884. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  3885. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  3886. if (opaque_key == RXD_OPAQUE_RING_STD) {
  3887. ri = &tp->prodring[0].rx_std_buffers[desc_idx];
  3888. dma_addr = dma_unmap_addr(ri, mapping);
  3889. skb = ri->skb;
  3890. post_ptr = &std_prod_idx;
  3891. rx_std_posted++;
  3892. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  3893. ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
  3894. dma_addr = dma_unmap_addr(ri, mapping);
  3895. skb = ri->skb;
  3896. post_ptr = &jmb_prod_idx;
  3897. } else
  3898. goto next_pkt_nopost;
  3899. work_mask |= opaque_key;
  3900. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  3901. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  3902. drop_it:
  3903. tg3_recycle_rx(tnapi, tpr, opaque_key,
  3904. desc_idx, *post_ptr);
  3905. drop_it_no_recycle:
  3906. /* Other statistics kept track of by card. */
  3907. tp->net_stats.rx_dropped++;
  3908. goto next_pkt;
  3909. }
  3910. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  3911. ETH_FCS_LEN;
  3912. if (len > TG3_RX_COPY_THRESH(tp)) {
  3913. int skb_size;
  3914. skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
  3915. *post_ptr);
  3916. if (skb_size < 0)
  3917. goto drop_it;
  3918. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  3919. PCI_DMA_FROMDEVICE);
  3920. /* Ensure that the update to the skb happens
  3921. * after the usage of the old DMA mapping.
  3922. */
  3923. smp_wmb();
  3924. ri->skb = NULL;
  3925. skb_put(skb, len);
  3926. } else {
  3927. struct sk_buff *copy_skb;
  3928. tg3_recycle_rx(tnapi, tpr, opaque_key,
  3929. desc_idx, *post_ptr);
  3930. copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
  3931. TG3_RAW_IP_ALIGN);
  3932. if (copy_skb == NULL)
  3933. goto drop_it_no_recycle;
  3934. skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
  3935. skb_put(copy_skb, len);
  3936. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3937. skb_copy_from_linear_data(skb, copy_skb->data, len);
  3938. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3939. /* We'll reuse the original ring buffer. */
  3940. skb = copy_skb;
  3941. }
  3942. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  3943. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  3944. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  3945. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  3946. skb->ip_summed = CHECKSUM_UNNECESSARY;
  3947. else
  3948. skb->ip_summed = CHECKSUM_NONE;
  3949. skb->protocol = eth_type_trans(skb, tp->dev);
  3950. if (len > (tp->dev->mtu + ETH_HLEN) &&
  3951. skb->protocol != htons(ETH_P_8021Q)) {
  3952. dev_kfree_skb(skb);
  3953. goto next_pkt;
  3954. }
  3955. if (desc->type_flags & RXD_FLAG_VLAN &&
  3956. !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
  3957. vtag = desc->err_vlan & RXD_VLAN_MASK;
  3958. #if TG3_VLAN_TAG_USED
  3959. if (tp->vlgrp)
  3960. hw_vlan = true;
  3961. else
  3962. #endif
  3963. {
  3964. struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
  3965. __skb_push(skb, VLAN_HLEN);
  3966. memmove(ve, skb->data + VLAN_HLEN,
  3967. ETH_ALEN * 2);
  3968. ve->h_vlan_proto = htons(ETH_P_8021Q);
  3969. ve->h_vlan_TCI = htons(vtag);
  3970. }
  3971. }
  3972. #if TG3_VLAN_TAG_USED
  3973. if (hw_vlan)
  3974. vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
  3975. else
  3976. #endif
  3977. napi_gro_receive(&tnapi->napi, skb);
  3978. received++;
  3979. budget--;
  3980. next_pkt:
  3981. (*post_ptr)++;
  3982. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  3983. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  3984. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  3985. tpr->rx_std_prod_idx);
  3986. work_mask &= ~RXD_OPAQUE_RING_STD;
  3987. rx_std_posted = 0;
  3988. }
  3989. next_pkt_nopost:
  3990. sw_idx++;
  3991. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  3992. /* Refresh hw_idx to see if there is new work */
  3993. if (sw_idx == hw_idx) {
  3994. hw_idx = *(tnapi->rx_rcb_prod_idx);
  3995. rmb();
  3996. }
  3997. }
  3998. /* ACK the status ring. */
  3999. tnapi->rx_rcb_ptr = sw_idx;
  4000. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  4001. /* Refill RX ring(s). */
  4002. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
  4003. if (work_mask & RXD_OPAQUE_RING_STD) {
  4004. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  4005. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4006. tpr->rx_std_prod_idx);
  4007. }
  4008. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  4009. tpr->rx_jmb_prod_idx = jmb_prod_idx %
  4010. TG3_RX_JUMBO_RING_SIZE;
  4011. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  4012. tpr->rx_jmb_prod_idx);
  4013. }
  4014. mmiowb();
  4015. } else if (work_mask) {
  4016. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  4017. * updated before the producer indices can be updated.
  4018. */
  4019. smp_wmb();
  4020. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  4021. tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
  4022. if (tnapi != &tp->napi[1])
  4023. napi_schedule(&tp->napi[1].napi);
  4024. }
  4025. return received;
  4026. }
  4027. static void tg3_poll_link(struct tg3 *tp)
  4028. {
  4029. /* handle link change and other phy events */
  4030. if (!(tp->tg3_flags &
  4031. (TG3_FLAG_USE_LINKCHG_REG |
  4032. TG3_FLAG_POLL_SERDES))) {
  4033. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  4034. if (sblk->status & SD_STATUS_LINK_CHG) {
  4035. sblk->status = SD_STATUS_UPDATED |
  4036. (sblk->status & ~SD_STATUS_LINK_CHG);
  4037. spin_lock(&tp->lock);
  4038. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  4039. tw32_f(MAC_STATUS,
  4040. (MAC_STATUS_SYNC_CHANGED |
  4041. MAC_STATUS_CFG_CHANGED |
  4042. MAC_STATUS_MI_COMPLETION |
  4043. MAC_STATUS_LNKSTATE_CHANGED));
  4044. udelay(40);
  4045. } else
  4046. tg3_setup_phy(tp, 0);
  4047. spin_unlock(&tp->lock);
  4048. }
  4049. }
  4050. }
  4051. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  4052. struct tg3_rx_prodring_set *dpr,
  4053. struct tg3_rx_prodring_set *spr)
  4054. {
  4055. u32 si, di, cpycnt, src_prod_idx;
  4056. int i, err = 0;
  4057. while (1) {
  4058. src_prod_idx = spr->rx_std_prod_idx;
  4059. /* Make sure updates to the rx_std_buffers[] entries and the
  4060. * standard producer index are seen in the correct order.
  4061. */
  4062. smp_rmb();
  4063. if (spr->rx_std_cons_idx == src_prod_idx)
  4064. break;
  4065. if (spr->rx_std_cons_idx < src_prod_idx)
  4066. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  4067. else
  4068. cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
  4069. cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
  4070. si = spr->rx_std_cons_idx;
  4071. di = dpr->rx_std_prod_idx;
  4072. for (i = di; i < di + cpycnt; i++) {
  4073. if (dpr->rx_std_buffers[i].skb) {
  4074. cpycnt = i - di;
  4075. err = -ENOSPC;
  4076. break;
  4077. }
  4078. }
  4079. if (!cpycnt)
  4080. break;
  4081. /* Ensure that updates to the rx_std_buffers ring and the
  4082. * shadowed hardware producer ring from tg3_recycle_skb() are
  4083. * ordered correctly WRT the skb check above.
  4084. */
  4085. smp_rmb();
  4086. memcpy(&dpr->rx_std_buffers[di],
  4087. &spr->rx_std_buffers[si],
  4088. cpycnt * sizeof(struct ring_info));
  4089. for (i = 0; i < cpycnt; i++, di++, si++) {
  4090. struct tg3_rx_buffer_desc *sbd, *dbd;
  4091. sbd = &spr->rx_std[si];
  4092. dbd = &dpr->rx_std[di];
  4093. dbd->addr_hi = sbd->addr_hi;
  4094. dbd->addr_lo = sbd->addr_lo;
  4095. }
  4096. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
  4097. TG3_RX_RING_SIZE;
  4098. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
  4099. TG3_RX_RING_SIZE;
  4100. }
  4101. while (1) {
  4102. src_prod_idx = spr->rx_jmb_prod_idx;
  4103. /* Make sure updates to the rx_jmb_buffers[] entries and
  4104. * the jumbo producer index are seen in the correct order.
  4105. */
  4106. smp_rmb();
  4107. if (spr->rx_jmb_cons_idx == src_prod_idx)
  4108. break;
  4109. if (spr->rx_jmb_cons_idx < src_prod_idx)
  4110. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  4111. else
  4112. cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
  4113. cpycnt = min(cpycnt,
  4114. TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
  4115. si = spr->rx_jmb_cons_idx;
  4116. di = dpr->rx_jmb_prod_idx;
  4117. for (i = di; i < di + cpycnt; i++) {
  4118. if (dpr->rx_jmb_buffers[i].skb) {
  4119. cpycnt = i - di;
  4120. err = -ENOSPC;
  4121. break;
  4122. }
  4123. }
  4124. if (!cpycnt)
  4125. break;
  4126. /* Ensure that updates to the rx_jmb_buffers ring and the
  4127. * shadowed hardware producer ring from tg3_recycle_skb() are
  4128. * ordered correctly WRT the skb check above.
  4129. */
  4130. smp_rmb();
  4131. memcpy(&dpr->rx_jmb_buffers[di],
  4132. &spr->rx_jmb_buffers[si],
  4133. cpycnt * sizeof(struct ring_info));
  4134. for (i = 0; i < cpycnt; i++, di++, si++) {
  4135. struct tg3_rx_buffer_desc *sbd, *dbd;
  4136. sbd = &spr->rx_jmb[si].std;
  4137. dbd = &dpr->rx_jmb[di].std;
  4138. dbd->addr_hi = sbd->addr_hi;
  4139. dbd->addr_lo = sbd->addr_lo;
  4140. }
  4141. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
  4142. TG3_RX_JUMBO_RING_SIZE;
  4143. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
  4144. TG3_RX_JUMBO_RING_SIZE;
  4145. }
  4146. return err;
  4147. }
  4148. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  4149. {
  4150. struct tg3 *tp = tnapi->tp;
  4151. /* run TX completion thread */
  4152. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  4153. tg3_tx(tnapi);
  4154. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4155. return work_done;
  4156. }
  4157. /* run RX thread, within the bounds set by NAPI.
  4158. * All RX "locking" is done by ensuring outside
  4159. * code synchronizes with tg3->napi.poll()
  4160. */
  4161. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  4162. work_done += tg3_rx(tnapi, budget - work_done);
  4163. if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
  4164. struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
  4165. int i, err = 0;
  4166. u32 std_prod_idx = dpr->rx_std_prod_idx;
  4167. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  4168. for (i = 1; i < tp->irq_cnt; i++)
  4169. err |= tg3_rx_prodring_xfer(tp, dpr,
  4170. tp->napi[i].prodring);
  4171. wmb();
  4172. if (std_prod_idx != dpr->rx_std_prod_idx)
  4173. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4174. dpr->rx_std_prod_idx);
  4175. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  4176. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  4177. dpr->rx_jmb_prod_idx);
  4178. mmiowb();
  4179. if (err)
  4180. tw32_f(HOSTCC_MODE, tp->coal_now);
  4181. }
  4182. return work_done;
  4183. }
  4184. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  4185. {
  4186. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4187. struct tg3 *tp = tnapi->tp;
  4188. int work_done = 0;
  4189. struct tg3_hw_status *sblk = tnapi->hw_status;
  4190. while (1) {
  4191. work_done = tg3_poll_work(tnapi, work_done, budget);
  4192. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4193. goto tx_recovery;
  4194. if (unlikely(work_done >= budget))
  4195. break;
  4196. /* tp->last_tag is used in tg3_int_reenable() below
  4197. * to tell the hw how much work has been processed,
  4198. * so we must read it before checking for more work.
  4199. */
  4200. tnapi->last_tag = sblk->status_tag;
  4201. tnapi->last_irq_tag = tnapi->last_tag;
  4202. rmb();
  4203. /* check for RX/TX work to do */
  4204. if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  4205. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
  4206. napi_complete(napi);
  4207. /* Reenable interrupts. */
  4208. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  4209. mmiowb();
  4210. break;
  4211. }
  4212. }
  4213. return work_done;
  4214. tx_recovery:
  4215. /* work_done is guaranteed to be less than budget. */
  4216. napi_complete(napi);
  4217. schedule_work(&tp->reset_task);
  4218. return work_done;
  4219. }
  4220. static int tg3_poll(struct napi_struct *napi, int budget)
  4221. {
  4222. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4223. struct tg3 *tp = tnapi->tp;
  4224. int work_done = 0;
  4225. struct tg3_hw_status *sblk = tnapi->hw_status;
  4226. while (1) {
  4227. tg3_poll_link(tp);
  4228. work_done = tg3_poll_work(tnapi, work_done, budget);
  4229. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4230. goto tx_recovery;
  4231. if (unlikely(work_done >= budget))
  4232. break;
  4233. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  4234. /* tp->last_tag is used in tg3_int_reenable() below
  4235. * to tell the hw how much work has been processed,
  4236. * so we must read it before checking for more work.
  4237. */
  4238. tnapi->last_tag = sblk->status_tag;
  4239. tnapi->last_irq_tag = tnapi->last_tag;
  4240. rmb();
  4241. } else
  4242. sblk->status &= ~SD_STATUS_UPDATED;
  4243. if (likely(!tg3_has_work(tnapi))) {
  4244. napi_complete(napi);
  4245. tg3_int_reenable(tnapi);
  4246. break;
  4247. }
  4248. }
  4249. return work_done;
  4250. tx_recovery:
  4251. /* work_done is guaranteed to be less than budget. */
  4252. napi_complete(napi);
  4253. schedule_work(&tp->reset_task);
  4254. return work_done;
  4255. }
  4256. static void tg3_irq_quiesce(struct tg3 *tp)
  4257. {
  4258. int i;
  4259. BUG_ON(tp->irq_sync);
  4260. tp->irq_sync = 1;
  4261. smp_mb();
  4262. for (i = 0; i < tp->irq_cnt; i++)
  4263. synchronize_irq(tp->napi[i].irq_vec);
  4264. }
  4265. static inline int tg3_irq_sync(struct tg3 *tp)
  4266. {
  4267. return tp->irq_sync;
  4268. }
  4269. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  4270. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  4271. * with as well. Most of the time, this is not necessary except when
  4272. * shutting down the device.
  4273. */
  4274. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  4275. {
  4276. spin_lock_bh(&tp->lock);
  4277. if (irq_sync)
  4278. tg3_irq_quiesce(tp);
  4279. }
  4280. static inline void tg3_full_unlock(struct tg3 *tp)
  4281. {
  4282. spin_unlock_bh(&tp->lock);
  4283. }
  4284. /* One-shot MSI handler - Chip automatically disables interrupt
  4285. * after sending MSI so driver doesn't have to do it.
  4286. */
  4287. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  4288. {
  4289. struct tg3_napi *tnapi = dev_id;
  4290. struct tg3 *tp = tnapi->tp;
  4291. prefetch(tnapi->hw_status);
  4292. if (tnapi->rx_rcb)
  4293. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4294. if (likely(!tg3_irq_sync(tp)))
  4295. napi_schedule(&tnapi->napi);
  4296. return IRQ_HANDLED;
  4297. }
  4298. /* MSI ISR - No need to check for interrupt sharing and no need to
  4299. * flush status block and interrupt mailbox. PCI ordering rules
  4300. * guarantee that MSI will arrive after the status block.
  4301. */
  4302. static irqreturn_t tg3_msi(int irq, void *dev_id)
  4303. {
  4304. struct tg3_napi *tnapi = dev_id;
  4305. struct tg3 *tp = tnapi->tp;
  4306. prefetch(tnapi->hw_status);
  4307. if (tnapi->rx_rcb)
  4308. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4309. /*
  4310. * Writing any value to intr-mbox-0 clears PCI INTA# and
  4311. * chip-internal interrupt pending events.
  4312. * Writing non-zero to intr-mbox-0 additional tells the
  4313. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4314. * event coalescing.
  4315. */
  4316. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4317. if (likely(!tg3_irq_sync(tp)))
  4318. napi_schedule(&tnapi->napi);
  4319. return IRQ_RETVAL(1);
  4320. }
  4321. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  4322. {
  4323. struct tg3_napi *tnapi = dev_id;
  4324. struct tg3 *tp = tnapi->tp;
  4325. struct tg3_hw_status *sblk = tnapi->hw_status;
  4326. unsigned int handled = 1;
  4327. /* In INTx mode, it is possible for the interrupt to arrive at
  4328. * the CPU before the status block posted prior to the interrupt.
  4329. * Reading the PCI State register will confirm whether the
  4330. * interrupt is ours and will flush the status block.
  4331. */
  4332. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  4333. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  4334. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4335. handled = 0;
  4336. goto out;
  4337. }
  4338. }
  4339. /*
  4340. * Writing any value to intr-mbox-0 clears PCI INTA# and
  4341. * chip-internal interrupt pending events.
  4342. * Writing non-zero to intr-mbox-0 additional tells the
  4343. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4344. * event coalescing.
  4345. *
  4346. * Flush the mailbox to de-assert the IRQ immediately to prevent
  4347. * spurious interrupts. The flush impacts performance but
  4348. * excessive spurious interrupts can be worse in some cases.
  4349. */
  4350. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4351. if (tg3_irq_sync(tp))
  4352. goto out;
  4353. sblk->status &= ~SD_STATUS_UPDATED;
  4354. if (likely(tg3_has_work(tnapi))) {
  4355. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4356. napi_schedule(&tnapi->napi);
  4357. } else {
  4358. /* No work, shared interrupt perhaps? re-enable
  4359. * interrupts, and flush that PCI write
  4360. */
  4361. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  4362. 0x00000000);
  4363. }
  4364. out:
  4365. return IRQ_RETVAL(handled);
  4366. }
  4367. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  4368. {
  4369. struct tg3_napi *tnapi = dev_id;
  4370. struct tg3 *tp = tnapi->tp;
  4371. struct tg3_hw_status *sblk = tnapi->hw_status;
  4372. unsigned int handled = 1;
  4373. /* In INTx mode, it is possible for the interrupt to arrive at
  4374. * the CPU before the status block posted prior to the interrupt.
  4375. * Reading the PCI State register will confirm whether the
  4376. * interrupt is ours and will flush the status block.
  4377. */
  4378. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  4379. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  4380. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4381. handled = 0;
  4382. goto out;
  4383. }
  4384. }
  4385. /*
  4386. * writing any value to intr-mbox-0 clears PCI INTA# and
  4387. * chip-internal interrupt pending events.
  4388. * writing non-zero to intr-mbox-0 additional tells the
  4389. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4390. * event coalescing.
  4391. *
  4392. * Flush the mailbox to de-assert the IRQ immediately to prevent
  4393. * spurious interrupts. The flush impacts performance but
  4394. * excessive spurious interrupts can be worse in some cases.
  4395. */
  4396. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4397. /*
  4398. * In a shared interrupt configuration, sometimes other devices'
  4399. * interrupts will scream. We record the current status tag here
  4400. * so that the above check can report that the screaming interrupts
  4401. * are unhandled. Eventually they will be silenced.
  4402. */
  4403. tnapi->last_irq_tag = sblk->status_tag;
  4404. if (tg3_irq_sync(tp))
  4405. goto out;
  4406. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4407. napi_schedule(&tnapi->napi);
  4408. out:
  4409. return IRQ_RETVAL(handled);
  4410. }
  4411. /* ISR for interrupt test */
  4412. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  4413. {
  4414. struct tg3_napi *tnapi = dev_id;
  4415. struct tg3 *tp = tnapi->tp;
  4416. struct tg3_hw_status *sblk = tnapi->hw_status;
  4417. if ((sblk->status & SD_STATUS_UPDATED) ||
  4418. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4419. tg3_disable_ints(tp);
  4420. return IRQ_RETVAL(1);
  4421. }
  4422. return IRQ_RETVAL(0);
  4423. }
  4424. static int tg3_init_hw(struct tg3 *, int);
  4425. static int tg3_halt(struct tg3 *, int, int);
  4426. /* Restart hardware after configuration changes, self-test, etc.
  4427. * Invoked with tp->lock held.
  4428. */
  4429. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  4430. __releases(tp->lock)
  4431. __acquires(tp->lock)
  4432. {
  4433. int err;
  4434. err = tg3_init_hw(tp, reset_phy);
  4435. if (err) {
  4436. netdev_err(tp->dev,
  4437. "Failed to re-initialize device, aborting\n");
  4438. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  4439. tg3_full_unlock(tp);
  4440. del_timer_sync(&tp->timer);
  4441. tp->irq_sync = 0;
  4442. tg3_napi_enable(tp);
  4443. dev_close(tp->dev);
  4444. tg3_full_lock(tp, 0);
  4445. }
  4446. return err;
  4447. }
  4448. #ifdef CONFIG_NET_POLL_CONTROLLER
  4449. static void tg3_poll_controller(struct net_device *dev)
  4450. {
  4451. int i;
  4452. struct tg3 *tp = netdev_priv(dev);
  4453. for (i = 0; i < tp->irq_cnt; i++)
  4454. tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
  4455. }
  4456. #endif
  4457. static void tg3_reset_task(struct work_struct *work)
  4458. {
  4459. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  4460. int err;
  4461. unsigned int restart_timer;
  4462. tg3_full_lock(tp, 0);
  4463. if (!netif_running(tp->dev)) {
  4464. tg3_full_unlock(tp);
  4465. return;
  4466. }
  4467. tg3_full_unlock(tp);
  4468. tg3_phy_stop(tp);
  4469. tg3_netif_stop(tp);
  4470. tg3_full_lock(tp, 1);
  4471. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  4472. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  4473. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  4474. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  4475. tp->write32_rx_mbox = tg3_write_flush_reg32;
  4476. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  4477. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  4478. }
  4479. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  4480. err = tg3_init_hw(tp, 1);
  4481. if (err)
  4482. goto out;
  4483. tg3_netif_start(tp);
  4484. if (restart_timer)
  4485. mod_timer(&tp->timer, jiffies + 1);
  4486. out:
  4487. tg3_full_unlock(tp);
  4488. if (!err)
  4489. tg3_phy_start(tp);
  4490. }
  4491. static void tg3_dump_short_state(struct tg3 *tp)
  4492. {
  4493. netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  4494. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  4495. netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  4496. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  4497. }
  4498. static void tg3_tx_timeout(struct net_device *dev)
  4499. {
  4500. struct tg3 *tp = netdev_priv(dev);
  4501. if (netif_msg_tx_err(tp)) {
  4502. netdev_err(dev, "transmit timed out, resetting\n");
  4503. tg3_dump_short_state(tp);
  4504. }
  4505. schedule_work(&tp->reset_task);
  4506. }
  4507. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  4508. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  4509. {
  4510. u32 base = (u32) mapping & 0xffffffff;
  4511. return ((base > 0xffffdcc0) &&
  4512. (base + len + 8 < base));
  4513. }
  4514. /* Test for DMA addresses > 40-bit */
  4515. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  4516. int len)
  4517. {
  4518. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  4519. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  4520. return (((u64) mapping + len) > DMA_BIT_MASK(40));
  4521. return 0;
  4522. #else
  4523. return 0;
  4524. #endif
  4525. }
  4526. static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
  4527. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  4528. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  4529. struct sk_buff *skb, u32 last_plus_one,
  4530. u32 *start, u32 base_flags, u32 mss)
  4531. {
  4532. struct tg3 *tp = tnapi->tp;
  4533. struct sk_buff *new_skb;
  4534. dma_addr_t new_addr = 0;
  4535. u32 entry = *start;
  4536. int i, ret = 0;
  4537. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  4538. new_skb = skb_copy(skb, GFP_ATOMIC);
  4539. else {
  4540. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  4541. new_skb = skb_copy_expand(skb,
  4542. skb_headroom(skb) + more_headroom,
  4543. skb_tailroom(skb), GFP_ATOMIC);
  4544. }
  4545. if (!new_skb) {
  4546. ret = -1;
  4547. } else {
  4548. /* New SKB is guaranteed to be linear. */
  4549. entry = *start;
  4550. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  4551. PCI_DMA_TODEVICE);
  4552. /* Make sure the mapping succeeded */
  4553. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  4554. ret = -1;
  4555. dev_kfree_skb(new_skb);
  4556. new_skb = NULL;
  4557. /* Make sure new skb does not cross any 4G boundaries.
  4558. * Drop the packet if it does.
  4559. */
  4560. } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4561. tg3_4g_overflow_test(new_addr, new_skb->len)) {
  4562. pci_unmap_single(tp->pdev, new_addr, new_skb->len,
  4563. PCI_DMA_TODEVICE);
  4564. ret = -1;
  4565. dev_kfree_skb(new_skb);
  4566. new_skb = NULL;
  4567. } else {
  4568. tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
  4569. base_flags, 1 | (mss << 1));
  4570. *start = NEXT_TX(entry);
  4571. }
  4572. }
  4573. /* Now clean up the sw ring entries. */
  4574. i = 0;
  4575. while (entry != last_plus_one) {
  4576. int len;
  4577. if (i == 0)
  4578. len = skb_headlen(skb);
  4579. else
  4580. len = skb_shinfo(skb)->frags[i-1].size;
  4581. pci_unmap_single(tp->pdev,
  4582. dma_unmap_addr(&tnapi->tx_buffers[entry],
  4583. mapping),
  4584. len, PCI_DMA_TODEVICE);
  4585. if (i == 0) {
  4586. tnapi->tx_buffers[entry].skb = new_skb;
  4587. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4588. new_addr);
  4589. } else {
  4590. tnapi->tx_buffers[entry].skb = NULL;
  4591. }
  4592. entry = NEXT_TX(entry);
  4593. i++;
  4594. }
  4595. dev_kfree_skb(skb);
  4596. return ret;
  4597. }
  4598. static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
  4599. dma_addr_t mapping, int len, u32 flags,
  4600. u32 mss_and_is_end)
  4601. {
  4602. struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
  4603. int is_end = (mss_and_is_end & 0x1);
  4604. u32 mss = (mss_and_is_end >> 1);
  4605. u32 vlan_tag = 0;
  4606. if (is_end)
  4607. flags |= TXD_FLAG_END;
  4608. if (flags & TXD_FLAG_VLAN) {
  4609. vlan_tag = flags >> 16;
  4610. flags &= 0xffff;
  4611. }
  4612. vlan_tag |= (mss << TXD_MSS_SHIFT);
  4613. txd->addr_hi = ((u64) mapping >> 32);
  4614. txd->addr_lo = ((u64) mapping & 0xffffffff);
  4615. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  4616. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  4617. }
  4618. /* hard_start_xmit for devices that don't have any bugs and
  4619. * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
  4620. */
  4621. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
  4622. struct net_device *dev)
  4623. {
  4624. struct tg3 *tp = netdev_priv(dev);
  4625. u32 len, entry, base_flags, mss;
  4626. dma_addr_t mapping;
  4627. struct tg3_napi *tnapi;
  4628. struct netdev_queue *txq;
  4629. unsigned int i, last;
  4630. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  4631. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  4632. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  4633. tnapi++;
  4634. /* We are running in BH disabled context with netif_tx_lock
  4635. * and TX reclaim runs via tp->napi.poll inside of a software
  4636. * interrupt. Furthermore, IRQ processing runs lockless so we have
  4637. * no IRQ context deadlocks to worry about either. Rejoice!
  4638. */
  4639. if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
  4640. if (!netif_tx_queue_stopped(txq)) {
  4641. netif_tx_stop_queue(txq);
  4642. /* This is a hard error, log it. */
  4643. netdev_err(dev,
  4644. "BUG! Tx Ring full when queue awake!\n");
  4645. }
  4646. return NETDEV_TX_BUSY;
  4647. }
  4648. entry = tnapi->tx_prod;
  4649. base_flags = 0;
  4650. mss = skb_shinfo(skb)->gso_size;
  4651. if (mss) {
  4652. int tcp_opt_len, ip_tcp_len;
  4653. u32 hdrlen;
  4654. if (skb_header_cloned(skb) &&
  4655. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4656. dev_kfree_skb(skb);
  4657. goto out_unlock;
  4658. }
  4659. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  4660. hdrlen = skb_headlen(skb) - ETH_HLEN;
  4661. else {
  4662. struct iphdr *iph = ip_hdr(skb);
  4663. tcp_opt_len = tcp_optlen(skb);
  4664. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4665. iph->check = 0;
  4666. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  4667. hdrlen = ip_tcp_len + tcp_opt_len;
  4668. }
  4669. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
  4670. mss |= (hdrlen & 0xc) << 12;
  4671. if (hdrlen & 0x10)
  4672. base_flags |= 0x00000010;
  4673. base_flags |= (hdrlen & 0x3e0) << 5;
  4674. } else
  4675. mss |= hdrlen << 9;
  4676. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  4677. TXD_FLAG_CPU_POST_DMA);
  4678. tcp_hdr(skb)->check = 0;
  4679. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  4680. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  4681. }
  4682. #if TG3_VLAN_TAG_USED
  4683. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  4684. base_flags |= (TXD_FLAG_VLAN |
  4685. (vlan_tx_tag_get(skb) << 16));
  4686. #endif
  4687. len = skb_headlen(skb);
  4688. /* Queue skb data, a.k.a. the main skb fragment. */
  4689. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4690. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  4691. dev_kfree_skb(skb);
  4692. goto out_unlock;
  4693. }
  4694. tnapi->tx_buffers[entry].skb = skb;
  4695. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  4696. if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
  4697. !mss && skb->len > ETH_DATA_LEN)
  4698. base_flags |= TXD_FLAG_JMB_PKT;
  4699. tg3_set_txd(tnapi, entry, mapping, len, base_flags,
  4700. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4701. entry = NEXT_TX(entry);
  4702. /* Now loop through additional data fragments, and queue them. */
  4703. if (skb_shinfo(skb)->nr_frags > 0) {
  4704. last = skb_shinfo(skb)->nr_frags - 1;
  4705. for (i = 0; i <= last; i++) {
  4706. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4707. len = frag->size;
  4708. mapping = pci_map_page(tp->pdev,
  4709. frag->page,
  4710. frag->page_offset,
  4711. len, PCI_DMA_TODEVICE);
  4712. if (pci_dma_mapping_error(tp->pdev, mapping))
  4713. goto dma_error;
  4714. tnapi->tx_buffers[entry].skb = NULL;
  4715. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4716. mapping);
  4717. tg3_set_txd(tnapi, entry, mapping, len,
  4718. base_flags, (i == last) | (mss << 1));
  4719. entry = NEXT_TX(entry);
  4720. }
  4721. }
  4722. /* Packets are ready, update Tx producer idx local and on card. */
  4723. tw32_tx_mbox(tnapi->prodmbox, entry);
  4724. tnapi->tx_prod = entry;
  4725. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  4726. netif_tx_stop_queue(txq);
  4727. /* netif_tx_stop_queue() must be done before checking
  4728. * checking tx index in tg3_tx_avail() below, because in
  4729. * tg3_tx(), we update tx index before checking for
  4730. * netif_tx_queue_stopped().
  4731. */
  4732. smp_mb();
  4733. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  4734. netif_tx_wake_queue(txq);
  4735. }
  4736. out_unlock:
  4737. mmiowb();
  4738. return NETDEV_TX_OK;
  4739. dma_error:
  4740. last = i;
  4741. entry = tnapi->tx_prod;
  4742. tnapi->tx_buffers[entry].skb = NULL;
  4743. pci_unmap_single(tp->pdev,
  4744. dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
  4745. skb_headlen(skb),
  4746. PCI_DMA_TODEVICE);
  4747. for (i = 0; i <= last; i++) {
  4748. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4749. entry = NEXT_TX(entry);
  4750. pci_unmap_page(tp->pdev,
  4751. dma_unmap_addr(&tnapi->tx_buffers[entry],
  4752. mapping),
  4753. frag->size, PCI_DMA_TODEVICE);
  4754. }
  4755. dev_kfree_skb(skb);
  4756. return NETDEV_TX_OK;
  4757. }
  4758. static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
  4759. struct net_device *);
  4760. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  4761. * TSO header is greater than 80 bytes.
  4762. */
  4763. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  4764. {
  4765. struct sk_buff *segs, *nskb;
  4766. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  4767. /* Estimate the number of fragments in the worst case */
  4768. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  4769. netif_stop_queue(tp->dev);
  4770. /* netif_tx_stop_queue() must be done before checking
  4771. * checking tx index in tg3_tx_avail() below, because in
  4772. * tg3_tx(), we update tx index before checking for
  4773. * netif_tx_queue_stopped().
  4774. */
  4775. smp_mb();
  4776. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  4777. return NETDEV_TX_BUSY;
  4778. netif_wake_queue(tp->dev);
  4779. }
  4780. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  4781. if (IS_ERR(segs))
  4782. goto tg3_tso_bug_end;
  4783. do {
  4784. nskb = segs;
  4785. segs = segs->next;
  4786. nskb->next = NULL;
  4787. tg3_start_xmit_dma_bug(nskb, tp->dev);
  4788. } while (segs);
  4789. tg3_tso_bug_end:
  4790. dev_kfree_skb(skb);
  4791. return NETDEV_TX_OK;
  4792. }
  4793. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  4794. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  4795. */
  4796. static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
  4797. struct net_device *dev)
  4798. {
  4799. struct tg3 *tp = netdev_priv(dev);
  4800. u32 len, entry, base_flags, mss;
  4801. int would_hit_hwbug;
  4802. dma_addr_t mapping;
  4803. struct tg3_napi *tnapi;
  4804. struct netdev_queue *txq;
  4805. unsigned int i, last;
  4806. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  4807. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  4808. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  4809. tnapi++;
  4810. /* We are running in BH disabled context with netif_tx_lock
  4811. * and TX reclaim runs via tp->napi.poll inside of a software
  4812. * interrupt. Furthermore, IRQ processing runs lockless so we have
  4813. * no IRQ context deadlocks to worry about either. Rejoice!
  4814. */
  4815. if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
  4816. if (!netif_tx_queue_stopped(txq)) {
  4817. netif_tx_stop_queue(txq);
  4818. /* This is a hard error, log it. */
  4819. netdev_err(dev,
  4820. "BUG! Tx Ring full when queue awake!\n");
  4821. }
  4822. return NETDEV_TX_BUSY;
  4823. }
  4824. entry = tnapi->tx_prod;
  4825. base_flags = 0;
  4826. if (skb->ip_summed == CHECKSUM_PARTIAL)
  4827. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  4828. mss = skb_shinfo(skb)->gso_size;
  4829. if (mss) {
  4830. struct iphdr *iph;
  4831. u32 tcp_opt_len, hdr_len;
  4832. if (skb_header_cloned(skb) &&
  4833. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4834. dev_kfree_skb(skb);
  4835. goto out_unlock;
  4836. }
  4837. iph = ip_hdr(skb);
  4838. tcp_opt_len = tcp_optlen(skb);
  4839. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
  4840. hdr_len = skb_headlen(skb) - ETH_HLEN;
  4841. } else {
  4842. u32 ip_tcp_len;
  4843. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4844. hdr_len = ip_tcp_len + tcp_opt_len;
  4845. iph->check = 0;
  4846. iph->tot_len = htons(mss + hdr_len);
  4847. }
  4848. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  4849. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  4850. return tg3_tso_bug(tp, skb);
  4851. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  4852. TXD_FLAG_CPU_POST_DMA);
  4853. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  4854. tcp_hdr(skb)->check = 0;
  4855. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  4856. } else
  4857. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  4858. iph->daddr, 0,
  4859. IPPROTO_TCP,
  4860. 0);
  4861. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
  4862. mss |= (hdr_len & 0xc) << 12;
  4863. if (hdr_len & 0x10)
  4864. base_flags |= 0x00000010;
  4865. base_flags |= (hdr_len & 0x3e0) << 5;
  4866. } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
  4867. mss |= hdr_len << 9;
  4868. else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
  4869. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4870. if (tcp_opt_len || iph->ihl > 5) {
  4871. int tsflags;
  4872. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4873. mss |= (tsflags << 11);
  4874. }
  4875. } else {
  4876. if (tcp_opt_len || iph->ihl > 5) {
  4877. int tsflags;
  4878. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4879. base_flags |= tsflags << 12;
  4880. }
  4881. }
  4882. }
  4883. #if TG3_VLAN_TAG_USED
  4884. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  4885. base_flags |= (TXD_FLAG_VLAN |
  4886. (vlan_tx_tag_get(skb) << 16));
  4887. #endif
  4888. if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
  4889. !mss && skb->len > ETH_DATA_LEN)
  4890. base_flags |= TXD_FLAG_JMB_PKT;
  4891. len = skb_headlen(skb);
  4892. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4893. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  4894. dev_kfree_skb(skb);
  4895. goto out_unlock;
  4896. }
  4897. tnapi->tx_buffers[entry].skb = skb;
  4898. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  4899. would_hit_hwbug = 0;
  4900. if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
  4901. would_hit_hwbug = 1;
  4902. if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4903. tg3_4g_overflow_test(mapping, len))
  4904. would_hit_hwbug = 1;
  4905. if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
  4906. tg3_40bit_overflow_test(tp, mapping, len))
  4907. would_hit_hwbug = 1;
  4908. if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
  4909. would_hit_hwbug = 1;
  4910. tg3_set_txd(tnapi, entry, mapping, len, base_flags,
  4911. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4912. entry = NEXT_TX(entry);
  4913. /* Now loop through additional data fragments, and queue them. */
  4914. if (skb_shinfo(skb)->nr_frags > 0) {
  4915. last = skb_shinfo(skb)->nr_frags - 1;
  4916. for (i = 0; i <= last; i++) {
  4917. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4918. len = frag->size;
  4919. mapping = pci_map_page(tp->pdev,
  4920. frag->page,
  4921. frag->page_offset,
  4922. len, PCI_DMA_TODEVICE);
  4923. tnapi->tx_buffers[entry].skb = NULL;
  4924. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4925. mapping);
  4926. if (pci_dma_mapping_error(tp->pdev, mapping))
  4927. goto dma_error;
  4928. if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
  4929. len <= 8)
  4930. would_hit_hwbug = 1;
  4931. if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4932. tg3_4g_overflow_test(mapping, len))
  4933. would_hit_hwbug = 1;
  4934. if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
  4935. tg3_40bit_overflow_test(tp, mapping, len))
  4936. would_hit_hwbug = 1;
  4937. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  4938. tg3_set_txd(tnapi, entry, mapping, len,
  4939. base_flags, (i == last)|(mss << 1));
  4940. else
  4941. tg3_set_txd(tnapi, entry, mapping, len,
  4942. base_flags, (i == last));
  4943. entry = NEXT_TX(entry);
  4944. }
  4945. }
  4946. if (would_hit_hwbug) {
  4947. u32 last_plus_one = entry;
  4948. u32 start;
  4949. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  4950. start &= (TG3_TX_RING_SIZE - 1);
  4951. /* If the workaround fails due to memory/mapping
  4952. * failure, silently drop this packet.
  4953. */
  4954. if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
  4955. &start, base_flags, mss))
  4956. goto out_unlock;
  4957. entry = start;
  4958. }
  4959. /* Packets are ready, update Tx producer idx local and on card. */
  4960. tw32_tx_mbox(tnapi->prodmbox, entry);
  4961. tnapi->tx_prod = entry;
  4962. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  4963. netif_tx_stop_queue(txq);
  4964. /* netif_tx_stop_queue() must be done before checking
  4965. * checking tx index in tg3_tx_avail() below, because in
  4966. * tg3_tx(), we update tx index before checking for
  4967. * netif_tx_queue_stopped().
  4968. */
  4969. smp_mb();
  4970. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  4971. netif_tx_wake_queue(txq);
  4972. }
  4973. out_unlock:
  4974. mmiowb();
  4975. return NETDEV_TX_OK;
  4976. dma_error:
  4977. last = i;
  4978. entry = tnapi->tx_prod;
  4979. tnapi->tx_buffers[entry].skb = NULL;
  4980. pci_unmap_single(tp->pdev,
  4981. dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
  4982. skb_headlen(skb),
  4983. PCI_DMA_TODEVICE);
  4984. for (i = 0; i <= last; i++) {
  4985. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4986. entry = NEXT_TX(entry);
  4987. pci_unmap_page(tp->pdev,
  4988. dma_unmap_addr(&tnapi->tx_buffers[entry],
  4989. mapping),
  4990. frag->size, PCI_DMA_TODEVICE);
  4991. }
  4992. dev_kfree_skb(skb);
  4993. return NETDEV_TX_OK;
  4994. }
  4995. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  4996. int new_mtu)
  4997. {
  4998. dev->mtu = new_mtu;
  4999. if (new_mtu > ETH_DATA_LEN) {
  5000. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  5001. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  5002. ethtool_op_set_tso(dev, 0);
  5003. } else {
  5004. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  5005. }
  5006. } else {
  5007. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  5008. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  5009. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  5010. }
  5011. }
  5012. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  5013. {
  5014. struct tg3 *tp = netdev_priv(dev);
  5015. int err;
  5016. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  5017. return -EINVAL;
  5018. if (!netif_running(dev)) {
  5019. /* We'll just catch it later when the
  5020. * device is up'd.
  5021. */
  5022. tg3_set_mtu(dev, tp, new_mtu);
  5023. return 0;
  5024. }
  5025. tg3_phy_stop(tp);
  5026. tg3_netif_stop(tp);
  5027. tg3_full_lock(tp, 1);
  5028. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  5029. tg3_set_mtu(dev, tp, new_mtu);
  5030. err = tg3_restart_hw(tp, 0);
  5031. if (!err)
  5032. tg3_netif_start(tp);
  5033. tg3_full_unlock(tp);
  5034. if (!err)
  5035. tg3_phy_start(tp);
  5036. return err;
  5037. }
  5038. static void tg3_rx_prodring_free(struct tg3 *tp,
  5039. struct tg3_rx_prodring_set *tpr)
  5040. {
  5041. int i;
  5042. if (tpr != &tp->prodring[0]) {
  5043. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  5044. i = (i + 1) % TG3_RX_RING_SIZE)
  5045. tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
  5046. tp->rx_pkt_map_sz);
  5047. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  5048. for (i = tpr->rx_jmb_cons_idx;
  5049. i != tpr->rx_jmb_prod_idx;
  5050. i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
  5051. tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
  5052. TG3_RX_JMB_MAP_SZ);
  5053. }
  5054. }
  5055. return;
  5056. }
  5057. for (i = 0; i < TG3_RX_RING_SIZE; i++)
  5058. tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
  5059. tp->rx_pkt_map_sz);
  5060. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  5061. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
  5062. tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
  5063. TG3_RX_JMB_MAP_SZ);
  5064. }
  5065. }
  5066. /* Initialize rx rings for packet processing.
  5067. *
  5068. * The chip has been shut down and the driver detached from
  5069. * the networking, so no interrupts or new tx packets will
  5070. * end up in the driver. tp->{tx,}lock are held and thus
  5071. * we may not sleep.
  5072. */
  5073. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  5074. struct tg3_rx_prodring_set *tpr)
  5075. {
  5076. u32 i, rx_pkt_dma_sz;
  5077. tpr->rx_std_cons_idx = 0;
  5078. tpr->rx_std_prod_idx = 0;
  5079. tpr->rx_jmb_cons_idx = 0;
  5080. tpr->rx_jmb_prod_idx = 0;
  5081. if (tpr != &tp->prodring[0]) {
  5082. memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
  5083. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
  5084. memset(&tpr->rx_jmb_buffers[0], 0,
  5085. TG3_RX_JMB_BUFF_RING_SIZE);
  5086. goto done;
  5087. }
  5088. /* Zero out all descriptors. */
  5089. memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
  5090. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  5091. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  5092. tp->dev->mtu > ETH_DATA_LEN)
  5093. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  5094. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  5095. /* Initialize invariants of the rings, we only set this
  5096. * stuff once. This works because the card does not
  5097. * write into the rx buffer posting rings.
  5098. */
  5099. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  5100. struct tg3_rx_buffer_desc *rxd;
  5101. rxd = &tpr->rx_std[i];
  5102. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  5103. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  5104. rxd->opaque = (RXD_OPAQUE_RING_STD |
  5105. (i << RXD_OPAQUE_INDEX_SHIFT));
  5106. }
  5107. /* Now allocate fresh SKBs for each rx ring. */
  5108. for (i = 0; i < tp->rx_pending; i++) {
  5109. if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
  5110. netdev_warn(tp->dev,
  5111. "Using a smaller RX standard ring. Only "
  5112. "%d out of %d buffers were allocated "
  5113. "successfully\n", i, tp->rx_pending);
  5114. if (i == 0)
  5115. goto initfail;
  5116. tp->rx_pending = i;
  5117. break;
  5118. }
  5119. }
  5120. if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
  5121. goto done;
  5122. memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
  5123. if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
  5124. goto done;
  5125. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  5126. struct tg3_rx_buffer_desc *rxd;
  5127. rxd = &tpr->rx_jmb[i].std;
  5128. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  5129. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  5130. RXD_FLAG_JUMBO;
  5131. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  5132. (i << RXD_OPAQUE_INDEX_SHIFT));
  5133. }
  5134. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  5135. if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
  5136. netdev_warn(tp->dev,
  5137. "Using a smaller RX jumbo ring. Only %d "
  5138. "out of %d buffers were allocated "
  5139. "successfully\n", i, tp->rx_jumbo_pending);
  5140. if (i == 0)
  5141. goto initfail;
  5142. tp->rx_jumbo_pending = i;
  5143. break;
  5144. }
  5145. }
  5146. done:
  5147. return 0;
  5148. initfail:
  5149. tg3_rx_prodring_free(tp, tpr);
  5150. return -ENOMEM;
  5151. }
  5152. static void tg3_rx_prodring_fini(struct tg3 *tp,
  5153. struct tg3_rx_prodring_set *tpr)
  5154. {
  5155. kfree(tpr->rx_std_buffers);
  5156. tpr->rx_std_buffers = NULL;
  5157. kfree(tpr->rx_jmb_buffers);
  5158. tpr->rx_jmb_buffers = NULL;
  5159. if (tpr->rx_std) {
  5160. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  5161. tpr->rx_std, tpr->rx_std_mapping);
  5162. tpr->rx_std = NULL;
  5163. }
  5164. if (tpr->rx_jmb) {
  5165. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  5166. tpr->rx_jmb, tpr->rx_jmb_mapping);
  5167. tpr->rx_jmb = NULL;
  5168. }
  5169. }
  5170. static int tg3_rx_prodring_init(struct tg3 *tp,
  5171. struct tg3_rx_prodring_set *tpr)
  5172. {
  5173. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
  5174. if (!tpr->rx_std_buffers)
  5175. return -ENOMEM;
  5176. tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  5177. &tpr->rx_std_mapping);
  5178. if (!tpr->rx_std)
  5179. goto err_out;
  5180. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  5181. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
  5182. GFP_KERNEL);
  5183. if (!tpr->rx_jmb_buffers)
  5184. goto err_out;
  5185. tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
  5186. TG3_RX_JUMBO_RING_BYTES,
  5187. &tpr->rx_jmb_mapping);
  5188. if (!tpr->rx_jmb)
  5189. goto err_out;
  5190. }
  5191. return 0;
  5192. err_out:
  5193. tg3_rx_prodring_fini(tp, tpr);
  5194. return -ENOMEM;
  5195. }
  5196. /* Free up pending packets in all rx/tx rings.
  5197. *
  5198. * The chip has been shut down and the driver detached from
  5199. * the networking, so no interrupts or new tx packets will
  5200. * end up in the driver. tp->{tx,}lock is not held and we are not
  5201. * in an interrupt context and thus may sleep.
  5202. */
  5203. static void tg3_free_rings(struct tg3 *tp)
  5204. {
  5205. int i, j;
  5206. for (j = 0; j < tp->irq_cnt; j++) {
  5207. struct tg3_napi *tnapi = &tp->napi[j];
  5208. tg3_rx_prodring_free(tp, &tp->prodring[j]);
  5209. if (!tnapi->tx_buffers)
  5210. continue;
  5211. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  5212. struct ring_info *txp;
  5213. struct sk_buff *skb;
  5214. unsigned int k;
  5215. txp = &tnapi->tx_buffers[i];
  5216. skb = txp->skb;
  5217. if (skb == NULL) {
  5218. i++;
  5219. continue;
  5220. }
  5221. pci_unmap_single(tp->pdev,
  5222. dma_unmap_addr(txp, mapping),
  5223. skb_headlen(skb),
  5224. PCI_DMA_TODEVICE);
  5225. txp->skb = NULL;
  5226. i++;
  5227. for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
  5228. txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  5229. pci_unmap_page(tp->pdev,
  5230. dma_unmap_addr(txp, mapping),
  5231. skb_shinfo(skb)->frags[k].size,
  5232. PCI_DMA_TODEVICE);
  5233. i++;
  5234. }
  5235. dev_kfree_skb_any(skb);
  5236. }
  5237. }
  5238. }
  5239. /* Initialize tx/rx rings for packet processing.
  5240. *
  5241. * The chip has been shut down and the driver detached from
  5242. * the networking, so no interrupts or new tx packets will
  5243. * end up in the driver. tp->{tx,}lock are held and thus
  5244. * we may not sleep.
  5245. */
  5246. static int tg3_init_rings(struct tg3 *tp)
  5247. {
  5248. int i;
  5249. /* Free up all the SKBs. */
  5250. tg3_free_rings(tp);
  5251. for (i = 0; i < tp->irq_cnt; i++) {
  5252. struct tg3_napi *tnapi = &tp->napi[i];
  5253. tnapi->last_tag = 0;
  5254. tnapi->last_irq_tag = 0;
  5255. tnapi->hw_status->status = 0;
  5256. tnapi->hw_status->status_tag = 0;
  5257. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5258. tnapi->tx_prod = 0;
  5259. tnapi->tx_cons = 0;
  5260. if (tnapi->tx_ring)
  5261. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  5262. tnapi->rx_rcb_ptr = 0;
  5263. if (tnapi->rx_rcb)
  5264. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  5265. if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
  5266. tg3_free_rings(tp);
  5267. return -ENOMEM;
  5268. }
  5269. }
  5270. return 0;
  5271. }
  5272. /*
  5273. * Must not be invoked with interrupt sources disabled and
  5274. * the hardware shutdown down.
  5275. */
  5276. static void tg3_free_consistent(struct tg3 *tp)
  5277. {
  5278. int i;
  5279. for (i = 0; i < tp->irq_cnt; i++) {
  5280. struct tg3_napi *tnapi = &tp->napi[i];
  5281. if (tnapi->tx_ring) {
  5282. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  5283. tnapi->tx_ring, tnapi->tx_desc_mapping);
  5284. tnapi->tx_ring = NULL;
  5285. }
  5286. kfree(tnapi->tx_buffers);
  5287. tnapi->tx_buffers = NULL;
  5288. if (tnapi->rx_rcb) {
  5289. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  5290. tnapi->rx_rcb,
  5291. tnapi->rx_rcb_mapping);
  5292. tnapi->rx_rcb = NULL;
  5293. }
  5294. if (tnapi->hw_status) {
  5295. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  5296. tnapi->hw_status,
  5297. tnapi->status_mapping);
  5298. tnapi->hw_status = NULL;
  5299. }
  5300. }
  5301. if (tp->hw_stats) {
  5302. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  5303. tp->hw_stats, tp->stats_mapping);
  5304. tp->hw_stats = NULL;
  5305. }
  5306. for (i = 0; i < tp->irq_cnt; i++)
  5307. tg3_rx_prodring_fini(tp, &tp->prodring[i]);
  5308. }
  5309. /*
  5310. * Must not be invoked with interrupt sources disabled and
  5311. * the hardware shutdown down. Can sleep.
  5312. */
  5313. static int tg3_alloc_consistent(struct tg3 *tp)
  5314. {
  5315. int i;
  5316. for (i = 0; i < tp->irq_cnt; i++) {
  5317. if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
  5318. goto err_out;
  5319. }
  5320. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  5321. sizeof(struct tg3_hw_stats),
  5322. &tp->stats_mapping);
  5323. if (!tp->hw_stats)
  5324. goto err_out;
  5325. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  5326. for (i = 0; i < tp->irq_cnt; i++) {
  5327. struct tg3_napi *tnapi = &tp->napi[i];
  5328. struct tg3_hw_status *sblk;
  5329. tnapi->hw_status = pci_alloc_consistent(tp->pdev,
  5330. TG3_HW_STATUS_SIZE,
  5331. &tnapi->status_mapping);
  5332. if (!tnapi->hw_status)
  5333. goto err_out;
  5334. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5335. sblk = tnapi->hw_status;
  5336. /* If multivector TSS is enabled, vector 0 does not handle
  5337. * tx interrupts. Don't allocate any resources for it.
  5338. */
  5339. if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
  5340. (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
  5341. tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
  5342. TG3_TX_RING_SIZE,
  5343. GFP_KERNEL);
  5344. if (!tnapi->tx_buffers)
  5345. goto err_out;
  5346. tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
  5347. TG3_TX_RING_BYTES,
  5348. &tnapi->tx_desc_mapping);
  5349. if (!tnapi->tx_ring)
  5350. goto err_out;
  5351. }
  5352. /*
  5353. * When RSS is enabled, the status block format changes
  5354. * slightly. The "rx_jumbo_consumer", "reserved",
  5355. * and "rx_mini_consumer" members get mapped to the
  5356. * other three rx return ring producer indexes.
  5357. */
  5358. switch (i) {
  5359. default:
  5360. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  5361. break;
  5362. case 2:
  5363. tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
  5364. break;
  5365. case 3:
  5366. tnapi->rx_rcb_prod_idx = &sblk->reserved;
  5367. break;
  5368. case 4:
  5369. tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
  5370. break;
  5371. }
  5372. tnapi->prodring = &tp->prodring[i];
  5373. /*
  5374. * If multivector RSS is enabled, vector 0 does not handle
  5375. * rx or tx interrupts. Don't allocate any resources for it.
  5376. */
  5377. if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
  5378. continue;
  5379. tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
  5380. TG3_RX_RCB_RING_BYTES(tp),
  5381. &tnapi->rx_rcb_mapping);
  5382. if (!tnapi->rx_rcb)
  5383. goto err_out;
  5384. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  5385. }
  5386. return 0;
  5387. err_out:
  5388. tg3_free_consistent(tp);
  5389. return -ENOMEM;
  5390. }
  5391. #define MAX_WAIT_CNT 1000
  5392. /* To stop a block, clear the enable bit and poll till it
  5393. * clears. tp->lock is held.
  5394. */
  5395. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  5396. {
  5397. unsigned int i;
  5398. u32 val;
  5399. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5400. switch (ofs) {
  5401. case RCVLSC_MODE:
  5402. case DMAC_MODE:
  5403. case MBFREE_MODE:
  5404. case BUFMGR_MODE:
  5405. case MEMARB_MODE:
  5406. /* We can't enable/disable these bits of the
  5407. * 5705/5750, just say success.
  5408. */
  5409. return 0;
  5410. default:
  5411. break;
  5412. }
  5413. }
  5414. val = tr32(ofs);
  5415. val &= ~enable_bit;
  5416. tw32_f(ofs, val);
  5417. for (i = 0; i < MAX_WAIT_CNT; i++) {
  5418. udelay(100);
  5419. val = tr32(ofs);
  5420. if ((val & enable_bit) == 0)
  5421. break;
  5422. }
  5423. if (i == MAX_WAIT_CNT && !silent) {
  5424. dev_err(&tp->pdev->dev,
  5425. "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
  5426. ofs, enable_bit);
  5427. return -ENODEV;
  5428. }
  5429. return 0;
  5430. }
  5431. /* tp->lock is held. */
  5432. static int tg3_abort_hw(struct tg3 *tp, int silent)
  5433. {
  5434. int i, err;
  5435. tg3_disable_ints(tp);
  5436. tp->rx_mode &= ~RX_MODE_ENABLE;
  5437. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5438. udelay(10);
  5439. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  5440. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  5441. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  5442. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  5443. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  5444. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  5445. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  5446. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  5447. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  5448. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  5449. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  5450. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  5451. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  5452. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  5453. tw32_f(MAC_MODE, tp->mac_mode);
  5454. udelay(40);
  5455. tp->tx_mode &= ~TX_MODE_ENABLE;
  5456. tw32_f(MAC_TX_MODE, tp->tx_mode);
  5457. for (i = 0; i < MAX_WAIT_CNT; i++) {
  5458. udelay(100);
  5459. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  5460. break;
  5461. }
  5462. if (i >= MAX_WAIT_CNT) {
  5463. dev_err(&tp->pdev->dev,
  5464. "%s timed out, TX_MODE_ENABLE will not clear "
  5465. "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
  5466. err |= -ENODEV;
  5467. }
  5468. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  5469. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  5470. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  5471. tw32(FTQ_RESET, 0xffffffff);
  5472. tw32(FTQ_RESET, 0x00000000);
  5473. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  5474. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  5475. for (i = 0; i < tp->irq_cnt; i++) {
  5476. struct tg3_napi *tnapi = &tp->napi[i];
  5477. if (tnapi->hw_status)
  5478. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5479. }
  5480. if (tp->hw_stats)
  5481. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  5482. return err;
  5483. }
  5484. static void tg3_ape_send_event(struct tg3 *tp, u32 event)
  5485. {
  5486. int i;
  5487. u32 apedata;
  5488. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  5489. if (apedata != APE_SEG_SIG_MAGIC)
  5490. return;
  5491. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  5492. if (!(apedata & APE_FW_STATUS_READY))
  5493. return;
  5494. /* Wait for up to 1 millisecond for APE to service previous event. */
  5495. for (i = 0; i < 10; i++) {
  5496. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  5497. return;
  5498. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  5499. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5500. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  5501. event | APE_EVENT_STATUS_EVENT_PENDING);
  5502. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  5503. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5504. break;
  5505. udelay(100);
  5506. }
  5507. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5508. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  5509. }
  5510. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  5511. {
  5512. u32 event;
  5513. u32 apedata;
  5514. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  5515. return;
  5516. switch (kind) {
  5517. case RESET_KIND_INIT:
  5518. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  5519. APE_HOST_SEG_SIG_MAGIC);
  5520. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  5521. APE_HOST_SEG_LEN_MAGIC);
  5522. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  5523. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  5524. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  5525. APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
  5526. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  5527. APE_HOST_BEHAV_NO_PHYLOCK);
  5528. event = APE_EVENT_STATUS_STATE_START;
  5529. break;
  5530. case RESET_KIND_SHUTDOWN:
  5531. /* With the interface we are currently using,
  5532. * APE does not track driver state. Wiping
  5533. * out the HOST SEGMENT SIGNATURE forces
  5534. * the APE to assume OS absent status.
  5535. */
  5536. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  5537. event = APE_EVENT_STATUS_STATE_UNLOAD;
  5538. break;
  5539. case RESET_KIND_SUSPEND:
  5540. event = APE_EVENT_STATUS_STATE_SUSPEND;
  5541. break;
  5542. default:
  5543. return;
  5544. }
  5545. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  5546. tg3_ape_send_event(tp, event);
  5547. }
  5548. /* tp->lock is held. */
  5549. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  5550. {
  5551. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  5552. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  5553. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  5554. switch (kind) {
  5555. case RESET_KIND_INIT:
  5556. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5557. DRV_STATE_START);
  5558. break;
  5559. case RESET_KIND_SHUTDOWN:
  5560. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5561. DRV_STATE_UNLOAD);
  5562. break;
  5563. case RESET_KIND_SUSPEND:
  5564. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5565. DRV_STATE_SUSPEND);
  5566. break;
  5567. default:
  5568. break;
  5569. }
  5570. }
  5571. if (kind == RESET_KIND_INIT ||
  5572. kind == RESET_KIND_SUSPEND)
  5573. tg3_ape_driver_state_change(tp, kind);
  5574. }
  5575. /* tp->lock is held. */
  5576. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  5577. {
  5578. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  5579. switch (kind) {
  5580. case RESET_KIND_INIT:
  5581. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5582. DRV_STATE_START_DONE);
  5583. break;
  5584. case RESET_KIND_SHUTDOWN:
  5585. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5586. DRV_STATE_UNLOAD_DONE);
  5587. break;
  5588. default:
  5589. break;
  5590. }
  5591. }
  5592. if (kind == RESET_KIND_SHUTDOWN)
  5593. tg3_ape_driver_state_change(tp, kind);
  5594. }
  5595. /* tp->lock is held. */
  5596. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  5597. {
  5598. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5599. switch (kind) {
  5600. case RESET_KIND_INIT:
  5601. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5602. DRV_STATE_START);
  5603. break;
  5604. case RESET_KIND_SHUTDOWN:
  5605. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5606. DRV_STATE_UNLOAD);
  5607. break;
  5608. case RESET_KIND_SUSPEND:
  5609. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5610. DRV_STATE_SUSPEND);
  5611. break;
  5612. default:
  5613. break;
  5614. }
  5615. }
  5616. }
  5617. static int tg3_poll_fw(struct tg3 *tp)
  5618. {
  5619. int i;
  5620. u32 val;
  5621. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5622. /* Wait up to 20ms for init done. */
  5623. for (i = 0; i < 200; i++) {
  5624. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  5625. return 0;
  5626. udelay(100);
  5627. }
  5628. return -ENODEV;
  5629. }
  5630. /* Wait for firmware initialization to complete. */
  5631. for (i = 0; i < 100000; i++) {
  5632. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  5633. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  5634. break;
  5635. udelay(10);
  5636. }
  5637. /* Chip might not be fitted with firmware. Some Sun onboard
  5638. * parts are configured like that. So don't signal the timeout
  5639. * of the above loop as an error, but do report the lack of
  5640. * running firmware once.
  5641. */
  5642. if (i >= 100000 &&
  5643. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  5644. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  5645. netdev_info(tp->dev, "No firmware running\n");
  5646. }
  5647. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
  5648. /* The 57765 A0 needs a little more
  5649. * time to do some important work.
  5650. */
  5651. mdelay(10);
  5652. }
  5653. return 0;
  5654. }
  5655. /* Save PCI command register before chip reset */
  5656. static void tg3_save_pci_state(struct tg3 *tp)
  5657. {
  5658. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  5659. }
  5660. /* Restore PCI state after chip reset */
  5661. static void tg3_restore_pci_state(struct tg3 *tp)
  5662. {
  5663. u32 val;
  5664. /* Re-enable indirect register accesses. */
  5665. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  5666. tp->misc_host_ctrl);
  5667. /* Set MAX PCI retry to zero. */
  5668. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  5669. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5670. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  5671. val |= PCISTATE_RETRY_SAME_DMA;
  5672. /* Allow reads and writes to the APE register and memory space. */
  5673. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  5674. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  5675. PCISTATE_ALLOW_APE_SHMEM_WR |
  5676. PCISTATE_ALLOW_APE_PSPACE_WR;
  5677. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  5678. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  5679. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
  5680. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5681. pcie_set_readrq(tp->pdev, 4096);
  5682. else {
  5683. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  5684. tp->pci_cacheline_sz);
  5685. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  5686. tp->pci_lat_timer);
  5687. }
  5688. }
  5689. /* Make sure PCI-X relaxed ordering bit is clear. */
  5690. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  5691. u16 pcix_cmd;
  5692. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5693. &pcix_cmd);
  5694. pcix_cmd &= ~PCI_X_CMD_ERO;
  5695. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5696. pcix_cmd);
  5697. }
  5698. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  5699. /* Chip reset on 5780 will reset MSI enable bit,
  5700. * so need to restore it.
  5701. */
  5702. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  5703. u16 ctrl;
  5704. pci_read_config_word(tp->pdev,
  5705. tp->msi_cap + PCI_MSI_FLAGS,
  5706. &ctrl);
  5707. pci_write_config_word(tp->pdev,
  5708. tp->msi_cap + PCI_MSI_FLAGS,
  5709. ctrl | PCI_MSI_FLAGS_ENABLE);
  5710. val = tr32(MSGINT_MODE);
  5711. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  5712. }
  5713. }
  5714. }
  5715. static void tg3_stop_fw(struct tg3 *);
  5716. /* tp->lock is held. */
  5717. static int tg3_chip_reset(struct tg3 *tp)
  5718. {
  5719. u32 val;
  5720. void (*write_op)(struct tg3 *, u32, u32);
  5721. int i, err;
  5722. tg3_nvram_lock(tp);
  5723. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  5724. /* No matching tg3_nvram_unlock() after this because
  5725. * chip reset below will undo the nvram lock.
  5726. */
  5727. tp->nvram_lock_cnt = 0;
  5728. /* GRC_MISC_CFG core clock reset will clear the memory
  5729. * enable bit in PCI register 4 and the MSI enable bit
  5730. * on some chips, so we save relevant registers here.
  5731. */
  5732. tg3_save_pci_state(tp);
  5733. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  5734. (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
  5735. tw32(GRC_FASTBOOT_PC, 0);
  5736. /*
  5737. * We must avoid the readl() that normally takes place.
  5738. * It locks machines, causes machine checks, and other
  5739. * fun things. So, temporarily disable the 5701
  5740. * hardware workaround, while we do the reset.
  5741. */
  5742. write_op = tp->write32;
  5743. if (write_op == tg3_write_flush_reg32)
  5744. tp->write32 = tg3_write32;
  5745. /* Prevent the irq handler from reading or writing PCI registers
  5746. * during chip reset when the memory enable bit in the PCI command
  5747. * register may be cleared. The chip does not generate interrupt
  5748. * at this time, but the irq handler may still be called due to irq
  5749. * sharing or irqpoll.
  5750. */
  5751. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  5752. for (i = 0; i < tp->irq_cnt; i++) {
  5753. struct tg3_napi *tnapi = &tp->napi[i];
  5754. if (tnapi->hw_status) {
  5755. tnapi->hw_status->status = 0;
  5756. tnapi->hw_status->status_tag = 0;
  5757. }
  5758. tnapi->last_tag = 0;
  5759. tnapi->last_irq_tag = 0;
  5760. }
  5761. smp_mb();
  5762. for (i = 0; i < tp->irq_cnt; i++)
  5763. synchronize_irq(tp->napi[i].irq_vec);
  5764. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  5765. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  5766. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  5767. }
  5768. /* do the reset */
  5769. val = GRC_MISC_CFG_CORECLK_RESET;
  5770. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  5771. /* Force PCIe 1.0a mode */
  5772. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  5773. !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  5774. tr32(TG3_PCIE_PHY_TSTCTL) ==
  5775. (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
  5776. tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
  5777. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  5778. tw32(GRC_MISC_CFG, (1 << 29));
  5779. val |= (1 << 29);
  5780. }
  5781. }
  5782. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5783. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  5784. tw32(GRC_VCPU_EXT_CTRL,
  5785. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  5786. }
  5787. /* Manage gphy power for all CPMU absent PCIe devices. */
  5788. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5789. !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
  5790. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  5791. tw32(GRC_MISC_CFG, val);
  5792. /* restore 5701 hardware bug workaround write method */
  5793. tp->write32 = write_op;
  5794. /* Unfortunately, we have to delay before the PCI read back.
  5795. * Some 575X chips even will not respond to a PCI cfg access
  5796. * when the reset command is given to the chip.
  5797. *
  5798. * How do these hardware designers expect things to work
  5799. * properly if the PCI write is posted for a long period
  5800. * of time? It is always necessary to have some method by
  5801. * which a register read back can occur to push the write
  5802. * out which does the reset.
  5803. *
  5804. * For most tg3 variants the trick below was working.
  5805. * Ho hum...
  5806. */
  5807. udelay(120);
  5808. /* Flush PCI posted writes. The normal MMIO registers
  5809. * are inaccessible at this time so this is the only
  5810. * way to make this reliably (actually, this is no longer
  5811. * the case, see above). I tried to use indirect
  5812. * register read/write but this upset some 5701 variants.
  5813. */
  5814. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  5815. udelay(120);
  5816. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
  5817. u16 val16;
  5818. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  5819. int i;
  5820. u32 cfg_val;
  5821. /* Wait for link training to complete. */
  5822. for (i = 0; i < 5000; i++)
  5823. udelay(100);
  5824. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  5825. pci_write_config_dword(tp->pdev, 0xc4,
  5826. cfg_val | (1 << 15));
  5827. }
  5828. /* Clear the "no snoop" and "relaxed ordering" bits. */
  5829. pci_read_config_word(tp->pdev,
  5830. tp->pcie_cap + PCI_EXP_DEVCTL,
  5831. &val16);
  5832. val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
  5833. PCI_EXP_DEVCTL_NOSNOOP_EN);
  5834. /*
  5835. * Older PCIe devices only support the 128 byte
  5836. * MPS setting. Enforce the restriction.
  5837. */
  5838. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
  5839. val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
  5840. pci_write_config_word(tp->pdev,
  5841. tp->pcie_cap + PCI_EXP_DEVCTL,
  5842. val16);
  5843. pcie_set_readrq(tp->pdev, 4096);
  5844. /* Clear error status */
  5845. pci_write_config_word(tp->pdev,
  5846. tp->pcie_cap + PCI_EXP_DEVSTA,
  5847. PCI_EXP_DEVSTA_CED |
  5848. PCI_EXP_DEVSTA_NFED |
  5849. PCI_EXP_DEVSTA_FED |
  5850. PCI_EXP_DEVSTA_URD);
  5851. }
  5852. tg3_restore_pci_state(tp);
  5853. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  5854. val = 0;
  5855. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  5856. val = tr32(MEMARB_MODE);
  5857. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  5858. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  5859. tg3_stop_fw(tp);
  5860. tw32(0x5000, 0x400);
  5861. }
  5862. tw32(GRC_MODE, tp->grc_mode);
  5863. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  5864. val = tr32(0xc4);
  5865. tw32(0xc4, val | (1 << 15));
  5866. }
  5867. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  5868. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5869. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  5870. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  5871. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  5872. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5873. }
  5874. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  5875. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  5876. tw32_f(MAC_MODE, tp->mac_mode);
  5877. } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  5878. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  5879. tw32_f(MAC_MODE, tp->mac_mode);
  5880. } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  5881. tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  5882. if (tp->mac_mode & MAC_MODE_APE_TX_EN)
  5883. tp->mac_mode |= MAC_MODE_TDE_ENABLE;
  5884. tw32_f(MAC_MODE, tp->mac_mode);
  5885. } else
  5886. tw32_f(MAC_MODE, 0);
  5887. udelay(40);
  5888. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  5889. err = tg3_poll_fw(tp);
  5890. if (err)
  5891. return err;
  5892. tg3_mdio_start(tp);
  5893. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  5894. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  5895. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  5896. !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
  5897. val = tr32(0x7c00);
  5898. tw32(0x7c00, val | (1 << 25));
  5899. }
  5900. /* Reprobe ASF enable state. */
  5901. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  5902. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  5903. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  5904. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  5905. u32 nic_cfg;
  5906. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  5907. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  5908. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  5909. tp->last_event_jiffies = jiffies;
  5910. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  5911. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  5912. }
  5913. }
  5914. return 0;
  5915. }
  5916. /* tp->lock is held. */
  5917. static void tg3_stop_fw(struct tg3 *tp)
  5918. {
  5919. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  5920. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  5921. /* Wait for RX cpu to ACK the previous event. */
  5922. tg3_wait_for_event_ack(tp);
  5923. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  5924. tg3_generate_fw_event(tp);
  5925. /* Wait for RX cpu to ACK this event. */
  5926. tg3_wait_for_event_ack(tp);
  5927. }
  5928. }
  5929. /* tp->lock is held. */
  5930. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  5931. {
  5932. int err;
  5933. tg3_stop_fw(tp);
  5934. tg3_write_sig_pre_reset(tp, kind);
  5935. tg3_abort_hw(tp, silent);
  5936. err = tg3_chip_reset(tp);
  5937. __tg3_set_mac_addr(tp, 0);
  5938. tg3_write_sig_legacy(tp, kind);
  5939. tg3_write_sig_post_reset(tp, kind);
  5940. if (err)
  5941. return err;
  5942. return 0;
  5943. }
  5944. #define RX_CPU_SCRATCH_BASE 0x30000
  5945. #define RX_CPU_SCRATCH_SIZE 0x04000
  5946. #define TX_CPU_SCRATCH_BASE 0x34000
  5947. #define TX_CPU_SCRATCH_SIZE 0x04000
  5948. /* tp->lock is held. */
  5949. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  5950. {
  5951. int i;
  5952. BUG_ON(offset == TX_CPU_BASE &&
  5953. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  5954. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5955. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  5956. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  5957. return 0;
  5958. }
  5959. if (offset == RX_CPU_BASE) {
  5960. for (i = 0; i < 10000; i++) {
  5961. tw32(offset + CPU_STATE, 0xffffffff);
  5962. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5963. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5964. break;
  5965. }
  5966. tw32(offset + CPU_STATE, 0xffffffff);
  5967. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  5968. udelay(10);
  5969. } else {
  5970. for (i = 0; i < 10000; i++) {
  5971. tw32(offset + CPU_STATE, 0xffffffff);
  5972. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5973. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5974. break;
  5975. }
  5976. }
  5977. if (i >= 10000) {
  5978. netdev_err(tp->dev, "%s timed out, %s CPU\n",
  5979. __func__, offset == RX_CPU_BASE ? "RX" : "TX");
  5980. return -ENODEV;
  5981. }
  5982. /* Clear firmware's nvram arbitration. */
  5983. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  5984. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  5985. return 0;
  5986. }
  5987. struct fw_info {
  5988. unsigned int fw_base;
  5989. unsigned int fw_len;
  5990. const __be32 *fw_data;
  5991. };
  5992. /* tp->lock is held. */
  5993. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  5994. int cpu_scratch_size, struct fw_info *info)
  5995. {
  5996. int err, lock_err, i;
  5997. void (*write_op)(struct tg3 *, u32, u32);
  5998. if (cpu_base == TX_CPU_BASE &&
  5999. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6000. netdev_err(tp->dev,
  6001. "%s: Trying to load TX cpu firmware which is 5705\n",
  6002. __func__);
  6003. return -EINVAL;
  6004. }
  6005. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  6006. write_op = tg3_write_mem;
  6007. else
  6008. write_op = tg3_write_indirect_reg32;
  6009. /* It is possible that bootcode is still loading at this point.
  6010. * Get the nvram lock first before halting the cpu.
  6011. */
  6012. lock_err = tg3_nvram_lock(tp);
  6013. err = tg3_halt_cpu(tp, cpu_base);
  6014. if (!lock_err)
  6015. tg3_nvram_unlock(tp);
  6016. if (err)
  6017. goto out;
  6018. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  6019. write_op(tp, cpu_scratch_base + i, 0);
  6020. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6021. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  6022. for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
  6023. write_op(tp, (cpu_scratch_base +
  6024. (info->fw_base & 0xffff) +
  6025. (i * sizeof(u32))),
  6026. be32_to_cpu(info->fw_data[i]));
  6027. err = 0;
  6028. out:
  6029. return err;
  6030. }
  6031. /* tp->lock is held. */
  6032. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  6033. {
  6034. struct fw_info info;
  6035. const __be32 *fw_data;
  6036. int err, i;
  6037. fw_data = (void *)tp->fw->data;
  6038. /* Firmware blob starts with version numbers, followed by
  6039. start address and length. We are setting complete length.
  6040. length = end_address_of_bss - start_address_of_text.
  6041. Remainder is the blob to be loaded contiguously
  6042. from start address. */
  6043. info.fw_base = be32_to_cpu(fw_data[1]);
  6044. info.fw_len = tp->fw->size - 12;
  6045. info.fw_data = &fw_data[3];
  6046. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  6047. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  6048. &info);
  6049. if (err)
  6050. return err;
  6051. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  6052. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  6053. &info);
  6054. if (err)
  6055. return err;
  6056. /* Now startup only the RX cpu. */
  6057. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6058. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  6059. for (i = 0; i < 5; i++) {
  6060. if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
  6061. break;
  6062. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6063. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  6064. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  6065. udelay(1000);
  6066. }
  6067. if (i >= 5) {
  6068. netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
  6069. "should be %08x\n", __func__,
  6070. tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
  6071. return -ENODEV;
  6072. }
  6073. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6074. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  6075. return 0;
  6076. }
  6077. /* 5705 needs a special version of the TSO firmware. */
  6078. /* tp->lock is held. */
  6079. static int tg3_load_tso_firmware(struct tg3 *tp)
  6080. {
  6081. struct fw_info info;
  6082. const __be32 *fw_data;
  6083. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  6084. int err, i;
  6085. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6086. return 0;
  6087. fw_data = (void *)tp->fw->data;
  6088. /* Firmware blob starts with version numbers, followed by
  6089. start address and length. We are setting complete length.
  6090. length = end_address_of_bss - start_address_of_text.
  6091. Remainder is the blob to be loaded contiguously
  6092. from start address. */
  6093. info.fw_base = be32_to_cpu(fw_data[1]);
  6094. cpu_scratch_size = tp->fw_len;
  6095. info.fw_len = tp->fw->size - 12;
  6096. info.fw_data = &fw_data[3];
  6097. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6098. cpu_base = RX_CPU_BASE;
  6099. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  6100. } else {
  6101. cpu_base = TX_CPU_BASE;
  6102. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  6103. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  6104. }
  6105. err = tg3_load_firmware_cpu(tp, cpu_base,
  6106. cpu_scratch_base, cpu_scratch_size,
  6107. &info);
  6108. if (err)
  6109. return err;
  6110. /* Now startup the cpu. */
  6111. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6112. tw32_f(cpu_base + CPU_PC, info.fw_base);
  6113. for (i = 0; i < 5; i++) {
  6114. if (tr32(cpu_base + CPU_PC) == info.fw_base)
  6115. break;
  6116. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6117. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  6118. tw32_f(cpu_base + CPU_PC, info.fw_base);
  6119. udelay(1000);
  6120. }
  6121. if (i >= 5) {
  6122. netdev_err(tp->dev,
  6123. "%s fails to set CPU PC, is %08x should be %08x\n",
  6124. __func__, tr32(cpu_base + CPU_PC), info.fw_base);
  6125. return -ENODEV;
  6126. }
  6127. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6128. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  6129. return 0;
  6130. }
  6131. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  6132. {
  6133. struct tg3 *tp = netdev_priv(dev);
  6134. struct sockaddr *addr = p;
  6135. int err = 0, skip_mac_1 = 0;
  6136. if (!is_valid_ether_addr(addr->sa_data))
  6137. return -EINVAL;
  6138. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  6139. if (!netif_running(dev))
  6140. return 0;
  6141. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  6142. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  6143. addr0_high = tr32(MAC_ADDR_0_HIGH);
  6144. addr0_low = tr32(MAC_ADDR_0_LOW);
  6145. addr1_high = tr32(MAC_ADDR_1_HIGH);
  6146. addr1_low = tr32(MAC_ADDR_1_LOW);
  6147. /* Skip MAC addr 1 if ASF is using it. */
  6148. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  6149. !(addr1_high == 0 && addr1_low == 0))
  6150. skip_mac_1 = 1;
  6151. }
  6152. spin_lock_bh(&tp->lock);
  6153. __tg3_set_mac_addr(tp, skip_mac_1);
  6154. spin_unlock_bh(&tp->lock);
  6155. return err;
  6156. }
  6157. /* tp->lock is held. */
  6158. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  6159. dma_addr_t mapping, u32 maxlen_flags,
  6160. u32 nic_addr)
  6161. {
  6162. tg3_write_mem(tp,
  6163. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6164. ((u64) mapping >> 32));
  6165. tg3_write_mem(tp,
  6166. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  6167. ((u64) mapping & 0xffffffff));
  6168. tg3_write_mem(tp,
  6169. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  6170. maxlen_flags);
  6171. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6172. tg3_write_mem(tp,
  6173. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  6174. nic_addr);
  6175. }
  6176. static void __tg3_set_rx_mode(struct net_device *);
  6177. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  6178. {
  6179. int i;
  6180. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
  6181. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  6182. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  6183. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  6184. } else {
  6185. tw32(HOSTCC_TXCOL_TICKS, 0);
  6186. tw32(HOSTCC_TXMAX_FRAMES, 0);
  6187. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  6188. }
  6189. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
  6190. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  6191. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  6192. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  6193. } else {
  6194. tw32(HOSTCC_RXCOL_TICKS, 0);
  6195. tw32(HOSTCC_RXMAX_FRAMES, 0);
  6196. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  6197. }
  6198. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6199. u32 val = ec->stats_block_coalesce_usecs;
  6200. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  6201. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  6202. if (!netif_carrier_ok(tp->dev))
  6203. val = 0;
  6204. tw32(HOSTCC_STAT_COAL_TICKS, val);
  6205. }
  6206. for (i = 0; i < tp->irq_cnt - 1; i++) {
  6207. u32 reg;
  6208. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  6209. tw32(reg, ec->rx_coalesce_usecs);
  6210. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  6211. tw32(reg, ec->rx_max_coalesced_frames);
  6212. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6213. tw32(reg, ec->rx_max_coalesced_frames_irq);
  6214. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
  6215. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  6216. tw32(reg, ec->tx_coalesce_usecs);
  6217. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  6218. tw32(reg, ec->tx_max_coalesced_frames);
  6219. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6220. tw32(reg, ec->tx_max_coalesced_frames_irq);
  6221. }
  6222. }
  6223. for (; i < tp->irq_max - 1; i++) {
  6224. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  6225. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6226. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6227. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
  6228. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  6229. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6230. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6231. }
  6232. }
  6233. }
  6234. /* tp->lock is held. */
  6235. static void tg3_rings_reset(struct tg3 *tp)
  6236. {
  6237. int i;
  6238. u32 stblk, txrcb, rxrcb, limit;
  6239. struct tg3_napi *tnapi = &tp->napi[0];
  6240. /* Disable all transmit rings but the first. */
  6241. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6242. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  6243. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6244. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  6245. else
  6246. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6247. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6248. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  6249. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6250. BDINFO_FLAGS_DISABLED);
  6251. /* Disable all receive return rings but the first. */
  6252. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  6253. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  6254. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  6255. else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6256. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  6257. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6258. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6259. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  6260. else
  6261. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6262. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6263. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  6264. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6265. BDINFO_FLAGS_DISABLED);
  6266. /* Disable interrupts */
  6267. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  6268. /* Zero mailbox registers. */
  6269. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
  6270. for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
  6271. tp->napi[i].tx_prod = 0;
  6272. tp->napi[i].tx_cons = 0;
  6273. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  6274. tw32_mailbox(tp->napi[i].prodmbox, 0);
  6275. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  6276. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  6277. }
  6278. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
  6279. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6280. } else {
  6281. tp->napi[0].tx_prod = 0;
  6282. tp->napi[0].tx_cons = 0;
  6283. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6284. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  6285. }
  6286. /* Make sure the NIC-based send BD rings are disabled. */
  6287. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6288. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  6289. for (i = 0; i < 16; i++)
  6290. tw32_tx_mbox(mbox + i * 8, 0);
  6291. }
  6292. txrcb = NIC_SRAM_SEND_RCB;
  6293. rxrcb = NIC_SRAM_RCV_RET_RCB;
  6294. /* Clear status block in ram. */
  6295. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6296. /* Set status block DMA address */
  6297. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6298. ((u64) tnapi->status_mapping >> 32));
  6299. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6300. ((u64) tnapi->status_mapping & 0xffffffff));
  6301. if (tnapi->tx_ring) {
  6302. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6303. (TG3_TX_RING_SIZE <<
  6304. BDINFO_FLAGS_MAXLEN_SHIFT),
  6305. NIC_SRAM_TX_BUFFER_DESC);
  6306. txrcb += TG3_BDINFO_SIZE;
  6307. }
  6308. if (tnapi->rx_rcb) {
  6309. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6310. (TG3_RX_RCB_RING_SIZE(tp) <<
  6311. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  6312. rxrcb += TG3_BDINFO_SIZE;
  6313. }
  6314. stblk = HOSTCC_STATBLCK_RING1;
  6315. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  6316. u64 mapping = (u64)tnapi->status_mapping;
  6317. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  6318. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  6319. /* Clear status block in ram. */
  6320. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6321. if (tnapi->tx_ring) {
  6322. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6323. (TG3_TX_RING_SIZE <<
  6324. BDINFO_FLAGS_MAXLEN_SHIFT),
  6325. NIC_SRAM_TX_BUFFER_DESC);
  6326. txrcb += TG3_BDINFO_SIZE;
  6327. }
  6328. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6329. (TG3_RX_RCB_RING_SIZE(tp) <<
  6330. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  6331. stblk += 8;
  6332. rxrcb += TG3_BDINFO_SIZE;
  6333. }
  6334. }
  6335. /* tp->lock is held. */
  6336. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  6337. {
  6338. u32 val, rdmac_mode;
  6339. int i, err, limit;
  6340. struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
  6341. tg3_disable_ints(tp);
  6342. tg3_stop_fw(tp);
  6343. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  6344. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
  6345. tg3_abort_hw(tp, 1);
  6346. if (reset_phy)
  6347. tg3_phy_reset(tp);
  6348. err = tg3_chip_reset(tp);
  6349. if (err)
  6350. return err;
  6351. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  6352. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  6353. val = tr32(TG3_CPMU_CTRL);
  6354. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  6355. tw32(TG3_CPMU_CTRL, val);
  6356. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  6357. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  6358. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  6359. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  6360. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  6361. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  6362. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  6363. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  6364. val = tr32(TG3_CPMU_HST_ACC);
  6365. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  6366. val |= CPMU_HST_ACC_MACCLK_6_25;
  6367. tw32(TG3_CPMU_HST_ACC, val);
  6368. }
  6369. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  6370. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  6371. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  6372. PCIE_PWR_MGMT_L1_THRESH_4MS;
  6373. tw32(PCIE_PWR_MGMT_THRESH, val);
  6374. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  6375. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  6376. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  6377. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  6378. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  6379. }
  6380. if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
  6381. u32 grc_mode = tr32(GRC_MODE);
  6382. /* Access the lower 1K of PL PCIE block registers. */
  6383. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6384. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  6385. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  6386. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  6387. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  6388. tw32(GRC_MODE, grc_mode);
  6389. }
  6390. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
  6391. u32 grc_mode = tr32(GRC_MODE);
  6392. /* Access the lower 1K of PL PCIE block registers. */
  6393. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6394. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  6395. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
  6396. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
  6397. val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
  6398. tw32(GRC_MODE, grc_mode);
  6399. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  6400. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  6401. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  6402. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  6403. }
  6404. /* This works around an issue with Athlon chipsets on
  6405. * B3 tigon3 silicon. This bit has no effect on any
  6406. * other revision. But do not set this on PCI Express
  6407. * chips and don't even touch the clocks if the CPMU is present.
  6408. */
  6409. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
  6410. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  6411. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  6412. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  6413. }
  6414. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  6415. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  6416. val = tr32(TG3PCI_PCISTATE);
  6417. val |= PCISTATE_RETRY_SAME_DMA;
  6418. tw32(TG3PCI_PCISTATE, val);
  6419. }
  6420. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  6421. /* Allow reads and writes to the
  6422. * APE register and memory space.
  6423. */
  6424. val = tr32(TG3PCI_PCISTATE);
  6425. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6426. PCISTATE_ALLOW_APE_SHMEM_WR |
  6427. PCISTATE_ALLOW_APE_PSPACE_WR;
  6428. tw32(TG3PCI_PCISTATE, val);
  6429. }
  6430. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  6431. /* Enable some hw fixes. */
  6432. val = tr32(TG3PCI_MSI_DATA);
  6433. val |= (1 << 26) | (1 << 28) | (1 << 29);
  6434. tw32(TG3PCI_MSI_DATA, val);
  6435. }
  6436. /* Descriptor ring init may make accesses to the
  6437. * NIC SRAM area to setup the TX descriptors, so we
  6438. * can only do this after the hardware has been
  6439. * successfully reset.
  6440. */
  6441. err = tg3_init_rings(tp);
  6442. if (err)
  6443. return err;
  6444. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  6445. val = tr32(TG3PCI_DMA_RW_CTRL) &
  6446. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  6447. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
  6448. val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
  6449. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  6450. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  6451. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
  6452. /* This value is determined during the probe time DMA
  6453. * engine test, tg3_test_dma.
  6454. */
  6455. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  6456. }
  6457. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  6458. GRC_MODE_4X_NIC_SEND_RINGS |
  6459. GRC_MODE_NO_TX_PHDR_CSUM |
  6460. GRC_MODE_NO_RX_PHDR_CSUM);
  6461. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  6462. /* Pseudo-header checksum is done by hardware logic and not
  6463. * the offload processers, so make the chip do the pseudo-
  6464. * header checksums on receive. For transmit it is more
  6465. * convenient to do the pseudo-header checksum in software
  6466. * as Linux does that on transmit for us in all cases.
  6467. */
  6468. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  6469. tw32(GRC_MODE,
  6470. tp->grc_mode |
  6471. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  6472. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  6473. val = tr32(GRC_MISC_CFG);
  6474. val &= ~0xff;
  6475. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  6476. tw32(GRC_MISC_CFG, val);
  6477. /* Initialize MBUF/DESC pool. */
  6478. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6479. /* Do nothing. */
  6480. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  6481. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  6482. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  6483. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  6484. else
  6485. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  6486. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  6487. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  6488. } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6489. int fw_len;
  6490. fw_len = tp->fw_len;
  6491. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  6492. tw32(BUFMGR_MB_POOL_ADDR,
  6493. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  6494. tw32(BUFMGR_MB_POOL_SIZE,
  6495. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  6496. }
  6497. if (tp->dev->mtu <= ETH_DATA_LEN) {
  6498. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6499. tp->bufmgr_config.mbuf_read_dma_low_water);
  6500. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6501. tp->bufmgr_config.mbuf_mac_rx_low_water);
  6502. tw32(BUFMGR_MB_HIGH_WATER,
  6503. tp->bufmgr_config.mbuf_high_water);
  6504. } else {
  6505. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6506. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  6507. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6508. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  6509. tw32(BUFMGR_MB_HIGH_WATER,
  6510. tp->bufmgr_config.mbuf_high_water_jumbo);
  6511. }
  6512. tw32(BUFMGR_DMA_LOW_WATER,
  6513. tp->bufmgr_config.dma_low_water);
  6514. tw32(BUFMGR_DMA_HIGH_WATER,
  6515. tp->bufmgr_config.dma_high_water);
  6516. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  6517. for (i = 0; i < 2000; i++) {
  6518. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  6519. break;
  6520. udelay(10);
  6521. }
  6522. if (i >= 2000) {
  6523. netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
  6524. return -ENODEV;
  6525. }
  6526. /* Setup replenish threshold. */
  6527. val = tp->rx_pending / 8;
  6528. if (val == 0)
  6529. val = 1;
  6530. else if (val > tp->rx_std_max_post)
  6531. val = tp->rx_std_max_post;
  6532. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  6533. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  6534. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  6535. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  6536. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  6537. }
  6538. tw32(RCVBDI_STD_THRESH, val);
  6539. /* Initialize TG3_BDINFO's at:
  6540. * RCVDBDI_STD_BD: standard eth size rx ring
  6541. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  6542. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  6543. *
  6544. * like so:
  6545. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  6546. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  6547. * ring attribute flags
  6548. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  6549. *
  6550. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  6551. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  6552. *
  6553. * The size of each ring is fixed in the firmware, but the location is
  6554. * configurable.
  6555. */
  6556. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6557. ((u64) tpr->rx_std_mapping >> 32));
  6558. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6559. ((u64) tpr->rx_std_mapping & 0xffffffff));
  6560. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  6561. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
  6562. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  6563. NIC_SRAM_RX_BUFFER_DESC);
  6564. /* Disable the mini ring */
  6565. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6566. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6567. BDINFO_FLAGS_DISABLED);
  6568. /* Program the jumbo buffer descriptor ring control
  6569. * blocks on those devices that have them.
  6570. */
  6571. if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
  6572. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  6573. /* Setup replenish threshold. */
  6574. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  6575. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  6576. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6577. ((u64) tpr->rx_jmb_mapping >> 32));
  6578. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6579. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  6580. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6581. (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
  6582. BDINFO_FLAGS_USE_EXT_RECV);
  6583. if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
  6584. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6585. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  6586. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  6587. } else {
  6588. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6589. BDINFO_FLAGS_DISABLED);
  6590. }
  6591. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
  6592. val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
  6593. (TG3_RX_STD_DMA_SZ << 2);
  6594. else
  6595. val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
  6596. } else
  6597. val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
  6598. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  6599. tpr->rx_std_prod_idx = tp->rx_pending;
  6600. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  6601. tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  6602. tp->rx_jumbo_pending : 0;
  6603. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  6604. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  6605. tw32(STD_REPLENISH_LWM, 32);
  6606. tw32(JMB_REPLENISH_LWM, 16);
  6607. }
  6608. tg3_rings_reset(tp);
  6609. /* Initialize MAC address and backoff seed. */
  6610. __tg3_set_mac_addr(tp, 0);
  6611. /* MTU + ethernet header + FCS + optional VLAN tag */
  6612. tw32(MAC_RX_MTU_SIZE,
  6613. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  6614. /* The slot time is changed by tg3_setup_phy if we
  6615. * run at gigabit with half duplex.
  6616. */
  6617. tw32(MAC_TX_LENGTHS,
  6618. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  6619. (6 << TX_LENGTHS_IPG_SHIFT) |
  6620. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  6621. /* Receive rules. */
  6622. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  6623. tw32(RCVLPC_CONFIG, 0x0181);
  6624. /* Calculate RDMAC_MODE setting early, we need it to determine
  6625. * the RCVLPC_STATE_ENABLE mask.
  6626. */
  6627. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  6628. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  6629. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  6630. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  6631. RDMAC_MODE_LNGREAD_ENAB);
  6632. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  6633. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  6634. rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
  6635. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  6636. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  6637. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  6638. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  6639. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  6640. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  6641. /* If statement applies to 5705 and 5750 PCI devices only */
  6642. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6643. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6644. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  6645. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  6646. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6647. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  6648. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6649. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  6650. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6651. }
  6652. }
  6653. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  6654. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6655. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6656. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  6657. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  6658. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  6659. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  6660. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  6661. /* Receive/send statistics. */
  6662. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6663. val = tr32(RCVLPC_STATS_ENABLE);
  6664. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  6665. tw32(RCVLPC_STATS_ENABLE, val);
  6666. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  6667. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6668. val = tr32(RCVLPC_STATS_ENABLE);
  6669. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  6670. tw32(RCVLPC_STATS_ENABLE, val);
  6671. } else {
  6672. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  6673. }
  6674. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  6675. tw32(SNDDATAI_STATSENAB, 0xffffff);
  6676. tw32(SNDDATAI_STATSCTRL,
  6677. (SNDDATAI_SCTRL_ENABLE |
  6678. SNDDATAI_SCTRL_FASTUPD));
  6679. /* Setup host coalescing engine. */
  6680. tw32(HOSTCC_MODE, 0);
  6681. for (i = 0; i < 2000; i++) {
  6682. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  6683. break;
  6684. udelay(10);
  6685. }
  6686. __tg3_set_coalesce(tp, &tp->coal);
  6687. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6688. /* Status/statistics block address. See tg3_timer,
  6689. * the tg3_periodic_fetch_stats call there, and
  6690. * tg3_get_stats to see how this works for 5705/5750 chips.
  6691. */
  6692. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6693. ((u64) tp->stats_mapping >> 32));
  6694. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6695. ((u64) tp->stats_mapping & 0xffffffff));
  6696. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  6697. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  6698. /* Clear statistics and status block memory areas */
  6699. for (i = NIC_SRAM_STATS_BLK;
  6700. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  6701. i += sizeof(u32)) {
  6702. tg3_write_mem(tp, i, 0);
  6703. udelay(40);
  6704. }
  6705. }
  6706. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  6707. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  6708. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  6709. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6710. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  6711. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  6712. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  6713. /* reset to prevent losing 1st rx packet intermittently */
  6714. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6715. udelay(10);
  6716. }
  6717. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6718. tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  6719. else
  6720. tp->mac_mode = 0;
  6721. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  6722. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  6723. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6724. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  6725. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  6726. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6727. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  6728. udelay(40);
  6729. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  6730. * If TG3_FLG2_IS_NIC is zero, we should read the
  6731. * register to preserve the GPIO settings for LOMs. The GPIOs,
  6732. * whether used as inputs or outputs, are set by boot code after
  6733. * reset.
  6734. */
  6735. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  6736. u32 gpio_mask;
  6737. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  6738. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  6739. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  6740. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  6741. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  6742. GRC_LCLCTRL_GPIO_OUTPUT3;
  6743. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  6744. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  6745. tp->grc_local_ctrl &= ~gpio_mask;
  6746. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  6747. /* GPIO1 must be driven high for eeprom write protect */
  6748. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  6749. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  6750. GRC_LCLCTRL_GPIO_OUTPUT1);
  6751. }
  6752. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6753. udelay(100);
  6754. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
  6755. val = tr32(MSGINT_MODE);
  6756. val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
  6757. tw32(MSGINT_MODE, val);
  6758. }
  6759. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6760. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  6761. udelay(40);
  6762. }
  6763. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  6764. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  6765. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  6766. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  6767. WDMAC_MODE_LNGREAD_ENAB);
  6768. /* If statement applies to 5705 and 5750 PCI devices only */
  6769. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6770. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6771. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  6772. if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  6773. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  6774. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  6775. /* nothing */
  6776. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6777. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  6778. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  6779. val |= WDMAC_MODE_RX_ACCEL;
  6780. }
  6781. }
  6782. /* Enable host coalescing bug fix */
  6783. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  6784. val |= WDMAC_MODE_STATUS_TAG_FIX;
  6785. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  6786. val |= WDMAC_MODE_BURST_ALL_DATA;
  6787. tw32_f(WDMAC_MODE, val);
  6788. udelay(40);
  6789. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  6790. u16 pcix_cmd;
  6791. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6792. &pcix_cmd);
  6793. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  6794. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  6795. pcix_cmd |= PCI_X_CMD_READ_2K;
  6796. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  6797. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  6798. pcix_cmd |= PCI_X_CMD_READ_2K;
  6799. }
  6800. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6801. pcix_cmd);
  6802. }
  6803. tw32_f(RDMAC_MODE, rdmac_mode);
  6804. udelay(40);
  6805. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  6806. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6807. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  6808. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  6809. tw32(SNDDATAC_MODE,
  6810. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  6811. else
  6812. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  6813. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  6814. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  6815. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  6816. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  6817. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6818. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  6819. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  6820. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  6821. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  6822. tw32(SNDBDI_MODE, val);
  6823. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  6824. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  6825. err = tg3_load_5701_a0_firmware_fix(tp);
  6826. if (err)
  6827. return err;
  6828. }
  6829. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6830. err = tg3_load_tso_firmware(tp);
  6831. if (err)
  6832. return err;
  6833. }
  6834. tp->tx_mode = TX_MODE_ENABLE;
  6835. if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  6836. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  6837. tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
  6838. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6839. udelay(100);
  6840. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
  6841. u32 reg = MAC_RSS_INDIR_TBL_0;
  6842. u8 *ent = (u8 *)&val;
  6843. /* Setup the indirection table */
  6844. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
  6845. int idx = i % sizeof(val);
  6846. ent[idx] = i % (tp->irq_cnt - 1);
  6847. if (idx == sizeof(val) - 1) {
  6848. tw32(reg, val);
  6849. reg += 4;
  6850. }
  6851. }
  6852. /* Setup the "secret" hash key. */
  6853. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  6854. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  6855. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  6856. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  6857. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  6858. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  6859. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  6860. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  6861. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  6862. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  6863. }
  6864. tp->rx_mode = RX_MODE_ENABLE;
  6865. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  6866. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  6867. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
  6868. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  6869. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  6870. RX_MODE_RSS_IPV6_HASH_EN |
  6871. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  6872. RX_MODE_RSS_IPV4_HASH_EN |
  6873. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  6874. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6875. udelay(10);
  6876. tw32(MAC_LED_CTRL, tp->led_ctrl);
  6877. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  6878. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  6879. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6880. udelay(10);
  6881. }
  6882. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6883. udelay(10);
  6884. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  6885. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  6886. !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
  6887. /* Set drive transmission level to 1.2V */
  6888. /* only if the signal pre-emphasis bit is not set */
  6889. val = tr32(MAC_SERDES_CFG);
  6890. val &= 0xfffff000;
  6891. val |= 0x880;
  6892. tw32(MAC_SERDES_CFG, val);
  6893. }
  6894. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  6895. tw32(MAC_SERDES_CFG, 0x616000);
  6896. }
  6897. /* Prevent chip from dropping frames when flow control
  6898. * is enabled.
  6899. */
  6900. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6901. val = 1;
  6902. else
  6903. val = 2;
  6904. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  6905. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  6906. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  6907. /* Use hardware link auto-negotiation */
  6908. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  6909. }
  6910. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  6911. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  6912. u32 tmp;
  6913. tmp = tr32(SERDES_RX_CTRL);
  6914. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  6915. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  6916. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  6917. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6918. }
  6919. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  6920. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  6921. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  6922. tp->link_config.speed = tp->link_config.orig_speed;
  6923. tp->link_config.duplex = tp->link_config.orig_duplex;
  6924. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  6925. }
  6926. err = tg3_setup_phy(tp, 0);
  6927. if (err)
  6928. return err;
  6929. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  6930. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  6931. u32 tmp;
  6932. /* Clear CRC stats. */
  6933. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  6934. tg3_writephy(tp, MII_TG3_TEST1,
  6935. tmp | MII_TG3_TEST1_CRC_EN);
  6936. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
  6937. }
  6938. }
  6939. }
  6940. __tg3_set_rx_mode(tp->dev);
  6941. /* Initialize receive rules. */
  6942. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  6943. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6944. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  6945. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6946. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6947. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  6948. limit = 8;
  6949. else
  6950. limit = 16;
  6951. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  6952. limit -= 4;
  6953. switch (limit) {
  6954. case 16:
  6955. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  6956. case 15:
  6957. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  6958. case 14:
  6959. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  6960. case 13:
  6961. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  6962. case 12:
  6963. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  6964. case 11:
  6965. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  6966. case 10:
  6967. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  6968. case 9:
  6969. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  6970. case 8:
  6971. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  6972. case 7:
  6973. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  6974. case 6:
  6975. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  6976. case 5:
  6977. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  6978. case 4:
  6979. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  6980. case 3:
  6981. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  6982. case 2:
  6983. case 1:
  6984. default:
  6985. break;
  6986. }
  6987. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6988. /* Write our heartbeat update interval to APE. */
  6989. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  6990. APE_HOST_HEARTBEAT_INT_DISABLE);
  6991. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  6992. return 0;
  6993. }
  6994. /* Called at device open time to get the chip ready for
  6995. * packet processing. Invoked with tp->lock held.
  6996. */
  6997. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  6998. {
  6999. tg3_switch_clocks(tp);
  7000. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  7001. return tg3_reset_hw(tp, reset_phy);
  7002. }
  7003. #define TG3_STAT_ADD32(PSTAT, REG) \
  7004. do { u32 __val = tr32(REG); \
  7005. (PSTAT)->low += __val; \
  7006. if ((PSTAT)->low < __val) \
  7007. (PSTAT)->high += 1; \
  7008. } while (0)
  7009. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  7010. {
  7011. struct tg3_hw_stats *sp = tp->hw_stats;
  7012. if (!netif_carrier_ok(tp->dev))
  7013. return;
  7014. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  7015. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  7016. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  7017. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  7018. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  7019. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  7020. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  7021. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  7022. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  7023. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  7024. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  7025. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  7026. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  7027. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  7028. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  7029. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  7030. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  7031. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  7032. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  7033. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  7034. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  7035. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  7036. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  7037. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  7038. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  7039. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  7040. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  7041. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  7042. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  7043. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  7044. }
  7045. static void tg3_timer(unsigned long __opaque)
  7046. {
  7047. struct tg3 *tp = (struct tg3 *) __opaque;
  7048. if (tp->irq_sync)
  7049. goto restart_timer;
  7050. spin_lock(&tp->lock);
  7051. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  7052. /* All of this garbage is because when using non-tagged
  7053. * IRQ status the mailbox/status_block protocol the chip
  7054. * uses with the cpu is race prone.
  7055. */
  7056. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  7057. tw32(GRC_LOCAL_CTRL,
  7058. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  7059. } else {
  7060. tw32(HOSTCC_MODE, tp->coalesce_mode |
  7061. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  7062. }
  7063. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  7064. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  7065. spin_unlock(&tp->lock);
  7066. schedule_work(&tp->reset_task);
  7067. return;
  7068. }
  7069. }
  7070. /* This part only runs once per second. */
  7071. if (!--tp->timer_counter) {
  7072. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  7073. tg3_periodic_fetch_stats(tp);
  7074. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  7075. u32 mac_stat;
  7076. int phy_event;
  7077. mac_stat = tr32(MAC_STATUS);
  7078. phy_event = 0;
  7079. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
  7080. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  7081. phy_event = 1;
  7082. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  7083. phy_event = 1;
  7084. if (phy_event)
  7085. tg3_setup_phy(tp, 0);
  7086. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  7087. u32 mac_stat = tr32(MAC_STATUS);
  7088. int need_setup = 0;
  7089. if (netif_carrier_ok(tp->dev) &&
  7090. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  7091. need_setup = 1;
  7092. }
  7093. if (!netif_carrier_ok(tp->dev) &&
  7094. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  7095. MAC_STATUS_SIGNAL_DET))) {
  7096. need_setup = 1;
  7097. }
  7098. if (need_setup) {
  7099. if (!tp->serdes_counter) {
  7100. tw32_f(MAC_MODE,
  7101. (tp->mac_mode &
  7102. ~MAC_MODE_PORT_MODE_MASK));
  7103. udelay(40);
  7104. tw32_f(MAC_MODE, tp->mac_mode);
  7105. udelay(40);
  7106. }
  7107. tg3_setup_phy(tp, 0);
  7108. }
  7109. } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  7110. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  7111. tg3_serdes_parallel_detect(tp);
  7112. }
  7113. tp->timer_counter = tp->timer_multiplier;
  7114. }
  7115. /* Heartbeat is only sent once every 2 seconds.
  7116. *
  7117. * The heartbeat is to tell the ASF firmware that the host
  7118. * driver is still alive. In the event that the OS crashes,
  7119. * ASF needs to reset the hardware to free up the FIFO space
  7120. * that may be filled with rx packets destined for the host.
  7121. * If the FIFO is full, ASF will no longer function properly.
  7122. *
  7123. * Unintended resets have been reported on real time kernels
  7124. * where the timer doesn't run on time. Netpoll will also have
  7125. * same problem.
  7126. *
  7127. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  7128. * to check the ring condition when the heartbeat is expiring
  7129. * before doing the reset. This will prevent most unintended
  7130. * resets.
  7131. */
  7132. if (!--tp->asf_counter) {
  7133. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  7134. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  7135. tg3_wait_for_event_ack(tp);
  7136. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  7137. FWCMD_NICDRV_ALIVE3);
  7138. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  7139. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
  7140. TG3_FW_UPDATE_TIMEOUT_SEC);
  7141. tg3_generate_fw_event(tp);
  7142. }
  7143. tp->asf_counter = tp->asf_multiplier;
  7144. }
  7145. spin_unlock(&tp->lock);
  7146. restart_timer:
  7147. tp->timer.expires = jiffies + tp->timer_offset;
  7148. add_timer(&tp->timer);
  7149. }
  7150. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  7151. {
  7152. irq_handler_t fn;
  7153. unsigned long flags;
  7154. char *name;
  7155. struct tg3_napi *tnapi = &tp->napi[irq_num];
  7156. if (tp->irq_cnt == 1)
  7157. name = tp->dev->name;
  7158. else {
  7159. name = &tnapi->irq_lbl[0];
  7160. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  7161. name[IFNAMSIZ-1] = 0;
  7162. }
  7163. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
  7164. fn = tg3_msi;
  7165. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  7166. fn = tg3_msi_1shot;
  7167. flags = IRQF_SAMPLE_RANDOM;
  7168. } else {
  7169. fn = tg3_interrupt;
  7170. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  7171. fn = tg3_interrupt_tagged;
  7172. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  7173. }
  7174. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  7175. }
  7176. static int tg3_test_interrupt(struct tg3 *tp)
  7177. {
  7178. struct tg3_napi *tnapi = &tp->napi[0];
  7179. struct net_device *dev = tp->dev;
  7180. int err, i, intr_ok = 0;
  7181. u32 val;
  7182. if (!netif_running(dev))
  7183. return -ENODEV;
  7184. tg3_disable_ints(tp);
  7185. free_irq(tnapi->irq_vec, tnapi);
  7186. /*
  7187. * Turn off MSI one shot mode. Otherwise this test has no
  7188. * observable way to know whether the interrupt was delivered.
  7189. */
  7190. if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  7191. (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
  7192. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  7193. tw32(MSGINT_MODE, val);
  7194. }
  7195. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  7196. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
  7197. if (err)
  7198. return err;
  7199. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  7200. tg3_enable_ints(tp);
  7201. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7202. tnapi->coal_now);
  7203. for (i = 0; i < 5; i++) {
  7204. u32 int_mbox, misc_host_ctrl;
  7205. int_mbox = tr32_mailbox(tnapi->int_mbox);
  7206. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  7207. if ((int_mbox != 0) ||
  7208. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  7209. intr_ok = 1;
  7210. break;
  7211. }
  7212. msleep(10);
  7213. }
  7214. tg3_disable_ints(tp);
  7215. free_irq(tnapi->irq_vec, tnapi);
  7216. err = tg3_request_irq(tp, 0);
  7217. if (err)
  7218. return err;
  7219. if (intr_ok) {
  7220. /* Reenable MSI one shot mode. */
  7221. if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  7222. (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
  7223. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  7224. tw32(MSGINT_MODE, val);
  7225. }
  7226. return 0;
  7227. }
  7228. return -EIO;
  7229. }
  7230. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  7231. * successfully restored
  7232. */
  7233. static int tg3_test_msi(struct tg3 *tp)
  7234. {
  7235. int err;
  7236. u16 pci_cmd;
  7237. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  7238. return 0;
  7239. /* Turn off SERR reporting in case MSI terminates with Master
  7240. * Abort.
  7241. */
  7242. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  7243. pci_write_config_word(tp->pdev, PCI_COMMAND,
  7244. pci_cmd & ~PCI_COMMAND_SERR);
  7245. err = tg3_test_interrupt(tp);
  7246. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  7247. if (!err)
  7248. return 0;
  7249. /* other failures */
  7250. if (err != -EIO)
  7251. return err;
  7252. /* MSI test failed, go back to INTx mode */
  7253. netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
  7254. "to INTx mode. Please report this failure to the PCI "
  7255. "maintainer and include system chipset information\n");
  7256. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7257. pci_disable_msi(tp->pdev);
  7258. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  7259. tp->napi[0].irq_vec = tp->pdev->irq;
  7260. err = tg3_request_irq(tp, 0);
  7261. if (err)
  7262. return err;
  7263. /* Need to reset the chip because the MSI cycle may have terminated
  7264. * with Master Abort.
  7265. */
  7266. tg3_full_lock(tp, 1);
  7267. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7268. err = tg3_init_hw(tp, 1);
  7269. tg3_full_unlock(tp);
  7270. if (err)
  7271. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7272. return err;
  7273. }
  7274. static int tg3_request_firmware(struct tg3 *tp)
  7275. {
  7276. const __be32 *fw_data;
  7277. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  7278. netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
  7279. tp->fw_needed);
  7280. return -ENOENT;
  7281. }
  7282. fw_data = (void *)tp->fw->data;
  7283. /* Firmware blob starts with version numbers, followed by
  7284. * start address and _full_ length including BSS sections
  7285. * (which must be longer than the actual data, of course
  7286. */
  7287. tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
  7288. if (tp->fw_len < (tp->fw->size - 12)) {
  7289. netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
  7290. tp->fw_len, tp->fw_needed);
  7291. release_firmware(tp->fw);
  7292. tp->fw = NULL;
  7293. return -EINVAL;
  7294. }
  7295. /* We no longer need firmware; we have it. */
  7296. tp->fw_needed = NULL;
  7297. return 0;
  7298. }
  7299. static bool tg3_enable_msix(struct tg3 *tp)
  7300. {
  7301. int i, rc, cpus = num_online_cpus();
  7302. struct msix_entry msix_ent[tp->irq_max];
  7303. if (cpus == 1)
  7304. /* Just fallback to the simpler MSI mode. */
  7305. return false;
  7306. /*
  7307. * We want as many rx rings enabled as there are cpus.
  7308. * The first MSIX vector only deals with link interrupts, etc,
  7309. * so we add one to the number of vectors we are requesting.
  7310. */
  7311. tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
  7312. for (i = 0; i < tp->irq_max; i++) {
  7313. msix_ent[i].entry = i;
  7314. msix_ent[i].vector = 0;
  7315. }
  7316. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  7317. if (rc < 0) {
  7318. return false;
  7319. } else if (rc != 0) {
  7320. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  7321. return false;
  7322. netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
  7323. tp->irq_cnt, rc);
  7324. tp->irq_cnt = rc;
  7325. }
  7326. for (i = 0; i < tp->irq_max; i++)
  7327. tp->napi[i].irq_vec = msix_ent[i].vector;
  7328. tp->dev->real_num_tx_queues = 1;
  7329. if (tp->irq_cnt > 1) {
  7330. tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
  7331. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  7332. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
  7333. tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
  7334. tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
  7335. }
  7336. }
  7337. return true;
  7338. }
  7339. static void tg3_ints_init(struct tg3 *tp)
  7340. {
  7341. if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
  7342. !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  7343. /* All MSI supporting chips should support tagged
  7344. * status. Assert that this is the case.
  7345. */
  7346. netdev_warn(tp->dev,
  7347. "MSI without TAGGED_STATUS? Not using MSI\n");
  7348. goto defcfg;
  7349. }
  7350. if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
  7351. tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
  7352. else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
  7353. pci_enable_msi(tp->pdev) == 0)
  7354. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  7355. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
  7356. u32 msi_mode = tr32(MSGINT_MODE);
  7357. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
  7358. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  7359. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  7360. }
  7361. defcfg:
  7362. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
  7363. tp->irq_cnt = 1;
  7364. tp->napi[0].irq_vec = tp->pdev->irq;
  7365. tp->dev->real_num_tx_queues = 1;
  7366. }
  7367. }
  7368. static void tg3_ints_fini(struct tg3 *tp)
  7369. {
  7370. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
  7371. pci_disable_msix(tp->pdev);
  7372. else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
  7373. pci_disable_msi(tp->pdev);
  7374. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
  7375. tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
  7376. }
  7377. static int tg3_open(struct net_device *dev)
  7378. {
  7379. struct tg3 *tp = netdev_priv(dev);
  7380. int i, err;
  7381. if (tp->fw_needed) {
  7382. err = tg3_request_firmware(tp);
  7383. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  7384. if (err)
  7385. return err;
  7386. } else if (err) {
  7387. netdev_warn(tp->dev, "TSO capability disabled\n");
  7388. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  7389. } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  7390. netdev_notice(tp->dev, "TSO capability restored\n");
  7391. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  7392. }
  7393. }
  7394. netif_carrier_off(tp->dev);
  7395. err = tg3_set_power_state(tp, PCI_D0);
  7396. if (err)
  7397. return err;
  7398. tg3_full_lock(tp, 0);
  7399. tg3_disable_ints(tp);
  7400. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  7401. tg3_full_unlock(tp);
  7402. /*
  7403. * Setup interrupts first so we know how
  7404. * many NAPI resources to allocate
  7405. */
  7406. tg3_ints_init(tp);
  7407. /* The placement of this call is tied
  7408. * to the setup and use of Host TX descriptors.
  7409. */
  7410. err = tg3_alloc_consistent(tp);
  7411. if (err)
  7412. goto err_out1;
  7413. tg3_napi_enable(tp);
  7414. for (i = 0; i < tp->irq_cnt; i++) {
  7415. struct tg3_napi *tnapi = &tp->napi[i];
  7416. err = tg3_request_irq(tp, i);
  7417. if (err) {
  7418. for (i--; i >= 0; i--)
  7419. free_irq(tnapi->irq_vec, tnapi);
  7420. break;
  7421. }
  7422. }
  7423. if (err)
  7424. goto err_out2;
  7425. tg3_full_lock(tp, 0);
  7426. err = tg3_init_hw(tp, 1);
  7427. if (err) {
  7428. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7429. tg3_free_rings(tp);
  7430. } else {
  7431. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  7432. tp->timer_offset = HZ;
  7433. else
  7434. tp->timer_offset = HZ / 10;
  7435. BUG_ON(tp->timer_offset > HZ);
  7436. tp->timer_counter = tp->timer_multiplier =
  7437. (HZ / tp->timer_offset);
  7438. tp->asf_counter = tp->asf_multiplier =
  7439. ((HZ / tp->timer_offset) * 2);
  7440. init_timer(&tp->timer);
  7441. tp->timer.expires = jiffies + tp->timer_offset;
  7442. tp->timer.data = (unsigned long) tp;
  7443. tp->timer.function = tg3_timer;
  7444. }
  7445. tg3_full_unlock(tp);
  7446. if (err)
  7447. goto err_out3;
  7448. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  7449. err = tg3_test_msi(tp);
  7450. if (err) {
  7451. tg3_full_lock(tp, 0);
  7452. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7453. tg3_free_rings(tp);
  7454. tg3_full_unlock(tp);
  7455. goto err_out2;
  7456. }
  7457. if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  7458. (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
  7459. u32 val = tr32(PCIE_TRANSACTION_CFG);
  7460. tw32(PCIE_TRANSACTION_CFG,
  7461. val | PCIE_TRANS_CFG_1SHOT_MSI);
  7462. }
  7463. }
  7464. tg3_phy_start(tp);
  7465. tg3_full_lock(tp, 0);
  7466. add_timer(&tp->timer);
  7467. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  7468. tg3_enable_ints(tp);
  7469. tg3_full_unlock(tp);
  7470. netif_tx_start_all_queues(dev);
  7471. return 0;
  7472. err_out3:
  7473. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  7474. struct tg3_napi *tnapi = &tp->napi[i];
  7475. free_irq(tnapi->irq_vec, tnapi);
  7476. }
  7477. err_out2:
  7478. tg3_napi_disable(tp);
  7479. tg3_free_consistent(tp);
  7480. err_out1:
  7481. tg3_ints_fini(tp);
  7482. return err;
  7483. }
  7484. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
  7485. struct rtnl_link_stats64 *);
  7486. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  7487. static int tg3_close(struct net_device *dev)
  7488. {
  7489. int i;
  7490. struct tg3 *tp = netdev_priv(dev);
  7491. tg3_napi_disable(tp);
  7492. cancel_work_sync(&tp->reset_task);
  7493. netif_tx_stop_all_queues(dev);
  7494. del_timer_sync(&tp->timer);
  7495. tg3_phy_stop(tp);
  7496. tg3_full_lock(tp, 1);
  7497. tg3_disable_ints(tp);
  7498. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7499. tg3_free_rings(tp);
  7500. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  7501. tg3_full_unlock(tp);
  7502. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  7503. struct tg3_napi *tnapi = &tp->napi[i];
  7504. free_irq(tnapi->irq_vec, tnapi);
  7505. }
  7506. tg3_ints_fini(tp);
  7507. tg3_get_stats64(tp->dev, &tp->net_stats_prev);
  7508. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  7509. sizeof(tp->estats_prev));
  7510. tg3_free_consistent(tp);
  7511. tg3_set_power_state(tp, PCI_D3hot);
  7512. netif_carrier_off(tp->dev);
  7513. return 0;
  7514. }
  7515. static inline u64 get_stat64(tg3_stat64_t *val)
  7516. {
  7517. return ((u64)val->high << 32) | ((u64)val->low);
  7518. }
  7519. static u64 calc_crc_errors(struct tg3 *tp)
  7520. {
  7521. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7522. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  7523. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  7524. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  7525. u32 val;
  7526. spin_lock_bh(&tp->lock);
  7527. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  7528. tg3_writephy(tp, MII_TG3_TEST1,
  7529. val | MII_TG3_TEST1_CRC_EN);
  7530. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
  7531. } else
  7532. val = 0;
  7533. spin_unlock_bh(&tp->lock);
  7534. tp->phy_crc_errors += val;
  7535. return tp->phy_crc_errors;
  7536. }
  7537. return get_stat64(&hw_stats->rx_fcs_errors);
  7538. }
  7539. #define ESTAT_ADD(member) \
  7540. estats->member = old_estats->member + \
  7541. get_stat64(&hw_stats->member)
  7542. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  7543. {
  7544. struct tg3_ethtool_stats *estats = &tp->estats;
  7545. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  7546. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7547. if (!hw_stats)
  7548. return old_estats;
  7549. ESTAT_ADD(rx_octets);
  7550. ESTAT_ADD(rx_fragments);
  7551. ESTAT_ADD(rx_ucast_packets);
  7552. ESTAT_ADD(rx_mcast_packets);
  7553. ESTAT_ADD(rx_bcast_packets);
  7554. ESTAT_ADD(rx_fcs_errors);
  7555. ESTAT_ADD(rx_align_errors);
  7556. ESTAT_ADD(rx_xon_pause_rcvd);
  7557. ESTAT_ADD(rx_xoff_pause_rcvd);
  7558. ESTAT_ADD(rx_mac_ctrl_rcvd);
  7559. ESTAT_ADD(rx_xoff_entered);
  7560. ESTAT_ADD(rx_frame_too_long_errors);
  7561. ESTAT_ADD(rx_jabbers);
  7562. ESTAT_ADD(rx_undersize_packets);
  7563. ESTAT_ADD(rx_in_length_errors);
  7564. ESTAT_ADD(rx_out_length_errors);
  7565. ESTAT_ADD(rx_64_or_less_octet_packets);
  7566. ESTAT_ADD(rx_65_to_127_octet_packets);
  7567. ESTAT_ADD(rx_128_to_255_octet_packets);
  7568. ESTAT_ADD(rx_256_to_511_octet_packets);
  7569. ESTAT_ADD(rx_512_to_1023_octet_packets);
  7570. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  7571. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  7572. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  7573. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  7574. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  7575. ESTAT_ADD(tx_octets);
  7576. ESTAT_ADD(tx_collisions);
  7577. ESTAT_ADD(tx_xon_sent);
  7578. ESTAT_ADD(tx_xoff_sent);
  7579. ESTAT_ADD(tx_flow_control);
  7580. ESTAT_ADD(tx_mac_errors);
  7581. ESTAT_ADD(tx_single_collisions);
  7582. ESTAT_ADD(tx_mult_collisions);
  7583. ESTAT_ADD(tx_deferred);
  7584. ESTAT_ADD(tx_excessive_collisions);
  7585. ESTAT_ADD(tx_late_collisions);
  7586. ESTAT_ADD(tx_collide_2times);
  7587. ESTAT_ADD(tx_collide_3times);
  7588. ESTAT_ADD(tx_collide_4times);
  7589. ESTAT_ADD(tx_collide_5times);
  7590. ESTAT_ADD(tx_collide_6times);
  7591. ESTAT_ADD(tx_collide_7times);
  7592. ESTAT_ADD(tx_collide_8times);
  7593. ESTAT_ADD(tx_collide_9times);
  7594. ESTAT_ADD(tx_collide_10times);
  7595. ESTAT_ADD(tx_collide_11times);
  7596. ESTAT_ADD(tx_collide_12times);
  7597. ESTAT_ADD(tx_collide_13times);
  7598. ESTAT_ADD(tx_collide_14times);
  7599. ESTAT_ADD(tx_collide_15times);
  7600. ESTAT_ADD(tx_ucast_packets);
  7601. ESTAT_ADD(tx_mcast_packets);
  7602. ESTAT_ADD(tx_bcast_packets);
  7603. ESTAT_ADD(tx_carrier_sense_errors);
  7604. ESTAT_ADD(tx_discards);
  7605. ESTAT_ADD(tx_errors);
  7606. ESTAT_ADD(dma_writeq_full);
  7607. ESTAT_ADD(dma_write_prioq_full);
  7608. ESTAT_ADD(rxbds_empty);
  7609. ESTAT_ADD(rx_discards);
  7610. ESTAT_ADD(rx_errors);
  7611. ESTAT_ADD(rx_threshold_hit);
  7612. ESTAT_ADD(dma_readq_full);
  7613. ESTAT_ADD(dma_read_prioq_full);
  7614. ESTAT_ADD(tx_comp_queue_full);
  7615. ESTAT_ADD(ring_set_send_prod_index);
  7616. ESTAT_ADD(ring_status_update);
  7617. ESTAT_ADD(nic_irqs);
  7618. ESTAT_ADD(nic_avoided_irqs);
  7619. ESTAT_ADD(nic_tx_threshold_hit);
  7620. return estats;
  7621. }
  7622. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
  7623. struct rtnl_link_stats64 *stats)
  7624. {
  7625. struct tg3 *tp = netdev_priv(dev);
  7626. struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
  7627. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7628. if (!hw_stats)
  7629. return old_stats;
  7630. stats->rx_packets = old_stats->rx_packets +
  7631. get_stat64(&hw_stats->rx_ucast_packets) +
  7632. get_stat64(&hw_stats->rx_mcast_packets) +
  7633. get_stat64(&hw_stats->rx_bcast_packets);
  7634. stats->tx_packets = old_stats->tx_packets +
  7635. get_stat64(&hw_stats->tx_ucast_packets) +
  7636. get_stat64(&hw_stats->tx_mcast_packets) +
  7637. get_stat64(&hw_stats->tx_bcast_packets);
  7638. stats->rx_bytes = old_stats->rx_bytes +
  7639. get_stat64(&hw_stats->rx_octets);
  7640. stats->tx_bytes = old_stats->tx_bytes +
  7641. get_stat64(&hw_stats->tx_octets);
  7642. stats->rx_errors = old_stats->rx_errors +
  7643. get_stat64(&hw_stats->rx_errors);
  7644. stats->tx_errors = old_stats->tx_errors +
  7645. get_stat64(&hw_stats->tx_errors) +
  7646. get_stat64(&hw_stats->tx_mac_errors) +
  7647. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  7648. get_stat64(&hw_stats->tx_discards);
  7649. stats->multicast = old_stats->multicast +
  7650. get_stat64(&hw_stats->rx_mcast_packets);
  7651. stats->collisions = old_stats->collisions +
  7652. get_stat64(&hw_stats->tx_collisions);
  7653. stats->rx_length_errors = old_stats->rx_length_errors +
  7654. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  7655. get_stat64(&hw_stats->rx_undersize_packets);
  7656. stats->rx_over_errors = old_stats->rx_over_errors +
  7657. get_stat64(&hw_stats->rxbds_empty);
  7658. stats->rx_frame_errors = old_stats->rx_frame_errors +
  7659. get_stat64(&hw_stats->rx_align_errors);
  7660. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  7661. get_stat64(&hw_stats->tx_discards);
  7662. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  7663. get_stat64(&hw_stats->tx_carrier_sense_errors);
  7664. stats->rx_crc_errors = old_stats->rx_crc_errors +
  7665. calc_crc_errors(tp);
  7666. stats->rx_missed_errors = old_stats->rx_missed_errors +
  7667. get_stat64(&hw_stats->rx_discards);
  7668. return stats;
  7669. }
  7670. static inline u32 calc_crc(unsigned char *buf, int len)
  7671. {
  7672. u32 reg;
  7673. u32 tmp;
  7674. int j, k;
  7675. reg = 0xffffffff;
  7676. for (j = 0; j < len; j++) {
  7677. reg ^= buf[j];
  7678. for (k = 0; k < 8; k++) {
  7679. tmp = reg & 0x01;
  7680. reg >>= 1;
  7681. if (tmp)
  7682. reg ^= 0xedb88320;
  7683. }
  7684. }
  7685. return ~reg;
  7686. }
  7687. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7688. {
  7689. /* accept or reject all multicast frames */
  7690. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7691. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7692. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7693. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7694. }
  7695. static void __tg3_set_rx_mode(struct net_device *dev)
  7696. {
  7697. struct tg3 *tp = netdev_priv(dev);
  7698. u32 rx_mode;
  7699. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7700. RX_MODE_KEEP_VLAN_TAG);
  7701. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7702. * flag clear.
  7703. */
  7704. #if TG3_VLAN_TAG_USED
  7705. if (!tp->vlgrp &&
  7706. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7707. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7708. #else
  7709. /* By definition, VLAN is disabled always in this
  7710. * case.
  7711. */
  7712. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7713. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7714. #endif
  7715. if (dev->flags & IFF_PROMISC) {
  7716. /* Promiscuous mode. */
  7717. rx_mode |= RX_MODE_PROMISC;
  7718. } else if (dev->flags & IFF_ALLMULTI) {
  7719. /* Accept all multicast. */
  7720. tg3_set_multi(tp, 1);
  7721. } else if (netdev_mc_empty(dev)) {
  7722. /* Reject all multicast. */
  7723. tg3_set_multi(tp, 0);
  7724. } else {
  7725. /* Accept one or more multicast(s). */
  7726. struct netdev_hw_addr *ha;
  7727. u32 mc_filter[4] = { 0, };
  7728. u32 regidx;
  7729. u32 bit;
  7730. u32 crc;
  7731. netdev_for_each_mc_addr(ha, dev) {
  7732. crc = calc_crc(ha->addr, ETH_ALEN);
  7733. bit = ~crc & 0x7f;
  7734. regidx = (bit & 0x60) >> 5;
  7735. bit &= 0x1f;
  7736. mc_filter[regidx] |= (1 << bit);
  7737. }
  7738. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7739. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7740. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7741. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7742. }
  7743. if (rx_mode != tp->rx_mode) {
  7744. tp->rx_mode = rx_mode;
  7745. tw32_f(MAC_RX_MODE, rx_mode);
  7746. udelay(10);
  7747. }
  7748. }
  7749. static void tg3_set_rx_mode(struct net_device *dev)
  7750. {
  7751. struct tg3 *tp = netdev_priv(dev);
  7752. if (!netif_running(dev))
  7753. return;
  7754. tg3_full_lock(tp, 0);
  7755. __tg3_set_rx_mode(dev);
  7756. tg3_full_unlock(tp);
  7757. }
  7758. #define TG3_REGDUMP_LEN (32 * 1024)
  7759. static int tg3_get_regs_len(struct net_device *dev)
  7760. {
  7761. return TG3_REGDUMP_LEN;
  7762. }
  7763. static void tg3_get_regs(struct net_device *dev,
  7764. struct ethtool_regs *regs, void *_p)
  7765. {
  7766. u32 *p = _p;
  7767. struct tg3 *tp = netdev_priv(dev);
  7768. u8 *orig_p = _p;
  7769. int i;
  7770. regs->version = 0;
  7771. memset(p, 0, TG3_REGDUMP_LEN);
  7772. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  7773. return;
  7774. tg3_full_lock(tp, 0);
  7775. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  7776. #define GET_REG32_LOOP(base, len) \
  7777. do { p = (u32 *)(orig_p + (base)); \
  7778. for (i = 0; i < len; i += 4) \
  7779. __GET_REG32((base) + i); \
  7780. } while (0)
  7781. #define GET_REG32_1(reg) \
  7782. do { p = (u32 *)(orig_p + (reg)); \
  7783. __GET_REG32((reg)); \
  7784. } while (0)
  7785. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  7786. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  7787. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  7788. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  7789. GET_REG32_1(SNDDATAC_MODE);
  7790. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  7791. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  7792. GET_REG32_1(SNDBDC_MODE);
  7793. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  7794. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  7795. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  7796. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  7797. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  7798. GET_REG32_1(RCVDCC_MODE);
  7799. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  7800. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  7801. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  7802. GET_REG32_1(MBFREE_MODE);
  7803. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  7804. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  7805. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  7806. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  7807. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  7808. GET_REG32_1(RX_CPU_MODE);
  7809. GET_REG32_1(RX_CPU_STATE);
  7810. GET_REG32_1(RX_CPU_PGMCTR);
  7811. GET_REG32_1(RX_CPU_HWBKPT);
  7812. GET_REG32_1(TX_CPU_MODE);
  7813. GET_REG32_1(TX_CPU_STATE);
  7814. GET_REG32_1(TX_CPU_PGMCTR);
  7815. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  7816. GET_REG32_LOOP(FTQ_RESET, 0x120);
  7817. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  7818. GET_REG32_1(DMAC_MODE);
  7819. GET_REG32_LOOP(GRC_MODE, 0x4c);
  7820. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  7821. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  7822. #undef __GET_REG32
  7823. #undef GET_REG32_LOOP
  7824. #undef GET_REG32_1
  7825. tg3_full_unlock(tp);
  7826. }
  7827. static int tg3_get_eeprom_len(struct net_device *dev)
  7828. {
  7829. struct tg3 *tp = netdev_priv(dev);
  7830. return tp->nvram_size;
  7831. }
  7832. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7833. {
  7834. struct tg3 *tp = netdev_priv(dev);
  7835. int ret;
  7836. u8 *pd;
  7837. u32 i, offset, len, b_offset, b_count;
  7838. __be32 val;
  7839. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
  7840. return -EINVAL;
  7841. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  7842. return -EAGAIN;
  7843. offset = eeprom->offset;
  7844. len = eeprom->len;
  7845. eeprom->len = 0;
  7846. eeprom->magic = TG3_EEPROM_MAGIC;
  7847. if (offset & 3) {
  7848. /* adjustments to start on required 4 byte boundary */
  7849. b_offset = offset & 3;
  7850. b_count = 4 - b_offset;
  7851. if (b_count > len) {
  7852. /* i.e. offset=1 len=2 */
  7853. b_count = len;
  7854. }
  7855. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  7856. if (ret)
  7857. return ret;
  7858. memcpy(data, ((char *)&val) + b_offset, b_count);
  7859. len -= b_count;
  7860. offset += b_count;
  7861. eeprom->len += b_count;
  7862. }
  7863. /* read bytes upto the last 4 byte boundary */
  7864. pd = &data[eeprom->len];
  7865. for (i = 0; i < (len - (len & 3)); i += 4) {
  7866. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  7867. if (ret) {
  7868. eeprom->len += i;
  7869. return ret;
  7870. }
  7871. memcpy(pd + i, &val, 4);
  7872. }
  7873. eeprom->len += i;
  7874. if (len & 3) {
  7875. /* read last bytes not ending on 4 byte boundary */
  7876. pd = &data[eeprom->len];
  7877. b_count = len & 3;
  7878. b_offset = offset + len - b_count;
  7879. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  7880. if (ret)
  7881. return ret;
  7882. memcpy(pd, &val, b_count);
  7883. eeprom->len += b_count;
  7884. }
  7885. return 0;
  7886. }
  7887. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  7888. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7889. {
  7890. struct tg3 *tp = netdev_priv(dev);
  7891. int ret;
  7892. u32 offset, len, b_offset, odd_len;
  7893. u8 *buf;
  7894. __be32 start, end;
  7895. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  7896. return -EAGAIN;
  7897. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  7898. eeprom->magic != TG3_EEPROM_MAGIC)
  7899. return -EINVAL;
  7900. offset = eeprom->offset;
  7901. len = eeprom->len;
  7902. if ((b_offset = (offset & 3))) {
  7903. /* adjustments to start on required 4 byte boundary */
  7904. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  7905. if (ret)
  7906. return ret;
  7907. len += b_offset;
  7908. offset &= ~3;
  7909. if (len < 4)
  7910. len = 4;
  7911. }
  7912. odd_len = 0;
  7913. if (len & 3) {
  7914. /* adjustments to end on required 4 byte boundary */
  7915. odd_len = 1;
  7916. len = (len + 3) & ~3;
  7917. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  7918. if (ret)
  7919. return ret;
  7920. }
  7921. buf = data;
  7922. if (b_offset || odd_len) {
  7923. buf = kmalloc(len, GFP_KERNEL);
  7924. if (!buf)
  7925. return -ENOMEM;
  7926. if (b_offset)
  7927. memcpy(buf, &start, 4);
  7928. if (odd_len)
  7929. memcpy(buf+len-4, &end, 4);
  7930. memcpy(buf + b_offset, data, eeprom->len);
  7931. }
  7932. ret = tg3_nvram_write_block(tp, offset, len, buf);
  7933. if (buf != data)
  7934. kfree(buf);
  7935. return ret;
  7936. }
  7937. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7938. {
  7939. struct tg3 *tp = netdev_priv(dev);
  7940. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7941. struct phy_device *phydev;
  7942. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  7943. return -EAGAIN;
  7944. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  7945. return phy_ethtool_gset(phydev, cmd);
  7946. }
  7947. cmd->supported = (SUPPORTED_Autoneg);
  7948. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  7949. cmd->supported |= (SUPPORTED_1000baseT_Half |
  7950. SUPPORTED_1000baseT_Full);
  7951. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  7952. cmd->supported |= (SUPPORTED_100baseT_Half |
  7953. SUPPORTED_100baseT_Full |
  7954. SUPPORTED_10baseT_Half |
  7955. SUPPORTED_10baseT_Full |
  7956. SUPPORTED_TP);
  7957. cmd->port = PORT_TP;
  7958. } else {
  7959. cmd->supported |= SUPPORTED_FIBRE;
  7960. cmd->port = PORT_FIBRE;
  7961. }
  7962. cmd->advertising = tp->link_config.advertising;
  7963. if (netif_running(dev)) {
  7964. cmd->speed = tp->link_config.active_speed;
  7965. cmd->duplex = tp->link_config.active_duplex;
  7966. }
  7967. cmd->phy_address = tp->phy_addr;
  7968. cmd->transceiver = XCVR_INTERNAL;
  7969. cmd->autoneg = tp->link_config.autoneg;
  7970. cmd->maxtxpkt = 0;
  7971. cmd->maxrxpkt = 0;
  7972. return 0;
  7973. }
  7974. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7975. {
  7976. struct tg3 *tp = netdev_priv(dev);
  7977. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  7978. struct phy_device *phydev;
  7979. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  7980. return -EAGAIN;
  7981. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  7982. return phy_ethtool_sset(phydev, cmd);
  7983. }
  7984. if (cmd->autoneg != AUTONEG_ENABLE &&
  7985. cmd->autoneg != AUTONEG_DISABLE)
  7986. return -EINVAL;
  7987. if (cmd->autoneg == AUTONEG_DISABLE &&
  7988. cmd->duplex != DUPLEX_FULL &&
  7989. cmd->duplex != DUPLEX_HALF)
  7990. return -EINVAL;
  7991. if (cmd->autoneg == AUTONEG_ENABLE) {
  7992. u32 mask = ADVERTISED_Autoneg |
  7993. ADVERTISED_Pause |
  7994. ADVERTISED_Asym_Pause;
  7995. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  7996. mask |= ADVERTISED_1000baseT_Half |
  7997. ADVERTISED_1000baseT_Full;
  7998. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  7999. mask |= ADVERTISED_100baseT_Half |
  8000. ADVERTISED_100baseT_Full |
  8001. ADVERTISED_10baseT_Half |
  8002. ADVERTISED_10baseT_Full |
  8003. ADVERTISED_TP;
  8004. else
  8005. mask |= ADVERTISED_FIBRE;
  8006. if (cmd->advertising & ~mask)
  8007. return -EINVAL;
  8008. mask &= (ADVERTISED_1000baseT_Half |
  8009. ADVERTISED_1000baseT_Full |
  8010. ADVERTISED_100baseT_Half |
  8011. ADVERTISED_100baseT_Full |
  8012. ADVERTISED_10baseT_Half |
  8013. ADVERTISED_10baseT_Full);
  8014. cmd->advertising &= mask;
  8015. } else {
  8016. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
  8017. if (cmd->speed != SPEED_1000)
  8018. return -EINVAL;
  8019. if (cmd->duplex != DUPLEX_FULL)
  8020. return -EINVAL;
  8021. } else {
  8022. if (cmd->speed != SPEED_100 &&
  8023. cmd->speed != SPEED_10)
  8024. return -EINVAL;
  8025. }
  8026. }
  8027. tg3_full_lock(tp, 0);
  8028. tp->link_config.autoneg = cmd->autoneg;
  8029. if (cmd->autoneg == AUTONEG_ENABLE) {
  8030. tp->link_config.advertising = (cmd->advertising |
  8031. ADVERTISED_Autoneg);
  8032. tp->link_config.speed = SPEED_INVALID;
  8033. tp->link_config.duplex = DUPLEX_INVALID;
  8034. } else {
  8035. tp->link_config.advertising = 0;
  8036. tp->link_config.speed = cmd->speed;
  8037. tp->link_config.duplex = cmd->duplex;
  8038. }
  8039. tp->link_config.orig_speed = tp->link_config.speed;
  8040. tp->link_config.orig_duplex = tp->link_config.duplex;
  8041. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  8042. if (netif_running(dev))
  8043. tg3_setup_phy(tp, 1);
  8044. tg3_full_unlock(tp);
  8045. return 0;
  8046. }
  8047. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  8048. {
  8049. struct tg3 *tp = netdev_priv(dev);
  8050. strcpy(info->driver, DRV_MODULE_NAME);
  8051. strcpy(info->version, DRV_MODULE_VERSION);
  8052. strcpy(info->fw_version, tp->fw_ver);
  8053. strcpy(info->bus_info, pci_name(tp->pdev));
  8054. }
  8055. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8056. {
  8057. struct tg3 *tp = netdev_priv(dev);
  8058. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  8059. device_can_wakeup(&tp->pdev->dev))
  8060. wol->supported = WAKE_MAGIC;
  8061. else
  8062. wol->supported = 0;
  8063. wol->wolopts = 0;
  8064. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  8065. device_can_wakeup(&tp->pdev->dev))
  8066. wol->wolopts = WAKE_MAGIC;
  8067. memset(&wol->sopass, 0, sizeof(wol->sopass));
  8068. }
  8069. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8070. {
  8071. struct tg3 *tp = netdev_priv(dev);
  8072. struct device *dp = &tp->pdev->dev;
  8073. if (wol->wolopts & ~WAKE_MAGIC)
  8074. return -EINVAL;
  8075. if ((wol->wolopts & WAKE_MAGIC) &&
  8076. !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
  8077. return -EINVAL;
  8078. spin_lock_bh(&tp->lock);
  8079. if (wol->wolopts & WAKE_MAGIC) {
  8080. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  8081. device_set_wakeup_enable(dp, true);
  8082. } else {
  8083. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  8084. device_set_wakeup_enable(dp, false);
  8085. }
  8086. spin_unlock_bh(&tp->lock);
  8087. return 0;
  8088. }
  8089. static u32 tg3_get_msglevel(struct net_device *dev)
  8090. {
  8091. struct tg3 *tp = netdev_priv(dev);
  8092. return tp->msg_enable;
  8093. }
  8094. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  8095. {
  8096. struct tg3 *tp = netdev_priv(dev);
  8097. tp->msg_enable = value;
  8098. }
  8099. static int tg3_set_tso(struct net_device *dev, u32 value)
  8100. {
  8101. struct tg3 *tp = netdev_priv(dev);
  8102. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  8103. if (value)
  8104. return -EINVAL;
  8105. return 0;
  8106. }
  8107. if ((dev->features & NETIF_F_IPV6_CSUM) &&
  8108. ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
  8109. (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
  8110. if (value) {
  8111. dev->features |= NETIF_F_TSO6;
  8112. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  8113. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  8114. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  8115. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  8116. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  8117. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  8118. dev->features |= NETIF_F_TSO_ECN;
  8119. } else
  8120. dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
  8121. }
  8122. return ethtool_op_set_tso(dev, value);
  8123. }
  8124. static int tg3_nway_reset(struct net_device *dev)
  8125. {
  8126. struct tg3 *tp = netdev_priv(dev);
  8127. int r;
  8128. if (!netif_running(dev))
  8129. return -EAGAIN;
  8130. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  8131. return -EINVAL;
  8132. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8133. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  8134. return -EAGAIN;
  8135. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  8136. } else {
  8137. u32 bmcr;
  8138. spin_lock_bh(&tp->lock);
  8139. r = -EINVAL;
  8140. tg3_readphy(tp, MII_BMCR, &bmcr);
  8141. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  8142. ((bmcr & BMCR_ANENABLE) ||
  8143. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
  8144. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  8145. BMCR_ANENABLE);
  8146. r = 0;
  8147. }
  8148. spin_unlock_bh(&tp->lock);
  8149. }
  8150. return r;
  8151. }
  8152. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8153. {
  8154. struct tg3 *tp = netdev_priv(dev);
  8155. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  8156. ering->rx_mini_max_pending = 0;
  8157. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  8158. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  8159. else
  8160. ering->rx_jumbo_max_pending = 0;
  8161. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  8162. ering->rx_pending = tp->rx_pending;
  8163. ering->rx_mini_pending = 0;
  8164. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  8165. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  8166. else
  8167. ering->rx_jumbo_pending = 0;
  8168. ering->tx_pending = tp->napi[0].tx_pending;
  8169. }
  8170. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8171. {
  8172. struct tg3 *tp = netdev_priv(dev);
  8173. int i, irq_sync = 0, err = 0;
  8174. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  8175. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  8176. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  8177. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  8178. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  8179. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  8180. return -EINVAL;
  8181. if (netif_running(dev)) {
  8182. tg3_phy_stop(tp);
  8183. tg3_netif_stop(tp);
  8184. irq_sync = 1;
  8185. }
  8186. tg3_full_lock(tp, irq_sync);
  8187. tp->rx_pending = ering->rx_pending;
  8188. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  8189. tp->rx_pending > 63)
  8190. tp->rx_pending = 63;
  8191. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  8192. for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
  8193. tp->napi[i].tx_pending = ering->tx_pending;
  8194. if (netif_running(dev)) {
  8195. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8196. err = tg3_restart_hw(tp, 1);
  8197. if (!err)
  8198. tg3_netif_start(tp);
  8199. }
  8200. tg3_full_unlock(tp);
  8201. if (irq_sync && !err)
  8202. tg3_phy_start(tp);
  8203. return err;
  8204. }
  8205. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8206. {
  8207. struct tg3 *tp = netdev_priv(dev);
  8208. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  8209. if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
  8210. epause->rx_pause = 1;
  8211. else
  8212. epause->rx_pause = 0;
  8213. if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
  8214. epause->tx_pause = 1;
  8215. else
  8216. epause->tx_pause = 0;
  8217. }
  8218. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8219. {
  8220. struct tg3 *tp = netdev_priv(dev);
  8221. int err = 0;
  8222. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8223. u32 newadv;
  8224. struct phy_device *phydev;
  8225. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8226. if (!(phydev->supported & SUPPORTED_Pause) ||
  8227. (!(phydev->supported & SUPPORTED_Asym_Pause) &&
  8228. ((epause->rx_pause && !epause->tx_pause) ||
  8229. (!epause->rx_pause && epause->tx_pause))))
  8230. return -EINVAL;
  8231. tp->link_config.flowctrl = 0;
  8232. if (epause->rx_pause) {
  8233. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8234. if (epause->tx_pause) {
  8235. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8236. newadv = ADVERTISED_Pause;
  8237. } else
  8238. newadv = ADVERTISED_Pause |
  8239. ADVERTISED_Asym_Pause;
  8240. } else if (epause->tx_pause) {
  8241. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8242. newadv = ADVERTISED_Asym_Pause;
  8243. } else
  8244. newadv = 0;
  8245. if (epause->autoneg)
  8246. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  8247. else
  8248. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  8249. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  8250. u32 oldadv = phydev->advertising &
  8251. (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
  8252. if (oldadv != newadv) {
  8253. phydev->advertising &=
  8254. ~(ADVERTISED_Pause |
  8255. ADVERTISED_Asym_Pause);
  8256. phydev->advertising |= newadv;
  8257. if (phydev->autoneg) {
  8258. /*
  8259. * Always renegotiate the link to
  8260. * inform our link partner of our
  8261. * flow control settings, even if the
  8262. * flow control is forced. Let
  8263. * tg3_adjust_link() do the final
  8264. * flow control setup.
  8265. */
  8266. return phy_start_aneg(phydev);
  8267. }
  8268. }
  8269. if (!epause->autoneg)
  8270. tg3_setup_flow_control(tp, 0, 0);
  8271. } else {
  8272. tp->link_config.orig_advertising &=
  8273. ~(ADVERTISED_Pause |
  8274. ADVERTISED_Asym_Pause);
  8275. tp->link_config.orig_advertising |= newadv;
  8276. }
  8277. } else {
  8278. int irq_sync = 0;
  8279. if (netif_running(dev)) {
  8280. tg3_netif_stop(tp);
  8281. irq_sync = 1;
  8282. }
  8283. tg3_full_lock(tp, irq_sync);
  8284. if (epause->autoneg)
  8285. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  8286. else
  8287. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  8288. if (epause->rx_pause)
  8289. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8290. else
  8291. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  8292. if (epause->tx_pause)
  8293. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8294. else
  8295. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  8296. if (netif_running(dev)) {
  8297. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8298. err = tg3_restart_hw(tp, 1);
  8299. if (!err)
  8300. tg3_netif_start(tp);
  8301. }
  8302. tg3_full_unlock(tp);
  8303. }
  8304. return err;
  8305. }
  8306. static u32 tg3_get_rx_csum(struct net_device *dev)
  8307. {
  8308. struct tg3 *tp = netdev_priv(dev);
  8309. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  8310. }
  8311. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  8312. {
  8313. struct tg3 *tp = netdev_priv(dev);
  8314. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  8315. if (data != 0)
  8316. return -EINVAL;
  8317. return 0;
  8318. }
  8319. spin_lock_bh(&tp->lock);
  8320. if (data)
  8321. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  8322. else
  8323. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  8324. spin_unlock_bh(&tp->lock);
  8325. return 0;
  8326. }
  8327. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  8328. {
  8329. struct tg3 *tp = netdev_priv(dev);
  8330. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  8331. if (data != 0)
  8332. return -EINVAL;
  8333. return 0;
  8334. }
  8335. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  8336. ethtool_op_set_tx_ipv6_csum(dev, data);
  8337. else
  8338. ethtool_op_set_tx_csum(dev, data);
  8339. return 0;
  8340. }
  8341. static int tg3_get_sset_count(struct net_device *dev, int sset)
  8342. {
  8343. switch (sset) {
  8344. case ETH_SS_TEST:
  8345. return TG3_NUM_TEST;
  8346. case ETH_SS_STATS:
  8347. return TG3_NUM_STATS;
  8348. default:
  8349. return -EOPNOTSUPP;
  8350. }
  8351. }
  8352. static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  8353. {
  8354. switch (stringset) {
  8355. case ETH_SS_STATS:
  8356. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  8357. break;
  8358. case ETH_SS_TEST:
  8359. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  8360. break;
  8361. default:
  8362. WARN_ON(1); /* we need a WARN() */
  8363. break;
  8364. }
  8365. }
  8366. static int tg3_phys_id(struct net_device *dev, u32 data)
  8367. {
  8368. struct tg3 *tp = netdev_priv(dev);
  8369. int i;
  8370. if (!netif_running(tp->dev))
  8371. return -EAGAIN;
  8372. if (data == 0)
  8373. data = UINT_MAX / 2;
  8374. for (i = 0; i < (data * 2); i++) {
  8375. if ((i % 2) == 0)
  8376. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8377. LED_CTRL_1000MBPS_ON |
  8378. LED_CTRL_100MBPS_ON |
  8379. LED_CTRL_10MBPS_ON |
  8380. LED_CTRL_TRAFFIC_OVERRIDE |
  8381. LED_CTRL_TRAFFIC_BLINK |
  8382. LED_CTRL_TRAFFIC_LED);
  8383. else
  8384. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8385. LED_CTRL_TRAFFIC_OVERRIDE);
  8386. if (msleep_interruptible(500))
  8387. break;
  8388. }
  8389. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8390. return 0;
  8391. }
  8392. static void tg3_get_ethtool_stats(struct net_device *dev,
  8393. struct ethtool_stats *estats, u64 *tmp_stats)
  8394. {
  8395. struct tg3 *tp = netdev_priv(dev);
  8396. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  8397. }
  8398. #define NVRAM_TEST_SIZE 0x100
  8399. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  8400. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  8401. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  8402. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  8403. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  8404. static int tg3_test_nvram(struct tg3 *tp)
  8405. {
  8406. u32 csum, magic;
  8407. __be32 *buf;
  8408. int i, j, k, err = 0, size;
  8409. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
  8410. return 0;
  8411. if (tg3_nvram_read(tp, 0, &magic) != 0)
  8412. return -EIO;
  8413. if (magic == TG3_EEPROM_MAGIC)
  8414. size = NVRAM_TEST_SIZE;
  8415. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  8416. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  8417. TG3_EEPROM_SB_FORMAT_1) {
  8418. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  8419. case TG3_EEPROM_SB_REVISION_0:
  8420. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  8421. break;
  8422. case TG3_EEPROM_SB_REVISION_2:
  8423. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  8424. break;
  8425. case TG3_EEPROM_SB_REVISION_3:
  8426. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  8427. break;
  8428. default:
  8429. return 0;
  8430. }
  8431. } else
  8432. return 0;
  8433. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  8434. size = NVRAM_SELFBOOT_HW_SIZE;
  8435. else
  8436. return -EIO;
  8437. buf = kmalloc(size, GFP_KERNEL);
  8438. if (buf == NULL)
  8439. return -ENOMEM;
  8440. err = -EIO;
  8441. for (i = 0, j = 0; i < size; i += 4, j++) {
  8442. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  8443. if (err)
  8444. break;
  8445. }
  8446. if (i < size)
  8447. goto out;
  8448. /* Selfboot format */
  8449. magic = be32_to_cpu(buf[0]);
  8450. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  8451. TG3_EEPROM_MAGIC_FW) {
  8452. u8 *buf8 = (u8 *) buf, csum8 = 0;
  8453. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  8454. TG3_EEPROM_SB_REVISION_2) {
  8455. /* For rev 2, the csum doesn't include the MBA. */
  8456. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  8457. csum8 += buf8[i];
  8458. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  8459. csum8 += buf8[i];
  8460. } else {
  8461. for (i = 0; i < size; i++)
  8462. csum8 += buf8[i];
  8463. }
  8464. if (csum8 == 0) {
  8465. err = 0;
  8466. goto out;
  8467. }
  8468. err = -EIO;
  8469. goto out;
  8470. }
  8471. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  8472. TG3_EEPROM_MAGIC_HW) {
  8473. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  8474. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  8475. u8 *buf8 = (u8 *) buf;
  8476. /* Separate the parity bits and the data bytes. */
  8477. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  8478. if ((i == 0) || (i == 8)) {
  8479. int l;
  8480. u8 msk;
  8481. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  8482. parity[k++] = buf8[i] & msk;
  8483. i++;
  8484. } else if (i == 16) {
  8485. int l;
  8486. u8 msk;
  8487. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  8488. parity[k++] = buf8[i] & msk;
  8489. i++;
  8490. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  8491. parity[k++] = buf8[i] & msk;
  8492. i++;
  8493. }
  8494. data[j++] = buf8[i];
  8495. }
  8496. err = -EIO;
  8497. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  8498. u8 hw8 = hweight8(data[i]);
  8499. if ((hw8 & 0x1) && parity[i])
  8500. goto out;
  8501. else if (!(hw8 & 0x1) && !parity[i])
  8502. goto out;
  8503. }
  8504. err = 0;
  8505. goto out;
  8506. }
  8507. /* Bootstrap checksum at offset 0x10 */
  8508. csum = calc_crc((unsigned char *) buf, 0x10);
  8509. if (csum != be32_to_cpu(buf[0x10/4]))
  8510. goto out;
  8511. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  8512. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  8513. if (csum != be32_to_cpu(buf[0xfc/4]))
  8514. goto out;
  8515. err = 0;
  8516. out:
  8517. kfree(buf);
  8518. return err;
  8519. }
  8520. #define TG3_SERDES_TIMEOUT_SEC 2
  8521. #define TG3_COPPER_TIMEOUT_SEC 6
  8522. static int tg3_test_link(struct tg3 *tp)
  8523. {
  8524. int i, max;
  8525. if (!netif_running(tp->dev))
  8526. return -ENODEV;
  8527. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  8528. max = TG3_SERDES_TIMEOUT_SEC;
  8529. else
  8530. max = TG3_COPPER_TIMEOUT_SEC;
  8531. for (i = 0; i < max; i++) {
  8532. if (netif_carrier_ok(tp->dev))
  8533. return 0;
  8534. if (msleep_interruptible(1000))
  8535. break;
  8536. }
  8537. return -EIO;
  8538. }
  8539. /* Only test the commonly used registers */
  8540. static int tg3_test_registers(struct tg3 *tp)
  8541. {
  8542. int i, is_5705, is_5750;
  8543. u32 offset, read_mask, write_mask, val, save_val, read_val;
  8544. static struct {
  8545. u16 offset;
  8546. u16 flags;
  8547. #define TG3_FL_5705 0x1
  8548. #define TG3_FL_NOT_5705 0x2
  8549. #define TG3_FL_NOT_5788 0x4
  8550. #define TG3_FL_NOT_5750 0x8
  8551. u32 read_mask;
  8552. u32 write_mask;
  8553. } reg_tbl[] = {
  8554. /* MAC Control Registers */
  8555. { MAC_MODE, TG3_FL_NOT_5705,
  8556. 0x00000000, 0x00ef6f8c },
  8557. { MAC_MODE, TG3_FL_5705,
  8558. 0x00000000, 0x01ef6b8c },
  8559. { MAC_STATUS, TG3_FL_NOT_5705,
  8560. 0x03800107, 0x00000000 },
  8561. { MAC_STATUS, TG3_FL_5705,
  8562. 0x03800100, 0x00000000 },
  8563. { MAC_ADDR_0_HIGH, 0x0000,
  8564. 0x00000000, 0x0000ffff },
  8565. { MAC_ADDR_0_LOW, 0x0000,
  8566. 0x00000000, 0xffffffff },
  8567. { MAC_RX_MTU_SIZE, 0x0000,
  8568. 0x00000000, 0x0000ffff },
  8569. { MAC_TX_MODE, 0x0000,
  8570. 0x00000000, 0x00000070 },
  8571. { MAC_TX_LENGTHS, 0x0000,
  8572. 0x00000000, 0x00003fff },
  8573. { MAC_RX_MODE, TG3_FL_NOT_5705,
  8574. 0x00000000, 0x000007fc },
  8575. { MAC_RX_MODE, TG3_FL_5705,
  8576. 0x00000000, 0x000007dc },
  8577. { MAC_HASH_REG_0, 0x0000,
  8578. 0x00000000, 0xffffffff },
  8579. { MAC_HASH_REG_1, 0x0000,
  8580. 0x00000000, 0xffffffff },
  8581. { MAC_HASH_REG_2, 0x0000,
  8582. 0x00000000, 0xffffffff },
  8583. { MAC_HASH_REG_3, 0x0000,
  8584. 0x00000000, 0xffffffff },
  8585. /* Receive Data and Receive BD Initiator Control Registers. */
  8586. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  8587. 0x00000000, 0xffffffff },
  8588. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  8589. 0x00000000, 0xffffffff },
  8590. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  8591. 0x00000000, 0x00000003 },
  8592. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  8593. 0x00000000, 0xffffffff },
  8594. { RCVDBDI_STD_BD+0, 0x0000,
  8595. 0x00000000, 0xffffffff },
  8596. { RCVDBDI_STD_BD+4, 0x0000,
  8597. 0x00000000, 0xffffffff },
  8598. { RCVDBDI_STD_BD+8, 0x0000,
  8599. 0x00000000, 0xffff0002 },
  8600. { RCVDBDI_STD_BD+0xc, 0x0000,
  8601. 0x00000000, 0xffffffff },
  8602. /* Receive BD Initiator Control Registers. */
  8603. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  8604. 0x00000000, 0xffffffff },
  8605. { RCVBDI_STD_THRESH, TG3_FL_5705,
  8606. 0x00000000, 0x000003ff },
  8607. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  8608. 0x00000000, 0xffffffff },
  8609. /* Host Coalescing Control Registers. */
  8610. { HOSTCC_MODE, TG3_FL_NOT_5705,
  8611. 0x00000000, 0x00000004 },
  8612. { HOSTCC_MODE, TG3_FL_5705,
  8613. 0x00000000, 0x000000f6 },
  8614. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  8615. 0x00000000, 0xffffffff },
  8616. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  8617. 0x00000000, 0x000003ff },
  8618. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  8619. 0x00000000, 0xffffffff },
  8620. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  8621. 0x00000000, 0x000003ff },
  8622. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  8623. 0x00000000, 0xffffffff },
  8624. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8625. 0x00000000, 0x000000ff },
  8626. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  8627. 0x00000000, 0xffffffff },
  8628. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8629. 0x00000000, 0x000000ff },
  8630. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8631. 0x00000000, 0xffffffff },
  8632. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8633. 0x00000000, 0xffffffff },
  8634. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8635. 0x00000000, 0xffffffff },
  8636. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8637. 0x00000000, 0x000000ff },
  8638. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8639. 0x00000000, 0xffffffff },
  8640. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8641. 0x00000000, 0x000000ff },
  8642. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  8643. 0x00000000, 0xffffffff },
  8644. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  8645. 0x00000000, 0xffffffff },
  8646. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  8647. 0x00000000, 0xffffffff },
  8648. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  8649. 0x00000000, 0xffffffff },
  8650. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  8651. 0x00000000, 0xffffffff },
  8652. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  8653. 0xffffffff, 0x00000000 },
  8654. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  8655. 0xffffffff, 0x00000000 },
  8656. /* Buffer Manager Control Registers. */
  8657. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  8658. 0x00000000, 0x007fff80 },
  8659. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  8660. 0x00000000, 0x007fffff },
  8661. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  8662. 0x00000000, 0x0000003f },
  8663. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  8664. 0x00000000, 0x000001ff },
  8665. { BUFMGR_MB_HIGH_WATER, 0x0000,
  8666. 0x00000000, 0x000001ff },
  8667. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  8668. 0xffffffff, 0x00000000 },
  8669. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  8670. 0xffffffff, 0x00000000 },
  8671. /* Mailbox Registers */
  8672. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  8673. 0x00000000, 0x000001ff },
  8674. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  8675. 0x00000000, 0x000001ff },
  8676. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  8677. 0x00000000, 0x000007ff },
  8678. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  8679. 0x00000000, 0x000001ff },
  8680. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  8681. };
  8682. is_5705 = is_5750 = 0;
  8683. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  8684. is_5705 = 1;
  8685. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8686. is_5750 = 1;
  8687. }
  8688. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  8689. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  8690. continue;
  8691. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  8692. continue;
  8693. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  8694. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  8695. continue;
  8696. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  8697. continue;
  8698. offset = (u32) reg_tbl[i].offset;
  8699. read_mask = reg_tbl[i].read_mask;
  8700. write_mask = reg_tbl[i].write_mask;
  8701. /* Save the original register content */
  8702. save_val = tr32(offset);
  8703. /* Determine the read-only value. */
  8704. read_val = save_val & read_mask;
  8705. /* Write zero to the register, then make sure the read-only bits
  8706. * are not changed and the read/write bits are all zeros.
  8707. */
  8708. tw32(offset, 0);
  8709. val = tr32(offset);
  8710. /* Test the read-only and read/write bits. */
  8711. if (((val & read_mask) != read_val) || (val & write_mask))
  8712. goto out;
  8713. /* Write ones to all the bits defined by RdMask and WrMask, then
  8714. * make sure the read-only bits are not changed and the
  8715. * read/write bits are all ones.
  8716. */
  8717. tw32(offset, read_mask | write_mask);
  8718. val = tr32(offset);
  8719. /* Test the read-only bits. */
  8720. if ((val & read_mask) != read_val)
  8721. goto out;
  8722. /* Test the read/write bits. */
  8723. if ((val & write_mask) != write_mask)
  8724. goto out;
  8725. tw32(offset, save_val);
  8726. }
  8727. return 0;
  8728. out:
  8729. if (netif_msg_hw(tp))
  8730. netdev_err(tp->dev,
  8731. "Register test failed at offset %x\n", offset);
  8732. tw32(offset, save_val);
  8733. return -EIO;
  8734. }
  8735. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  8736. {
  8737. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  8738. int i;
  8739. u32 j;
  8740. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  8741. for (j = 0; j < len; j += 4) {
  8742. u32 val;
  8743. tg3_write_mem(tp, offset + j, test_pattern[i]);
  8744. tg3_read_mem(tp, offset + j, &val);
  8745. if (val != test_pattern[i])
  8746. return -EIO;
  8747. }
  8748. }
  8749. return 0;
  8750. }
  8751. static int tg3_test_memory(struct tg3 *tp)
  8752. {
  8753. static struct mem_entry {
  8754. u32 offset;
  8755. u32 len;
  8756. } mem_tbl_570x[] = {
  8757. { 0x00000000, 0x00b50},
  8758. { 0x00002000, 0x1c000},
  8759. { 0xffffffff, 0x00000}
  8760. }, mem_tbl_5705[] = {
  8761. { 0x00000100, 0x0000c},
  8762. { 0x00000200, 0x00008},
  8763. { 0x00004000, 0x00800},
  8764. { 0x00006000, 0x01000},
  8765. { 0x00008000, 0x02000},
  8766. { 0x00010000, 0x0e000},
  8767. { 0xffffffff, 0x00000}
  8768. }, mem_tbl_5755[] = {
  8769. { 0x00000200, 0x00008},
  8770. { 0x00004000, 0x00800},
  8771. { 0x00006000, 0x00800},
  8772. { 0x00008000, 0x02000},
  8773. { 0x00010000, 0x0c000},
  8774. { 0xffffffff, 0x00000}
  8775. }, mem_tbl_5906[] = {
  8776. { 0x00000200, 0x00008},
  8777. { 0x00004000, 0x00400},
  8778. { 0x00006000, 0x00400},
  8779. { 0x00008000, 0x01000},
  8780. { 0x00010000, 0x01000},
  8781. { 0xffffffff, 0x00000}
  8782. }, mem_tbl_5717[] = {
  8783. { 0x00000200, 0x00008},
  8784. { 0x00010000, 0x0a000},
  8785. { 0x00020000, 0x13c00},
  8786. { 0xffffffff, 0x00000}
  8787. }, mem_tbl_57765[] = {
  8788. { 0x00000200, 0x00008},
  8789. { 0x00004000, 0x00800},
  8790. { 0x00006000, 0x09800},
  8791. { 0x00010000, 0x0a000},
  8792. { 0xffffffff, 0x00000}
  8793. };
  8794. struct mem_entry *mem_tbl;
  8795. int err = 0;
  8796. int i;
  8797. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  8798. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  8799. mem_tbl = mem_tbl_5717;
  8800. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  8801. mem_tbl = mem_tbl_57765;
  8802. else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  8803. mem_tbl = mem_tbl_5755;
  8804. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8805. mem_tbl = mem_tbl_5906;
  8806. else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  8807. mem_tbl = mem_tbl_5705;
  8808. else
  8809. mem_tbl = mem_tbl_570x;
  8810. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  8811. err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
  8812. if (err)
  8813. break;
  8814. }
  8815. return err;
  8816. }
  8817. #define TG3_MAC_LOOPBACK 0
  8818. #define TG3_PHY_LOOPBACK 1
  8819. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  8820. {
  8821. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  8822. u32 desc_idx, coal_now;
  8823. struct sk_buff *skb, *rx_skb;
  8824. u8 *tx_data;
  8825. dma_addr_t map;
  8826. int num_pkts, tx_len, rx_len, i, err;
  8827. struct tg3_rx_buffer_desc *desc;
  8828. struct tg3_napi *tnapi, *rnapi;
  8829. struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
  8830. tnapi = &tp->napi[0];
  8831. rnapi = &tp->napi[0];
  8832. if (tp->irq_cnt > 1) {
  8833. rnapi = &tp->napi[1];
  8834. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  8835. tnapi = &tp->napi[1];
  8836. }
  8837. coal_now = tnapi->coal_now | rnapi->coal_now;
  8838. if (loopback_mode == TG3_MAC_LOOPBACK) {
  8839. /* HW errata - mac loopback fails in some cases on 5780.
  8840. * Normal traffic and PHY loopback are not affected by
  8841. * errata.
  8842. */
  8843. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  8844. return 0;
  8845. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  8846. MAC_MODE_PORT_INT_LPBACK;
  8847. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8848. mac_mode |= MAC_MODE_LINK_POLARITY;
  8849. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  8850. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8851. else
  8852. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8853. tw32(MAC_MODE, mac_mode);
  8854. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  8855. u32 val;
  8856. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  8857. tg3_phy_fet_toggle_apd(tp, false);
  8858. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  8859. } else
  8860. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  8861. tg3_phy_toggle_automdix(tp, 0);
  8862. tg3_writephy(tp, MII_BMCR, val);
  8863. udelay(40);
  8864. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  8865. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  8866. tg3_writephy(tp, MII_TG3_FET_PTEST,
  8867. MII_TG3_FET_PTEST_FRC_TX_LINK |
  8868. MII_TG3_FET_PTEST_FRC_TX_LOCK);
  8869. /* The write needs to be flushed for the AC131 */
  8870. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  8871. tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
  8872. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8873. } else
  8874. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8875. /* reset to prevent losing 1st rx packet intermittently */
  8876. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  8877. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8878. udelay(10);
  8879. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8880. }
  8881. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  8882. u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
  8883. if (masked_phy_id == TG3_PHY_ID_BCM5401)
  8884. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  8885. else if (masked_phy_id == TG3_PHY_ID_BCM5411)
  8886. mac_mode |= MAC_MODE_LINK_POLARITY;
  8887. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  8888. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  8889. }
  8890. tw32(MAC_MODE, mac_mode);
  8891. } else {
  8892. return -EINVAL;
  8893. }
  8894. err = -EIO;
  8895. tx_len = 1514;
  8896. skb = netdev_alloc_skb(tp->dev, tx_len);
  8897. if (!skb)
  8898. return -ENOMEM;
  8899. tx_data = skb_put(skb, tx_len);
  8900. memcpy(tx_data, tp->dev->dev_addr, 6);
  8901. memset(tx_data + 6, 0x0, 8);
  8902. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  8903. for (i = 14; i < tx_len; i++)
  8904. tx_data[i] = (u8) (i & 0xff);
  8905. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  8906. if (pci_dma_mapping_error(tp->pdev, map)) {
  8907. dev_kfree_skb(skb);
  8908. return -EIO;
  8909. }
  8910. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8911. rnapi->coal_now);
  8912. udelay(10);
  8913. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  8914. num_pkts = 0;
  8915. tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
  8916. tnapi->tx_prod++;
  8917. num_pkts++;
  8918. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  8919. tr32_mailbox(tnapi->prodmbox);
  8920. udelay(10);
  8921. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  8922. for (i = 0; i < 35; i++) {
  8923. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8924. coal_now);
  8925. udelay(10);
  8926. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  8927. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  8928. if ((tx_idx == tnapi->tx_prod) &&
  8929. (rx_idx == (rx_start_idx + num_pkts)))
  8930. break;
  8931. }
  8932. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  8933. dev_kfree_skb(skb);
  8934. if (tx_idx != tnapi->tx_prod)
  8935. goto out;
  8936. if (rx_idx != rx_start_idx + num_pkts)
  8937. goto out;
  8938. desc = &rnapi->rx_rcb[rx_start_idx];
  8939. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  8940. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  8941. if (opaque_key != RXD_OPAQUE_RING_STD)
  8942. goto out;
  8943. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  8944. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  8945. goto out;
  8946. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  8947. if (rx_len != tx_len)
  8948. goto out;
  8949. rx_skb = tpr->rx_std_buffers[desc_idx].skb;
  8950. map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
  8951. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  8952. for (i = 14; i < tx_len; i++) {
  8953. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  8954. goto out;
  8955. }
  8956. err = 0;
  8957. /* tg3_free_rings will unmap and free the rx_skb */
  8958. out:
  8959. return err;
  8960. }
  8961. #define TG3_MAC_LOOPBACK_FAILED 1
  8962. #define TG3_PHY_LOOPBACK_FAILED 2
  8963. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  8964. TG3_PHY_LOOPBACK_FAILED)
  8965. static int tg3_test_loopback(struct tg3 *tp)
  8966. {
  8967. int err = 0;
  8968. u32 cpmuctrl = 0;
  8969. if (!netif_running(tp->dev))
  8970. return TG3_LOOPBACK_FAILED;
  8971. err = tg3_reset_hw(tp, 1);
  8972. if (err)
  8973. return TG3_LOOPBACK_FAILED;
  8974. /* Turn off gphy autopowerdown. */
  8975. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  8976. tg3_phy_toggle_apd(tp, false);
  8977. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
  8978. int i;
  8979. u32 status;
  8980. tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
  8981. /* Wait for up to 40 microseconds to acquire lock. */
  8982. for (i = 0; i < 4; i++) {
  8983. status = tr32(TG3_CPMU_MUTEX_GNT);
  8984. if (status == CPMU_MUTEX_GNT_DRIVER)
  8985. break;
  8986. udelay(10);
  8987. }
  8988. if (status != CPMU_MUTEX_GNT_DRIVER)
  8989. return TG3_LOOPBACK_FAILED;
  8990. /* Turn off link-based power management. */
  8991. cpmuctrl = tr32(TG3_CPMU_CTRL);
  8992. tw32(TG3_CPMU_CTRL,
  8993. cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
  8994. CPMU_CTRL_LINK_AWARE_MODE));
  8995. }
  8996. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  8997. err |= TG3_MAC_LOOPBACK_FAILED;
  8998. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
  8999. tw32(TG3_CPMU_CTRL, cpmuctrl);
  9000. /* Release the mutex */
  9001. tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
  9002. }
  9003. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  9004. !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  9005. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  9006. err |= TG3_PHY_LOOPBACK_FAILED;
  9007. }
  9008. /* Re-enable gphy autopowerdown. */
  9009. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  9010. tg3_phy_toggle_apd(tp, true);
  9011. return err;
  9012. }
  9013. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  9014. u64 *data)
  9015. {
  9016. struct tg3 *tp = netdev_priv(dev);
  9017. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9018. tg3_set_power_state(tp, PCI_D0);
  9019. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  9020. if (tg3_test_nvram(tp) != 0) {
  9021. etest->flags |= ETH_TEST_FL_FAILED;
  9022. data[0] = 1;
  9023. }
  9024. if (tg3_test_link(tp) != 0) {
  9025. etest->flags |= ETH_TEST_FL_FAILED;
  9026. data[1] = 1;
  9027. }
  9028. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  9029. int err, err2 = 0, irq_sync = 0;
  9030. if (netif_running(dev)) {
  9031. tg3_phy_stop(tp);
  9032. tg3_netif_stop(tp);
  9033. irq_sync = 1;
  9034. }
  9035. tg3_full_lock(tp, irq_sync);
  9036. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  9037. err = tg3_nvram_lock(tp);
  9038. tg3_halt_cpu(tp, RX_CPU_BASE);
  9039. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  9040. tg3_halt_cpu(tp, TX_CPU_BASE);
  9041. if (!err)
  9042. tg3_nvram_unlock(tp);
  9043. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  9044. tg3_phy_reset(tp);
  9045. if (tg3_test_registers(tp) != 0) {
  9046. etest->flags |= ETH_TEST_FL_FAILED;
  9047. data[2] = 1;
  9048. }
  9049. if (tg3_test_memory(tp) != 0) {
  9050. etest->flags |= ETH_TEST_FL_FAILED;
  9051. data[3] = 1;
  9052. }
  9053. if ((data[4] = tg3_test_loopback(tp)) != 0)
  9054. etest->flags |= ETH_TEST_FL_FAILED;
  9055. tg3_full_unlock(tp);
  9056. if (tg3_test_interrupt(tp) != 0) {
  9057. etest->flags |= ETH_TEST_FL_FAILED;
  9058. data[5] = 1;
  9059. }
  9060. tg3_full_lock(tp, 0);
  9061. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9062. if (netif_running(dev)) {
  9063. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  9064. err2 = tg3_restart_hw(tp, 1);
  9065. if (!err2)
  9066. tg3_netif_start(tp);
  9067. }
  9068. tg3_full_unlock(tp);
  9069. if (irq_sync && !err2)
  9070. tg3_phy_start(tp);
  9071. }
  9072. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9073. tg3_set_power_state(tp, PCI_D3hot);
  9074. }
  9075. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  9076. {
  9077. struct mii_ioctl_data *data = if_mii(ifr);
  9078. struct tg3 *tp = netdev_priv(dev);
  9079. int err;
  9080. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  9081. struct phy_device *phydev;
  9082. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9083. return -EAGAIN;
  9084. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9085. return phy_mii_ioctl(phydev, ifr, cmd);
  9086. }
  9087. switch (cmd) {
  9088. case SIOCGMIIPHY:
  9089. data->phy_id = tp->phy_addr;
  9090. /* fallthru */
  9091. case SIOCGMIIREG: {
  9092. u32 mii_regval;
  9093. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9094. break; /* We have no PHY */
  9095. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9096. return -EAGAIN;
  9097. spin_lock_bh(&tp->lock);
  9098. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  9099. spin_unlock_bh(&tp->lock);
  9100. data->val_out = mii_regval;
  9101. return err;
  9102. }
  9103. case SIOCSMIIREG:
  9104. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9105. break; /* We have no PHY */
  9106. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9107. return -EAGAIN;
  9108. spin_lock_bh(&tp->lock);
  9109. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  9110. spin_unlock_bh(&tp->lock);
  9111. return err;
  9112. default:
  9113. /* do nothing */
  9114. break;
  9115. }
  9116. return -EOPNOTSUPP;
  9117. }
  9118. #if TG3_VLAN_TAG_USED
  9119. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  9120. {
  9121. struct tg3 *tp = netdev_priv(dev);
  9122. if (!netif_running(dev)) {
  9123. tp->vlgrp = grp;
  9124. return;
  9125. }
  9126. tg3_netif_stop(tp);
  9127. tg3_full_lock(tp, 0);
  9128. tp->vlgrp = grp;
  9129. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  9130. __tg3_set_rx_mode(dev);
  9131. tg3_netif_start(tp);
  9132. tg3_full_unlock(tp);
  9133. }
  9134. #endif
  9135. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9136. {
  9137. struct tg3 *tp = netdev_priv(dev);
  9138. memcpy(ec, &tp->coal, sizeof(*ec));
  9139. return 0;
  9140. }
  9141. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9142. {
  9143. struct tg3 *tp = netdev_priv(dev);
  9144. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  9145. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  9146. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  9147. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  9148. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  9149. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  9150. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  9151. }
  9152. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  9153. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  9154. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  9155. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  9156. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  9157. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  9158. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  9159. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  9160. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  9161. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  9162. return -EINVAL;
  9163. /* No rx interrupts will be generated if both are zero */
  9164. if ((ec->rx_coalesce_usecs == 0) &&
  9165. (ec->rx_max_coalesced_frames == 0))
  9166. return -EINVAL;
  9167. /* No tx interrupts will be generated if both are zero */
  9168. if ((ec->tx_coalesce_usecs == 0) &&
  9169. (ec->tx_max_coalesced_frames == 0))
  9170. return -EINVAL;
  9171. /* Only copy relevant parameters, ignore all others. */
  9172. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  9173. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  9174. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  9175. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  9176. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  9177. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  9178. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  9179. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  9180. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  9181. if (netif_running(dev)) {
  9182. tg3_full_lock(tp, 0);
  9183. __tg3_set_coalesce(tp, &tp->coal);
  9184. tg3_full_unlock(tp);
  9185. }
  9186. return 0;
  9187. }
  9188. static const struct ethtool_ops tg3_ethtool_ops = {
  9189. .get_settings = tg3_get_settings,
  9190. .set_settings = tg3_set_settings,
  9191. .get_drvinfo = tg3_get_drvinfo,
  9192. .get_regs_len = tg3_get_regs_len,
  9193. .get_regs = tg3_get_regs,
  9194. .get_wol = tg3_get_wol,
  9195. .set_wol = tg3_set_wol,
  9196. .get_msglevel = tg3_get_msglevel,
  9197. .set_msglevel = tg3_set_msglevel,
  9198. .nway_reset = tg3_nway_reset,
  9199. .get_link = ethtool_op_get_link,
  9200. .get_eeprom_len = tg3_get_eeprom_len,
  9201. .get_eeprom = tg3_get_eeprom,
  9202. .set_eeprom = tg3_set_eeprom,
  9203. .get_ringparam = tg3_get_ringparam,
  9204. .set_ringparam = tg3_set_ringparam,
  9205. .get_pauseparam = tg3_get_pauseparam,
  9206. .set_pauseparam = tg3_set_pauseparam,
  9207. .get_rx_csum = tg3_get_rx_csum,
  9208. .set_rx_csum = tg3_set_rx_csum,
  9209. .set_tx_csum = tg3_set_tx_csum,
  9210. .set_sg = ethtool_op_set_sg,
  9211. .set_tso = tg3_set_tso,
  9212. .self_test = tg3_self_test,
  9213. .get_strings = tg3_get_strings,
  9214. .phys_id = tg3_phys_id,
  9215. .get_ethtool_stats = tg3_get_ethtool_stats,
  9216. .get_coalesce = tg3_get_coalesce,
  9217. .set_coalesce = tg3_set_coalesce,
  9218. .get_sset_count = tg3_get_sset_count,
  9219. };
  9220. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  9221. {
  9222. u32 cursize, val, magic;
  9223. tp->nvram_size = EEPROM_CHIP_SIZE;
  9224. if (tg3_nvram_read(tp, 0, &magic) != 0)
  9225. return;
  9226. if ((magic != TG3_EEPROM_MAGIC) &&
  9227. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  9228. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  9229. return;
  9230. /*
  9231. * Size the chip by reading offsets at increasing powers of two.
  9232. * When we encounter our validation signature, we know the addressing
  9233. * has wrapped around, and thus have our chip size.
  9234. */
  9235. cursize = 0x10;
  9236. while (cursize < tp->nvram_size) {
  9237. if (tg3_nvram_read(tp, cursize, &val) != 0)
  9238. return;
  9239. if (val == magic)
  9240. break;
  9241. cursize <<= 1;
  9242. }
  9243. tp->nvram_size = cursize;
  9244. }
  9245. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  9246. {
  9247. u32 val;
  9248. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  9249. tg3_nvram_read(tp, 0, &val) != 0)
  9250. return;
  9251. /* Selfboot format */
  9252. if (val != TG3_EEPROM_MAGIC) {
  9253. tg3_get_eeprom_size(tp);
  9254. return;
  9255. }
  9256. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  9257. if (val != 0) {
  9258. /* This is confusing. We want to operate on the
  9259. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  9260. * call will read from NVRAM and byteswap the data
  9261. * according to the byteswapping settings for all
  9262. * other register accesses. This ensures the data we
  9263. * want will always reside in the lower 16-bits.
  9264. * However, the data in NVRAM is in LE format, which
  9265. * means the data from the NVRAM read will always be
  9266. * opposite the endianness of the CPU. The 16-bit
  9267. * byteswap then brings the data to CPU endianness.
  9268. */
  9269. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  9270. return;
  9271. }
  9272. }
  9273. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9274. }
  9275. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  9276. {
  9277. u32 nvcfg1;
  9278. nvcfg1 = tr32(NVRAM_CFG1);
  9279. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  9280. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9281. } else {
  9282. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9283. tw32(NVRAM_CFG1, nvcfg1);
  9284. }
  9285. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  9286. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9287. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  9288. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  9289. tp->nvram_jedecnum = JEDEC_ATMEL;
  9290. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9291. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9292. break;
  9293. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  9294. tp->nvram_jedecnum = JEDEC_ATMEL;
  9295. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  9296. break;
  9297. case FLASH_VENDOR_ATMEL_EEPROM:
  9298. tp->nvram_jedecnum = JEDEC_ATMEL;
  9299. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9300. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9301. break;
  9302. case FLASH_VENDOR_ST:
  9303. tp->nvram_jedecnum = JEDEC_ST;
  9304. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  9305. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9306. break;
  9307. case FLASH_VENDOR_SAIFUN:
  9308. tp->nvram_jedecnum = JEDEC_SAIFUN;
  9309. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  9310. break;
  9311. case FLASH_VENDOR_SST_SMALL:
  9312. case FLASH_VENDOR_SST_LARGE:
  9313. tp->nvram_jedecnum = JEDEC_SST;
  9314. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  9315. break;
  9316. }
  9317. } else {
  9318. tp->nvram_jedecnum = JEDEC_ATMEL;
  9319. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9320. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9321. }
  9322. }
  9323. static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  9324. {
  9325. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  9326. case FLASH_5752PAGE_SIZE_256:
  9327. tp->nvram_pagesize = 256;
  9328. break;
  9329. case FLASH_5752PAGE_SIZE_512:
  9330. tp->nvram_pagesize = 512;
  9331. break;
  9332. case FLASH_5752PAGE_SIZE_1K:
  9333. tp->nvram_pagesize = 1024;
  9334. break;
  9335. case FLASH_5752PAGE_SIZE_2K:
  9336. tp->nvram_pagesize = 2048;
  9337. break;
  9338. case FLASH_5752PAGE_SIZE_4K:
  9339. tp->nvram_pagesize = 4096;
  9340. break;
  9341. case FLASH_5752PAGE_SIZE_264:
  9342. tp->nvram_pagesize = 264;
  9343. break;
  9344. case FLASH_5752PAGE_SIZE_528:
  9345. tp->nvram_pagesize = 528;
  9346. break;
  9347. }
  9348. }
  9349. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  9350. {
  9351. u32 nvcfg1;
  9352. nvcfg1 = tr32(NVRAM_CFG1);
  9353. /* NVRAM protection for TPM */
  9354. if (nvcfg1 & (1 << 27))
  9355. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9356. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9357. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  9358. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  9359. tp->nvram_jedecnum = JEDEC_ATMEL;
  9360. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9361. break;
  9362. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9363. tp->nvram_jedecnum = JEDEC_ATMEL;
  9364. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9365. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9366. break;
  9367. case FLASH_5752VENDOR_ST_M45PE10:
  9368. case FLASH_5752VENDOR_ST_M45PE20:
  9369. case FLASH_5752VENDOR_ST_M45PE40:
  9370. tp->nvram_jedecnum = JEDEC_ST;
  9371. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9372. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9373. break;
  9374. }
  9375. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  9376. tg3_nvram_get_pagesize(tp, nvcfg1);
  9377. } else {
  9378. /* For eeprom, set pagesize to maximum eeprom size */
  9379. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9380. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9381. tw32(NVRAM_CFG1, nvcfg1);
  9382. }
  9383. }
  9384. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  9385. {
  9386. u32 nvcfg1, protect = 0;
  9387. nvcfg1 = tr32(NVRAM_CFG1);
  9388. /* NVRAM protection for TPM */
  9389. if (nvcfg1 & (1 << 27)) {
  9390. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9391. protect = 1;
  9392. }
  9393. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  9394. switch (nvcfg1) {
  9395. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  9396. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  9397. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  9398. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  9399. tp->nvram_jedecnum = JEDEC_ATMEL;
  9400. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9401. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9402. tp->nvram_pagesize = 264;
  9403. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  9404. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  9405. tp->nvram_size = (protect ? 0x3e200 :
  9406. TG3_NVRAM_SIZE_512KB);
  9407. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  9408. tp->nvram_size = (protect ? 0x1f200 :
  9409. TG3_NVRAM_SIZE_256KB);
  9410. else
  9411. tp->nvram_size = (protect ? 0x1f200 :
  9412. TG3_NVRAM_SIZE_128KB);
  9413. break;
  9414. case FLASH_5752VENDOR_ST_M45PE10:
  9415. case FLASH_5752VENDOR_ST_M45PE20:
  9416. case FLASH_5752VENDOR_ST_M45PE40:
  9417. tp->nvram_jedecnum = JEDEC_ST;
  9418. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9419. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9420. tp->nvram_pagesize = 256;
  9421. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  9422. tp->nvram_size = (protect ?
  9423. TG3_NVRAM_SIZE_64KB :
  9424. TG3_NVRAM_SIZE_128KB);
  9425. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  9426. tp->nvram_size = (protect ?
  9427. TG3_NVRAM_SIZE_64KB :
  9428. TG3_NVRAM_SIZE_256KB);
  9429. else
  9430. tp->nvram_size = (protect ?
  9431. TG3_NVRAM_SIZE_128KB :
  9432. TG3_NVRAM_SIZE_512KB);
  9433. break;
  9434. }
  9435. }
  9436. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  9437. {
  9438. u32 nvcfg1;
  9439. nvcfg1 = tr32(NVRAM_CFG1);
  9440. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9441. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  9442. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  9443. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  9444. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  9445. tp->nvram_jedecnum = JEDEC_ATMEL;
  9446. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9447. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9448. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9449. tw32(NVRAM_CFG1, nvcfg1);
  9450. break;
  9451. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9452. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  9453. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  9454. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  9455. tp->nvram_jedecnum = JEDEC_ATMEL;
  9456. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9457. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9458. tp->nvram_pagesize = 264;
  9459. break;
  9460. case FLASH_5752VENDOR_ST_M45PE10:
  9461. case FLASH_5752VENDOR_ST_M45PE20:
  9462. case FLASH_5752VENDOR_ST_M45PE40:
  9463. tp->nvram_jedecnum = JEDEC_ST;
  9464. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9465. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9466. tp->nvram_pagesize = 256;
  9467. break;
  9468. }
  9469. }
  9470. static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
  9471. {
  9472. u32 nvcfg1, protect = 0;
  9473. nvcfg1 = tr32(NVRAM_CFG1);
  9474. /* NVRAM protection for TPM */
  9475. if (nvcfg1 & (1 << 27)) {
  9476. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9477. protect = 1;
  9478. }
  9479. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  9480. switch (nvcfg1) {
  9481. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9482. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9483. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9484. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9485. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9486. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9487. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9488. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9489. tp->nvram_jedecnum = JEDEC_ATMEL;
  9490. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9491. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9492. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9493. tp->nvram_pagesize = 256;
  9494. break;
  9495. case FLASH_5761VENDOR_ST_A_M45PE20:
  9496. case FLASH_5761VENDOR_ST_A_M45PE40:
  9497. case FLASH_5761VENDOR_ST_A_M45PE80:
  9498. case FLASH_5761VENDOR_ST_A_M45PE16:
  9499. case FLASH_5761VENDOR_ST_M_M45PE20:
  9500. case FLASH_5761VENDOR_ST_M_M45PE40:
  9501. case FLASH_5761VENDOR_ST_M_M45PE80:
  9502. case FLASH_5761VENDOR_ST_M_M45PE16:
  9503. tp->nvram_jedecnum = JEDEC_ST;
  9504. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9505. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9506. tp->nvram_pagesize = 256;
  9507. break;
  9508. }
  9509. if (protect) {
  9510. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  9511. } else {
  9512. switch (nvcfg1) {
  9513. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9514. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9515. case FLASH_5761VENDOR_ST_A_M45PE16:
  9516. case FLASH_5761VENDOR_ST_M_M45PE16:
  9517. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  9518. break;
  9519. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9520. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9521. case FLASH_5761VENDOR_ST_A_M45PE80:
  9522. case FLASH_5761VENDOR_ST_M_M45PE80:
  9523. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  9524. break;
  9525. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9526. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9527. case FLASH_5761VENDOR_ST_A_M45PE40:
  9528. case FLASH_5761VENDOR_ST_M_M45PE40:
  9529. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9530. break;
  9531. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9532. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9533. case FLASH_5761VENDOR_ST_A_M45PE20:
  9534. case FLASH_5761VENDOR_ST_M_M45PE20:
  9535. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9536. break;
  9537. }
  9538. }
  9539. }
  9540. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  9541. {
  9542. tp->nvram_jedecnum = JEDEC_ATMEL;
  9543. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9544. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9545. }
  9546. static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
  9547. {
  9548. u32 nvcfg1;
  9549. nvcfg1 = tr32(NVRAM_CFG1);
  9550. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9551. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  9552. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  9553. tp->nvram_jedecnum = JEDEC_ATMEL;
  9554. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9555. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9556. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9557. tw32(NVRAM_CFG1, nvcfg1);
  9558. return;
  9559. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9560. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  9561. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  9562. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  9563. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  9564. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  9565. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  9566. tp->nvram_jedecnum = JEDEC_ATMEL;
  9567. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9568. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9569. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9570. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9571. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  9572. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  9573. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9574. break;
  9575. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  9576. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  9577. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9578. break;
  9579. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  9580. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  9581. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9582. break;
  9583. }
  9584. break;
  9585. case FLASH_5752VENDOR_ST_M45PE10:
  9586. case FLASH_5752VENDOR_ST_M45PE20:
  9587. case FLASH_5752VENDOR_ST_M45PE40:
  9588. tp->nvram_jedecnum = JEDEC_ST;
  9589. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9590. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9591. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9592. case FLASH_5752VENDOR_ST_M45PE10:
  9593. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9594. break;
  9595. case FLASH_5752VENDOR_ST_M45PE20:
  9596. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9597. break;
  9598. case FLASH_5752VENDOR_ST_M45PE40:
  9599. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9600. break;
  9601. }
  9602. break;
  9603. default:
  9604. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
  9605. return;
  9606. }
  9607. tg3_nvram_get_pagesize(tp, nvcfg1);
  9608. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  9609. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9610. }
  9611. static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
  9612. {
  9613. u32 nvcfg1;
  9614. nvcfg1 = tr32(NVRAM_CFG1);
  9615. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9616. case FLASH_5717VENDOR_ATMEL_EEPROM:
  9617. case FLASH_5717VENDOR_MICRO_EEPROM:
  9618. tp->nvram_jedecnum = JEDEC_ATMEL;
  9619. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9620. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9621. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9622. tw32(NVRAM_CFG1, nvcfg1);
  9623. return;
  9624. case FLASH_5717VENDOR_ATMEL_MDB011D:
  9625. case FLASH_5717VENDOR_ATMEL_ADB011B:
  9626. case FLASH_5717VENDOR_ATMEL_ADB011D:
  9627. case FLASH_5717VENDOR_ATMEL_MDB021D:
  9628. case FLASH_5717VENDOR_ATMEL_ADB021B:
  9629. case FLASH_5717VENDOR_ATMEL_ADB021D:
  9630. case FLASH_5717VENDOR_ATMEL_45USPT:
  9631. tp->nvram_jedecnum = JEDEC_ATMEL;
  9632. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9633. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9634. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9635. case FLASH_5717VENDOR_ATMEL_MDB021D:
  9636. case FLASH_5717VENDOR_ATMEL_ADB021B:
  9637. case FLASH_5717VENDOR_ATMEL_ADB021D:
  9638. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9639. break;
  9640. default:
  9641. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9642. break;
  9643. }
  9644. break;
  9645. case FLASH_5717VENDOR_ST_M_M25PE10:
  9646. case FLASH_5717VENDOR_ST_A_M25PE10:
  9647. case FLASH_5717VENDOR_ST_M_M45PE10:
  9648. case FLASH_5717VENDOR_ST_A_M45PE10:
  9649. case FLASH_5717VENDOR_ST_M_M25PE20:
  9650. case FLASH_5717VENDOR_ST_A_M25PE20:
  9651. case FLASH_5717VENDOR_ST_M_M45PE20:
  9652. case FLASH_5717VENDOR_ST_A_M45PE20:
  9653. case FLASH_5717VENDOR_ST_25USPT:
  9654. case FLASH_5717VENDOR_ST_45USPT:
  9655. tp->nvram_jedecnum = JEDEC_ST;
  9656. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9657. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9658. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9659. case FLASH_5717VENDOR_ST_M_M25PE20:
  9660. case FLASH_5717VENDOR_ST_A_M25PE20:
  9661. case FLASH_5717VENDOR_ST_M_M45PE20:
  9662. case FLASH_5717VENDOR_ST_A_M45PE20:
  9663. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9664. break;
  9665. default:
  9666. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9667. break;
  9668. }
  9669. break;
  9670. default:
  9671. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
  9672. return;
  9673. }
  9674. tg3_nvram_get_pagesize(tp, nvcfg1);
  9675. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  9676. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9677. }
  9678. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  9679. static void __devinit tg3_nvram_init(struct tg3 *tp)
  9680. {
  9681. tw32_f(GRC_EEPROM_ADDR,
  9682. (EEPROM_ADDR_FSM_RESET |
  9683. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  9684. EEPROM_ADDR_CLKPERD_SHIFT)));
  9685. msleep(1);
  9686. /* Enable seeprom accesses. */
  9687. tw32_f(GRC_LOCAL_CTRL,
  9688. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  9689. udelay(100);
  9690. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9691. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  9692. tp->tg3_flags |= TG3_FLAG_NVRAM;
  9693. if (tg3_nvram_lock(tp)) {
  9694. netdev_warn(tp->dev,
  9695. "Cannot get nvram lock, %s failed\n",
  9696. __func__);
  9697. return;
  9698. }
  9699. tg3_enable_nvram_access(tp);
  9700. tp->nvram_size = 0;
  9701. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9702. tg3_get_5752_nvram_info(tp);
  9703. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9704. tg3_get_5755_nvram_info(tp);
  9705. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9706. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9707. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  9708. tg3_get_5787_nvram_info(tp);
  9709. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  9710. tg3_get_5761_nvram_info(tp);
  9711. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9712. tg3_get_5906_nvram_info(tp);
  9713. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  9714. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  9715. tg3_get_57780_nvram_info(tp);
  9716. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  9717. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  9718. tg3_get_5717_nvram_info(tp);
  9719. else
  9720. tg3_get_nvram_info(tp);
  9721. if (tp->nvram_size == 0)
  9722. tg3_get_nvram_size(tp);
  9723. tg3_disable_nvram_access(tp);
  9724. tg3_nvram_unlock(tp);
  9725. } else {
  9726. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  9727. tg3_get_eeprom_size(tp);
  9728. }
  9729. }
  9730. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  9731. u32 offset, u32 len, u8 *buf)
  9732. {
  9733. int i, j, rc = 0;
  9734. u32 val;
  9735. for (i = 0; i < len; i += 4) {
  9736. u32 addr;
  9737. __be32 data;
  9738. addr = offset + i;
  9739. memcpy(&data, buf + i, 4);
  9740. /*
  9741. * The SEEPROM interface expects the data to always be opposite
  9742. * the native endian format. We accomplish this by reversing
  9743. * all the operations that would have been performed on the
  9744. * data from a call to tg3_nvram_read_be32().
  9745. */
  9746. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  9747. val = tr32(GRC_EEPROM_ADDR);
  9748. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  9749. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  9750. EEPROM_ADDR_READ);
  9751. tw32(GRC_EEPROM_ADDR, val |
  9752. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  9753. (addr & EEPROM_ADDR_ADDR_MASK) |
  9754. EEPROM_ADDR_START |
  9755. EEPROM_ADDR_WRITE);
  9756. for (j = 0; j < 1000; j++) {
  9757. val = tr32(GRC_EEPROM_ADDR);
  9758. if (val & EEPROM_ADDR_COMPLETE)
  9759. break;
  9760. msleep(1);
  9761. }
  9762. if (!(val & EEPROM_ADDR_COMPLETE)) {
  9763. rc = -EBUSY;
  9764. break;
  9765. }
  9766. }
  9767. return rc;
  9768. }
  9769. /* offset and length are dword aligned */
  9770. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  9771. u8 *buf)
  9772. {
  9773. int ret = 0;
  9774. u32 pagesize = tp->nvram_pagesize;
  9775. u32 pagemask = pagesize - 1;
  9776. u32 nvram_cmd;
  9777. u8 *tmp;
  9778. tmp = kmalloc(pagesize, GFP_KERNEL);
  9779. if (tmp == NULL)
  9780. return -ENOMEM;
  9781. while (len) {
  9782. int j;
  9783. u32 phy_addr, page_off, size;
  9784. phy_addr = offset & ~pagemask;
  9785. for (j = 0; j < pagesize; j += 4) {
  9786. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  9787. (__be32 *) (tmp + j));
  9788. if (ret)
  9789. break;
  9790. }
  9791. if (ret)
  9792. break;
  9793. page_off = offset & pagemask;
  9794. size = pagesize;
  9795. if (len < size)
  9796. size = len;
  9797. len -= size;
  9798. memcpy(tmp + page_off, buf, size);
  9799. offset = offset + (pagesize - page_off);
  9800. tg3_enable_nvram_access(tp);
  9801. /*
  9802. * Before we can erase the flash page, we need
  9803. * to issue a special "write enable" command.
  9804. */
  9805. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9806. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9807. break;
  9808. /* Erase the target page */
  9809. tw32(NVRAM_ADDR, phy_addr);
  9810. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  9811. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  9812. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9813. break;
  9814. /* Issue another write enable to start the write. */
  9815. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9816. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9817. break;
  9818. for (j = 0; j < pagesize; j += 4) {
  9819. __be32 data;
  9820. data = *((__be32 *) (tmp + j));
  9821. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9822. tw32(NVRAM_ADDR, phy_addr + j);
  9823. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  9824. NVRAM_CMD_WR;
  9825. if (j == 0)
  9826. nvram_cmd |= NVRAM_CMD_FIRST;
  9827. else if (j == (pagesize - 4))
  9828. nvram_cmd |= NVRAM_CMD_LAST;
  9829. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  9830. break;
  9831. }
  9832. if (ret)
  9833. break;
  9834. }
  9835. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9836. tg3_nvram_exec_cmd(tp, nvram_cmd);
  9837. kfree(tmp);
  9838. return ret;
  9839. }
  9840. /* offset and length are dword aligned */
  9841. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  9842. u8 *buf)
  9843. {
  9844. int i, ret = 0;
  9845. for (i = 0; i < len; i += 4, offset += 4) {
  9846. u32 page_off, phy_addr, nvram_cmd;
  9847. __be32 data;
  9848. memcpy(&data, buf + i, 4);
  9849. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9850. page_off = offset % tp->nvram_pagesize;
  9851. phy_addr = tg3_nvram_phys_addr(tp, offset);
  9852. tw32(NVRAM_ADDR, phy_addr);
  9853. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  9854. if (page_off == 0 || i == 0)
  9855. nvram_cmd |= NVRAM_CMD_FIRST;
  9856. if (page_off == (tp->nvram_pagesize - 4))
  9857. nvram_cmd |= NVRAM_CMD_LAST;
  9858. if (i == (len - 4))
  9859. nvram_cmd |= NVRAM_CMD_LAST;
  9860. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  9861. !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
  9862. (tp->nvram_jedecnum == JEDEC_ST) &&
  9863. (nvram_cmd & NVRAM_CMD_FIRST)) {
  9864. if ((ret = tg3_nvram_exec_cmd(tp,
  9865. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  9866. NVRAM_CMD_DONE)))
  9867. break;
  9868. }
  9869. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  9870. /* We always do complete word writes to eeprom. */
  9871. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  9872. }
  9873. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  9874. break;
  9875. }
  9876. return ret;
  9877. }
  9878. /* offset and length are dword aligned */
  9879. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  9880. {
  9881. int ret;
  9882. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  9883. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  9884. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  9885. udelay(40);
  9886. }
  9887. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  9888. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  9889. } else {
  9890. u32 grc_mode;
  9891. ret = tg3_nvram_lock(tp);
  9892. if (ret)
  9893. return ret;
  9894. tg3_enable_nvram_access(tp);
  9895. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  9896. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
  9897. tw32(NVRAM_WRITE1, 0x406);
  9898. grc_mode = tr32(GRC_MODE);
  9899. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  9900. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  9901. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  9902. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  9903. buf);
  9904. } else {
  9905. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  9906. buf);
  9907. }
  9908. grc_mode = tr32(GRC_MODE);
  9909. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  9910. tg3_disable_nvram_access(tp);
  9911. tg3_nvram_unlock(tp);
  9912. }
  9913. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  9914. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  9915. udelay(40);
  9916. }
  9917. return ret;
  9918. }
  9919. struct subsys_tbl_ent {
  9920. u16 subsys_vendor, subsys_devid;
  9921. u32 phy_id;
  9922. };
  9923. static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
  9924. /* Broadcom boards. */
  9925. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9926. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
  9927. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9928. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
  9929. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9930. TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
  9931. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9932. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
  9933. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9934. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
  9935. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9936. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
  9937. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9938. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
  9939. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9940. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
  9941. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9942. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
  9943. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9944. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
  9945. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  9946. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
  9947. /* 3com boards. */
  9948. { TG3PCI_SUBVENDOR_ID_3COM,
  9949. TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
  9950. { TG3PCI_SUBVENDOR_ID_3COM,
  9951. TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
  9952. { TG3PCI_SUBVENDOR_ID_3COM,
  9953. TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
  9954. { TG3PCI_SUBVENDOR_ID_3COM,
  9955. TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
  9956. { TG3PCI_SUBVENDOR_ID_3COM,
  9957. TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
  9958. /* DELL boards. */
  9959. { TG3PCI_SUBVENDOR_ID_DELL,
  9960. TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
  9961. { TG3PCI_SUBVENDOR_ID_DELL,
  9962. TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
  9963. { TG3PCI_SUBVENDOR_ID_DELL,
  9964. TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
  9965. { TG3PCI_SUBVENDOR_ID_DELL,
  9966. TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
  9967. /* Compaq boards. */
  9968. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  9969. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
  9970. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  9971. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
  9972. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  9973. TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
  9974. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  9975. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
  9976. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  9977. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
  9978. /* IBM boards. */
  9979. { TG3PCI_SUBVENDOR_ID_IBM,
  9980. TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
  9981. };
  9982. static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
  9983. {
  9984. int i;
  9985. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  9986. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  9987. tp->pdev->subsystem_vendor) &&
  9988. (subsys_id_to_phy_id[i].subsys_devid ==
  9989. tp->pdev->subsystem_device))
  9990. return &subsys_id_to_phy_id[i];
  9991. }
  9992. return NULL;
  9993. }
  9994. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  9995. {
  9996. u32 val;
  9997. u16 pmcsr;
  9998. /* On some early chips the SRAM cannot be accessed in D3hot state,
  9999. * so need make sure we're in D0.
  10000. */
  10001. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  10002. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  10003. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  10004. msleep(1);
  10005. /* Make sure register accesses (indirect or otherwise)
  10006. * will function correctly.
  10007. */
  10008. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10009. tp->misc_host_ctrl);
  10010. /* The memory arbiter has to be enabled in order for SRAM accesses
  10011. * to succeed. Normally on powerup the tg3 chip firmware will make
  10012. * sure it is enabled, but other entities such as system netboot
  10013. * code might disable it.
  10014. */
  10015. val = tr32(MEMARB_MODE);
  10016. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  10017. tp->phy_id = TG3_PHY_ID_INVALID;
  10018. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10019. /* Assume an onboard device and WOL capable by default. */
  10020. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  10021. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10022. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  10023. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10024. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  10025. }
  10026. val = tr32(VCPU_CFGSHDW);
  10027. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  10028. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  10029. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  10030. (val & VCPU_CFGSHDW_WOL_MAGPKT))
  10031. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  10032. goto done;
  10033. }
  10034. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  10035. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  10036. u32 nic_cfg, led_cfg;
  10037. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  10038. int eeprom_phy_serdes = 0;
  10039. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  10040. tp->nic_sram_data_cfg = nic_cfg;
  10041. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  10042. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  10043. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  10044. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  10045. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  10046. (ver > 0) && (ver < 0x100))
  10047. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  10048. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  10049. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  10050. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  10051. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  10052. eeprom_phy_serdes = 1;
  10053. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  10054. if (nic_phy_id != 0) {
  10055. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  10056. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  10057. eeprom_phy_id = (id1 >> 16) << 10;
  10058. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  10059. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  10060. } else
  10061. eeprom_phy_id = 0;
  10062. tp->phy_id = eeprom_phy_id;
  10063. if (eeprom_phy_serdes) {
  10064. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  10065. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  10066. else
  10067. tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
  10068. }
  10069. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  10070. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  10071. SHASTA_EXT_LED_MODE_MASK);
  10072. else
  10073. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  10074. switch (led_cfg) {
  10075. default:
  10076. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  10077. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10078. break;
  10079. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  10080. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10081. break;
  10082. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  10083. tp->led_ctrl = LED_CTRL_MODE_MAC;
  10084. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  10085. * read on some older 5700/5701 bootcode.
  10086. */
  10087. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10088. ASIC_REV_5700 ||
  10089. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10090. ASIC_REV_5701)
  10091. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10092. break;
  10093. case SHASTA_EXT_LED_SHARED:
  10094. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  10095. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  10096. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  10097. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10098. LED_CTRL_MODE_PHY_2);
  10099. break;
  10100. case SHASTA_EXT_LED_MAC:
  10101. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  10102. break;
  10103. case SHASTA_EXT_LED_COMBO:
  10104. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  10105. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  10106. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10107. LED_CTRL_MODE_PHY_2);
  10108. break;
  10109. }
  10110. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10111. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  10112. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  10113. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10114. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
  10115. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10116. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  10117. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  10118. if ((tp->pdev->subsystem_vendor ==
  10119. PCI_VENDOR_ID_ARIMA) &&
  10120. (tp->pdev->subsystem_device == 0x205a ||
  10121. tp->pdev->subsystem_device == 0x2063))
  10122. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10123. } else {
  10124. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10125. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  10126. }
  10127. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  10128. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  10129. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  10130. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  10131. }
  10132. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  10133. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  10134. tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
  10135. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
  10136. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  10137. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  10138. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  10139. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
  10140. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  10141. if (cfg2 & (1 << 17))
  10142. tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
  10143. /* serdes signal pre-emphasis in register 0x590 set by */
  10144. /* bootcode if bit 18 is set */
  10145. if (cfg2 & (1 << 18))
  10146. tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
  10147. if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  10148. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
  10149. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  10150. tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
  10151. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  10152. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  10153. !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
  10154. u32 cfg3;
  10155. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  10156. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  10157. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  10158. }
  10159. if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
  10160. tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
  10161. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  10162. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
  10163. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  10164. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
  10165. }
  10166. done:
  10167. device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
  10168. device_set_wakeup_enable(&tp->pdev->dev,
  10169. tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
  10170. }
  10171. static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  10172. {
  10173. int i;
  10174. u32 val;
  10175. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  10176. tw32(OTP_CTRL, cmd);
  10177. /* Wait for up to 1 ms for command to execute. */
  10178. for (i = 0; i < 100; i++) {
  10179. val = tr32(OTP_STATUS);
  10180. if (val & OTP_STATUS_CMD_DONE)
  10181. break;
  10182. udelay(10);
  10183. }
  10184. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  10185. }
  10186. /* Read the gphy configuration from the OTP region of the chip. The gphy
  10187. * configuration is a 32-bit value that straddles the alignment boundary.
  10188. * We do two 32-bit reads and then shift and merge the results.
  10189. */
  10190. static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
  10191. {
  10192. u32 bhalf_otp, thalf_otp;
  10193. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  10194. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  10195. return 0;
  10196. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  10197. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10198. return 0;
  10199. thalf_otp = tr32(OTP_READ_DATA);
  10200. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  10201. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10202. return 0;
  10203. bhalf_otp = tr32(OTP_READ_DATA);
  10204. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  10205. }
  10206. static int __devinit tg3_phy_probe(struct tg3 *tp)
  10207. {
  10208. u32 hw_phy_id_1, hw_phy_id_2;
  10209. u32 hw_phy_id, hw_phy_id_masked;
  10210. int err;
  10211. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  10212. return tg3_phy_init(tp);
  10213. /* Reading the PHY ID register can conflict with ASF
  10214. * firmware access to the PHY hardware.
  10215. */
  10216. err = 0;
  10217. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  10218. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  10219. hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
  10220. } else {
  10221. /* Now read the physical PHY_ID from the chip and verify
  10222. * that it is sane. If it doesn't look good, we fall back
  10223. * to either the hard-coded table based PHY_ID and failing
  10224. * that the value found in the eeprom area.
  10225. */
  10226. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  10227. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  10228. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  10229. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  10230. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  10231. hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
  10232. }
  10233. if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
  10234. tp->phy_id = hw_phy_id;
  10235. if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
  10236. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  10237. else
  10238. tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
  10239. } else {
  10240. if (tp->phy_id != TG3_PHY_ID_INVALID) {
  10241. /* Do nothing, phy ID already set up in
  10242. * tg3_get_eeprom_hw_cfg().
  10243. */
  10244. } else {
  10245. struct subsys_tbl_ent *p;
  10246. /* No eeprom signature? Try the hardcoded
  10247. * subsys device table.
  10248. */
  10249. p = tg3_lookup_by_subsys(tp);
  10250. if (!p)
  10251. return -ENODEV;
  10252. tp->phy_id = p->phy_id;
  10253. if (!tp->phy_id ||
  10254. tp->phy_id == TG3_PHY_ID_BCM8002)
  10255. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  10256. }
  10257. }
  10258. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  10259. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
  10260. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  10261. u32 bmsr, adv_reg, tg3_ctrl, mask;
  10262. tg3_readphy(tp, MII_BMSR, &bmsr);
  10263. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  10264. (bmsr & BMSR_LSTATUS))
  10265. goto skip_phy_reset;
  10266. err = tg3_phy_reset(tp);
  10267. if (err)
  10268. return err;
  10269. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  10270. ADVERTISE_100HALF | ADVERTISE_100FULL |
  10271. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  10272. tg3_ctrl = 0;
  10273. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  10274. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  10275. MII_TG3_CTRL_ADV_1000_FULL);
  10276. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  10277. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  10278. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  10279. MII_TG3_CTRL_ENABLE_AS_MASTER);
  10280. }
  10281. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  10282. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  10283. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  10284. if (!tg3_copper_is_advertising_all(tp, mask)) {
  10285. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  10286. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  10287. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  10288. tg3_writephy(tp, MII_BMCR,
  10289. BMCR_ANENABLE | BMCR_ANRESTART);
  10290. }
  10291. tg3_phy_set_wirespeed(tp);
  10292. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  10293. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  10294. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  10295. }
  10296. skip_phy_reset:
  10297. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  10298. err = tg3_init_5401phy_dsp(tp);
  10299. if (err)
  10300. return err;
  10301. err = tg3_init_5401phy_dsp(tp);
  10302. }
  10303. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  10304. tp->link_config.advertising =
  10305. (ADVERTISED_1000baseT_Half |
  10306. ADVERTISED_1000baseT_Full |
  10307. ADVERTISED_Autoneg |
  10308. ADVERTISED_FIBRE);
  10309. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  10310. tp->link_config.advertising &=
  10311. ~(ADVERTISED_1000baseT_Half |
  10312. ADVERTISED_1000baseT_Full);
  10313. return err;
  10314. }
  10315. static void __devinit tg3_read_vpd(struct tg3 *tp)
  10316. {
  10317. u8 vpd_data[TG3_NVM_VPD_LEN];
  10318. unsigned int block_end, rosize, len;
  10319. int j, i = 0;
  10320. u32 magic;
  10321. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  10322. tg3_nvram_read(tp, 0x0, &magic))
  10323. goto out_not_found;
  10324. if (magic == TG3_EEPROM_MAGIC) {
  10325. for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
  10326. u32 tmp;
  10327. /* The data is in little-endian format in NVRAM.
  10328. * Use the big-endian read routines to preserve
  10329. * the byte order as it exists in NVRAM.
  10330. */
  10331. if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
  10332. goto out_not_found;
  10333. memcpy(&vpd_data[i], &tmp, sizeof(tmp));
  10334. }
  10335. } else {
  10336. ssize_t cnt;
  10337. unsigned int pos = 0;
  10338. for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
  10339. cnt = pci_read_vpd(tp->pdev, pos,
  10340. TG3_NVM_VPD_LEN - pos,
  10341. &vpd_data[pos]);
  10342. if (cnt == -ETIMEDOUT || -EINTR)
  10343. cnt = 0;
  10344. else if (cnt < 0)
  10345. goto out_not_found;
  10346. }
  10347. if (pos != TG3_NVM_VPD_LEN)
  10348. goto out_not_found;
  10349. }
  10350. i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
  10351. PCI_VPD_LRDT_RO_DATA);
  10352. if (i < 0)
  10353. goto out_not_found;
  10354. rosize = pci_vpd_lrdt_size(&vpd_data[i]);
  10355. block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
  10356. i += PCI_VPD_LRDT_TAG_SIZE;
  10357. if (block_end > TG3_NVM_VPD_LEN)
  10358. goto out_not_found;
  10359. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  10360. PCI_VPD_RO_KEYWORD_MFR_ID);
  10361. if (j > 0) {
  10362. len = pci_vpd_info_field_size(&vpd_data[j]);
  10363. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  10364. if (j + len > block_end || len != 4 ||
  10365. memcmp(&vpd_data[j], "1028", 4))
  10366. goto partno;
  10367. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  10368. PCI_VPD_RO_KEYWORD_VENDOR0);
  10369. if (j < 0)
  10370. goto partno;
  10371. len = pci_vpd_info_field_size(&vpd_data[j]);
  10372. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  10373. if (j + len > block_end)
  10374. goto partno;
  10375. memcpy(tp->fw_ver, &vpd_data[j], len);
  10376. strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
  10377. }
  10378. partno:
  10379. i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  10380. PCI_VPD_RO_KEYWORD_PARTNO);
  10381. if (i < 0)
  10382. goto out_not_found;
  10383. len = pci_vpd_info_field_size(&vpd_data[i]);
  10384. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  10385. if (len > TG3_BPN_SIZE ||
  10386. (len + i) > TG3_NVM_VPD_LEN)
  10387. goto out_not_found;
  10388. memcpy(tp->board_part_number, &vpd_data[i], len);
  10389. return;
  10390. out_not_found:
  10391. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10392. strcpy(tp->board_part_number, "BCM95906");
  10393. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10394. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  10395. strcpy(tp->board_part_number, "BCM57780");
  10396. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10397. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  10398. strcpy(tp->board_part_number, "BCM57760");
  10399. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10400. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  10401. strcpy(tp->board_part_number, "BCM57790");
  10402. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10403. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  10404. strcpy(tp->board_part_number, "BCM57788");
  10405. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10406. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
  10407. strcpy(tp->board_part_number, "BCM57761");
  10408. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10409. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
  10410. strcpy(tp->board_part_number, "BCM57765");
  10411. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10412. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
  10413. strcpy(tp->board_part_number, "BCM57781");
  10414. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10415. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
  10416. strcpy(tp->board_part_number, "BCM57785");
  10417. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10418. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
  10419. strcpy(tp->board_part_number, "BCM57791");
  10420. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  10421. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  10422. strcpy(tp->board_part_number, "BCM57795");
  10423. else
  10424. strcpy(tp->board_part_number, "none");
  10425. }
  10426. static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  10427. {
  10428. u32 val;
  10429. if (tg3_nvram_read(tp, offset, &val) ||
  10430. (val & 0xfc000000) != 0x0c000000 ||
  10431. tg3_nvram_read(tp, offset + 4, &val) ||
  10432. val != 0)
  10433. return 0;
  10434. return 1;
  10435. }
  10436. static void __devinit tg3_read_bc_ver(struct tg3 *tp)
  10437. {
  10438. u32 val, offset, start, ver_offset;
  10439. int i, dst_off;
  10440. bool newver = false;
  10441. if (tg3_nvram_read(tp, 0xc, &offset) ||
  10442. tg3_nvram_read(tp, 0x4, &start))
  10443. return;
  10444. offset = tg3_nvram_logical_addr(tp, offset);
  10445. if (tg3_nvram_read(tp, offset, &val))
  10446. return;
  10447. if ((val & 0xfc000000) == 0x0c000000) {
  10448. if (tg3_nvram_read(tp, offset + 4, &val))
  10449. return;
  10450. if (val == 0)
  10451. newver = true;
  10452. }
  10453. dst_off = strlen(tp->fw_ver);
  10454. if (newver) {
  10455. if (TG3_VER_SIZE - dst_off < 16 ||
  10456. tg3_nvram_read(tp, offset + 8, &ver_offset))
  10457. return;
  10458. offset = offset + ver_offset - start;
  10459. for (i = 0; i < 16; i += 4) {
  10460. __be32 v;
  10461. if (tg3_nvram_read_be32(tp, offset + i, &v))
  10462. return;
  10463. memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
  10464. }
  10465. } else {
  10466. u32 major, minor;
  10467. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  10468. return;
  10469. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  10470. TG3_NVM_BCVER_MAJSFT;
  10471. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  10472. snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
  10473. "v%d.%02d", major, minor);
  10474. }
  10475. }
  10476. static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
  10477. {
  10478. u32 val, major, minor;
  10479. /* Use native endian representation */
  10480. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  10481. return;
  10482. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  10483. TG3_NVM_HWSB_CFG1_MAJSFT;
  10484. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  10485. TG3_NVM_HWSB_CFG1_MINSFT;
  10486. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  10487. }
  10488. static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
  10489. {
  10490. u32 offset, major, minor, build;
  10491. strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
  10492. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  10493. return;
  10494. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  10495. case TG3_EEPROM_SB_REVISION_0:
  10496. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  10497. break;
  10498. case TG3_EEPROM_SB_REVISION_2:
  10499. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  10500. break;
  10501. case TG3_EEPROM_SB_REVISION_3:
  10502. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  10503. break;
  10504. case TG3_EEPROM_SB_REVISION_4:
  10505. offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
  10506. break;
  10507. case TG3_EEPROM_SB_REVISION_5:
  10508. offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
  10509. break;
  10510. default:
  10511. return;
  10512. }
  10513. if (tg3_nvram_read(tp, offset, &val))
  10514. return;
  10515. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  10516. TG3_EEPROM_SB_EDH_BLD_SHFT;
  10517. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  10518. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  10519. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  10520. if (minor > 99 || build > 26)
  10521. return;
  10522. offset = strlen(tp->fw_ver);
  10523. snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
  10524. " v%d.%02d", major, minor);
  10525. if (build > 0) {
  10526. offset = strlen(tp->fw_ver);
  10527. if (offset < TG3_VER_SIZE - 1)
  10528. tp->fw_ver[offset] = 'a' + build - 1;
  10529. }
  10530. }
  10531. static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
  10532. {
  10533. u32 val, offset, start;
  10534. int i, vlen;
  10535. for (offset = TG3_NVM_DIR_START;
  10536. offset < TG3_NVM_DIR_END;
  10537. offset += TG3_NVM_DIRENT_SIZE) {
  10538. if (tg3_nvram_read(tp, offset, &val))
  10539. return;
  10540. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  10541. break;
  10542. }
  10543. if (offset == TG3_NVM_DIR_END)
  10544. return;
  10545. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  10546. start = 0x08000000;
  10547. else if (tg3_nvram_read(tp, offset - 4, &start))
  10548. return;
  10549. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  10550. !tg3_fw_img_is_valid(tp, offset) ||
  10551. tg3_nvram_read(tp, offset + 8, &val))
  10552. return;
  10553. offset += val - start;
  10554. vlen = strlen(tp->fw_ver);
  10555. tp->fw_ver[vlen++] = ',';
  10556. tp->fw_ver[vlen++] = ' ';
  10557. for (i = 0; i < 4; i++) {
  10558. __be32 v;
  10559. if (tg3_nvram_read_be32(tp, offset, &v))
  10560. return;
  10561. offset += sizeof(v);
  10562. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  10563. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  10564. break;
  10565. }
  10566. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  10567. vlen += sizeof(v);
  10568. }
  10569. }
  10570. static void __devinit tg3_read_dash_ver(struct tg3 *tp)
  10571. {
  10572. int vlen;
  10573. u32 apedata;
  10574. char *fwtype;
  10575. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
  10576. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  10577. return;
  10578. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  10579. if (apedata != APE_SEG_SIG_MAGIC)
  10580. return;
  10581. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  10582. if (!(apedata & APE_FW_STATUS_READY))
  10583. return;
  10584. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  10585. if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
  10586. fwtype = "NCSI";
  10587. else
  10588. fwtype = "DASH";
  10589. vlen = strlen(tp->fw_ver);
  10590. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
  10591. fwtype,
  10592. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  10593. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  10594. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  10595. (apedata & APE_FW_VERSION_BLDMSK));
  10596. }
  10597. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  10598. {
  10599. u32 val;
  10600. bool vpd_vers = false;
  10601. if (tp->fw_ver[0] != 0)
  10602. vpd_vers = true;
  10603. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
  10604. strcat(tp->fw_ver, "sb");
  10605. return;
  10606. }
  10607. if (tg3_nvram_read(tp, 0, &val))
  10608. return;
  10609. if (val == TG3_EEPROM_MAGIC)
  10610. tg3_read_bc_ver(tp);
  10611. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  10612. tg3_read_sb_ver(tp, val);
  10613. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  10614. tg3_read_hwsb_ver(tp);
  10615. else
  10616. return;
  10617. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  10618. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
  10619. goto done;
  10620. tg3_read_mgmtfw_ver(tp);
  10621. done:
  10622. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  10623. }
  10624. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  10625. static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
  10626. {
  10627. #if TG3_VLAN_TAG_USED
  10628. dev->vlan_features |= flags;
  10629. #endif
  10630. }
  10631. static int __devinit tg3_get_invariants(struct tg3 *tp)
  10632. {
  10633. static struct pci_device_id write_reorder_chipsets[] = {
  10634. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  10635. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  10636. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  10637. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  10638. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  10639. PCI_DEVICE_ID_VIA_8385_0) },
  10640. { },
  10641. };
  10642. u32 misc_ctrl_reg;
  10643. u32 pci_state_reg, grc_misc_cfg;
  10644. u32 val;
  10645. u16 pci_cmd;
  10646. int err;
  10647. /* Force memory write invalidate off. If we leave it on,
  10648. * then on 5700_BX chips we have to enable a workaround.
  10649. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  10650. * to match the cacheline size. The Broadcom driver have this
  10651. * workaround but turns MWI off all the times so never uses
  10652. * it. This seems to suggest that the workaround is insufficient.
  10653. */
  10654. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  10655. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  10656. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  10657. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  10658. * has the register indirect write enable bit set before
  10659. * we try to access any of the MMIO registers. It is also
  10660. * critical that the PCI-X hw workaround situation is decided
  10661. * before that as well.
  10662. */
  10663. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10664. &misc_ctrl_reg);
  10665. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  10666. MISC_HOST_CTRL_CHIPREV_SHIFT);
  10667. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  10668. u32 prod_id_asic_rev;
  10669. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  10670. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  10671. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
  10672. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
  10673. pci_read_config_dword(tp->pdev,
  10674. TG3PCI_GEN2_PRODID_ASICREV,
  10675. &prod_id_asic_rev);
  10676. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  10677. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  10678. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  10679. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  10680. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  10681. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  10682. pci_read_config_dword(tp->pdev,
  10683. TG3PCI_GEN15_PRODID_ASICREV,
  10684. &prod_id_asic_rev);
  10685. else
  10686. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  10687. &prod_id_asic_rev);
  10688. tp->pci_chip_rev_id = prod_id_asic_rev;
  10689. }
  10690. /* Wrong chip ID in 5752 A0. This code can be removed later
  10691. * as A0 is not in production.
  10692. */
  10693. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  10694. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  10695. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  10696. * we need to disable memory and use config. cycles
  10697. * only to access all registers. The 5702/03 chips
  10698. * can mistakenly decode the special cycles from the
  10699. * ICH chipsets as memory write cycles, causing corruption
  10700. * of register and memory space. Only certain ICH bridges
  10701. * will drive special cycles with non-zero data during the
  10702. * address phase which can fall within the 5703's address
  10703. * range. This is not an ICH bug as the PCI spec allows
  10704. * non-zero address during special cycles. However, only
  10705. * these ICH bridges are known to drive non-zero addresses
  10706. * during special cycles.
  10707. *
  10708. * Since special cycles do not cross PCI bridges, we only
  10709. * enable this workaround if the 5703 is on the secondary
  10710. * bus of these ICH bridges.
  10711. */
  10712. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  10713. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  10714. static struct tg3_dev_id {
  10715. u32 vendor;
  10716. u32 device;
  10717. u32 rev;
  10718. } ich_chipsets[] = {
  10719. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  10720. PCI_ANY_ID },
  10721. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  10722. PCI_ANY_ID },
  10723. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  10724. 0xa },
  10725. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  10726. PCI_ANY_ID },
  10727. { },
  10728. };
  10729. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  10730. struct pci_dev *bridge = NULL;
  10731. while (pci_id->vendor != 0) {
  10732. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  10733. bridge);
  10734. if (!bridge) {
  10735. pci_id++;
  10736. continue;
  10737. }
  10738. if (pci_id->rev != PCI_ANY_ID) {
  10739. if (bridge->revision > pci_id->rev)
  10740. continue;
  10741. }
  10742. if (bridge->subordinate &&
  10743. (bridge->subordinate->number ==
  10744. tp->pdev->bus->number)) {
  10745. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  10746. pci_dev_put(bridge);
  10747. break;
  10748. }
  10749. }
  10750. }
  10751. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  10752. static struct tg3_dev_id {
  10753. u32 vendor;
  10754. u32 device;
  10755. } bridge_chipsets[] = {
  10756. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  10757. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  10758. { },
  10759. };
  10760. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  10761. struct pci_dev *bridge = NULL;
  10762. while (pci_id->vendor != 0) {
  10763. bridge = pci_get_device(pci_id->vendor,
  10764. pci_id->device,
  10765. bridge);
  10766. if (!bridge) {
  10767. pci_id++;
  10768. continue;
  10769. }
  10770. if (bridge->subordinate &&
  10771. (bridge->subordinate->number <=
  10772. tp->pdev->bus->number) &&
  10773. (bridge->subordinate->subordinate >=
  10774. tp->pdev->bus->number)) {
  10775. tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
  10776. pci_dev_put(bridge);
  10777. break;
  10778. }
  10779. }
  10780. }
  10781. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  10782. * DMA addresses > 40-bit. This bridge may have other additional
  10783. * 57xx devices behind it in some 4-port NIC designs for example.
  10784. * Any tg3 device found behind the bridge will also need the 40-bit
  10785. * DMA workaround.
  10786. */
  10787. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  10788. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  10789. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  10790. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10791. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  10792. } else {
  10793. struct pci_dev *bridge = NULL;
  10794. do {
  10795. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  10796. PCI_DEVICE_ID_SERVERWORKS_EPB,
  10797. bridge);
  10798. if (bridge && bridge->subordinate &&
  10799. (bridge->subordinate->number <=
  10800. tp->pdev->bus->number) &&
  10801. (bridge->subordinate->subordinate >=
  10802. tp->pdev->bus->number)) {
  10803. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10804. pci_dev_put(bridge);
  10805. break;
  10806. }
  10807. } while (bridge);
  10808. }
  10809. /* Initialize misc host control in PCI block. */
  10810. tp->misc_host_ctrl |= (misc_ctrl_reg &
  10811. MISC_HOST_CTRL_CHIPREV);
  10812. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10813. tp->misc_host_ctrl);
  10814. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  10815. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
  10816. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  10817. tp->pdev_peer = tg3_find_peer(tp);
  10818. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10819. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  10820. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10821. tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
  10822. /* Intentionally exclude ASIC_REV_5906 */
  10823. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10824. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10825. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10826. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10827. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  10828. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  10829. (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
  10830. tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
  10831. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  10832. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  10833. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10834. (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10835. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  10836. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  10837. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  10838. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  10839. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  10840. /* 5700 B0 chips do not support checksumming correctly due
  10841. * to hardware bugs.
  10842. */
  10843. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  10844. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  10845. else {
  10846. unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
  10847. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10848. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  10849. features |= NETIF_F_IPV6_CSUM;
  10850. tp->dev->features |= features;
  10851. vlan_features_add(tp->dev, features);
  10852. }
  10853. /* Determine TSO capabilities */
  10854. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
  10855. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
  10856. else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10857. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10858. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  10859. else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  10860. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  10861. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
  10862. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  10863. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  10864. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10865. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  10866. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  10867. tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
  10868. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  10869. tp->fw_needed = FIRMWARE_TG3TSO5;
  10870. else
  10871. tp->fw_needed = FIRMWARE_TG3TSO;
  10872. }
  10873. tp->irq_max = 1;
  10874. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  10875. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  10876. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  10877. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  10878. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  10879. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  10880. tp->pdev_peer == tp->pdev))
  10881. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  10882. if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10883. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10884. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  10885. }
  10886. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  10887. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
  10888. tp->irq_max = TG3_IRQ_MAX_VECS;
  10889. }
  10890. }
  10891. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10892. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  10893. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10894. tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
  10895. else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
  10896. tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
  10897. tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
  10898. }
  10899. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
  10900. tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
  10901. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  10902. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  10903. (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
  10904. tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
  10905. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10906. &pci_state_reg);
  10907. tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  10908. if (tp->pcie_cap != 0) {
  10909. u16 lnkctl;
  10910. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  10911. pcie_set_readrq(tp->pdev, 4096);
  10912. pci_read_config_word(tp->pdev,
  10913. tp->pcie_cap + PCI_EXP_LNKCTL,
  10914. &lnkctl);
  10915. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  10916. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10917. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  10918. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10919. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10920. tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
  10921. tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
  10922. tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
  10923. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
  10924. tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
  10925. }
  10926. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  10927. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  10928. } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  10929. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  10930. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  10931. if (!tp->pcix_cap) {
  10932. dev_err(&tp->pdev->dev,
  10933. "Cannot find PCI-X capability, aborting\n");
  10934. return -EIO;
  10935. }
  10936. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  10937. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  10938. }
  10939. /* If we have an AMD 762 or VIA K8T800 chipset, write
  10940. * reordering to the mailbox registers done by the host
  10941. * controller can cause major troubles. We read back from
  10942. * every mailbox register write to force the writes to be
  10943. * posted to the chip in order.
  10944. */
  10945. if (pci_dev_present(write_reorder_chipsets) &&
  10946. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  10947. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  10948. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  10949. &tp->pci_cacheline_sz);
  10950. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  10951. &tp->pci_lat_timer);
  10952. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  10953. tp->pci_lat_timer < 64) {
  10954. tp->pci_lat_timer = 64;
  10955. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  10956. tp->pci_lat_timer);
  10957. }
  10958. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  10959. /* 5700 BX chips need to have their TX producer index
  10960. * mailboxes written twice to workaround a bug.
  10961. */
  10962. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  10963. /* If we are in PCI-X mode, enable register write workaround.
  10964. *
  10965. * The workaround is to use indirect register accesses
  10966. * for all chip writes not to mailbox registers.
  10967. */
  10968. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  10969. u32 pm_reg;
  10970. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  10971. /* The chip can have it's power management PCI config
  10972. * space registers clobbered due to this bug.
  10973. * So explicitly force the chip into D0 here.
  10974. */
  10975. pci_read_config_dword(tp->pdev,
  10976. tp->pm_cap + PCI_PM_CTRL,
  10977. &pm_reg);
  10978. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  10979. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  10980. pci_write_config_dword(tp->pdev,
  10981. tp->pm_cap + PCI_PM_CTRL,
  10982. pm_reg);
  10983. /* Also, force SERR#/PERR# in PCI command. */
  10984. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  10985. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  10986. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  10987. }
  10988. }
  10989. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  10990. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  10991. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  10992. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  10993. /* Chip-specific fixup from Broadcom driver */
  10994. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  10995. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  10996. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  10997. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  10998. }
  10999. /* Default fast path register access methods */
  11000. tp->read32 = tg3_read32;
  11001. tp->write32 = tg3_write32;
  11002. tp->read32_mbox = tg3_read32;
  11003. tp->write32_mbox = tg3_write32;
  11004. tp->write32_tx_mbox = tg3_write32;
  11005. tp->write32_rx_mbox = tg3_write32;
  11006. /* Various workaround register access methods */
  11007. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  11008. tp->write32 = tg3_write_indirect_reg32;
  11009. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  11010. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  11011. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  11012. /*
  11013. * Back to back register writes can cause problems on these
  11014. * chips, the workaround is to read back all reg writes
  11015. * except those to mailbox regs.
  11016. *
  11017. * See tg3_write_indirect_reg32().
  11018. */
  11019. tp->write32 = tg3_write_flush_reg32;
  11020. }
  11021. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  11022. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  11023. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  11024. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  11025. tp->write32_rx_mbox = tg3_write_flush_reg32;
  11026. }
  11027. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  11028. tp->read32 = tg3_read_indirect_reg32;
  11029. tp->write32 = tg3_write_indirect_reg32;
  11030. tp->read32_mbox = tg3_read_indirect_mbox;
  11031. tp->write32_mbox = tg3_write_indirect_mbox;
  11032. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  11033. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  11034. iounmap(tp->regs);
  11035. tp->regs = NULL;
  11036. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11037. pci_cmd &= ~PCI_COMMAND_MEMORY;
  11038. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11039. }
  11040. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11041. tp->read32_mbox = tg3_read32_mbox_5906;
  11042. tp->write32_mbox = tg3_write32_mbox_5906;
  11043. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  11044. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  11045. }
  11046. if (tp->write32 == tg3_write_indirect_reg32 ||
  11047. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  11048. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11049. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  11050. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  11051. /* Get eeprom hw config before calling tg3_set_power_state().
  11052. * In particular, the TG3_FLG2_IS_NIC flag must be
  11053. * determined before calling tg3_set_power_state() so that
  11054. * we know whether or not to switch out of Vaux power.
  11055. * When the flag is set, it means that GPIO1 is used for eeprom
  11056. * write protect and also implies that it is a LOM where GPIOs
  11057. * are not used to switch power.
  11058. */
  11059. tg3_get_eeprom_hw_cfg(tp);
  11060. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  11061. /* Allow reads and writes to the
  11062. * APE register and memory space.
  11063. */
  11064. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  11065. PCISTATE_ALLOW_APE_SHMEM_WR |
  11066. PCISTATE_ALLOW_APE_PSPACE_WR;
  11067. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11068. pci_state_reg);
  11069. }
  11070. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11071. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11072. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11073. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11074. (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
  11075. tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
  11076. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  11077. * GPIO1 driven high will bring 5700's external PHY out of reset.
  11078. * It is also used as eeprom write protect on LOMs.
  11079. */
  11080. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  11081. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  11082. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  11083. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  11084. GRC_LCLCTRL_GPIO_OUTPUT1);
  11085. /* Unused GPIO3 must be driven as output on 5752 because there
  11086. * are no pull-up resistors on unused GPIO pins.
  11087. */
  11088. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  11089. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  11090. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11091. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11092. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  11093. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11094. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  11095. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  11096. /* Turn off the debug UART. */
  11097. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11098. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  11099. /* Keep VMain power. */
  11100. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  11101. GRC_LCLCTRL_GPIO_OUTPUT0;
  11102. }
  11103. /* Force the chip into D0. */
  11104. err = tg3_set_power_state(tp, PCI_D0);
  11105. if (err) {
  11106. dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
  11107. return err;
  11108. }
  11109. /* Derive initial jumbo mode from MTU assigned in
  11110. * ether_setup() via the alloc_etherdev() call
  11111. */
  11112. if (tp->dev->mtu > ETH_DATA_LEN &&
  11113. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  11114. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  11115. /* Determine WakeOnLan speed to use. */
  11116. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11117. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  11118. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  11119. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  11120. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  11121. } else {
  11122. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  11123. }
  11124. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11125. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  11126. /* A few boards don't want Ethernet@WireSpeed phy feature */
  11127. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  11128. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  11129. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  11130. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  11131. (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
  11132. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  11133. tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
  11134. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  11135. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  11136. tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
  11137. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  11138. tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
  11139. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  11140. !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  11141. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  11142. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
  11143. !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
  11144. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11145. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  11146. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11147. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  11148. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  11149. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  11150. tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
  11151. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  11152. tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
  11153. } else
  11154. tp->phy_flags |= TG3_PHYFLG_BER_BUG;
  11155. }
  11156. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  11157. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  11158. tp->phy_otp = tg3_read_otp_phycfg(tp);
  11159. if (tp->phy_otp == 0)
  11160. tp->phy_otp = TG3_OTP_DEFAULT;
  11161. }
  11162. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
  11163. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  11164. else
  11165. tp->mi_mode = MAC_MI_MODE_BASE;
  11166. tp->coalesce_mode = 0;
  11167. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  11168. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  11169. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  11170. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11171. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  11172. tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
  11173. err = tg3_mdio_init(tp);
  11174. if (err)
  11175. return err;
  11176. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
  11177. tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  11178. return -ENOTSUPP;
  11179. /* Initialize data/descriptor byte/word swapping. */
  11180. val = tr32(GRC_MODE);
  11181. val &= GRC_MODE_HOST_STACKUP;
  11182. tw32(GRC_MODE, val | tp->grc_mode);
  11183. tg3_switch_clocks(tp);
  11184. /* Clear this out for sanity. */
  11185. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  11186. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11187. &pci_state_reg);
  11188. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  11189. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  11190. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  11191. if (chiprevid == CHIPREV_ID_5701_A0 ||
  11192. chiprevid == CHIPREV_ID_5701_B0 ||
  11193. chiprevid == CHIPREV_ID_5701_B2 ||
  11194. chiprevid == CHIPREV_ID_5701_B5) {
  11195. void __iomem *sram_base;
  11196. /* Write some dummy words into the SRAM status block
  11197. * area, see if it reads back correctly. If the return
  11198. * value is bad, force enable the PCIX workaround.
  11199. */
  11200. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  11201. writel(0x00000000, sram_base);
  11202. writel(0x00000000, sram_base + 4);
  11203. writel(0xffffffff, sram_base + 4);
  11204. if (readl(sram_base) != 0x00000000)
  11205. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  11206. }
  11207. }
  11208. udelay(50);
  11209. tg3_nvram_init(tp);
  11210. grc_misc_cfg = tr32(GRC_MISC_CFG);
  11211. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  11212. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  11213. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  11214. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  11215. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  11216. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  11217. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  11218. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  11219. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  11220. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  11221. HOSTCC_MODE_CLRTICK_TXBD);
  11222. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  11223. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  11224. tp->misc_host_ctrl);
  11225. }
  11226. /* Preserve the APE MAC_MODE bits */
  11227. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  11228. tp->mac_mode = tr32(MAC_MODE) |
  11229. MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  11230. else
  11231. tp->mac_mode = TG3_DEF_MAC_MODE;
  11232. /* these are limited to 10/100 only */
  11233. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  11234. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  11235. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  11236. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  11237. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  11238. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  11239. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  11240. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  11241. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  11242. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  11243. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  11244. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
  11245. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  11246. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
  11247. (tp->phy_flags & TG3_PHYFLG_IS_FET))
  11248. tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
  11249. err = tg3_phy_probe(tp);
  11250. if (err) {
  11251. dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
  11252. /* ... but do not return immediately ... */
  11253. tg3_mdio_fini(tp);
  11254. }
  11255. tg3_read_vpd(tp);
  11256. tg3_read_fw_ver(tp);
  11257. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  11258. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  11259. } else {
  11260. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  11261. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  11262. else
  11263. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  11264. }
  11265. /* 5700 {AX,BX} chips have a broken status block link
  11266. * change bit implementation, so we must use the
  11267. * status register in those cases.
  11268. */
  11269. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  11270. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  11271. else
  11272. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  11273. /* The led_ctrl is set during tg3_phy_probe, here we might
  11274. * have to force the link status polling mechanism based
  11275. * upon subsystem IDs.
  11276. */
  11277. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  11278. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  11279. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  11280. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  11281. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  11282. }
  11283. /* For all SERDES we poll the MAC status register. */
  11284. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  11285. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  11286. else
  11287. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  11288. tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
  11289. tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
  11290. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  11291. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
  11292. tp->rx_offset -= NET_IP_ALIGN;
  11293. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  11294. tp->rx_copy_thresh = ~(u16)0;
  11295. #endif
  11296. }
  11297. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  11298. /* Increment the rx prod index on the rx std ring by at most
  11299. * 8 for these chips to workaround hw errata.
  11300. */
  11301. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  11302. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  11303. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  11304. tp->rx_std_max_post = 8;
  11305. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  11306. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  11307. PCIE_PWR_MGMT_L1_THRESH_MSK;
  11308. return err;
  11309. }
  11310. #ifdef CONFIG_SPARC
  11311. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  11312. {
  11313. struct net_device *dev = tp->dev;
  11314. struct pci_dev *pdev = tp->pdev;
  11315. struct device_node *dp = pci_device_to_OF_node(pdev);
  11316. const unsigned char *addr;
  11317. int len;
  11318. addr = of_get_property(dp, "local-mac-address", &len);
  11319. if (addr && len == 6) {
  11320. memcpy(dev->dev_addr, addr, 6);
  11321. memcpy(dev->perm_addr, dev->dev_addr, 6);
  11322. return 0;
  11323. }
  11324. return -ENODEV;
  11325. }
  11326. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  11327. {
  11328. struct net_device *dev = tp->dev;
  11329. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  11330. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  11331. return 0;
  11332. }
  11333. #endif
  11334. static int __devinit tg3_get_device_address(struct tg3 *tp)
  11335. {
  11336. struct net_device *dev = tp->dev;
  11337. u32 hi, lo, mac_offset;
  11338. int addr_ok = 0;
  11339. #ifdef CONFIG_SPARC
  11340. if (!tg3_get_macaddr_sparc(tp))
  11341. return 0;
  11342. #endif
  11343. mac_offset = 0x7c;
  11344. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  11345. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  11346. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  11347. mac_offset = 0xcc;
  11348. if (tg3_nvram_lock(tp))
  11349. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  11350. else
  11351. tg3_nvram_unlock(tp);
  11352. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11353. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
  11354. if (PCI_FUNC(tp->pdev->devfn) & 1)
  11355. mac_offset = 0xcc;
  11356. if (PCI_FUNC(tp->pdev->devfn) > 1)
  11357. mac_offset += 0x18c;
  11358. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11359. mac_offset = 0x10;
  11360. /* First try to get it from MAC address mailbox. */
  11361. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  11362. if ((hi >> 16) == 0x484b) {
  11363. dev->dev_addr[0] = (hi >> 8) & 0xff;
  11364. dev->dev_addr[1] = (hi >> 0) & 0xff;
  11365. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  11366. dev->dev_addr[2] = (lo >> 24) & 0xff;
  11367. dev->dev_addr[3] = (lo >> 16) & 0xff;
  11368. dev->dev_addr[4] = (lo >> 8) & 0xff;
  11369. dev->dev_addr[5] = (lo >> 0) & 0xff;
  11370. /* Some old bootcode may report a 0 MAC address in SRAM */
  11371. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  11372. }
  11373. if (!addr_ok) {
  11374. /* Next, try NVRAM. */
  11375. if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
  11376. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  11377. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  11378. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  11379. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  11380. }
  11381. /* Finally just fetch it out of the MAC control regs. */
  11382. else {
  11383. hi = tr32(MAC_ADDR_0_HIGH);
  11384. lo = tr32(MAC_ADDR_0_LOW);
  11385. dev->dev_addr[5] = lo & 0xff;
  11386. dev->dev_addr[4] = (lo >> 8) & 0xff;
  11387. dev->dev_addr[3] = (lo >> 16) & 0xff;
  11388. dev->dev_addr[2] = (lo >> 24) & 0xff;
  11389. dev->dev_addr[1] = hi & 0xff;
  11390. dev->dev_addr[0] = (hi >> 8) & 0xff;
  11391. }
  11392. }
  11393. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  11394. #ifdef CONFIG_SPARC
  11395. if (!tg3_get_default_macaddr_sparc(tp))
  11396. return 0;
  11397. #endif
  11398. return -EINVAL;
  11399. }
  11400. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  11401. return 0;
  11402. }
  11403. #define BOUNDARY_SINGLE_CACHELINE 1
  11404. #define BOUNDARY_MULTI_CACHELINE 2
  11405. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  11406. {
  11407. int cacheline_size;
  11408. u8 byte;
  11409. int goal;
  11410. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  11411. if (byte == 0)
  11412. cacheline_size = 1024;
  11413. else
  11414. cacheline_size = (int) byte * 4;
  11415. /* On 5703 and later chips, the boundary bits have no
  11416. * effect.
  11417. */
  11418. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  11419. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  11420. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  11421. goto out;
  11422. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  11423. goal = BOUNDARY_MULTI_CACHELINE;
  11424. #else
  11425. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  11426. goal = BOUNDARY_SINGLE_CACHELINE;
  11427. #else
  11428. goal = 0;
  11429. #endif
  11430. #endif
  11431. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  11432. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  11433. goto out;
  11434. }
  11435. if (!goal)
  11436. goto out;
  11437. /* PCI controllers on most RISC systems tend to disconnect
  11438. * when a device tries to burst across a cache-line boundary.
  11439. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  11440. *
  11441. * Unfortunately, for PCI-E there are only limited
  11442. * write-side controls for this, and thus for reads
  11443. * we will still get the disconnects. We'll also waste
  11444. * these PCI cycles for both read and write for chips
  11445. * other than 5700 and 5701 which do not implement the
  11446. * boundary bits.
  11447. */
  11448. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  11449. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  11450. switch (cacheline_size) {
  11451. case 16:
  11452. case 32:
  11453. case 64:
  11454. case 128:
  11455. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11456. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  11457. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  11458. } else {
  11459. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  11460. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  11461. }
  11462. break;
  11463. case 256:
  11464. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  11465. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  11466. break;
  11467. default:
  11468. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  11469. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  11470. break;
  11471. }
  11472. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11473. switch (cacheline_size) {
  11474. case 16:
  11475. case 32:
  11476. case 64:
  11477. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11478. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  11479. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  11480. break;
  11481. }
  11482. /* fallthrough */
  11483. case 128:
  11484. default:
  11485. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  11486. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  11487. break;
  11488. }
  11489. } else {
  11490. switch (cacheline_size) {
  11491. case 16:
  11492. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11493. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  11494. DMA_RWCTRL_WRITE_BNDRY_16);
  11495. break;
  11496. }
  11497. /* fallthrough */
  11498. case 32:
  11499. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11500. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  11501. DMA_RWCTRL_WRITE_BNDRY_32);
  11502. break;
  11503. }
  11504. /* fallthrough */
  11505. case 64:
  11506. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11507. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  11508. DMA_RWCTRL_WRITE_BNDRY_64);
  11509. break;
  11510. }
  11511. /* fallthrough */
  11512. case 128:
  11513. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11514. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  11515. DMA_RWCTRL_WRITE_BNDRY_128);
  11516. break;
  11517. }
  11518. /* fallthrough */
  11519. case 256:
  11520. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  11521. DMA_RWCTRL_WRITE_BNDRY_256);
  11522. break;
  11523. case 512:
  11524. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  11525. DMA_RWCTRL_WRITE_BNDRY_512);
  11526. break;
  11527. case 1024:
  11528. default:
  11529. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  11530. DMA_RWCTRL_WRITE_BNDRY_1024);
  11531. break;
  11532. }
  11533. }
  11534. out:
  11535. return val;
  11536. }
  11537. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  11538. {
  11539. struct tg3_internal_buffer_desc test_desc;
  11540. u32 sram_dma_descs;
  11541. int i, ret;
  11542. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  11543. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  11544. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  11545. tw32(RDMAC_STATUS, 0);
  11546. tw32(WDMAC_STATUS, 0);
  11547. tw32(BUFMGR_MODE, 0);
  11548. tw32(FTQ_RESET, 0);
  11549. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  11550. test_desc.addr_lo = buf_dma & 0xffffffff;
  11551. test_desc.nic_mbuf = 0x00002100;
  11552. test_desc.len = size;
  11553. /*
  11554. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  11555. * the *second* time the tg3 driver was getting loaded after an
  11556. * initial scan.
  11557. *
  11558. * Broadcom tells me:
  11559. * ...the DMA engine is connected to the GRC block and a DMA
  11560. * reset may affect the GRC block in some unpredictable way...
  11561. * The behavior of resets to individual blocks has not been tested.
  11562. *
  11563. * Broadcom noted the GRC reset will also reset all sub-components.
  11564. */
  11565. if (to_device) {
  11566. test_desc.cqid_sqid = (13 << 8) | 2;
  11567. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  11568. udelay(40);
  11569. } else {
  11570. test_desc.cqid_sqid = (16 << 8) | 7;
  11571. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  11572. udelay(40);
  11573. }
  11574. test_desc.flags = 0x00000005;
  11575. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  11576. u32 val;
  11577. val = *(((u32 *)&test_desc) + i);
  11578. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  11579. sram_dma_descs + (i * sizeof(u32)));
  11580. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  11581. }
  11582. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  11583. if (to_device)
  11584. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  11585. else
  11586. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  11587. ret = -ENODEV;
  11588. for (i = 0; i < 40; i++) {
  11589. u32 val;
  11590. if (to_device)
  11591. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  11592. else
  11593. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  11594. if ((val & 0xffff) == sram_dma_descs) {
  11595. ret = 0;
  11596. break;
  11597. }
  11598. udelay(100);
  11599. }
  11600. return ret;
  11601. }
  11602. #define TEST_BUFFER_SIZE 0x2000
  11603. static int __devinit tg3_test_dma(struct tg3 *tp)
  11604. {
  11605. dma_addr_t buf_dma;
  11606. u32 *buf, saved_dma_rwctrl;
  11607. int ret = 0;
  11608. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  11609. if (!buf) {
  11610. ret = -ENOMEM;
  11611. goto out_nofree;
  11612. }
  11613. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  11614. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  11615. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  11616. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
  11617. goto out;
  11618. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11619. /* DMA read watermark not used on PCIE */
  11620. tp->dma_rwctrl |= 0x00180000;
  11621. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  11622. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  11623. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  11624. tp->dma_rwctrl |= 0x003f0000;
  11625. else
  11626. tp->dma_rwctrl |= 0x003f000f;
  11627. } else {
  11628. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  11629. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  11630. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  11631. u32 read_water = 0x7;
  11632. /* If the 5704 is behind the EPB bridge, we can
  11633. * do the less restrictive ONE_DMA workaround for
  11634. * better performance.
  11635. */
  11636. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  11637. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  11638. tp->dma_rwctrl |= 0x8000;
  11639. else if (ccval == 0x6 || ccval == 0x7)
  11640. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  11641. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  11642. read_water = 4;
  11643. /* Set bit 23 to enable PCIX hw bug fix */
  11644. tp->dma_rwctrl |=
  11645. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  11646. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  11647. (1 << 23);
  11648. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  11649. /* 5780 always in PCIX mode */
  11650. tp->dma_rwctrl |= 0x00144000;
  11651. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  11652. /* 5714 always in PCIX mode */
  11653. tp->dma_rwctrl |= 0x00148000;
  11654. } else {
  11655. tp->dma_rwctrl |= 0x001b000f;
  11656. }
  11657. }
  11658. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  11659. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  11660. tp->dma_rwctrl &= 0xfffffff0;
  11661. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11662. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  11663. /* Remove this if it causes problems for some boards. */
  11664. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  11665. /* On 5700/5701 chips, we need to set this bit.
  11666. * Otherwise the chip will issue cacheline transactions
  11667. * to streamable DMA memory with not all the byte
  11668. * enables turned on. This is an error on several
  11669. * RISC PCI controllers, in particular sparc64.
  11670. *
  11671. * On 5703/5704 chips, this bit has been reassigned
  11672. * a different meaning. In particular, it is used
  11673. * on those chips to enable a PCI-X workaround.
  11674. */
  11675. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  11676. }
  11677. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11678. #if 0
  11679. /* Unneeded, already done by tg3_get_invariants. */
  11680. tg3_switch_clocks(tp);
  11681. #endif
  11682. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  11683. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  11684. goto out;
  11685. /* It is best to perform DMA test with maximum write burst size
  11686. * to expose the 5700/5701 write DMA bug.
  11687. */
  11688. saved_dma_rwctrl = tp->dma_rwctrl;
  11689. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11690. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11691. while (1) {
  11692. u32 *p = buf, i;
  11693. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  11694. p[i] = i;
  11695. /* Send the buffer to the chip. */
  11696. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  11697. if (ret) {
  11698. dev_err(&tp->pdev->dev,
  11699. "%s: Buffer write failed. err = %d\n",
  11700. __func__, ret);
  11701. break;
  11702. }
  11703. #if 0
  11704. /* validate data reached card RAM correctly. */
  11705. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  11706. u32 val;
  11707. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  11708. if (le32_to_cpu(val) != p[i]) {
  11709. dev_err(&tp->pdev->dev,
  11710. "%s: Buffer corrupted on device! "
  11711. "(%d != %d)\n", __func__, val, i);
  11712. /* ret = -ENODEV here? */
  11713. }
  11714. p[i] = 0;
  11715. }
  11716. #endif
  11717. /* Now read it back. */
  11718. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  11719. if (ret) {
  11720. dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
  11721. "err = %d\n", __func__, ret);
  11722. break;
  11723. }
  11724. /* Verify it. */
  11725. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  11726. if (p[i] == i)
  11727. continue;
  11728. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  11729. DMA_RWCTRL_WRITE_BNDRY_16) {
  11730. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11731. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  11732. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11733. break;
  11734. } else {
  11735. dev_err(&tp->pdev->dev,
  11736. "%s: Buffer corrupted on read back! "
  11737. "(%d != %d)\n", __func__, p[i], i);
  11738. ret = -ENODEV;
  11739. goto out;
  11740. }
  11741. }
  11742. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  11743. /* Success. */
  11744. ret = 0;
  11745. break;
  11746. }
  11747. }
  11748. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  11749. DMA_RWCTRL_WRITE_BNDRY_16) {
  11750. static struct pci_device_id dma_wait_state_chipsets[] = {
  11751. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  11752. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  11753. { },
  11754. };
  11755. /* DMA test passed without adjusting DMA boundary,
  11756. * now look for chipsets that are known to expose the
  11757. * DMA bug without failing the test.
  11758. */
  11759. if (pci_dev_present(dma_wait_state_chipsets)) {
  11760. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11761. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  11762. } else {
  11763. /* Safe to use the calculated DMA boundary. */
  11764. tp->dma_rwctrl = saved_dma_rwctrl;
  11765. }
  11766. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11767. }
  11768. out:
  11769. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  11770. out_nofree:
  11771. return ret;
  11772. }
  11773. static void __devinit tg3_init_link_config(struct tg3 *tp)
  11774. {
  11775. tp->link_config.advertising =
  11776. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  11777. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  11778. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  11779. ADVERTISED_Autoneg | ADVERTISED_MII);
  11780. tp->link_config.speed = SPEED_INVALID;
  11781. tp->link_config.duplex = DUPLEX_INVALID;
  11782. tp->link_config.autoneg = AUTONEG_ENABLE;
  11783. tp->link_config.active_speed = SPEED_INVALID;
  11784. tp->link_config.active_duplex = DUPLEX_INVALID;
  11785. tp->link_config.orig_speed = SPEED_INVALID;
  11786. tp->link_config.orig_duplex = DUPLEX_INVALID;
  11787. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  11788. }
  11789. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  11790. {
  11791. if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  11792. tp->bufmgr_config.mbuf_read_dma_low_water =
  11793. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11794. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11795. DEFAULT_MB_MACRX_LOW_WATER_57765;
  11796. tp->bufmgr_config.mbuf_high_water =
  11797. DEFAULT_MB_HIGH_WATER_57765;
  11798. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11799. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11800. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11801. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  11802. tp->bufmgr_config.mbuf_high_water_jumbo =
  11803. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  11804. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  11805. tp->bufmgr_config.mbuf_read_dma_low_water =
  11806. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11807. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11808. DEFAULT_MB_MACRX_LOW_WATER_5705;
  11809. tp->bufmgr_config.mbuf_high_water =
  11810. DEFAULT_MB_HIGH_WATER_5705;
  11811. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11812. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11813. DEFAULT_MB_MACRX_LOW_WATER_5906;
  11814. tp->bufmgr_config.mbuf_high_water =
  11815. DEFAULT_MB_HIGH_WATER_5906;
  11816. }
  11817. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11818. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  11819. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11820. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  11821. tp->bufmgr_config.mbuf_high_water_jumbo =
  11822. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  11823. } else {
  11824. tp->bufmgr_config.mbuf_read_dma_low_water =
  11825. DEFAULT_MB_RDMA_LOW_WATER;
  11826. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11827. DEFAULT_MB_MACRX_LOW_WATER;
  11828. tp->bufmgr_config.mbuf_high_water =
  11829. DEFAULT_MB_HIGH_WATER;
  11830. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11831. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  11832. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11833. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  11834. tp->bufmgr_config.mbuf_high_water_jumbo =
  11835. DEFAULT_MB_HIGH_WATER_JUMBO;
  11836. }
  11837. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  11838. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  11839. }
  11840. static char * __devinit tg3_phy_string(struct tg3 *tp)
  11841. {
  11842. switch (tp->phy_id & TG3_PHY_ID_MASK) {
  11843. case TG3_PHY_ID_BCM5400: return "5400";
  11844. case TG3_PHY_ID_BCM5401: return "5401";
  11845. case TG3_PHY_ID_BCM5411: return "5411";
  11846. case TG3_PHY_ID_BCM5701: return "5701";
  11847. case TG3_PHY_ID_BCM5703: return "5703";
  11848. case TG3_PHY_ID_BCM5704: return "5704";
  11849. case TG3_PHY_ID_BCM5705: return "5705";
  11850. case TG3_PHY_ID_BCM5750: return "5750";
  11851. case TG3_PHY_ID_BCM5752: return "5752";
  11852. case TG3_PHY_ID_BCM5714: return "5714";
  11853. case TG3_PHY_ID_BCM5780: return "5780";
  11854. case TG3_PHY_ID_BCM5755: return "5755";
  11855. case TG3_PHY_ID_BCM5787: return "5787";
  11856. case TG3_PHY_ID_BCM5784: return "5784";
  11857. case TG3_PHY_ID_BCM5756: return "5722/5756";
  11858. case TG3_PHY_ID_BCM5906: return "5906";
  11859. case TG3_PHY_ID_BCM5761: return "5761";
  11860. case TG3_PHY_ID_BCM5718C: return "5718C";
  11861. case TG3_PHY_ID_BCM5718S: return "5718S";
  11862. case TG3_PHY_ID_BCM57765: return "57765";
  11863. case TG3_PHY_ID_BCM5719C: return "5719C";
  11864. case TG3_PHY_ID_BCM8002: return "8002/serdes";
  11865. case 0: return "serdes";
  11866. default: return "unknown";
  11867. }
  11868. }
  11869. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  11870. {
  11871. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11872. strcpy(str, "PCI Express");
  11873. return str;
  11874. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  11875. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  11876. strcpy(str, "PCIX:");
  11877. if ((clock_ctrl == 7) ||
  11878. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  11879. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  11880. strcat(str, "133MHz");
  11881. else if (clock_ctrl == 0)
  11882. strcat(str, "33MHz");
  11883. else if (clock_ctrl == 2)
  11884. strcat(str, "50MHz");
  11885. else if (clock_ctrl == 4)
  11886. strcat(str, "66MHz");
  11887. else if (clock_ctrl == 6)
  11888. strcat(str, "100MHz");
  11889. } else {
  11890. strcpy(str, "PCI:");
  11891. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  11892. strcat(str, "66MHz");
  11893. else
  11894. strcat(str, "33MHz");
  11895. }
  11896. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  11897. strcat(str, ":32-bit");
  11898. else
  11899. strcat(str, ":64-bit");
  11900. return str;
  11901. }
  11902. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  11903. {
  11904. struct pci_dev *peer;
  11905. unsigned int func, devnr = tp->pdev->devfn & ~7;
  11906. for (func = 0; func < 8; func++) {
  11907. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  11908. if (peer && peer != tp->pdev)
  11909. break;
  11910. pci_dev_put(peer);
  11911. }
  11912. /* 5704 can be configured in single-port mode, set peer to
  11913. * tp->pdev in that case.
  11914. */
  11915. if (!peer) {
  11916. peer = tp->pdev;
  11917. return peer;
  11918. }
  11919. /*
  11920. * We don't need to keep the refcount elevated; there's no way
  11921. * to remove one half of this device without removing the other
  11922. */
  11923. pci_dev_put(peer);
  11924. return peer;
  11925. }
  11926. static void __devinit tg3_init_coal(struct tg3 *tp)
  11927. {
  11928. struct ethtool_coalesce *ec = &tp->coal;
  11929. memset(ec, 0, sizeof(*ec));
  11930. ec->cmd = ETHTOOL_GCOALESCE;
  11931. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  11932. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  11933. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  11934. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  11935. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  11936. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  11937. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  11938. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  11939. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  11940. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  11941. HOSTCC_MODE_CLRTICK_TXBD)) {
  11942. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  11943. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  11944. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  11945. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  11946. }
  11947. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  11948. ec->rx_coalesce_usecs_irq = 0;
  11949. ec->tx_coalesce_usecs_irq = 0;
  11950. ec->stats_block_coalesce_usecs = 0;
  11951. }
  11952. }
  11953. static const struct net_device_ops tg3_netdev_ops = {
  11954. .ndo_open = tg3_open,
  11955. .ndo_stop = tg3_close,
  11956. .ndo_start_xmit = tg3_start_xmit,
  11957. .ndo_get_stats64 = tg3_get_stats64,
  11958. .ndo_validate_addr = eth_validate_addr,
  11959. .ndo_set_multicast_list = tg3_set_rx_mode,
  11960. .ndo_set_mac_address = tg3_set_mac_addr,
  11961. .ndo_do_ioctl = tg3_ioctl,
  11962. .ndo_tx_timeout = tg3_tx_timeout,
  11963. .ndo_change_mtu = tg3_change_mtu,
  11964. #if TG3_VLAN_TAG_USED
  11965. .ndo_vlan_rx_register = tg3_vlan_rx_register,
  11966. #endif
  11967. #ifdef CONFIG_NET_POLL_CONTROLLER
  11968. .ndo_poll_controller = tg3_poll_controller,
  11969. #endif
  11970. };
  11971. static const struct net_device_ops tg3_netdev_ops_dma_bug = {
  11972. .ndo_open = tg3_open,
  11973. .ndo_stop = tg3_close,
  11974. .ndo_start_xmit = tg3_start_xmit_dma_bug,
  11975. .ndo_get_stats64 = tg3_get_stats64,
  11976. .ndo_validate_addr = eth_validate_addr,
  11977. .ndo_set_multicast_list = tg3_set_rx_mode,
  11978. .ndo_set_mac_address = tg3_set_mac_addr,
  11979. .ndo_do_ioctl = tg3_ioctl,
  11980. .ndo_tx_timeout = tg3_tx_timeout,
  11981. .ndo_change_mtu = tg3_change_mtu,
  11982. #if TG3_VLAN_TAG_USED
  11983. .ndo_vlan_rx_register = tg3_vlan_rx_register,
  11984. #endif
  11985. #ifdef CONFIG_NET_POLL_CONTROLLER
  11986. .ndo_poll_controller = tg3_poll_controller,
  11987. #endif
  11988. };
  11989. static int __devinit tg3_init_one(struct pci_dev *pdev,
  11990. const struct pci_device_id *ent)
  11991. {
  11992. struct net_device *dev;
  11993. struct tg3 *tp;
  11994. int i, err, pm_cap;
  11995. u32 sndmbx, rcvmbx, intmbx;
  11996. char str[40];
  11997. u64 dma_mask, persist_dma_mask;
  11998. printk_once(KERN_INFO "%s\n", version);
  11999. err = pci_enable_device(pdev);
  12000. if (err) {
  12001. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  12002. return err;
  12003. }
  12004. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  12005. if (err) {
  12006. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  12007. goto err_out_disable_pdev;
  12008. }
  12009. pci_set_master(pdev);
  12010. /* Find power-management capability. */
  12011. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  12012. if (pm_cap == 0) {
  12013. dev_err(&pdev->dev,
  12014. "Cannot find Power Management capability, aborting\n");
  12015. err = -EIO;
  12016. goto err_out_free_res;
  12017. }
  12018. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  12019. if (!dev) {
  12020. dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
  12021. err = -ENOMEM;
  12022. goto err_out_free_res;
  12023. }
  12024. SET_NETDEV_DEV(dev, &pdev->dev);
  12025. #if TG3_VLAN_TAG_USED
  12026. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  12027. #endif
  12028. tp = netdev_priv(dev);
  12029. tp->pdev = pdev;
  12030. tp->dev = dev;
  12031. tp->pm_cap = pm_cap;
  12032. tp->rx_mode = TG3_DEF_RX_MODE;
  12033. tp->tx_mode = TG3_DEF_TX_MODE;
  12034. if (tg3_debug > 0)
  12035. tp->msg_enable = tg3_debug;
  12036. else
  12037. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  12038. /* The word/byte swap controls here control register access byte
  12039. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  12040. * setting below.
  12041. */
  12042. tp->misc_host_ctrl =
  12043. MISC_HOST_CTRL_MASK_PCI_INT |
  12044. MISC_HOST_CTRL_WORD_SWAP |
  12045. MISC_HOST_CTRL_INDIR_ACCESS |
  12046. MISC_HOST_CTRL_PCISTATE_RW;
  12047. /* The NONFRM (non-frame) byte/word swap controls take effect
  12048. * on descriptor entries, anything which isn't packet data.
  12049. *
  12050. * The StrongARM chips on the board (one for tx, one for rx)
  12051. * are running in big-endian mode.
  12052. */
  12053. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  12054. GRC_MODE_WSWAP_NONFRM_DATA);
  12055. #ifdef __BIG_ENDIAN
  12056. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  12057. #endif
  12058. spin_lock_init(&tp->lock);
  12059. spin_lock_init(&tp->indirect_lock);
  12060. INIT_WORK(&tp->reset_task, tg3_reset_task);
  12061. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  12062. if (!tp->regs) {
  12063. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  12064. err = -ENOMEM;
  12065. goto err_out_free_dev;
  12066. }
  12067. tg3_init_link_config(tp);
  12068. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  12069. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  12070. dev->ethtool_ops = &tg3_ethtool_ops;
  12071. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  12072. dev->irq = pdev->irq;
  12073. err = tg3_get_invariants(tp);
  12074. if (err) {
  12075. dev_err(&pdev->dev,
  12076. "Problem fetching invariants of chip, aborting\n");
  12077. goto err_out_iounmap;
  12078. }
  12079. if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
  12080. tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
  12081. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
  12082. dev->netdev_ops = &tg3_netdev_ops;
  12083. else
  12084. dev->netdev_ops = &tg3_netdev_ops_dma_bug;
  12085. /* The EPB bridge inside 5714, 5715, and 5780 and any
  12086. * device behind the EPB cannot support DMA addresses > 40-bit.
  12087. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  12088. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  12089. * do DMA address check in tg3_start_xmit().
  12090. */
  12091. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  12092. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  12093. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  12094. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  12095. #ifdef CONFIG_HIGHMEM
  12096. dma_mask = DMA_BIT_MASK(64);
  12097. #endif
  12098. } else
  12099. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  12100. /* Configure DMA attributes. */
  12101. if (dma_mask > DMA_BIT_MASK(32)) {
  12102. err = pci_set_dma_mask(pdev, dma_mask);
  12103. if (!err) {
  12104. dev->features |= NETIF_F_HIGHDMA;
  12105. err = pci_set_consistent_dma_mask(pdev,
  12106. persist_dma_mask);
  12107. if (err < 0) {
  12108. dev_err(&pdev->dev, "Unable to obtain 64 bit "
  12109. "DMA for consistent allocations\n");
  12110. goto err_out_iounmap;
  12111. }
  12112. }
  12113. }
  12114. if (err || dma_mask == DMA_BIT_MASK(32)) {
  12115. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  12116. if (err) {
  12117. dev_err(&pdev->dev,
  12118. "No usable DMA configuration, aborting\n");
  12119. goto err_out_iounmap;
  12120. }
  12121. }
  12122. tg3_init_bufmgr_config(tp);
  12123. /* Selectively allow TSO based on operating conditions */
  12124. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  12125. (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
  12126. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  12127. else {
  12128. tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
  12129. tp->fw_needed = NULL;
  12130. }
  12131. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
  12132. tp->fw_needed = FIRMWARE_TG3;
  12133. /* TSO is on by default on chips that support hardware TSO.
  12134. * Firmware TSO on older chips gives lower performance, so it
  12135. * is off by default, but can be enabled using ethtool.
  12136. */
  12137. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
  12138. (dev->features & NETIF_F_IP_CSUM)) {
  12139. dev->features |= NETIF_F_TSO;
  12140. vlan_features_add(dev, NETIF_F_TSO);
  12141. }
  12142. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
  12143. (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
  12144. if (dev->features & NETIF_F_IPV6_CSUM) {
  12145. dev->features |= NETIF_F_TSO6;
  12146. vlan_features_add(dev, NETIF_F_TSO6);
  12147. }
  12148. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  12149. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  12150. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  12151. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  12152. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  12153. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  12154. dev->features |= NETIF_F_TSO_ECN;
  12155. vlan_features_add(dev, NETIF_F_TSO_ECN);
  12156. }
  12157. }
  12158. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  12159. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  12160. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  12161. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  12162. tp->rx_pending = 63;
  12163. }
  12164. err = tg3_get_device_address(tp);
  12165. if (err) {
  12166. dev_err(&pdev->dev,
  12167. "Could not obtain valid ethernet address, aborting\n");
  12168. goto err_out_iounmap;
  12169. }
  12170. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  12171. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  12172. if (!tp->aperegs) {
  12173. dev_err(&pdev->dev,
  12174. "Cannot map APE registers, aborting\n");
  12175. err = -ENOMEM;
  12176. goto err_out_iounmap;
  12177. }
  12178. tg3_ape_lock_init(tp);
  12179. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  12180. tg3_read_dash_ver(tp);
  12181. }
  12182. /*
  12183. * Reset chip in case UNDI or EFI driver did not shutdown
  12184. * DMA self test will enable WDMAC and we'll see (spurious)
  12185. * pending DMA on the PCI bus at that point.
  12186. */
  12187. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  12188. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  12189. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  12190. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  12191. }
  12192. err = tg3_test_dma(tp);
  12193. if (err) {
  12194. dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
  12195. goto err_out_apeunmap;
  12196. }
  12197. /* flow control autonegotiation is default behavior */
  12198. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  12199. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  12200. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  12201. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  12202. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  12203. for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
  12204. struct tg3_napi *tnapi = &tp->napi[i];
  12205. tnapi->tp = tp;
  12206. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  12207. tnapi->int_mbox = intmbx;
  12208. if (i < 4)
  12209. intmbx += 0x8;
  12210. else
  12211. intmbx += 0x4;
  12212. tnapi->consmbox = rcvmbx;
  12213. tnapi->prodmbox = sndmbx;
  12214. if (i) {
  12215. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  12216. netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
  12217. } else {
  12218. tnapi->coal_now = HOSTCC_MODE_NOW;
  12219. netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
  12220. }
  12221. if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
  12222. break;
  12223. /*
  12224. * If we support MSIX, we'll be using RSS. If we're using
  12225. * RSS, the first vector only handles link interrupts and the
  12226. * remaining vectors handle rx and tx interrupts. Reuse the
  12227. * mailbox values for the next iteration. The values we setup
  12228. * above are still useful for the single vectored mode.
  12229. */
  12230. if (!i)
  12231. continue;
  12232. rcvmbx += 0x8;
  12233. if (sndmbx & 0x4)
  12234. sndmbx -= 0x4;
  12235. else
  12236. sndmbx += 0xc;
  12237. }
  12238. tg3_init_coal(tp);
  12239. pci_set_drvdata(pdev, dev);
  12240. err = register_netdev(dev);
  12241. if (err) {
  12242. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  12243. goto err_out_apeunmap;
  12244. }
  12245. netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  12246. tp->board_part_number,
  12247. tp->pci_chip_rev_id,
  12248. tg3_bus_string(tp, str),
  12249. dev->dev_addr);
  12250. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  12251. struct phy_device *phydev;
  12252. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  12253. netdev_info(dev,
  12254. "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  12255. phydev->drv->name, dev_name(&phydev->dev));
  12256. } else {
  12257. char *ethtype;
  12258. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  12259. ethtype = "10/100Base-TX";
  12260. else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  12261. ethtype = "1000Base-SX";
  12262. else
  12263. ethtype = "10/100/1000Base-T";
  12264. netdev_info(dev, "attached PHY is %s (%s Ethernet) "
  12265. "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
  12266. (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
  12267. }
  12268. netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  12269. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  12270. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  12271. (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
  12272. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  12273. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  12274. netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  12275. tp->dma_rwctrl,
  12276. pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
  12277. ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
  12278. return 0;
  12279. err_out_apeunmap:
  12280. if (tp->aperegs) {
  12281. iounmap(tp->aperegs);
  12282. tp->aperegs = NULL;
  12283. }
  12284. err_out_iounmap:
  12285. if (tp->regs) {
  12286. iounmap(tp->regs);
  12287. tp->regs = NULL;
  12288. }
  12289. err_out_free_dev:
  12290. free_netdev(dev);
  12291. err_out_free_res:
  12292. pci_release_regions(pdev);
  12293. err_out_disable_pdev:
  12294. pci_disable_device(pdev);
  12295. pci_set_drvdata(pdev, NULL);
  12296. return err;
  12297. }
  12298. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  12299. {
  12300. struct net_device *dev = pci_get_drvdata(pdev);
  12301. if (dev) {
  12302. struct tg3 *tp = netdev_priv(dev);
  12303. if (tp->fw)
  12304. release_firmware(tp->fw);
  12305. flush_scheduled_work();
  12306. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  12307. tg3_phy_fini(tp);
  12308. tg3_mdio_fini(tp);
  12309. }
  12310. unregister_netdev(dev);
  12311. if (tp->aperegs) {
  12312. iounmap(tp->aperegs);
  12313. tp->aperegs = NULL;
  12314. }
  12315. if (tp->regs) {
  12316. iounmap(tp->regs);
  12317. tp->regs = NULL;
  12318. }
  12319. free_netdev(dev);
  12320. pci_release_regions(pdev);
  12321. pci_disable_device(pdev);
  12322. pci_set_drvdata(pdev, NULL);
  12323. }
  12324. }
  12325. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  12326. {
  12327. struct net_device *dev = pci_get_drvdata(pdev);
  12328. struct tg3 *tp = netdev_priv(dev);
  12329. pci_power_t target_state;
  12330. int err;
  12331. /* PCI register 4 needs to be saved whether netif_running() or not.
  12332. * MSI address and data need to be saved if using MSI and
  12333. * netif_running().
  12334. */
  12335. pci_save_state(pdev);
  12336. if (!netif_running(dev))
  12337. return 0;
  12338. flush_scheduled_work();
  12339. tg3_phy_stop(tp);
  12340. tg3_netif_stop(tp);
  12341. del_timer_sync(&tp->timer);
  12342. tg3_full_lock(tp, 1);
  12343. tg3_disable_ints(tp);
  12344. tg3_full_unlock(tp);
  12345. netif_device_detach(dev);
  12346. tg3_full_lock(tp, 0);
  12347. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  12348. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  12349. tg3_full_unlock(tp);
  12350. target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
  12351. err = tg3_set_power_state(tp, target_state);
  12352. if (err) {
  12353. int err2;
  12354. tg3_full_lock(tp, 0);
  12355. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  12356. err2 = tg3_restart_hw(tp, 1);
  12357. if (err2)
  12358. goto out;
  12359. tp->timer.expires = jiffies + tp->timer_offset;
  12360. add_timer(&tp->timer);
  12361. netif_device_attach(dev);
  12362. tg3_netif_start(tp);
  12363. out:
  12364. tg3_full_unlock(tp);
  12365. if (!err2)
  12366. tg3_phy_start(tp);
  12367. }
  12368. return err;
  12369. }
  12370. static int tg3_resume(struct pci_dev *pdev)
  12371. {
  12372. struct net_device *dev = pci_get_drvdata(pdev);
  12373. struct tg3 *tp = netdev_priv(dev);
  12374. int err;
  12375. pci_restore_state(tp->pdev);
  12376. if (!netif_running(dev))
  12377. return 0;
  12378. err = tg3_set_power_state(tp, PCI_D0);
  12379. if (err)
  12380. return err;
  12381. netif_device_attach(dev);
  12382. tg3_full_lock(tp, 0);
  12383. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  12384. err = tg3_restart_hw(tp, 1);
  12385. if (err)
  12386. goto out;
  12387. tp->timer.expires = jiffies + tp->timer_offset;
  12388. add_timer(&tp->timer);
  12389. tg3_netif_start(tp);
  12390. out:
  12391. tg3_full_unlock(tp);
  12392. if (!err)
  12393. tg3_phy_start(tp);
  12394. return err;
  12395. }
  12396. static struct pci_driver tg3_driver = {
  12397. .name = DRV_MODULE_NAME,
  12398. .id_table = tg3_pci_tbl,
  12399. .probe = tg3_init_one,
  12400. .remove = __devexit_p(tg3_remove_one),
  12401. .suspend = tg3_suspend,
  12402. .resume = tg3_resume
  12403. };
  12404. static int __init tg3_init(void)
  12405. {
  12406. return pci_register_driver(&tg3_driver);
  12407. }
  12408. static void __exit tg3_cleanup(void)
  12409. {
  12410. pci_unregister_driver(&tg3_driver);
  12411. }
  12412. module_init(tg3_init);
  12413. module_exit(tg3_cleanup);