smsc911x.c 57 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. *
  30. */
  31. #include <linux/crc32.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/init.h>
  37. #include <linux/ioport.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/sched.h>
  43. #include <linux/timer.h>
  44. #include <linux/bug.h>
  45. #include <linux/bitops.h>
  46. #include <linux/irq.h>
  47. #include <linux/io.h>
  48. #include <linux/swab.h>
  49. #include <linux/phy.h>
  50. #include <linux/smsc911x.h>
  51. #include <linux/device.h>
  52. #include "smsc911x.h"
  53. #define SMSC_CHIPNAME "smsc911x"
  54. #define SMSC_MDIONAME "smsc911x-mdio"
  55. #define SMSC_DRV_VERSION "2008-10-21"
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(SMSC_DRV_VERSION);
  58. #if USE_DEBUG > 0
  59. static int debug = 16;
  60. #else
  61. static int debug = 3;
  62. #endif
  63. module_param(debug, int, 0);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. struct smsc911x_data {
  66. void __iomem *ioaddr;
  67. unsigned int idrev;
  68. /* used to decide which workarounds apply */
  69. unsigned int generation;
  70. /* device configuration (copied from platform_data during probe) */
  71. struct smsc911x_platform_config config;
  72. /* This needs to be acquired before calling any of below:
  73. * smsc911x_mac_read(), smsc911x_mac_write()
  74. */
  75. spinlock_t mac_lock;
  76. /* spinlock to ensure register accesses are serialised */
  77. spinlock_t dev_lock;
  78. struct phy_device *phy_dev;
  79. struct mii_bus *mii_bus;
  80. int phy_irq[PHY_MAX_ADDR];
  81. unsigned int using_extphy;
  82. int last_duplex;
  83. int last_carrier;
  84. u32 msg_enable;
  85. unsigned int gpio_setting;
  86. unsigned int gpio_orig_setting;
  87. struct net_device *dev;
  88. struct napi_struct napi;
  89. unsigned int software_irq_signal;
  90. #ifdef USE_PHY_WORK_AROUND
  91. #define MIN_PACKET_SIZE (64)
  92. char loopback_tx_pkt[MIN_PACKET_SIZE];
  93. char loopback_rx_pkt[MIN_PACKET_SIZE];
  94. unsigned int resetcount;
  95. #endif
  96. /* Members for Multicast filter workaround */
  97. unsigned int multicast_update_pending;
  98. unsigned int set_bits_mask;
  99. unsigned int clear_bits_mask;
  100. unsigned int hashhi;
  101. unsigned int hashlo;
  102. };
  103. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  104. {
  105. if (pdata->config.flags & SMSC911X_USE_32BIT)
  106. return readl(pdata->ioaddr + reg);
  107. if (pdata->config.flags & SMSC911X_USE_16BIT)
  108. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  109. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  110. BUG();
  111. return 0;
  112. }
  113. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  114. {
  115. u32 data;
  116. unsigned long flags;
  117. spin_lock_irqsave(&pdata->dev_lock, flags);
  118. data = __smsc911x_reg_read(pdata, reg);
  119. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  120. return data;
  121. }
  122. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  123. u32 val)
  124. {
  125. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  126. writel(val, pdata->ioaddr + reg);
  127. return;
  128. }
  129. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  130. writew(val & 0xFFFF, pdata->ioaddr + reg);
  131. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  132. return;
  133. }
  134. BUG();
  135. }
  136. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  137. u32 val)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&pdata->dev_lock, flags);
  141. __smsc911x_reg_write(pdata, reg, val);
  142. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  143. }
  144. /* Writes a packet to the TX_DATA_FIFO */
  145. static inline void
  146. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  147. unsigned int wordcount)
  148. {
  149. unsigned long flags;
  150. spin_lock_irqsave(&pdata->dev_lock, flags);
  151. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  152. while (wordcount--)
  153. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  154. swab32(*buf++));
  155. goto out;
  156. }
  157. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  158. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  159. goto out;
  160. }
  161. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  162. while (wordcount--)
  163. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  164. goto out;
  165. }
  166. BUG();
  167. out:
  168. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  169. }
  170. /* Reads a packet out of the RX_DATA_FIFO */
  171. static inline void
  172. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  173. unsigned int wordcount)
  174. {
  175. unsigned long flags;
  176. spin_lock_irqsave(&pdata->dev_lock, flags);
  177. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  178. while (wordcount--)
  179. *buf++ = swab32(__smsc911x_reg_read(pdata,
  180. RX_DATA_FIFO));
  181. goto out;
  182. }
  183. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  184. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  185. goto out;
  186. }
  187. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  188. while (wordcount--)
  189. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  190. goto out;
  191. }
  192. BUG();
  193. out:
  194. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  195. }
  196. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  197. * and smsc911x_mac_write, so assumes mac_lock is held */
  198. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  199. {
  200. int i;
  201. u32 val;
  202. SMSC_ASSERT_MAC_LOCK(pdata);
  203. for (i = 0; i < 40; i++) {
  204. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  205. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  206. return 0;
  207. }
  208. SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
  209. "MAC_CSR_CMD: 0x%08X", val);
  210. return -EIO;
  211. }
  212. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  213. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  214. {
  215. unsigned int temp;
  216. SMSC_ASSERT_MAC_LOCK(pdata);
  217. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  218. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  219. SMSC_WARNING(HW, "MAC busy at entry");
  220. return 0xFFFFFFFF;
  221. }
  222. /* Send the MAC cmd */
  223. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  224. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  225. /* Workaround for hardware read-after-write restriction */
  226. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  227. /* Wait for the read to complete */
  228. if (likely(smsc911x_mac_complete(pdata) == 0))
  229. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  230. SMSC_WARNING(HW, "MAC busy after read");
  231. return 0xFFFFFFFF;
  232. }
  233. /* Set a mac register, mac_lock must be acquired before calling */
  234. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  235. unsigned int offset, u32 val)
  236. {
  237. unsigned int temp;
  238. SMSC_ASSERT_MAC_LOCK(pdata);
  239. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  240. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  241. SMSC_WARNING(HW,
  242. "smsc911x_mac_write failed, MAC busy at entry");
  243. return;
  244. }
  245. /* Send data to write */
  246. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  247. /* Write the actual data */
  248. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  249. MAC_CSR_CMD_CSR_BUSY_));
  250. /* Workaround for hardware read-after-write restriction */
  251. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  252. /* Wait for the write to complete */
  253. if (likely(smsc911x_mac_complete(pdata) == 0))
  254. return;
  255. SMSC_WARNING(HW,
  256. "smsc911x_mac_write failed, MAC busy after write");
  257. }
  258. /* Get a phy register */
  259. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  260. {
  261. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  262. unsigned long flags;
  263. unsigned int addr;
  264. int i, reg;
  265. spin_lock_irqsave(&pdata->mac_lock, flags);
  266. /* Confirm MII not busy */
  267. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  268. SMSC_WARNING(HW,
  269. "MII is busy in smsc911x_mii_read???");
  270. reg = -EIO;
  271. goto out;
  272. }
  273. /* Set the address, index & direction (read from PHY) */
  274. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  275. smsc911x_mac_write(pdata, MII_ACC, addr);
  276. /* Wait for read to complete w/ timeout */
  277. for (i = 0; i < 100; i++)
  278. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  279. reg = smsc911x_mac_read(pdata, MII_DATA);
  280. goto out;
  281. }
  282. SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
  283. reg = -EIO;
  284. out:
  285. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  286. return reg;
  287. }
  288. /* Set a phy register */
  289. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  290. u16 val)
  291. {
  292. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  293. unsigned long flags;
  294. unsigned int addr;
  295. int i, reg;
  296. spin_lock_irqsave(&pdata->mac_lock, flags);
  297. /* Confirm MII not busy */
  298. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  299. SMSC_WARNING(HW,
  300. "MII is busy in smsc911x_mii_write???");
  301. reg = -EIO;
  302. goto out;
  303. }
  304. /* Put the data to write in the MAC */
  305. smsc911x_mac_write(pdata, MII_DATA, val);
  306. /* Set the address, index & direction (write to PHY) */
  307. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  308. MII_ACC_MII_WRITE_;
  309. smsc911x_mac_write(pdata, MII_ACC, addr);
  310. /* Wait for write to complete w/ timeout */
  311. for (i = 0; i < 100; i++)
  312. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  313. reg = 0;
  314. goto out;
  315. }
  316. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  317. reg = -EIO;
  318. out:
  319. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  320. return reg;
  321. }
  322. /* Switch to external phy. Assumes tx and rx are stopped. */
  323. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  324. {
  325. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  326. /* Disable phy clocks to the MAC */
  327. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  328. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  329. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  330. udelay(10); /* Enough time for clocks to stop */
  331. /* Switch to external phy */
  332. hwcfg |= HW_CFG_EXT_PHY_EN_;
  333. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  334. /* Enable phy clocks to the MAC */
  335. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  336. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  337. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  338. udelay(10); /* Enough time for clocks to restart */
  339. hwcfg |= HW_CFG_SMI_SEL_;
  340. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  341. }
  342. /* Autodetects and enables external phy if present on supported chips.
  343. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  344. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  345. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  346. {
  347. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  348. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  349. SMSC_TRACE(HW, "Forcing internal PHY");
  350. pdata->using_extphy = 0;
  351. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  352. SMSC_TRACE(HW, "Forcing external PHY");
  353. smsc911x_phy_enable_external(pdata);
  354. pdata->using_extphy = 1;
  355. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  356. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
  357. smsc911x_phy_enable_external(pdata);
  358. pdata->using_extphy = 1;
  359. } else {
  360. SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
  361. pdata->using_extphy = 0;
  362. }
  363. }
  364. /* Fetches a tx status out of the status fifo */
  365. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  366. {
  367. unsigned int result =
  368. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  369. if (result != 0)
  370. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  371. return result;
  372. }
  373. /* Fetches the next rx status */
  374. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  375. {
  376. unsigned int result =
  377. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  378. if (result != 0)
  379. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  380. return result;
  381. }
  382. #ifdef USE_PHY_WORK_AROUND
  383. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  384. {
  385. unsigned int tries;
  386. u32 wrsz;
  387. u32 rdsz;
  388. ulong bufp;
  389. for (tries = 0; tries < 10; tries++) {
  390. unsigned int txcmd_a;
  391. unsigned int txcmd_b;
  392. unsigned int status;
  393. unsigned int pktlength;
  394. unsigned int i;
  395. /* Zero-out rx packet memory */
  396. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  397. /* Write tx packet to 118 */
  398. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  399. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  400. txcmd_a |= MIN_PACKET_SIZE;
  401. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  402. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  403. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  404. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  405. wrsz = MIN_PACKET_SIZE + 3;
  406. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  407. wrsz >>= 2;
  408. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  409. /* Wait till transmit is done */
  410. i = 60;
  411. do {
  412. udelay(5);
  413. status = smsc911x_tx_get_txstatus(pdata);
  414. } while ((i--) && (!status));
  415. if (!status) {
  416. SMSC_WARNING(HW, "Failed to transmit "
  417. "during loopback test");
  418. continue;
  419. }
  420. if (status & TX_STS_ES_) {
  421. SMSC_WARNING(HW, "Transmit encountered "
  422. "errors during loopback test");
  423. continue;
  424. }
  425. /* Wait till receive is done */
  426. i = 60;
  427. do {
  428. udelay(5);
  429. status = smsc911x_rx_get_rxstatus(pdata);
  430. } while ((i--) && (!status));
  431. if (!status) {
  432. SMSC_WARNING(HW,
  433. "Failed to receive during loopback test");
  434. continue;
  435. }
  436. if (status & RX_STS_ES_) {
  437. SMSC_WARNING(HW, "Receive encountered "
  438. "errors during loopback test");
  439. continue;
  440. }
  441. pktlength = ((status & 0x3FFF0000UL) >> 16);
  442. bufp = (ulong)pdata->loopback_rx_pkt;
  443. rdsz = pktlength + 3;
  444. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  445. rdsz >>= 2;
  446. smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  447. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  448. SMSC_WARNING(HW, "Unexpected packet size "
  449. "during loop back test, size=%d, will retry",
  450. pktlength);
  451. } else {
  452. unsigned int j;
  453. int mismatch = 0;
  454. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  455. if (pdata->loopback_tx_pkt[j]
  456. != pdata->loopback_rx_pkt[j]) {
  457. mismatch = 1;
  458. break;
  459. }
  460. }
  461. if (!mismatch) {
  462. SMSC_TRACE(HW, "Successfully verified "
  463. "loopback packet");
  464. return 0;
  465. } else {
  466. SMSC_WARNING(HW, "Data mismatch "
  467. "during loop back test, will retry");
  468. }
  469. }
  470. }
  471. return -EIO;
  472. }
  473. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  474. {
  475. struct phy_device *phy_dev = pdata->phy_dev;
  476. unsigned int temp;
  477. unsigned int i = 100000;
  478. BUG_ON(!phy_dev);
  479. BUG_ON(!phy_dev->bus);
  480. SMSC_TRACE(HW, "Performing PHY BCR Reset");
  481. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  482. do {
  483. msleep(1);
  484. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  485. MII_BMCR);
  486. } while ((i--) && (temp & BMCR_RESET));
  487. if (temp & BMCR_RESET) {
  488. SMSC_WARNING(HW, "PHY reset failed to complete.");
  489. return -EIO;
  490. }
  491. /* Extra delay required because the phy may not be completed with
  492. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  493. * enough delay but using 1ms here to be safe */
  494. msleep(1);
  495. return 0;
  496. }
  497. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  498. {
  499. struct smsc911x_data *pdata = netdev_priv(dev);
  500. struct phy_device *phy_dev = pdata->phy_dev;
  501. int result = -EIO;
  502. unsigned int i, val;
  503. unsigned long flags;
  504. /* Initialise tx packet using broadcast destination address */
  505. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  506. /* Use incrementing source address */
  507. for (i = 6; i < 12; i++)
  508. pdata->loopback_tx_pkt[i] = (char)i;
  509. /* Set length type field */
  510. pdata->loopback_tx_pkt[12] = 0x00;
  511. pdata->loopback_tx_pkt[13] = 0x00;
  512. for (i = 14; i < MIN_PACKET_SIZE; i++)
  513. pdata->loopback_tx_pkt[i] = (char)i;
  514. val = smsc911x_reg_read(pdata, HW_CFG);
  515. val &= HW_CFG_TX_FIF_SZ_;
  516. val |= HW_CFG_SF_;
  517. smsc911x_reg_write(pdata, HW_CFG, val);
  518. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  519. smsc911x_reg_write(pdata, RX_CFG,
  520. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  521. for (i = 0; i < 10; i++) {
  522. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  523. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  524. BMCR_LOOPBACK | BMCR_FULLDPLX);
  525. /* Enable MAC tx/rx, FD */
  526. spin_lock_irqsave(&pdata->mac_lock, flags);
  527. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  528. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  529. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  530. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  531. result = 0;
  532. break;
  533. }
  534. pdata->resetcount++;
  535. /* Disable MAC rx */
  536. spin_lock_irqsave(&pdata->mac_lock, flags);
  537. smsc911x_mac_write(pdata, MAC_CR, 0);
  538. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  539. smsc911x_phy_reset(pdata);
  540. }
  541. /* Disable MAC */
  542. spin_lock_irqsave(&pdata->mac_lock, flags);
  543. smsc911x_mac_write(pdata, MAC_CR, 0);
  544. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  545. /* Cancel PHY loopback mode */
  546. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  547. smsc911x_reg_write(pdata, TX_CFG, 0);
  548. smsc911x_reg_write(pdata, RX_CFG, 0);
  549. return result;
  550. }
  551. #endif /* USE_PHY_WORK_AROUND */
  552. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  553. {
  554. struct phy_device *phy_dev = pdata->phy_dev;
  555. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  556. u32 flow;
  557. unsigned long flags;
  558. if (phy_dev->duplex == DUPLEX_FULL) {
  559. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  560. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  561. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  562. if (cap & FLOW_CTRL_RX)
  563. flow = 0xFFFF0002;
  564. else
  565. flow = 0;
  566. if (cap & FLOW_CTRL_TX)
  567. afc |= 0xF;
  568. else
  569. afc &= ~0xF;
  570. SMSC_TRACE(HW, "rx pause %s, tx pause %s",
  571. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  572. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  573. } else {
  574. SMSC_TRACE(HW, "half duplex");
  575. flow = 0;
  576. afc |= 0xF;
  577. }
  578. spin_lock_irqsave(&pdata->mac_lock, flags);
  579. smsc911x_mac_write(pdata, FLOW, flow);
  580. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  581. smsc911x_reg_write(pdata, AFC_CFG, afc);
  582. }
  583. /* Update link mode if anything has changed. Called periodically when the
  584. * PHY is in polling mode, even if nothing has changed. */
  585. static void smsc911x_phy_adjust_link(struct net_device *dev)
  586. {
  587. struct smsc911x_data *pdata = netdev_priv(dev);
  588. struct phy_device *phy_dev = pdata->phy_dev;
  589. unsigned long flags;
  590. int carrier;
  591. if (phy_dev->duplex != pdata->last_duplex) {
  592. unsigned int mac_cr;
  593. SMSC_TRACE(HW, "duplex state has changed");
  594. spin_lock_irqsave(&pdata->mac_lock, flags);
  595. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  596. if (phy_dev->duplex) {
  597. SMSC_TRACE(HW,
  598. "configuring for full duplex mode");
  599. mac_cr |= MAC_CR_FDPX_;
  600. } else {
  601. SMSC_TRACE(HW,
  602. "configuring for half duplex mode");
  603. mac_cr &= ~MAC_CR_FDPX_;
  604. }
  605. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  606. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  607. smsc911x_phy_update_flowcontrol(pdata);
  608. pdata->last_duplex = phy_dev->duplex;
  609. }
  610. carrier = netif_carrier_ok(dev);
  611. if (carrier != pdata->last_carrier) {
  612. SMSC_TRACE(HW, "carrier state has changed");
  613. if (carrier) {
  614. SMSC_TRACE(HW, "configuring for carrier OK");
  615. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  616. (!pdata->using_extphy)) {
  617. /* Restore original GPIO configuration */
  618. pdata->gpio_setting = pdata->gpio_orig_setting;
  619. smsc911x_reg_write(pdata, GPIO_CFG,
  620. pdata->gpio_setting);
  621. }
  622. } else {
  623. SMSC_TRACE(HW, "configuring for no carrier");
  624. /* Check global setting that LED1
  625. * usage is 10/100 indicator */
  626. pdata->gpio_setting = smsc911x_reg_read(pdata,
  627. GPIO_CFG);
  628. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  629. (!pdata->using_extphy)) {
  630. /* Force 10/100 LED off, after saving
  631. * original GPIO configuration */
  632. pdata->gpio_orig_setting = pdata->gpio_setting;
  633. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  634. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  635. | GPIO_CFG_GPIODIR0_
  636. | GPIO_CFG_GPIOD0_);
  637. smsc911x_reg_write(pdata, GPIO_CFG,
  638. pdata->gpio_setting);
  639. }
  640. }
  641. pdata->last_carrier = carrier;
  642. }
  643. }
  644. static int smsc911x_mii_probe(struct net_device *dev)
  645. {
  646. struct smsc911x_data *pdata = netdev_priv(dev);
  647. struct phy_device *phydev = NULL;
  648. int ret;
  649. /* find the first phy */
  650. phydev = phy_find_first(pdata->mii_bus);
  651. if (!phydev) {
  652. pr_err("%s: no PHY found\n", dev->name);
  653. return -ENODEV;
  654. }
  655. SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
  656. phy_addr, phydev->addr, phydev->phy_id);
  657. ret = phy_connect_direct(dev, phydev,
  658. &smsc911x_phy_adjust_link, 0,
  659. pdata->config.phy_interface);
  660. if (ret) {
  661. pr_err("%s: Could not attach to PHY\n", dev->name);
  662. return ret;
  663. }
  664. pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  665. dev->name, phydev->drv->name,
  666. dev_name(&phydev->dev), phydev->irq);
  667. /* mask with MAC supported features */
  668. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  669. SUPPORTED_Asym_Pause);
  670. phydev->advertising = phydev->supported;
  671. pdata->phy_dev = phydev;
  672. pdata->last_duplex = -1;
  673. pdata->last_carrier = -1;
  674. #ifdef USE_PHY_WORK_AROUND
  675. if (smsc911x_phy_loopbacktest(dev) < 0) {
  676. SMSC_WARNING(HW, "Failed Loop Back Test");
  677. return -ENODEV;
  678. }
  679. SMSC_TRACE(HW, "Passed Loop Back Test");
  680. #endif /* USE_PHY_WORK_AROUND */
  681. SMSC_TRACE(HW, "phy initialised successfully");
  682. return 0;
  683. }
  684. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  685. struct net_device *dev)
  686. {
  687. struct smsc911x_data *pdata = netdev_priv(dev);
  688. int err = -ENXIO, i;
  689. pdata->mii_bus = mdiobus_alloc();
  690. if (!pdata->mii_bus) {
  691. err = -ENOMEM;
  692. goto err_out_1;
  693. }
  694. pdata->mii_bus->name = SMSC_MDIONAME;
  695. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  696. pdata->mii_bus->priv = pdata;
  697. pdata->mii_bus->read = smsc911x_mii_read;
  698. pdata->mii_bus->write = smsc911x_mii_write;
  699. pdata->mii_bus->irq = pdata->phy_irq;
  700. for (i = 0; i < PHY_MAX_ADDR; ++i)
  701. pdata->mii_bus->irq[i] = PHY_POLL;
  702. pdata->mii_bus->parent = &pdev->dev;
  703. switch (pdata->idrev & 0xFFFF0000) {
  704. case 0x01170000:
  705. case 0x01150000:
  706. case 0x117A0000:
  707. case 0x115A0000:
  708. /* External PHY supported, try to autodetect */
  709. smsc911x_phy_initialise_external(pdata);
  710. break;
  711. default:
  712. SMSC_TRACE(HW, "External PHY is not supported, "
  713. "using internal PHY");
  714. pdata->using_extphy = 0;
  715. break;
  716. }
  717. if (!pdata->using_extphy) {
  718. /* Mask all PHYs except ID 1 (internal) */
  719. pdata->mii_bus->phy_mask = ~(1 << 1);
  720. }
  721. if (mdiobus_register(pdata->mii_bus)) {
  722. SMSC_WARNING(PROBE, "Error registering mii bus");
  723. goto err_out_free_bus_2;
  724. }
  725. if (smsc911x_mii_probe(dev) < 0) {
  726. SMSC_WARNING(PROBE, "Error registering mii bus");
  727. goto err_out_unregister_bus_3;
  728. }
  729. return 0;
  730. err_out_unregister_bus_3:
  731. mdiobus_unregister(pdata->mii_bus);
  732. err_out_free_bus_2:
  733. mdiobus_free(pdata->mii_bus);
  734. err_out_1:
  735. return err;
  736. }
  737. /* Gets the number of tx statuses in the fifo */
  738. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  739. {
  740. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  741. & TX_FIFO_INF_TSUSED_) >> 16;
  742. }
  743. /* Reads tx statuses and increments counters where necessary */
  744. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  745. {
  746. struct smsc911x_data *pdata = netdev_priv(dev);
  747. unsigned int tx_stat;
  748. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  749. if (unlikely(tx_stat & 0x80000000)) {
  750. /* In this driver the packet tag is used as the packet
  751. * length. Since a packet length can never reach the
  752. * size of 0x8000, this bit is reserved. It is worth
  753. * noting that the "reserved bit" in the warning above
  754. * does not reference a hardware defined reserved bit
  755. * but rather a driver defined one.
  756. */
  757. SMSC_WARNING(HW,
  758. "Packet tag reserved bit is high");
  759. } else {
  760. if (unlikely(tx_stat & TX_STS_ES_)) {
  761. dev->stats.tx_errors++;
  762. } else {
  763. dev->stats.tx_packets++;
  764. dev->stats.tx_bytes += (tx_stat >> 16);
  765. }
  766. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  767. dev->stats.collisions += 16;
  768. dev->stats.tx_aborted_errors += 1;
  769. } else {
  770. dev->stats.collisions +=
  771. ((tx_stat >> 3) & 0xF);
  772. }
  773. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  774. dev->stats.tx_carrier_errors += 1;
  775. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  776. dev->stats.collisions++;
  777. dev->stats.tx_aborted_errors++;
  778. }
  779. }
  780. }
  781. }
  782. /* Increments the Rx error counters */
  783. static void
  784. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  785. {
  786. int crc_err = 0;
  787. if (unlikely(rxstat & RX_STS_ES_)) {
  788. dev->stats.rx_errors++;
  789. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  790. dev->stats.rx_crc_errors++;
  791. crc_err = 1;
  792. }
  793. }
  794. if (likely(!crc_err)) {
  795. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  796. (rxstat & RX_STS_LENGTH_ERR_)))
  797. dev->stats.rx_length_errors++;
  798. if (rxstat & RX_STS_MCAST_)
  799. dev->stats.multicast++;
  800. }
  801. }
  802. /* Quickly dumps bad packets */
  803. static void
  804. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  805. {
  806. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  807. if (likely(pktwords >= 4)) {
  808. unsigned int timeout = 500;
  809. unsigned int val;
  810. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  811. do {
  812. udelay(1);
  813. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  814. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  815. if (unlikely(timeout == 0))
  816. SMSC_WARNING(HW, "Timed out waiting for "
  817. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  818. } else {
  819. unsigned int temp;
  820. while (pktwords--)
  821. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  822. }
  823. }
  824. /* NAPI poll function */
  825. static int smsc911x_poll(struct napi_struct *napi, int budget)
  826. {
  827. struct smsc911x_data *pdata =
  828. container_of(napi, struct smsc911x_data, napi);
  829. struct net_device *dev = pdata->dev;
  830. int npackets = 0;
  831. while (npackets < budget) {
  832. unsigned int pktlength;
  833. unsigned int pktwords;
  834. struct sk_buff *skb;
  835. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  836. if (!rxstat) {
  837. unsigned int temp;
  838. /* We processed all packets available. Tell NAPI it can
  839. * stop polling then re-enable rx interrupts */
  840. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  841. napi_complete(napi);
  842. temp = smsc911x_reg_read(pdata, INT_EN);
  843. temp |= INT_EN_RSFL_EN_;
  844. smsc911x_reg_write(pdata, INT_EN, temp);
  845. break;
  846. }
  847. /* Count packet for NAPI scheduling, even if it has an error.
  848. * Error packets still require cycles to discard */
  849. npackets++;
  850. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  851. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  852. smsc911x_rx_counterrors(dev, rxstat);
  853. if (unlikely(rxstat & RX_STS_ES_)) {
  854. SMSC_WARNING(RX_ERR,
  855. "Discarding packet with error bit set");
  856. /* Packet has an error, discard it and continue with
  857. * the next */
  858. smsc911x_rx_fastforward(pdata, pktwords);
  859. dev->stats.rx_dropped++;
  860. continue;
  861. }
  862. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  863. if (unlikely(!skb)) {
  864. SMSC_WARNING(RX_ERR,
  865. "Unable to allocate skb for rx packet");
  866. /* Drop the packet and stop this polling iteration */
  867. smsc911x_rx_fastforward(pdata, pktwords);
  868. dev->stats.rx_dropped++;
  869. break;
  870. }
  871. skb->data = skb->head;
  872. skb_reset_tail_pointer(skb);
  873. /* Align IP on 16B boundary */
  874. skb_reserve(skb, NET_IP_ALIGN);
  875. skb_put(skb, pktlength - 4);
  876. smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
  877. pktwords);
  878. skb->protocol = eth_type_trans(skb, dev);
  879. skb->ip_summed = CHECKSUM_NONE;
  880. netif_receive_skb(skb);
  881. /* Update counters */
  882. dev->stats.rx_packets++;
  883. dev->stats.rx_bytes += (pktlength - 4);
  884. }
  885. /* Return total received packets */
  886. return npackets;
  887. }
  888. /* Returns hash bit number for given MAC address
  889. * Example:
  890. * 01 00 5E 00 00 01 -> returns bit number 31 */
  891. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  892. {
  893. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  894. }
  895. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  896. {
  897. /* Performs the multicast & mac_cr update. This is called when
  898. * safe on the current hardware, and with the mac_lock held */
  899. unsigned int mac_cr;
  900. SMSC_ASSERT_MAC_LOCK(pdata);
  901. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  902. mac_cr |= pdata->set_bits_mask;
  903. mac_cr &= ~(pdata->clear_bits_mask);
  904. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  905. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  906. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  907. SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  908. mac_cr, pdata->hashhi, pdata->hashlo);
  909. }
  910. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  911. {
  912. unsigned int mac_cr;
  913. /* This function is only called for older LAN911x devices
  914. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  915. * be modified during Rx - newer devices immediately update the
  916. * registers.
  917. *
  918. * This is called from interrupt context */
  919. spin_lock(&pdata->mac_lock);
  920. /* Check Rx has stopped */
  921. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  922. SMSC_WARNING(DRV, "Rx not stopped");
  923. /* Perform the update - safe to do now Rx has stopped */
  924. smsc911x_rx_multicast_update(pdata);
  925. /* Re-enable Rx */
  926. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  927. mac_cr |= MAC_CR_RXEN_;
  928. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  929. pdata->multicast_update_pending = 0;
  930. spin_unlock(&pdata->mac_lock);
  931. }
  932. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  933. {
  934. unsigned int timeout;
  935. unsigned int temp;
  936. /* Reset the LAN911x */
  937. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  938. timeout = 10;
  939. do {
  940. udelay(10);
  941. temp = smsc911x_reg_read(pdata, HW_CFG);
  942. } while ((--timeout) && (temp & HW_CFG_SRST_));
  943. if (unlikely(temp & HW_CFG_SRST_)) {
  944. SMSC_WARNING(DRV, "Failed to complete reset");
  945. return -EIO;
  946. }
  947. return 0;
  948. }
  949. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  950. static void
  951. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  952. {
  953. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  954. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  955. (dev_addr[1] << 8) | dev_addr[0];
  956. SMSC_ASSERT_MAC_LOCK(pdata);
  957. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  958. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  959. }
  960. static int smsc911x_open(struct net_device *dev)
  961. {
  962. struct smsc911x_data *pdata = netdev_priv(dev);
  963. unsigned int timeout;
  964. unsigned int temp;
  965. unsigned int intcfg;
  966. /* if the phy is not yet registered, retry later*/
  967. if (!pdata->phy_dev) {
  968. SMSC_WARNING(HW, "phy_dev is NULL");
  969. return -EAGAIN;
  970. }
  971. if (!is_valid_ether_addr(dev->dev_addr)) {
  972. SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
  973. return -EADDRNOTAVAIL;
  974. }
  975. /* Reset the LAN911x */
  976. if (smsc911x_soft_reset(pdata)) {
  977. SMSC_WARNING(HW, "soft reset failed");
  978. return -EIO;
  979. }
  980. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  981. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  982. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  983. timeout = 50;
  984. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  985. --timeout) {
  986. udelay(10);
  987. }
  988. if (unlikely(timeout == 0))
  989. SMSC_WARNING(IFUP,
  990. "Timed out waiting for EEPROM busy bit to clear");
  991. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  992. /* The soft reset above cleared the device's MAC address,
  993. * restore it from local copy (set in probe) */
  994. spin_lock_irq(&pdata->mac_lock);
  995. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  996. spin_unlock_irq(&pdata->mac_lock);
  997. /* Initialise irqs, but leave all sources disabled */
  998. smsc911x_reg_write(pdata, INT_EN, 0);
  999. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1000. /* Set interrupt deassertion to 100uS */
  1001. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1002. if (pdata->config.irq_polarity) {
  1003. SMSC_TRACE(IFUP, "irq polarity: active high");
  1004. intcfg |= INT_CFG_IRQ_POL_;
  1005. } else {
  1006. SMSC_TRACE(IFUP, "irq polarity: active low");
  1007. }
  1008. if (pdata->config.irq_type) {
  1009. SMSC_TRACE(IFUP, "irq type: push-pull");
  1010. intcfg |= INT_CFG_IRQ_TYPE_;
  1011. } else {
  1012. SMSC_TRACE(IFUP, "irq type: open drain");
  1013. }
  1014. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1015. SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
  1016. pdata->software_irq_signal = 0;
  1017. smp_wmb();
  1018. temp = smsc911x_reg_read(pdata, INT_EN);
  1019. temp |= INT_EN_SW_INT_EN_;
  1020. smsc911x_reg_write(pdata, INT_EN, temp);
  1021. timeout = 1000;
  1022. while (timeout--) {
  1023. if (pdata->software_irq_signal)
  1024. break;
  1025. msleep(1);
  1026. }
  1027. if (!pdata->software_irq_signal) {
  1028. dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
  1029. dev->irq);
  1030. return -ENODEV;
  1031. }
  1032. SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
  1033. dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1034. (unsigned long)pdata->ioaddr, dev->irq);
  1035. /* Reset the last known duplex and carrier */
  1036. pdata->last_duplex = -1;
  1037. pdata->last_carrier = -1;
  1038. /* Bring the PHY up */
  1039. phy_start(pdata->phy_dev);
  1040. temp = smsc911x_reg_read(pdata, HW_CFG);
  1041. /* Preserve TX FIFO size and external PHY configuration */
  1042. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1043. temp |= HW_CFG_SF_;
  1044. smsc911x_reg_write(pdata, HW_CFG, temp);
  1045. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1046. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1047. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1048. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1049. /* set RX Data offset to 2 bytes for alignment */
  1050. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1051. /* enable NAPI polling before enabling RX interrupts */
  1052. napi_enable(&pdata->napi);
  1053. temp = smsc911x_reg_read(pdata, INT_EN);
  1054. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1055. smsc911x_reg_write(pdata, INT_EN, temp);
  1056. spin_lock_irq(&pdata->mac_lock);
  1057. temp = smsc911x_mac_read(pdata, MAC_CR);
  1058. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1059. smsc911x_mac_write(pdata, MAC_CR, temp);
  1060. spin_unlock_irq(&pdata->mac_lock);
  1061. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1062. netif_start_queue(dev);
  1063. return 0;
  1064. }
  1065. /* Entry point for stopping the interface */
  1066. static int smsc911x_stop(struct net_device *dev)
  1067. {
  1068. struct smsc911x_data *pdata = netdev_priv(dev);
  1069. unsigned int temp;
  1070. /* Disable all device interrupts */
  1071. temp = smsc911x_reg_read(pdata, INT_CFG);
  1072. temp &= ~INT_CFG_IRQ_EN_;
  1073. smsc911x_reg_write(pdata, INT_CFG, temp);
  1074. /* Stop Tx and Rx polling */
  1075. netif_stop_queue(dev);
  1076. napi_disable(&pdata->napi);
  1077. /* At this point all Rx and Tx activity is stopped */
  1078. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1079. smsc911x_tx_update_txcounters(dev);
  1080. /* Bring the PHY down */
  1081. if (pdata->phy_dev)
  1082. phy_stop(pdata->phy_dev);
  1083. SMSC_TRACE(IFDOWN, "Interface stopped");
  1084. return 0;
  1085. }
  1086. /* Entry point for transmitting a packet */
  1087. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1088. {
  1089. struct smsc911x_data *pdata = netdev_priv(dev);
  1090. unsigned int freespace;
  1091. unsigned int tx_cmd_a;
  1092. unsigned int tx_cmd_b;
  1093. unsigned int temp;
  1094. u32 wrsz;
  1095. ulong bufp;
  1096. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1097. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1098. SMSC_WARNING(TX_ERR,
  1099. "Tx data fifo low, space available: %d", freespace);
  1100. /* Word alignment adjustment */
  1101. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1102. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1103. tx_cmd_a |= (unsigned int)skb->len;
  1104. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1105. tx_cmd_b |= (unsigned int)skb->len;
  1106. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1107. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1108. bufp = (ulong)skb->data & (~0x3);
  1109. wrsz = (u32)skb->len + 3;
  1110. wrsz += (u32)((ulong)skb->data & 0x3);
  1111. wrsz >>= 2;
  1112. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1113. freespace -= (skb->len + 32);
  1114. dev_kfree_skb(skb);
  1115. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1116. smsc911x_tx_update_txcounters(dev);
  1117. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1118. netif_stop_queue(dev);
  1119. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1120. temp &= 0x00FFFFFF;
  1121. temp |= 0x32000000;
  1122. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1123. }
  1124. return NETDEV_TX_OK;
  1125. }
  1126. /* Entry point for getting status counters */
  1127. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1128. {
  1129. struct smsc911x_data *pdata = netdev_priv(dev);
  1130. smsc911x_tx_update_txcounters(dev);
  1131. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1132. return &dev->stats;
  1133. }
  1134. /* Entry point for setting addressing modes */
  1135. static void smsc911x_set_multicast_list(struct net_device *dev)
  1136. {
  1137. struct smsc911x_data *pdata = netdev_priv(dev);
  1138. unsigned long flags;
  1139. if (dev->flags & IFF_PROMISC) {
  1140. /* Enabling promiscuous mode */
  1141. pdata->set_bits_mask = MAC_CR_PRMS_;
  1142. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1143. pdata->hashhi = 0;
  1144. pdata->hashlo = 0;
  1145. } else if (dev->flags & IFF_ALLMULTI) {
  1146. /* Enabling all multicast mode */
  1147. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1148. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1149. pdata->hashhi = 0;
  1150. pdata->hashlo = 0;
  1151. } else if (!netdev_mc_empty(dev)) {
  1152. /* Enabling specific multicast addresses */
  1153. unsigned int hash_high = 0;
  1154. unsigned int hash_low = 0;
  1155. struct netdev_hw_addr *ha;
  1156. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1157. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1158. netdev_for_each_mc_addr(ha, dev) {
  1159. unsigned int bitnum = smsc911x_hash(ha->addr);
  1160. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1161. if (bitnum & 0x20)
  1162. hash_high |= mask;
  1163. else
  1164. hash_low |= mask;
  1165. }
  1166. pdata->hashhi = hash_high;
  1167. pdata->hashlo = hash_low;
  1168. } else {
  1169. /* Enabling local MAC address only */
  1170. pdata->set_bits_mask = 0;
  1171. pdata->clear_bits_mask =
  1172. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1173. pdata->hashhi = 0;
  1174. pdata->hashlo = 0;
  1175. }
  1176. spin_lock_irqsave(&pdata->mac_lock, flags);
  1177. if (pdata->generation <= 1) {
  1178. /* Older hardware revision - cannot change these flags while
  1179. * receiving data */
  1180. if (!pdata->multicast_update_pending) {
  1181. unsigned int temp;
  1182. SMSC_TRACE(HW, "scheduling mcast update");
  1183. pdata->multicast_update_pending = 1;
  1184. /* Request the hardware to stop, then perform the
  1185. * update when we get an RX_STOP interrupt */
  1186. temp = smsc911x_mac_read(pdata, MAC_CR);
  1187. temp &= ~(MAC_CR_RXEN_);
  1188. smsc911x_mac_write(pdata, MAC_CR, temp);
  1189. } else {
  1190. /* There is another update pending, this should now
  1191. * use the newer values */
  1192. }
  1193. } else {
  1194. /* Newer hardware revision - can write immediately */
  1195. smsc911x_rx_multicast_update(pdata);
  1196. }
  1197. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1198. }
  1199. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1200. {
  1201. struct net_device *dev = dev_id;
  1202. struct smsc911x_data *pdata = netdev_priv(dev);
  1203. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1204. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1205. int serviced = IRQ_NONE;
  1206. u32 temp;
  1207. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1208. temp = smsc911x_reg_read(pdata, INT_EN);
  1209. temp &= (~INT_EN_SW_INT_EN_);
  1210. smsc911x_reg_write(pdata, INT_EN, temp);
  1211. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1212. pdata->software_irq_signal = 1;
  1213. smp_wmb();
  1214. serviced = IRQ_HANDLED;
  1215. }
  1216. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1217. /* Called when there is a multicast update scheduled and
  1218. * it is now safe to complete the update */
  1219. SMSC_TRACE(INTR, "RX Stop interrupt");
  1220. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1221. if (pdata->multicast_update_pending)
  1222. smsc911x_rx_multicast_update_workaround(pdata);
  1223. serviced = IRQ_HANDLED;
  1224. }
  1225. if (intsts & inten & INT_STS_TDFA_) {
  1226. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1227. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1228. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1229. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1230. netif_wake_queue(dev);
  1231. serviced = IRQ_HANDLED;
  1232. }
  1233. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1234. SMSC_TRACE(INTR, "RX Error interrupt");
  1235. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1236. serviced = IRQ_HANDLED;
  1237. }
  1238. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1239. if (likely(napi_schedule_prep(&pdata->napi))) {
  1240. /* Disable Rx interrupts */
  1241. temp = smsc911x_reg_read(pdata, INT_EN);
  1242. temp &= (~INT_EN_RSFL_EN_);
  1243. smsc911x_reg_write(pdata, INT_EN, temp);
  1244. /* Schedule a NAPI poll */
  1245. __napi_schedule(&pdata->napi);
  1246. } else {
  1247. SMSC_WARNING(RX_ERR,
  1248. "napi_schedule_prep failed");
  1249. }
  1250. serviced = IRQ_HANDLED;
  1251. }
  1252. return serviced;
  1253. }
  1254. #ifdef CONFIG_NET_POLL_CONTROLLER
  1255. static void smsc911x_poll_controller(struct net_device *dev)
  1256. {
  1257. disable_irq(dev->irq);
  1258. smsc911x_irqhandler(0, dev);
  1259. enable_irq(dev->irq);
  1260. }
  1261. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1262. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1263. {
  1264. struct smsc911x_data *pdata = netdev_priv(dev);
  1265. struct sockaddr *addr = p;
  1266. /* On older hardware revisions we cannot change the mac address
  1267. * registers while receiving data. Newer devices can safely change
  1268. * this at any time. */
  1269. if (pdata->generation <= 1 && netif_running(dev))
  1270. return -EBUSY;
  1271. if (!is_valid_ether_addr(addr->sa_data))
  1272. return -EADDRNOTAVAIL;
  1273. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1274. spin_lock_irq(&pdata->mac_lock);
  1275. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1276. spin_unlock_irq(&pdata->mac_lock);
  1277. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1278. return 0;
  1279. }
  1280. /* Standard ioctls for mii-tool */
  1281. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1282. {
  1283. struct smsc911x_data *pdata = netdev_priv(dev);
  1284. if (!netif_running(dev) || !pdata->phy_dev)
  1285. return -EINVAL;
  1286. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1287. }
  1288. static int
  1289. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1290. {
  1291. struct smsc911x_data *pdata = netdev_priv(dev);
  1292. cmd->maxtxpkt = 1;
  1293. cmd->maxrxpkt = 1;
  1294. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1295. }
  1296. static int
  1297. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1298. {
  1299. struct smsc911x_data *pdata = netdev_priv(dev);
  1300. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1301. }
  1302. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1303. struct ethtool_drvinfo *info)
  1304. {
  1305. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1306. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1307. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1308. sizeof(info->bus_info));
  1309. }
  1310. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1311. {
  1312. struct smsc911x_data *pdata = netdev_priv(dev);
  1313. return phy_start_aneg(pdata->phy_dev);
  1314. }
  1315. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1316. {
  1317. struct smsc911x_data *pdata = netdev_priv(dev);
  1318. return pdata->msg_enable;
  1319. }
  1320. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1321. {
  1322. struct smsc911x_data *pdata = netdev_priv(dev);
  1323. pdata->msg_enable = level;
  1324. }
  1325. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1326. {
  1327. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1328. sizeof(u32);
  1329. }
  1330. static void
  1331. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1332. void *buf)
  1333. {
  1334. struct smsc911x_data *pdata = netdev_priv(dev);
  1335. struct phy_device *phy_dev = pdata->phy_dev;
  1336. unsigned long flags;
  1337. unsigned int i;
  1338. unsigned int j = 0;
  1339. u32 *data = buf;
  1340. regs->version = pdata->idrev;
  1341. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1342. data[j++] = smsc911x_reg_read(pdata, i);
  1343. for (i = MAC_CR; i <= WUCSR; i++) {
  1344. spin_lock_irqsave(&pdata->mac_lock, flags);
  1345. data[j++] = smsc911x_mac_read(pdata, i);
  1346. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1347. }
  1348. for (i = 0; i <= 31; i++)
  1349. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1350. }
  1351. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1352. {
  1353. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1354. temp &= ~GPIO_CFG_EEPR_EN_;
  1355. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1356. msleep(1);
  1357. }
  1358. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1359. {
  1360. int timeout = 100;
  1361. u32 e2cmd;
  1362. SMSC_TRACE(DRV, "op 0x%08x", op);
  1363. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1364. SMSC_WARNING(DRV, "Busy at start");
  1365. return -EBUSY;
  1366. }
  1367. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1368. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1369. do {
  1370. msleep(1);
  1371. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1372. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1373. if (!timeout) {
  1374. SMSC_TRACE(DRV, "TIMED OUT");
  1375. return -EAGAIN;
  1376. }
  1377. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1378. SMSC_TRACE(DRV, "Error occured during eeprom operation");
  1379. return -EINVAL;
  1380. }
  1381. return 0;
  1382. }
  1383. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1384. u8 address, u8 *data)
  1385. {
  1386. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1387. int ret;
  1388. SMSC_TRACE(DRV, "address 0x%x", address);
  1389. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1390. if (!ret)
  1391. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1392. return ret;
  1393. }
  1394. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1395. u8 address, u8 data)
  1396. {
  1397. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1398. u32 temp;
  1399. int ret;
  1400. SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
  1401. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1402. if (!ret) {
  1403. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1404. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1405. /* Workaround for hardware read-after-write restriction */
  1406. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1407. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1408. }
  1409. return ret;
  1410. }
  1411. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1412. {
  1413. return SMSC911X_EEPROM_SIZE;
  1414. }
  1415. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1416. struct ethtool_eeprom *eeprom, u8 *data)
  1417. {
  1418. struct smsc911x_data *pdata = netdev_priv(dev);
  1419. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1420. int len;
  1421. int i;
  1422. smsc911x_eeprom_enable_access(pdata);
  1423. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1424. for (i = 0; i < len; i++) {
  1425. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1426. if (ret < 0) {
  1427. eeprom->len = 0;
  1428. return ret;
  1429. }
  1430. }
  1431. memcpy(data, &eeprom_data[eeprom->offset], len);
  1432. eeprom->len = len;
  1433. return 0;
  1434. }
  1435. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1436. struct ethtool_eeprom *eeprom, u8 *data)
  1437. {
  1438. int ret;
  1439. struct smsc911x_data *pdata = netdev_priv(dev);
  1440. smsc911x_eeprom_enable_access(pdata);
  1441. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1442. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1443. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1444. /* Single byte write, according to man page */
  1445. eeprom->len = 1;
  1446. return ret;
  1447. }
  1448. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1449. .get_settings = smsc911x_ethtool_getsettings,
  1450. .set_settings = smsc911x_ethtool_setsettings,
  1451. .get_link = ethtool_op_get_link,
  1452. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1453. .nway_reset = smsc911x_ethtool_nwayreset,
  1454. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1455. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1456. .get_regs_len = smsc911x_ethtool_getregslen,
  1457. .get_regs = smsc911x_ethtool_getregs,
  1458. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1459. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1460. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1461. };
  1462. static const struct net_device_ops smsc911x_netdev_ops = {
  1463. .ndo_open = smsc911x_open,
  1464. .ndo_stop = smsc911x_stop,
  1465. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1466. .ndo_get_stats = smsc911x_get_stats,
  1467. .ndo_set_multicast_list = smsc911x_set_multicast_list,
  1468. .ndo_do_ioctl = smsc911x_do_ioctl,
  1469. .ndo_change_mtu = eth_change_mtu,
  1470. .ndo_validate_addr = eth_validate_addr,
  1471. .ndo_set_mac_address = smsc911x_set_mac_address,
  1472. #ifdef CONFIG_NET_POLL_CONTROLLER
  1473. .ndo_poll_controller = smsc911x_poll_controller,
  1474. #endif
  1475. };
  1476. /* copies the current mac address from hardware to dev->dev_addr */
  1477. static void __devinit smsc911x_read_mac_address(struct net_device *dev)
  1478. {
  1479. struct smsc911x_data *pdata = netdev_priv(dev);
  1480. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1481. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1482. dev->dev_addr[0] = (u8)(mac_low32);
  1483. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1484. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1485. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1486. dev->dev_addr[4] = (u8)(mac_high16);
  1487. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1488. }
  1489. /* Initializing private device structures, only called from probe */
  1490. static int __devinit smsc911x_init(struct net_device *dev)
  1491. {
  1492. struct smsc911x_data *pdata = netdev_priv(dev);
  1493. unsigned int byte_test;
  1494. SMSC_TRACE(PROBE, "Driver Parameters:");
  1495. SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
  1496. (unsigned long)pdata->ioaddr);
  1497. SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
  1498. SMSC_TRACE(PROBE, "PHY will be autodetected.");
  1499. spin_lock_init(&pdata->dev_lock);
  1500. if (pdata->ioaddr == 0) {
  1501. SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
  1502. return -ENODEV;
  1503. }
  1504. /* Check byte ordering */
  1505. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1506. SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
  1507. if (byte_test == 0x43218765) {
  1508. SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
  1509. "applying WORD_SWAP");
  1510. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1511. /* 1 dummy read of BYTE_TEST is needed after a write to
  1512. * WORD_SWAP before its contents are valid */
  1513. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1514. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1515. }
  1516. if (byte_test != 0x87654321) {
  1517. SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
  1518. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1519. SMSC_WARNING(PROBE,
  1520. "top 16 bits equal to bottom 16 bits");
  1521. SMSC_TRACE(PROBE, "This may mean the chip is set "
  1522. "for 32 bit while the bus is reading 16 bit");
  1523. }
  1524. return -ENODEV;
  1525. }
  1526. /* Default generation to zero (all workarounds apply) */
  1527. pdata->generation = 0;
  1528. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1529. switch (pdata->idrev & 0xFFFF0000) {
  1530. case 0x01180000:
  1531. case 0x01170000:
  1532. case 0x01160000:
  1533. case 0x01150000:
  1534. /* LAN911[5678] family */
  1535. pdata->generation = pdata->idrev & 0x0000FFFF;
  1536. break;
  1537. case 0x118A0000:
  1538. case 0x117A0000:
  1539. case 0x116A0000:
  1540. case 0x115A0000:
  1541. /* LAN921[5678] family */
  1542. pdata->generation = 3;
  1543. break;
  1544. case 0x92100000:
  1545. case 0x92110000:
  1546. case 0x92200000:
  1547. case 0x92210000:
  1548. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1549. pdata->generation = 4;
  1550. break;
  1551. default:
  1552. SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
  1553. pdata->idrev);
  1554. return -ENODEV;
  1555. }
  1556. SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
  1557. pdata->idrev, pdata->generation);
  1558. if (pdata->generation == 0)
  1559. SMSC_WARNING(PROBE,
  1560. "This driver is not intended for this chip revision");
  1561. /* workaround for platforms without an eeprom, where the mac address
  1562. * is stored elsewhere and set by the bootloader. This saves the
  1563. * mac address before resetting the device */
  1564. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
  1565. smsc911x_read_mac_address(dev);
  1566. /* Reset the LAN911x */
  1567. if (smsc911x_soft_reset(pdata))
  1568. return -ENODEV;
  1569. /* Disable all interrupt sources until we bring the device up */
  1570. smsc911x_reg_write(pdata, INT_EN, 0);
  1571. ether_setup(dev);
  1572. dev->flags |= IFF_MULTICAST;
  1573. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1574. dev->netdev_ops = &smsc911x_netdev_ops;
  1575. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1576. return 0;
  1577. }
  1578. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1579. {
  1580. struct net_device *dev;
  1581. struct smsc911x_data *pdata;
  1582. struct resource *res;
  1583. dev = platform_get_drvdata(pdev);
  1584. BUG_ON(!dev);
  1585. pdata = netdev_priv(dev);
  1586. BUG_ON(!pdata);
  1587. BUG_ON(!pdata->ioaddr);
  1588. BUG_ON(!pdata->phy_dev);
  1589. SMSC_TRACE(IFDOWN, "Stopping driver.");
  1590. phy_disconnect(pdata->phy_dev);
  1591. pdata->phy_dev = NULL;
  1592. mdiobus_unregister(pdata->mii_bus);
  1593. mdiobus_free(pdata->mii_bus);
  1594. platform_set_drvdata(pdev, NULL);
  1595. unregister_netdev(dev);
  1596. free_irq(dev->irq, dev);
  1597. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1598. "smsc911x-memory");
  1599. if (!res)
  1600. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1601. release_mem_region(res->start, resource_size(res));
  1602. iounmap(pdata->ioaddr);
  1603. free_netdev(dev);
  1604. return 0;
  1605. }
  1606. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1607. {
  1608. struct net_device *dev;
  1609. struct smsc911x_data *pdata;
  1610. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1611. struct resource *res, *irq_res;
  1612. unsigned int intcfg = 0;
  1613. int res_size, irq_flags;
  1614. int retval;
  1615. pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
  1616. /* platform data specifies irq & dynamic bus configuration */
  1617. if (!pdev->dev.platform_data) {
  1618. pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
  1619. retval = -ENODEV;
  1620. goto out_0;
  1621. }
  1622. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1623. "smsc911x-memory");
  1624. if (!res)
  1625. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1626. if (!res) {
  1627. pr_warning("%s: Could not allocate resource.\n",
  1628. SMSC_CHIPNAME);
  1629. retval = -ENODEV;
  1630. goto out_0;
  1631. }
  1632. res_size = resource_size(res);
  1633. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1634. if (!irq_res) {
  1635. pr_warning("%s: Could not allocate irq resource.\n",
  1636. SMSC_CHIPNAME);
  1637. retval = -ENODEV;
  1638. goto out_0;
  1639. }
  1640. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1641. retval = -EBUSY;
  1642. goto out_0;
  1643. }
  1644. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1645. if (!dev) {
  1646. pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
  1647. retval = -ENOMEM;
  1648. goto out_release_io_1;
  1649. }
  1650. SET_NETDEV_DEV(dev, &pdev->dev);
  1651. pdata = netdev_priv(dev);
  1652. dev->irq = irq_res->start;
  1653. irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
  1654. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1655. /* copy config parameters across to pdata */
  1656. memcpy(&pdata->config, config, sizeof(pdata->config));
  1657. pdata->dev = dev;
  1658. pdata->msg_enable = ((1 << debug) - 1);
  1659. if (pdata->ioaddr == NULL) {
  1660. SMSC_WARNING(PROBE,
  1661. "Error smsc911x base address invalid");
  1662. retval = -ENOMEM;
  1663. goto out_free_netdev_2;
  1664. }
  1665. retval = smsc911x_init(dev);
  1666. if (retval < 0)
  1667. goto out_unmap_io_3;
  1668. /* configure irq polarity and type before connecting isr */
  1669. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1670. intcfg |= INT_CFG_IRQ_POL_;
  1671. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1672. intcfg |= INT_CFG_IRQ_TYPE_;
  1673. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1674. /* Ensure interrupts are globally disabled before connecting ISR */
  1675. smsc911x_reg_write(pdata, INT_EN, 0);
  1676. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1677. retval = request_irq(dev->irq, smsc911x_irqhandler,
  1678. irq_flags | IRQF_SHARED, dev->name, dev);
  1679. if (retval) {
  1680. SMSC_WARNING(PROBE,
  1681. "Unable to claim requested irq: %d", dev->irq);
  1682. goto out_unmap_io_3;
  1683. }
  1684. platform_set_drvdata(pdev, dev);
  1685. retval = register_netdev(dev);
  1686. if (retval) {
  1687. SMSC_WARNING(PROBE,
  1688. "Error %i registering device", retval);
  1689. goto out_unset_drvdata_4;
  1690. } else {
  1691. SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
  1692. }
  1693. spin_lock_init(&pdata->mac_lock);
  1694. retval = smsc911x_mii_init(pdev, dev);
  1695. if (retval) {
  1696. SMSC_WARNING(PROBE,
  1697. "Error %i initialising mii", retval);
  1698. goto out_unregister_netdev_5;
  1699. }
  1700. spin_lock_irq(&pdata->mac_lock);
  1701. /* Check if mac address has been specified when bringing interface up */
  1702. if (is_valid_ether_addr(dev->dev_addr)) {
  1703. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1704. SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
  1705. } else if (is_valid_ether_addr(pdata->config.mac)) {
  1706. memcpy(dev->dev_addr, pdata->config.mac, 6);
  1707. SMSC_TRACE(PROBE, "MAC Address specified by platform data");
  1708. } else {
  1709. /* Try reading mac address from device. if EEPROM is present
  1710. * it will already have been set */
  1711. smsc911x_read_mac_address(dev);
  1712. if (is_valid_ether_addr(dev->dev_addr)) {
  1713. /* eeprom values are valid so use them */
  1714. SMSC_TRACE(PROBE,
  1715. "Mac Address is read from LAN911x EEPROM");
  1716. } else {
  1717. /* eeprom values are invalid, generate random MAC */
  1718. random_ether_addr(dev->dev_addr);
  1719. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1720. SMSC_TRACE(PROBE,
  1721. "MAC Address is set to random_ether_addr");
  1722. }
  1723. }
  1724. spin_unlock_irq(&pdata->mac_lock);
  1725. dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
  1726. return 0;
  1727. out_unregister_netdev_5:
  1728. unregister_netdev(dev);
  1729. out_unset_drvdata_4:
  1730. platform_set_drvdata(pdev, NULL);
  1731. free_irq(dev->irq, dev);
  1732. out_unmap_io_3:
  1733. iounmap(pdata->ioaddr);
  1734. out_free_netdev_2:
  1735. free_netdev(dev);
  1736. out_release_io_1:
  1737. release_mem_region(res->start, resource_size(res));
  1738. out_0:
  1739. return retval;
  1740. }
  1741. #ifdef CONFIG_PM
  1742. /* This implementation assumes the devices remains powered on its VDDVARIO
  1743. * pins during suspend. */
  1744. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  1745. static int smsc911x_suspend(struct device *dev)
  1746. {
  1747. struct net_device *ndev = dev_get_drvdata(dev);
  1748. struct smsc911x_data *pdata = netdev_priv(ndev);
  1749. /* enable wake on LAN, energy detection and the external PME
  1750. * signal. */
  1751. smsc911x_reg_write(pdata, PMT_CTRL,
  1752. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  1753. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  1754. return 0;
  1755. }
  1756. static int smsc911x_resume(struct device *dev)
  1757. {
  1758. struct net_device *ndev = dev_get_drvdata(dev);
  1759. struct smsc911x_data *pdata = netdev_priv(ndev);
  1760. unsigned int to = 100;
  1761. /* Note 3.11 from the datasheet:
  1762. * "When the LAN9220 is in a power saving state, a write of any
  1763. * data to the BYTE_TEST register will wake-up the device."
  1764. */
  1765. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  1766. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  1767. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  1768. * if it failed. */
  1769. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  1770. udelay(1000);
  1771. return (to == 0) ? -EIO : 0;
  1772. }
  1773. static const struct dev_pm_ops smsc911x_pm_ops = {
  1774. .suspend = smsc911x_suspend,
  1775. .resume = smsc911x_resume,
  1776. };
  1777. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  1778. #else
  1779. #define SMSC911X_PM_OPS NULL
  1780. #endif
  1781. static struct platform_driver smsc911x_driver = {
  1782. .probe = smsc911x_drv_probe,
  1783. .remove = __devexit_p(smsc911x_drv_remove),
  1784. .driver = {
  1785. .name = SMSC_CHIPNAME,
  1786. .owner = THIS_MODULE,
  1787. .pm = SMSC911X_PM_OPS,
  1788. },
  1789. };
  1790. /* Entry point for loading the module */
  1791. static int __init smsc911x_init_module(void)
  1792. {
  1793. return platform_driver_register(&smsc911x_driver);
  1794. }
  1795. /* entry point for unloading the module */
  1796. static void __exit smsc911x_cleanup_module(void)
  1797. {
  1798. platform_driver_unregister(&smsc911x_driver);
  1799. }
  1800. module_init(smsc911x_init_module);
  1801. module_exit(smsc911x_cleanup_module);