sky2.c 130 KB

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  1. /*
  2. * New driver for Marvell Yukon 2 chipset.
  3. * Based on earlier sk98lin, and skge driver.
  4. *
  5. * This driver intentionally does not support all the features
  6. * of the original driver such as link fail-over and link management because
  7. * those should be done at higher levels.
  8. *
  9. * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25. #include <linux/crc32.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/pci.h>
  33. #include <linux/ip.h>
  34. #include <linux/slab.h>
  35. #include <net/ip.h>
  36. #include <linux/tcp.h>
  37. #include <linux/in.h>
  38. #include <linux/delay.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/if_vlan.h>
  41. #include <linux/prefetch.h>
  42. #include <linux/debugfs.h>
  43. #include <linux/mii.h>
  44. #include <asm/irq.h>
  45. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  46. #define SKY2_VLAN_TAG_USED 1
  47. #endif
  48. #include "sky2.h"
  49. #define DRV_NAME "sky2"
  50. #define DRV_VERSION "1.28"
  51. /*
  52. * The Yukon II chipset takes 64 bit command blocks (called list elements)
  53. * that are organized into three (receive, transmit, status) different rings
  54. * similar to Tigon3.
  55. */
  56. #define RX_LE_SIZE 1024
  57. #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  58. #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
  59. #define RX_DEF_PENDING RX_MAX_PENDING
  60. /* This is the worst case number of transmit list elements for a single skb:
  61. VLAN:GSO + CKSUM + Data + skb_frags * DMA */
  62. #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
  63. #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
  64. #define TX_MAX_PENDING 1024
  65. #define TX_DEF_PENDING 127
  66. #define TX_WATCHDOG (5 * HZ)
  67. #define NAPI_WEIGHT 64
  68. #define PHY_RETRIES 1000
  69. #define SKY2_EEPROM_MAGIC 0x9955aabb
  70. #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
  71. static const u32 default_msg =
  72. NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  73. | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
  74. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  75. static int debug = -1; /* defaults above */
  76. module_param(debug, int, 0);
  77. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  78. static int copybreak __read_mostly = 128;
  79. module_param(copybreak, int, 0);
  80. MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  81. static int disable_msi = 0;
  82. module_param(disable_msi, int, 0);
  83. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  84. static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
  85. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
  86. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
  87. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
  88. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
  89. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
  90. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
  91. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
  92. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
  93. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
  94. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
  95. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
  96. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
  97. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
  98. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
  99. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
  100. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
  101. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
  102. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
  103. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
  104. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
  105. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
  106. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
  107. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
  108. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
  109. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
  110. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
  111. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
  112. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
  113. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
  114. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
  115. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
  116. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
  117. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
  118. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
  119. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
  120. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
  121. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
  122. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
  123. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
  124. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
  125. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
  126. { 0 }
  127. };
  128. MODULE_DEVICE_TABLE(pci, sky2_id_table);
  129. /* Avoid conditionals by using array */
  130. static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
  131. static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
  132. static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
  133. static void sky2_set_multicast(struct net_device *dev);
  134. /* Access to PHY via serial interconnect */
  135. static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
  136. {
  137. int i;
  138. gma_write16(hw, port, GM_SMI_DATA, val);
  139. gma_write16(hw, port, GM_SMI_CTRL,
  140. GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
  141. for (i = 0; i < PHY_RETRIES; i++) {
  142. u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
  143. if (ctrl == 0xffff)
  144. goto io_error;
  145. if (!(ctrl & GM_SMI_CT_BUSY))
  146. return 0;
  147. udelay(10);
  148. }
  149. dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
  150. return -ETIMEDOUT;
  151. io_error:
  152. dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
  153. return -EIO;
  154. }
  155. static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
  156. {
  157. int i;
  158. gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
  159. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  160. for (i = 0; i < PHY_RETRIES; i++) {
  161. u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
  162. if (ctrl == 0xffff)
  163. goto io_error;
  164. if (ctrl & GM_SMI_CT_RD_VAL) {
  165. *val = gma_read16(hw, port, GM_SMI_DATA);
  166. return 0;
  167. }
  168. udelay(10);
  169. }
  170. dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
  171. return -ETIMEDOUT;
  172. io_error:
  173. dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
  174. return -EIO;
  175. }
  176. static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
  177. {
  178. u16 v;
  179. __gm_phy_read(hw, port, reg, &v);
  180. return v;
  181. }
  182. static void sky2_power_on(struct sky2_hw *hw)
  183. {
  184. /* switch power to VCC (WA for VAUX problem) */
  185. sky2_write8(hw, B0_POWER_CTRL,
  186. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  187. /* disable Core Clock Division, */
  188. sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
  189. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
  190. /* enable bits are inverted */
  191. sky2_write8(hw, B2_Y2_CLK_GATE,
  192. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  193. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  194. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  195. else
  196. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  197. if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
  198. u32 reg;
  199. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  200. reg = sky2_pci_read32(hw, PCI_DEV_REG4);
  201. /* set all bits to 0 except bits 15..12 and 8 */
  202. reg &= P_ASPM_CONTROL_MSK;
  203. sky2_pci_write32(hw, PCI_DEV_REG4, reg);
  204. reg = sky2_pci_read32(hw, PCI_DEV_REG5);
  205. /* set all bits to 0 except bits 28 & 27 */
  206. reg &= P_CTL_TIM_VMAIN_AV_MSK;
  207. sky2_pci_write32(hw, PCI_DEV_REG5, reg);
  208. sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
  209. sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
  210. /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
  211. reg = sky2_read32(hw, B2_GP_IO);
  212. reg |= GLB_GPIO_STAT_RACE_DIS;
  213. sky2_write32(hw, B2_GP_IO, reg);
  214. sky2_read32(hw, B2_GP_IO);
  215. }
  216. /* Turn on "driver loaded" LED */
  217. sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
  218. }
  219. static void sky2_power_aux(struct sky2_hw *hw)
  220. {
  221. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
  222. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  223. else
  224. /* enable bits are inverted */
  225. sky2_write8(hw, B2_Y2_CLK_GATE,
  226. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  227. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  228. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  229. /* switch power to VAUX if supported and PME from D3cold */
  230. if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
  231. pci_pme_capable(hw->pdev, PCI_D3cold))
  232. sky2_write8(hw, B0_POWER_CTRL,
  233. (PC_VAUX_ENA | PC_VCC_ENA |
  234. PC_VAUX_ON | PC_VCC_OFF));
  235. /* turn off "driver loaded LED" */
  236. sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
  237. }
  238. static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
  239. {
  240. u16 reg;
  241. /* disable all GMAC IRQ's */
  242. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  243. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  244. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  245. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  246. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  247. reg = gma_read16(hw, port, GM_RX_CTRL);
  248. reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
  249. gma_write16(hw, port, GM_RX_CTRL, reg);
  250. }
  251. /* flow control to advertise bits */
  252. static const u16 copper_fc_adv[] = {
  253. [FC_NONE] = 0,
  254. [FC_TX] = PHY_M_AN_ASP,
  255. [FC_RX] = PHY_M_AN_PC,
  256. [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
  257. };
  258. /* flow control to advertise bits when using 1000BaseX */
  259. static const u16 fiber_fc_adv[] = {
  260. [FC_NONE] = PHY_M_P_NO_PAUSE_X,
  261. [FC_TX] = PHY_M_P_ASYM_MD_X,
  262. [FC_RX] = PHY_M_P_SYM_MD_X,
  263. [FC_BOTH] = PHY_M_P_BOTH_MD_X,
  264. };
  265. /* flow control to GMA disable bits */
  266. static const u16 gm_fc_disable[] = {
  267. [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
  268. [FC_TX] = GM_GPCR_FC_RX_DIS,
  269. [FC_RX] = GM_GPCR_FC_TX_DIS,
  270. [FC_BOTH] = 0,
  271. };
  272. static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
  273. {
  274. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  275. u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
  276. if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
  277. !(hw->flags & SKY2_HW_NEWER_PHY)) {
  278. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  279. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  280. PHY_M_EC_MAC_S_MSK);
  281. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  282. /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
  283. if (hw->chip_id == CHIP_ID_YUKON_EC)
  284. /* set downshift counter to 3x and enable downshift */
  285. ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
  286. else
  287. /* set master & slave downshift counter to 1x */
  288. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  289. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  290. }
  291. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  292. if (sky2_is_copper(hw)) {
  293. if (!(hw->flags & SKY2_HW_GIGABIT)) {
  294. /* enable automatic crossover */
  295. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
  296. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  297. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  298. u16 spec;
  299. /* Enable Class A driver for FE+ A0 */
  300. spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
  301. spec |= PHY_M_FESC_SEL_CL_A;
  302. gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
  303. }
  304. } else {
  305. /* disable energy detect */
  306. ctrl &= ~PHY_M_PC_EN_DET_MSK;
  307. /* enable automatic crossover */
  308. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
  309. /* downshift on PHY 88E1112 and 88E1149 is changed */
  310. if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
  311. (hw->flags & SKY2_HW_NEWER_PHY)) {
  312. /* set downshift counter to 3x and enable downshift */
  313. ctrl &= ~PHY_M_PC_DSC_MSK;
  314. ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
  315. }
  316. }
  317. } else {
  318. /* workaround for deviation #4.88 (CRC errors) */
  319. /* disable Automatic Crossover */
  320. ctrl &= ~PHY_M_PC_MDIX_MSK;
  321. }
  322. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  323. /* special setup for PHY 88E1112 Fiber */
  324. if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
  325. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  326. /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
  327. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  328. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  329. ctrl &= ~PHY_M_MAC_MD_MSK;
  330. ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
  331. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  332. if (hw->pmd_type == 'P') {
  333. /* select page 1 to access Fiber registers */
  334. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
  335. /* for SFP-module set SIGDET polarity to low */
  336. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  337. ctrl |= PHY_M_FIB_SIGD_POL;
  338. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  339. }
  340. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  341. }
  342. ctrl = PHY_CT_RESET;
  343. ct1000 = 0;
  344. adv = PHY_AN_CSMA;
  345. reg = 0;
  346. if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
  347. if (sky2_is_copper(hw)) {
  348. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  349. ct1000 |= PHY_M_1000C_AFD;
  350. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  351. ct1000 |= PHY_M_1000C_AHD;
  352. if (sky2->advertising & ADVERTISED_100baseT_Full)
  353. adv |= PHY_M_AN_100_FD;
  354. if (sky2->advertising & ADVERTISED_100baseT_Half)
  355. adv |= PHY_M_AN_100_HD;
  356. if (sky2->advertising & ADVERTISED_10baseT_Full)
  357. adv |= PHY_M_AN_10_FD;
  358. if (sky2->advertising & ADVERTISED_10baseT_Half)
  359. adv |= PHY_M_AN_10_HD;
  360. } else { /* special defines for FIBER (88E1040S only) */
  361. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  362. adv |= PHY_M_AN_1000X_AFD;
  363. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  364. adv |= PHY_M_AN_1000X_AHD;
  365. }
  366. /* Restart Auto-negotiation */
  367. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  368. } else {
  369. /* forced speed/duplex settings */
  370. ct1000 = PHY_M_1000C_MSE;
  371. /* Disable auto update for duplex flow control and duplex */
  372. reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
  373. switch (sky2->speed) {
  374. case SPEED_1000:
  375. ctrl |= PHY_CT_SP1000;
  376. reg |= GM_GPCR_SPEED_1000;
  377. break;
  378. case SPEED_100:
  379. ctrl |= PHY_CT_SP100;
  380. reg |= GM_GPCR_SPEED_100;
  381. break;
  382. }
  383. if (sky2->duplex == DUPLEX_FULL) {
  384. reg |= GM_GPCR_DUP_FULL;
  385. ctrl |= PHY_CT_DUP_MD;
  386. } else if (sky2->speed < SPEED_1000)
  387. sky2->flow_mode = FC_NONE;
  388. }
  389. if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
  390. if (sky2_is_copper(hw))
  391. adv |= copper_fc_adv[sky2->flow_mode];
  392. else
  393. adv |= fiber_fc_adv[sky2->flow_mode];
  394. } else {
  395. reg |= GM_GPCR_AU_FCT_DIS;
  396. reg |= gm_fc_disable[sky2->flow_mode];
  397. /* Forward pause packets to GMAC? */
  398. if (sky2->flow_mode & FC_RX)
  399. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  400. else
  401. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  402. }
  403. gma_write16(hw, port, GM_GP_CTRL, reg);
  404. if (hw->flags & SKY2_HW_GIGABIT)
  405. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  406. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  407. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  408. /* Setup Phy LED's */
  409. ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
  410. ledover = 0;
  411. switch (hw->chip_id) {
  412. case CHIP_ID_YUKON_FE:
  413. /* on 88E3082 these bits are at 11..9 (shifted left) */
  414. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
  415. ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
  416. /* delete ACT LED control bits */
  417. ctrl &= ~PHY_M_FELP_LED1_MSK;
  418. /* change ACT LED control to blink mode */
  419. ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
  420. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  421. break;
  422. case CHIP_ID_YUKON_FE_P:
  423. /* Enable Link Partner Next Page */
  424. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  425. ctrl |= PHY_M_PC_ENA_LIP_NP;
  426. /* disable Energy Detect and enable scrambler */
  427. ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
  428. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  429. /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
  430. ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
  431. PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
  432. PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
  433. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  434. break;
  435. case CHIP_ID_YUKON_XL:
  436. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  437. /* select page 3 to access LED control register */
  438. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  439. /* set LED Function Control register */
  440. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  441. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  442. PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
  443. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  444. PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
  445. /* set Polarity Control register */
  446. gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
  447. (PHY_M_POLC_LS1_P_MIX(4) |
  448. PHY_M_POLC_IS0_P_MIX(4) |
  449. PHY_M_POLC_LOS_CTRL(2) |
  450. PHY_M_POLC_INIT_CTRL(2) |
  451. PHY_M_POLC_STA1_CTRL(2) |
  452. PHY_M_POLC_STA0_CTRL(2)));
  453. /* restore page register */
  454. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  455. break;
  456. case CHIP_ID_YUKON_EC_U:
  457. case CHIP_ID_YUKON_EX:
  458. case CHIP_ID_YUKON_SUPR:
  459. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  460. /* select page 3 to access LED control register */
  461. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  462. /* set LED Function Control register */
  463. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  464. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  465. PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
  466. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  467. PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
  468. /* set Blink Rate in LED Timer Control Register */
  469. gm_phy_write(hw, port, PHY_MARV_INT_MASK,
  470. ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
  471. /* restore page register */
  472. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  473. break;
  474. default:
  475. /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
  476. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
  477. /* turn off the Rx LED (LED_RX) */
  478. ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
  479. }
  480. if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
  481. /* apply fixes in PHY AFE */
  482. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
  483. /* increase differential signal amplitude in 10BASE-T */
  484. gm_phy_write(hw, port, 0x18, 0xaa99);
  485. gm_phy_write(hw, port, 0x17, 0x2011);
  486. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  487. /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
  488. gm_phy_write(hw, port, 0x18, 0xa204);
  489. gm_phy_write(hw, port, 0x17, 0x2002);
  490. }
  491. /* set page register to 0 */
  492. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  493. } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  494. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  495. /* apply workaround for integrated resistors calibration */
  496. gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
  497. gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
  498. } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
  499. /* apply fixes in PHY AFE */
  500. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
  501. /* apply RDAC termination workaround */
  502. gm_phy_write(hw, port, 24, 0x2800);
  503. gm_phy_write(hw, port, 23, 0x2001);
  504. /* set page register back to 0 */
  505. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  506. } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
  507. hw->chip_id < CHIP_ID_YUKON_SUPR) {
  508. /* no effect on Yukon-XL */
  509. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  510. if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
  511. sky2->speed == SPEED_100) {
  512. /* turn on 100 Mbps LED (LED_LINK100) */
  513. ledover |= PHY_M_LED_MO_100(MO_LED_ON);
  514. }
  515. if (ledover)
  516. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  517. }
  518. /* Enable phy interrupt on auto-negotiation complete (or link up) */
  519. if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
  520. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
  521. else
  522. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  523. }
  524. static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
  525. static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
  526. static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
  527. {
  528. u32 reg1;
  529. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  530. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  531. reg1 &= ~phy_power[port];
  532. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
  533. reg1 |= coma_mode[port];
  534. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  535. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  536. sky2_pci_read32(hw, PCI_DEV_REG1);
  537. if (hw->chip_id == CHIP_ID_YUKON_FE)
  538. gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
  539. else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
  540. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  541. }
  542. static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
  543. {
  544. u32 reg1;
  545. u16 ctrl;
  546. /* release GPHY Control reset */
  547. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  548. /* release GMAC reset */
  549. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  550. if (hw->flags & SKY2_HW_NEWER_PHY) {
  551. /* select page 2 to access MAC control register */
  552. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  553. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  554. /* allow GMII Power Down */
  555. ctrl &= ~PHY_M_MAC_GMIF_PUP;
  556. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  557. /* set page register back to 0 */
  558. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  559. }
  560. /* setup General Purpose Control Register */
  561. gma_write16(hw, port, GM_GP_CTRL,
  562. GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
  563. GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
  564. GM_GPCR_AU_SPD_DIS);
  565. if (hw->chip_id != CHIP_ID_YUKON_EC) {
  566. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  567. /* select page 2 to access MAC control register */
  568. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  569. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  570. /* enable Power Down */
  571. ctrl |= PHY_M_PC_POW_D_ENA;
  572. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  573. /* set page register back to 0 */
  574. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  575. }
  576. /* set IEEE compatible Power Down Mode (dev. #4.99) */
  577. gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
  578. }
  579. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  580. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  581. reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
  582. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  583. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  584. }
  585. /* Enable Rx/Tx */
  586. static void sky2_enable_rx_tx(struct sky2_port *sky2)
  587. {
  588. struct sky2_hw *hw = sky2->hw;
  589. unsigned port = sky2->port;
  590. u16 reg;
  591. reg = gma_read16(hw, port, GM_GP_CTRL);
  592. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  593. gma_write16(hw, port, GM_GP_CTRL, reg);
  594. }
  595. /* Force a renegotiation */
  596. static void sky2_phy_reinit(struct sky2_port *sky2)
  597. {
  598. spin_lock_bh(&sky2->phy_lock);
  599. sky2_phy_init(sky2->hw, sky2->port);
  600. sky2_enable_rx_tx(sky2);
  601. spin_unlock_bh(&sky2->phy_lock);
  602. }
  603. /* Put device in state to listen for Wake On Lan */
  604. static void sky2_wol_init(struct sky2_port *sky2)
  605. {
  606. struct sky2_hw *hw = sky2->hw;
  607. unsigned port = sky2->port;
  608. enum flow_control save_mode;
  609. u16 ctrl;
  610. /* Bring hardware out of reset */
  611. sky2_write16(hw, B0_CTST, CS_RST_CLR);
  612. sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
  613. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  614. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  615. /* Force to 10/100
  616. * sky2_reset will re-enable on resume
  617. */
  618. save_mode = sky2->flow_mode;
  619. ctrl = sky2->advertising;
  620. sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
  621. sky2->flow_mode = FC_NONE;
  622. spin_lock_bh(&sky2->phy_lock);
  623. sky2_phy_power_up(hw, port);
  624. sky2_phy_init(hw, port);
  625. spin_unlock_bh(&sky2->phy_lock);
  626. sky2->flow_mode = save_mode;
  627. sky2->advertising = ctrl;
  628. /* Set GMAC to no flow control and auto update for speed/duplex */
  629. gma_write16(hw, port, GM_GP_CTRL,
  630. GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
  631. GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
  632. /* Set WOL address */
  633. memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
  634. sky2->netdev->dev_addr, ETH_ALEN);
  635. /* Turn on appropriate WOL control bits */
  636. sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
  637. ctrl = 0;
  638. if (sky2->wol & WAKE_PHY)
  639. ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
  640. else
  641. ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
  642. if (sky2->wol & WAKE_MAGIC)
  643. ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
  644. else
  645. ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
  646. ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
  647. sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
  648. /* Disable PiG firmware */
  649. sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
  650. /* block receiver */
  651. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  652. }
  653. static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
  654. {
  655. struct net_device *dev = hw->dev[port];
  656. if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
  657. hw->chip_rev != CHIP_REV_YU_EX_A0) ||
  658. hw->chip_id >= CHIP_ID_YUKON_FE_P) {
  659. /* Yukon-Extreme B0 and further Extreme devices */
  660. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
  661. } else if (dev->mtu > ETH_DATA_LEN) {
  662. /* set Tx GMAC FIFO Almost Empty Threshold */
  663. sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
  664. (ECU_JUMBO_WM << 16) | ECU_AE_THR);
  665. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
  666. } else
  667. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
  668. }
  669. static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
  670. {
  671. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  672. u16 reg;
  673. u32 rx_reg;
  674. int i;
  675. const u8 *addr = hw->dev[port]->dev_addr;
  676. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  677. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  678. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  679. if (hw->chip_id == CHIP_ID_YUKON_XL &&
  680. hw->chip_rev == CHIP_REV_YU_XL_A0 &&
  681. port == 1) {
  682. /* WA DEV_472 -- looks like crossed wires on port 2 */
  683. /* clear GMAC 1 Control reset */
  684. sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
  685. do {
  686. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
  687. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
  688. } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
  689. gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
  690. gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
  691. }
  692. sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  693. /* Enable Transmit FIFO Underrun */
  694. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  695. spin_lock_bh(&sky2->phy_lock);
  696. sky2_phy_power_up(hw, port);
  697. sky2_phy_init(hw, port);
  698. spin_unlock_bh(&sky2->phy_lock);
  699. /* MIB clear */
  700. reg = gma_read16(hw, port, GM_PHY_ADDR);
  701. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  702. for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
  703. gma_read16(hw, port, i);
  704. gma_write16(hw, port, GM_PHY_ADDR, reg);
  705. /* transmit control */
  706. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  707. /* receive control reg: unicast + multicast + no FCS */
  708. gma_write16(hw, port, GM_RX_CTRL,
  709. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  710. /* transmit flow control */
  711. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  712. /* transmit parameter */
  713. gma_write16(hw, port, GM_TX_PARAM,
  714. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  715. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  716. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
  717. TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
  718. /* serial mode register */
  719. reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  720. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  721. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  722. reg |= GM_SMOD_JUMBO_ENA;
  723. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  724. hw->chip_rev == CHIP_REV_YU_EC_U_B1)
  725. reg |= GM_NEW_FLOW_CTRL;
  726. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  727. /* virtual address for data */
  728. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  729. /* physical address: used for pause frames */
  730. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  731. /* ignore counter overflows */
  732. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  733. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  734. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  735. /* Configure Rx MAC FIFO */
  736. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  737. rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  738. if (hw->chip_id == CHIP_ID_YUKON_EX ||
  739. hw->chip_id == CHIP_ID_YUKON_FE_P)
  740. rx_reg |= GMF_RX_OVER_ON;
  741. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
  742. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  743. /* Hardware errata - clear flush mask */
  744. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
  745. } else {
  746. /* Flush Rx MAC FIFO on any flow control or error */
  747. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
  748. }
  749. /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
  750. reg = RX_GMF_FL_THR_DEF + 1;
  751. /* Another magic mystery workaround from sk98lin */
  752. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  753. hw->chip_rev == CHIP_REV_YU_FE2_A0)
  754. reg = 0x178;
  755. sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
  756. /* Configure Tx MAC FIFO */
  757. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  758. sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  759. /* On chips without ram buffer, pause is controled by MAC level */
  760. if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
  761. /* Pause threshold is scaled by 8 in bytes */
  762. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  763. hw->chip_rev == CHIP_REV_YU_FE2_A0)
  764. reg = 1568 / 8;
  765. else
  766. reg = 1024 / 8;
  767. sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
  768. sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
  769. sky2_set_tx_stfwd(hw, port);
  770. }
  771. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  772. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  773. /* disable dynamic watermark */
  774. reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
  775. reg &= ~TX_DYN_WM_ENA;
  776. sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
  777. }
  778. }
  779. /* Assign Ram Buffer allocation to queue */
  780. static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
  781. {
  782. u32 end;
  783. /* convert from K bytes to qwords used for hw register */
  784. start *= 1024/8;
  785. space *= 1024/8;
  786. end = start + space - 1;
  787. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  788. sky2_write32(hw, RB_ADDR(q, RB_START), start);
  789. sky2_write32(hw, RB_ADDR(q, RB_END), end);
  790. sky2_write32(hw, RB_ADDR(q, RB_WP), start);
  791. sky2_write32(hw, RB_ADDR(q, RB_RP), start);
  792. if (q == Q_R1 || q == Q_R2) {
  793. u32 tp = space - space/4;
  794. /* On receive queue's set the thresholds
  795. * give receiver priority when > 3/4 full
  796. * send pause when down to 2K
  797. */
  798. sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
  799. sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
  800. tp = space - 2048/8;
  801. sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
  802. sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
  803. } else {
  804. /* Enable store & forward on Tx queue's because
  805. * Tx FIFO is only 1K on Yukon
  806. */
  807. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  808. }
  809. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  810. sky2_read8(hw, RB_ADDR(q, RB_CTRL));
  811. }
  812. /* Setup Bus Memory Interface */
  813. static void sky2_qset(struct sky2_hw *hw, u16 q)
  814. {
  815. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
  816. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
  817. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
  818. sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
  819. }
  820. /* Setup prefetch unit registers. This is the interface between
  821. * hardware and driver list elements
  822. */
  823. static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
  824. dma_addr_t addr, u32 last)
  825. {
  826. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  827. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
  828. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
  829. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
  830. sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
  831. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
  832. sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
  833. }
  834. static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
  835. {
  836. struct sky2_tx_le *le = sky2->tx_le + *slot;
  837. *slot = RING_NEXT(*slot, sky2->tx_ring_size);
  838. le->ctrl = 0;
  839. return le;
  840. }
  841. static void tx_init(struct sky2_port *sky2)
  842. {
  843. struct sky2_tx_le *le;
  844. sky2->tx_prod = sky2->tx_cons = 0;
  845. sky2->tx_tcpsum = 0;
  846. sky2->tx_last_mss = 0;
  847. le = get_tx_le(sky2, &sky2->tx_prod);
  848. le->addr = 0;
  849. le->opcode = OP_ADDR64 | HW_OWNER;
  850. sky2->tx_last_upper = 0;
  851. }
  852. /* Update chip's next pointer */
  853. static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
  854. {
  855. /* Make sure write' to descriptors are complete before we tell hardware */
  856. wmb();
  857. sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
  858. /* Synchronize I/O on since next processor may write to tail */
  859. mmiowb();
  860. }
  861. static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
  862. {
  863. struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
  864. sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
  865. le->ctrl = 0;
  866. return le;
  867. }
  868. static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
  869. {
  870. unsigned size;
  871. /* Space needed for frame data + headers rounded up */
  872. size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
  873. /* Stopping point for hardware truncation */
  874. return (size - 8) / sizeof(u32);
  875. }
  876. static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
  877. {
  878. struct rx_ring_info *re;
  879. unsigned size;
  880. /* Space needed for frame data + headers rounded up */
  881. size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
  882. sky2->rx_nfrags = size >> PAGE_SHIFT;
  883. BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
  884. /* Compute residue after pages */
  885. size -= sky2->rx_nfrags << PAGE_SHIFT;
  886. /* Optimize to handle small packets and headers */
  887. if (size < copybreak)
  888. size = copybreak;
  889. if (size < ETH_HLEN)
  890. size = ETH_HLEN;
  891. return size;
  892. }
  893. /* Build description to hardware for one receive segment */
  894. static void sky2_rx_add(struct sky2_port *sky2, u8 op,
  895. dma_addr_t map, unsigned len)
  896. {
  897. struct sky2_rx_le *le;
  898. if (sizeof(dma_addr_t) > sizeof(u32)) {
  899. le = sky2_next_rx(sky2);
  900. le->addr = cpu_to_le32(upper_32_bits(map));
  901. le->opcode = OP_ADDR64 | HW_OWNER;
  902. }
  903. le = sky2_next_rx(sky2);
  904. le->addr = cpu_to_le32(lower_32_bits(map));
  905. le->length = cpu_to_le16(len);
  906. le->opcode = op | HW_OWNER;
  907. }
  908. /* Build description to hardware for one possibly fragmented skb */
  909. static void sky2_rx_submit(struct sky2_port *sky2,
  910. const struct rx_ring_info *re)
  911. {
  912. int i;
  913. sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
  914. for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
  915. sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
  916. }
  917. static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
  918. unsigned size)
  919. {
  920. struct sk_buff *skb = re->skb;
  921. int i;
  922. re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
  923. if (pci_dma_mapping_error(pdev, re->data_addr))
  924. goto mapping_error;
  925. dma_unmap_len_set(re, data_size, size);
  926. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  927. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  928. re->frag_addr[i] = pci_map_page(pdev, frag->page,
  929. frag->page_offset,
  930. frag->size,
  931. PCI_DMA_FROMDEVICE);
  932. if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
  933. goto map_page_error;
  934. }
  935. return 0;
  936. map_page_error:
  937. while (--i >= 0) {
  938. pci_unmap_page(pdev, re->frag_addr[i],
  939. skb_shinfo(skb)->frags[i].size,
  940. PCI_DMA_FROMDEVICE);
  941. }
  942. pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
  943. PCI_DMA_FROMDEVICE);
  944. mapping_error:
  945. if (net_ratelimit())
  946. dev_warn(&pdev->dev, "%s: rx mapping error\n",
  947. skb->dev->name);
  948. return -EIO;
  949. }
  950. static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
  951. {
  952. struct sk_buff *skb = re->skb;
  953. int i;
  954. pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
  955. PCI_DMA_FROMDEVICE);
  956. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
  957. pci_unmap_page(pdev, re->frag_addr[i],
  958. skb_shinfo(skb)->frags[i].size,
  959. PCI_DMA_FROMDEVICE);
  960. }
  961. /* Tell chip where to start receive checksum.
  962. * Actually has two checksums, but set both same to avoid possible byte
  963. * order problems.
  964. */
  965. static void rx_set_checksum(struct sky2_port *sky2)
  966. {
  967. struct sky2_rx_le *le = sky2_next_rx(sky2);
  968. le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
  969. le->ctrl = 0;
  970. le->opcode = OP_TCPSTART | HW_OWNER;
  971. sky2_write32(sky2->hw,
  972. Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  973. (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
  974. ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  975. }
  976. /* Enable/disable receive hash calculation (RSS) */
  977. static void rx_set_rss(struct net_device *dev)
  978. {
  979. struct sky2_port *sky2 = netdev_priv(dev);
  980. struct sky2_hw *hw = sky2->hw;
  981. int i, nkeys = 4;
  982. /* Supports IPv6 and other modes */
  983. if (hw->flags & SKY2_HW_NEW_LE) {
  984. nkeys = 10;
  985. sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
  986. }
  987. /* Program RSS initial values */
  988. if (dev->features & NETIF_F_RXHASH) {
  989. u32 key[nkeys];
  990. get_random_bytes(key, nkeys * sizeof(u32));
  991. for (i = 0; i < nkeys; i++)
  992. sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
  993. key[i]);
  994. /* Need to turn on (undocumented) flag to make hashing work */
  995. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
  996. RX_STFW_ENA);
  997. sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  998. BMU_ENA_RX_RSS_HASH);
  999. } else
  1000. sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  1001. BMU_DIS_RX_RSS_HASH);
  1002. }
  1003. /*
  1004. * The RX Stop command will not work for Yukon-2 if the BMU does not
  1005. * reach the end of packet and since we can't make sure that we have
  1006. * incoming data, we must reset the BMU while it is not doing a DMA
  1007. * transfer. Since it is possible that the RX path is still active,
  1008. * the RX RAM buffer will be stopped first, so any possible incoming
  1009. * data will not trigger a DMA. After the RAM buffer is stopped, the
  1010. * BMU is polled until any DMA in progress is ended and only then it
  1011. * will be reset.
  1012. */
  1013. static void sky2_rx_stop(struct sky2_port *sky2)
  1014. {
  1015. struct sky2_hw *hw = sky2->hw;
  1016. unsigned rxq = rxqaddr[sky2->port];
  1017. int i;
  1018. /* disable the RAM Buffer receive queue */
  1019. sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
  1020. for (i = 0; i < 0xffff; i++)
  1021. if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
  1022. == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
  1023. goto stopped;
  1024. netdev_warn(sky2->netdev, "receiver stop failed\n");
  1025. stopped:
  1026. sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
  1027. /* reset the Rx prefetch unit */
  1028. sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  1029. mmiowb();
  1030. }
  1031. /* Clean out receive buffer area, assumes receiver hardware stopped */
  1032. static void sky2_rx_clean(struct sky2_port *sky2)
  1033. {
  1034. unsigned i;
  1035. memset(sky2->rx_le, 0, RX_LE_BYTES);
  1036. for (i = 0; i < sky2->rx_pending; i++) {
  1037. struct rx_ring_info *re = sky2->rx_ring + i;
  1038. if (re->skb) {
  1039. sky2_rx_unmap_skb(sky2->hw->pdev, re);
  1040. kfree_skb(re->skb);
  1041. re->skb = NULL;
  1042. }
  1043. }
  1044. }
  1045. /* Basic MII support */
  1046. static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1047. {
  1048. struct mii_ioctl_data *data = if_mii(ifr);
  1049. struct sky2_port *sky2 = netdev_priv(dev);
  1050. struct sky2_hw *hw = sky2->hw;
  1051. int err = -EOPNOTSUPP;
  1052. if (!netif_running(dev))
  1053. return -ENODEV; /* Phy still in reset */
  1054. switch (cmd) {
  1055. case SIOCGMIIPHY:
  1056. data->phy_id = PHY_ADDR_MARV;
  1057. /* fallthru */
  1058. case SIOCGMIIREG: {
  1059. u16 val = 0;
  1060. spin_lock_bh(&sky2->phy_lock);
  1061. err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
  1062. spin_unlock_bh(&sky2->phy_lock);
  1063. data->val_out = val;
  1064. break;
  1065. }
  1066. case SIOCSMIIREG:
  1067. spin_lock_bh(&sky2->phy_lock);
  1068. err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
  1069. data->val_in);
  1070. spin_unlock_bh(&sky2->phy_lock);
  1071. break;
  1072. }
  1073. return err;
  1074. }
  1075. #ifdef SKY2_VLAN_TAG_USED
  1076. static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
  1077. {
  1078. if (onoff) {
  1079. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
  1080. RX_VLAN_STRIP_ON);
  1081. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  1082. TX_VLAN_TAG_ON);
  1083. } else {
  1084. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
  1085. RX_VLAN_STRIP_OFF);
  1086. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  1087. TX_VLAN_TAG_OFF);
  1088. }
  1089. }
  1090. static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  1091. {
  1092. struct sky2_port *sky2 = netdev_priv(dev);
  1093. struct sky2_hw *hw = sky2->hw;
  1094. u16 port = sky2->port;
  1095. netif_tx_lock_bh(dev);
  1096. napi_disable(&hw->napi);
  1097. sky2->vlgrp = grp;
  1098. sky2_set_vlan_mode(hw, port, grp != NULL);
  1099. sky2_read32(hw, B0_Y2_SP_LISR);
  1100. napi_enable(&hw->napi);
  1101. netif_tx_unlock_bh(dev);
  1102. }
  1103. #endif
  1104. /* Amount of required worst case padding in rx buffer */
  1105. static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
  1106. {
  1107. return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
  1108. }
  1109. /*
  1110. * Allocate an skb for receiving. If the MTU is large enough
  1111. * make the skb non-linear with a fragment list of pages.
  1112. */
  1113. static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
  1114. {
  1115. struct sk_buff *skb;
  1116. int i;
  1117. skb = netdev_alloc_skb(sky2->netdev,
  1118. sky2->rx_data_size + sky2_rx_pad(sky2->hw));
  1119. if (!skb)
  1120. goto nomem;
  1121. if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
  1122. unsigned char *start;
  1123. /*
  1124. * Workaround for a bug in FIFO that cause hang
  1125. * if the FIFO if the receive buffer is not 64 byte aligned.
  1126. * The buffer returned from netdev_alloc_skb is
  1127. * aligned except if slab debugging is enabled.
  1128. */
  1129. start = PTR_ALIGN(skb->data, 8);
  1130. skb_reserve(skb, start - skb->data);
  1131. } else
  1132. skb_reserve(skb, NET_IP_ALIGN);
  1133. for (i = 0; i < sky2->rx_nfrags; i++) {
  1134. struct page *page = alloc_page(GFP_ATOMIC);
  1135. if (!page)
  1136. goto free_partial;
  1137. skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
  1138. }
  1139. return skb;
  1140. free_partial:
  1141. kfree_skb(skb);
  1142. nomem:
  1143. return NULL;
  1144. }
  1145. static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
  1146. {
  1147. sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
  1148. }
  1149. static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
  1150. {
  1151. struct sky2_hw *hw = sky2->hw;
  1152. unsigned i;
  1153. sky2->rx_data_size = sky2_get_rx_data_size(sky2);
  1154. /* Fill Rx ring */
  1155. for (i = 0; i < sky2->rx_pending; i++) {
  1156. struct rx_ring_info *re = sky2->rx_ring + i;
  1157. re->skb = sky2_rx_alloc(sky2);
  1158. if (!re->skb)
  1159. return -ENOMEM;
  1160. if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
  1161. dev_kfree_skb(re->skb);
  1162. re->skb = NULL;
  1163. return -ENOMEM;
  1164. }
  1165. }
  1166. return 0;
  1167. }
  1168. /*
  1169. * Setup receiver buffer pool.
  1170. * Normal case this ends up creating one list element for skb
  1171. * in the receive ring. Worst case if using large MTU and each
  1172. * allocation falls on a different 64 bit region, that results
  1173. * in 6 list elements per ring entry.
  1174. * One element is used for checksum enable/disable, and one
  1175. * extra to avoid wrap.
  1176. */
  1177. static void sky2_rx_start(struct sky2_port *sky2)
  1178. {
  1179. struct sky2_hw *hw = sky2->hw;
  1180. struct rx_ring_info *re;
  1181. unsigned rxq = rxqaddr[sky2->port];
  1182. unsigned i, thresh;
  1183. sky2->rx_put = sky2->rx_next = 0;
  1184. sky2_qset(hw, rxq);
  1185. /* On PCI express lowering the watermark gives better performance */
  1186. if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
  1187. sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
  1188. /* These chips have no ram buffer?
  1189. * MAC Rx RAM Read is controlled by hardware */
  1190. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  1191. hw->chip_rev > CHIP_REV_YU_EC_U_A0)
  1192. sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
  1193. sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
  1194. if (!(hw->flags & SKY2_HW_NEW_LE))
  1195. rx_set_checksum(sky2);
  1196. if (!(hw->flags & SKY2_HW_RSS_BROKEN))
  1197. rx_set_rss(sky2->netdev);
  1198. /* submit Rx ring */
  1199. for (i = 0; i < sky2->rx_pending; i++) {
  1200. re = sky2->rx_ring + i;
  1201. sky2_rx_submit(sky2, re);
  1202. }
  1203. /*
  1204. * The receiver hangs if it receives frames larger than the
  1205. * packet buffer. As a workaround, truncate oversize frames, but
  1206. * the register is limited to 9 bits, so if you do frames > 2052
  1207. * you better get the MTU right!
  1208. */
  1209. thresh = sky2_get_rx_threshold(sky2);
  1210. if (thresh > 0x1ff)
  1211. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
  1212. else {
  1213. sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
  1214. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
  1215. }
  1216. /* Tell chip about available buffers */
  1217. sky2_rx_update(sky2, rxq);
  1218. if (hw->chip_id == CHIP_ID_YUKON_EX ||
  1219. hw->chip_id == CHIP_ID_YUKON_SUPR) {
  1220. /*
  1221. * Disable flushing of non ASF packets;
  1222. * must be done after initializing the BMUs;
  1223. * drivers without ASF support should do this too, otherwise
  1224. * it may happen that they cannot run on ASF devices;
  1225. * remember that the MAC FIFO isn't reset during initialization.
  1226. */
  1227. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
  1228. }
  1229. if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
  1230. /* Enable RX Home Address & Routing Header checksum fix */
  1231. sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
  1232. RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
  1233. /* Enable TX Home Address & Routing Header checksum fix */
  1234. sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
  1235. TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
  1236. }
  1237. }
  1238. static int sky2_alloc_buffers(struct sky2_port *sky2)
  1239. {
  1240. struct sky2_hw *hw = sky2->hw;
  1241. /* must be power of 2 */
  1242. sky2->tx_le = pci_alloc_consistent(hw->pdev,
  1243. sky2->tx_ring_size *
  1244. sizeof(struct sky2_tx_le),
  1245. &sky2->tx_le_map);
  1246. if (!sky2->tx_le)
  1247. goto nomem;
  1248. sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
  1249. GFP_KERNEL);
  1250. if (!sky2->tx_ring)
  1251. goto nomem;
  1252. sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
  1253. &sky2->rx_le_map);
  1254. if (!sky2->rx_le)
  1255. goto nomem;
  1256. memset(sky2->rx_le, 0, RX_LE_BYTES);
  1257. sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
  1258. GFP_KERNEL);
  1259. if (!sky2->rx_ring)
  1260. goto nomem;
  1261. return sky2_alloc_rx_skbs(sky2);
  1262. nomem:
  1263. return -ENOMEM;
  1264. }
  1265. static void sky2_free_buffers(struct sky2_port *sky2)
  1266. {
  1267. struct sky2_hw *hw = sky2->hw;
  1268. sky2_rx_clean(sky2);
  1269. if (sky2->rx_le) {
  1270. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  1271. sky2->rx_le, sky2->rx_le_map);
  1272. sky2->rx_le = NULL;
  1273. }
  1274. if (sky2->tx_le) {
  1275. pci_free_consistent(hw->pdev,
  1276. sky2->tx_ring_size * sizeof(struct sky2_tx_le),
  1277. sky2->tx_le, sky2->tx_le_map);
  1278. sky2->tx_le = NULL;
  1279. }
  1280. kfree(sky2->tx_ring);
  1281. kfree(sky2->rx_ring);
  1282. sky2->tx_ring = NULL;
  1283. sky2->rx_ring = NULL;
  1284. }
  1285. static void sky2_hw_up(struct sky2_port *sky2)
  1286. {
  1287. struct sky2_hw *hw = sky2->hw;
  1288. unsigned port = sky2->port;
  1289. u32 ramsize;
  1290. int cap;
  1291. struct net_device *otherdev = hw->dev[sky2->port^1];
  1292. tx_init(sky2);
  1293. /*
  1294. * On dual port PCI-X card, there is an problem where status
  1295. * can be received out of order due to split transactions
  1296. */
  1297. if (otherdev && netif_running(otherdev) &&
  1298. (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
  1299. u16 cmd;
  1300. cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
  1301. cmd &= ~PCI_X_CMD_MAX_SPLIT;
  1302. sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
  1303. }
  1304. sky2_mac_init(hw, port);
  1305. /* Register is number of 4K blocks on internal RAM buffer. */
  1306. ramsize = sky2_read8(hw, B2_E_0) * 4;
  1307. if (ramsize > 0) {
  1308. u32 rxspace;
  1309. netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
  1310. if (ramsize < 16)
  1311. rxspace = ramsize / 2;
  1312. else
  1313. rxspace = 8 + (2*(ramsize - 16))/3;
  1314. sky2_ramset(hw, rxqaddr[port], 0, rxspace);
  1315. sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
  1316. /* Make sure SyncQ is disabled */
  1317. sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
  1318. RB_RST_SET);
  1319. }
  1320. sky2_qset(hw, txqaddr[port]);
  1321. /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
  1322. if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
  1323. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
  1324. /* Set almost empty threshold */
  1325. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  1326. hw->chip_rev == CHIP_REV_YU_EC_U_A0)
  1327. sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
  1328. sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
  1329. sky2->tx_ring_size - 1);
  1330. #ifdef SKY2_VLAN_TAG_USED
  1331. sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
  1332. #endif
  1333. sky2_rx_start(sky2);
  1334. }
  1335. /* Bring up network interface. */
  1336. static int sky2_up(struct net_device *dev)
  1337. {
  1338. struct sky2_port *sky2 = netdev_priv(dev);
  1339. struct sky2_hw *hw = sky2->hw;
  1340. unsigned port = sky2->port;
  1341. u32 imask;
  1342. int err;
  1343. netif_carrier_off(dev);
  1344. err = sky2_alloc_buffers(sky2);
  1345. if (err)
  1346. goto err_out;
  1347. sky2_hw_up(sky2);
  1348. /* Enable interrupts from phy/mac for port */
  1349. imask = sky2_read32(hw, B0_IMSK);
  1350. imask |= portirq_msk[port];
  1351. sky2_write32(hw, B0_IMSK, imask);
  1352. sky2_read32(hw, B0_IMSK);
  1353. netif_info(sky2, ifup, dev, "enabling interface\n");
  1354. return 0;
  1355. err_out:
  1356. sky2_free_buffers(sky2);
  1357. return err;
  1358. }
  1359. /* Modular subtraction in ring */
  1360. static inline int tx_inuse(const struct sky2_port *sky2)
  1361. {
  1362. return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
  1363. }
  1364. /* Number of list elements available for next tx */
  1365. static inline int tx_avail(const struct sky2_port *sky2)
  1366. {
  1367. return sky2->tx_pending - tx_inuse(sky2);
  1368. }
  1369. /* Estimate of number of transmit list elements required */
  1370. static unsigned tx_le_req(const struct sk_buff *skb)
  1371. {
  1372. unsigned count;
  1373. count = (skb_shinfo(skb)->nr_frags + 1)
  1374. * (sizeof(dma_addr_t) / sizeof(u32));
  1375. if (skb_is_gso(skb))
  1376. ++count;
  1377. else if (sizeof(dma_addr_t) == sizeof(u32))
  1378. ++count; /* possible vlan */
  1379. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1380. ++count;
  1381. return count;
  1382. }
  1383. static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  1384. {
  1385. if (re->flags & TX_MAP_SINGLE)
  1386. pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
  1387. dma_unmap_len(re, maplen),
  1388. PCI_DMA_TODEVICE);
  1389. else if (re->flags & TX_MAP_PAGE)
  1390. pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
  1391. dma_unmap_len(re, maplen),
  1392. PCI_DMA_TODEVICE);
  1393. re->flags = 0;
  1394. }
  1395. /*
  1396. * Put one packet in ring for transmit.
  1397. * A single packet can generate multiple list elements, and
  1398. * the number of ring elements will probably be less than the number
  1399. * of list elements used.
  1400. */
  1401. static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
  1402. struct net_device *dev)
  1403. {
  1404. struct sky2_port *sky2 = netdev_priv(dev);
  1405. struct sky2_hw *hw = sky2->hw;
  1406. struct sky2_tx_le *le = NULL;
  1407. struct tx_ring_info *re;
  1408. unsigned i, len;
  1409. dma_addr_t mapping;
  1410. u32 upper;
  1411. u16 slot;
  1412. u16 mss;
  1413. u8 ctrl;
  1414. if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
  1415. return NETDEV_TX_BUSY;
  1416. len = skb_headlen(skb);
  1417. mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1418. if (pci_dma_mapping_error(hw->pdev, mapping))
  1419. goto mapping_error;
  1420. slot = sky2->tx_prod;
  1421. netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
  1422. "tx queued, slot %u, len %d\n", slot, skb->len);
  1423. /* Send high bits if needed */
  1424. upper = upper_32_bits(mapping);
  1425. if (upper != sky2->tx_last_upper) {
  1426. le = get_tx_le(sky2, &slot);
  1427. le->addr = cpu_to_le32(upper);
  1428. sky2->tx_last_upper = upper;
  1429. le->opcode = OP_ADDR64 | HW_OWNER;
  1430. }
  1431. /* Check for TCP Segmentation Offload */
  1432. mss = skb_shinfo(skb)->gso_size;
  1433. if (mss != 0) {
  1434. if (!(hw->flags & SKY2_HW_NEW_LE))
  1435. mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
  1436. if (mss != sky2->tx_last_mss) {
  1437. le = get_tx_le(sky2, &slot);
  1438. le->addr = cpu_to_le32(mss);
  1439. if (hw->flags & SKY2_HW_NEW_LE)
  1440. le->opcode = OP_MSS | HW_OWNER;
  1441. else
  1442. le->opcode = OP_LRGLEN | HW_OWNER;
  1443. sky2->tx_last_mss = mss;
  1444. }
  1445. }
  1446. ctrl = 0;
  1447. #ifdef SKY2_VLAN_TAG_USED
  1448. /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
  1449. if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
  1450. if (!le) {
  1451. le = get_tx_le(sky2, &slot);
  1452. le->addr = 0;
  1453. le->opcode = OP_VLAN|HW_OWNER;
  1454. } else
  1455. le->opcode |= OP_VLAN;
  1456. le->length = cpu_to_be16(vlan_tx_tag_get(skb));
  1457. ctrl |= INS_VLAN;
  1458. }
  1459. #endif
  1460. /* Handle TCP checksum offload */
  1461. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1462. /* On Yukon EX (some versions) encoding change. */
  1463. if (hw->flags & SKY2_HW_AUTO_TX_SUM)
  1464. ctrl |= CALSUM; /* auto checksum */
  1465. else {
  1466. const unsigned offset = skb_transport_offset(skb);
  1467. u32 tcpsum;
  1468. tcpsum = offset << 16; /* sum start */
  1469. tcpsum |= offset + skb->csum_offset; /* sum write */
  1470. ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
  1471. if (ip_hdr(skb)->protocol == IPPROTO_UDP)
  1472. ctrl |= UDPTCP;
  1473. if (tcpsum != sky2->tx_tcpsum) {
  1474. sky2->tx_tcpsum = tcpsum;
  1475. le = get_tx_le(sky2, &slot);
  1476. le->addr = cpu_to_le32(tcpsum);
  1477. le->length = 0; /* initial checksum value */
  1478. le->ctrl = 1; /* one packet */
  1479. le->opcode = OP_TCPLISW | HW_OWNER;
  1480. }
  1481. }
  1482. }
  1483. re = sky2->tx_ring + slot;
  1484. re->flags = TX_MAP_SINGLE;
  1485. dma_unmap_addr_set(re, mapaddr, mapping);
  1486. dma_unmap_len_set(re, maplen, len);
  1487. le = get_tx_le(sky2, &slot);
  1488. le->addr = cpu_to_le32(lower_32_bits(mapping));
  1489. le->length = cpu_to_le16(len);
  1490. le->ctrl = ctrl;
  1491. le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
  1492. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1493. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1494. mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  1495. frag->size, PCI_DMA_TODEVICE);
  1496. if (pci_dma_mapping_error(hw->pdev, mapping))
  1497. goto mapping_unwind;
  1498. upper = upper_32_bits(mapping);
  1499. if (upper != sky2->tx_last_upper) {
  1500. le = get_tx_le(sky2, &slot);
  1501. le->addr = cpu_to_le32(upper);
  1502. sky2->tx_last_upper = upper;
  1503. le->opcode = OP_ADDR64 | HW_OWNER;
  1504. }
  1505. re = sky2->tx_ring + slot;
  1506. re->flags = TX_MAP_PAGE;
  1507. dma_unmap_addr_set(re, mapaddr, mapping);
  1508. dma_unmap_len_set(re, maplen, frag->size);
  1509. le = get_tx_le(sky2, &slot);
  1510. le->addr = cpu_to_le32(lower_32_bits(mapping));
  1511. le->length = cpu_to_le16(frag->size);
  1512. le->ctrl = ctrl;
  1513. le->opcode = OP_BUFFER | HW_OWNER;
  1514. }
  1515. re->skb = skb;
  1516. le->ctrl |= EOP;
  1517. sky2->tx_prod = slot;
  1518. if (tx_avail(sky2) <= MAX_SKB_TX_LE)
  1519. netif_stop_queue(dev);
  1520. sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
  1521. return NETDEV_TX_OK;
  1522. mapping_unwind:
  1523. for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
  1524. re = sky2->tx_ring + i;
  1525. sky2_tx_unmap(hw->pdev, re);
  1526. }
  1527. mapping_error:
  1528. if (net_ratelimit())
  1529. dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
  1530. dev_kfree_skb(skb);
  1531. return NETDEV_TX_OK;
  1532. }
  1533. /*
  1534. * Free ring elements from starting at tx_cons until "done"
  1535. *
  1536. * NB:
  1537. * 1. The hardware will tell us about partial completion of multi-part
  1538. * buffers so make sure not to free skb to early.
  1539. * 2. This may run in parallel start_xmit because the it only
  1540. * looks at the tail of the queue of FIFO (tx_cons), not
  1541. * the head (tx_prod)
  1542. */
  1543. static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
  1544. {
  1545. struct net_device *dev = sky2->netdev;
  1546. unsigned idx;
  1547. BUG_ON(done >= sky2->tx_ring_size);
  1548. for (idx = sky2->tx_cons; idx != done;
  1549. idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  1550. struct tx_ring_info *re = sky2->tx_ring + idx;
  1551. struct sk_buff *skb = re->skb;
  1552. sky2_tx_unmap(sky2->hw->pdev, re);
  1553. if (skb) {
  1554. netif_printk(sky2, tx_done, KERN_DEBUG, dev,
  1555. "tx done %u\n", idx);
  1556. dev->stats.tx_packets++;
  1557. dev->stats.tx_bytes += skb->len;
  1558. re->skb = NULL;
  1559. dev_kfree_skb_any(skb);
  1560. sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  1561. }
  1562. }
  1563. sky2->tx_cons = idx;
  1564. smp_mb();
  1565. }
  1566. static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
  1567. {
  1568. /* Disable Force Sync bit and Enable Alloc bit */
  1569. sky2_write8(hw, SK_REG(port, TXA_CTRL),
  1570. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1571. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1572. sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1573. sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1574. /* Reset the PCI FIFO of the async Tx queue */
  1575. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
  1576. BMU_RST_SET | BMU_FIFO_RST);
  1577. /* Reset the Tx prefetch units */
  1578. sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
  1579. PREF_UNIT_RST_SET);
  1580. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1581. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1582. }
  1583. static void sky2_hw_down(struct sky2_port *sky2)
  1584. {
  1585. struct sky2_hw *hw = sky2->hw;
  1586. unsigned port = sky2->port;
  1587. u16 ctrl;
  1588. /* Force flow control off */
  1589. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1590. /* Stop transmitter */
  1591. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
  1592. sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
  1593. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1594. RB_RST_SET | RB_DIS_OP_MD);
  1595. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1596. ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
  1597. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1598. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1599. /* Workaround shared GMAC reset */
  1600. if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
  1601. port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
  1602. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1603. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1604. /* Force any delayed status interrrupt and NAPI */
  1605. sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
  1606. sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
  1607. sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
  1608. sky2_read8(hw, STAT_ISR_TIMER_CTRL);
  1609. sky2_rx_stop(sky2);
  1610. spin_lock_bh(&sky2->phy_lock);
  1611. sky2_phy_power_down(hw, port);
  1612. spin_unlock_bh(&sky2->phy_lock);
  1613. sky2_tx_reset(hw, port);
  1614. /* Free any pending frames stuck in HW queue */
  1615. sky2_tx_complete(sky2, sky2->tx_prod);
  1616. }
  1617. /* Network shutdown */
  1618. static int sky2_down(struct net_device *dev)
  1619. {
  1620. struct sky2_port *sky2 = netdev_priv(dev);
  1621. struct sky2_hw *hw = sky2->hw;
  1622. /* Never really got started! */
  1623. if (!sky2->tx_le)
  1624. return 0;
  1625. netif_info(sky2, ifdown, dev, "disabling interface\n");
  1626. /* Disable port IRQ */
  1627. sky2_write32(hw, B0_IMSK,
  1628. sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
  1629. sky2_read32(hw, B0_IMSK);
  1630. synchronize_irq(hw->pdev->irq);
  1631. napi_synchronize(&hw->napi);
  1632. sky2_hw_down(sky2);
  1633. sky2_free_buffers(sky2);
  1634. return 0;
  1635. }
  1636. static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
  1637. {
  1638. if (hw->flags & SKY2_HW_FIBRE_PHY)
  1639. return SPEED_1000;
  1640. if (!(hw->flags & SKY2_HW_GIGABIT)) {
  1641. if (aux & PHY_M_PS_SPEED_100)
  1642. return SPEED_100;
  1643. else
  1644. return SPEED_10;
  1645. }
  1646. switch (aux & PHY_M_PS_SPEED_MSK) {
  1647. case PHY_M_PS_SPEED_1000:
  1648. return SPEED_1000;
  1649. case PHY_M_PS_SPEED_100:
  1650. return SPEED_100;
  1651. default:
  1652. return SPEED_10;
  1653. }
  1654. }
  1655. static void sky2_link_up(struct sky2_port *sky2)
  1656. {
  1657. struct sky2_hw *hw = sky2->hw;
  1658. unsigned port = sky2->port;
  1659. static const char *fc_name[] = {
  1660. [FC_NONE] = "none",
  1661. [FC_TX] = "tx",
  1662. [FC_RX] = "rx",
  1663. [FC_BOTH] = "both",
  1664. };
  1665. sky2_enable_rx_tx(sky2);
  1666. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  1667. netif_carrier_on(sky2->netdev);
  1668. mod_timer(&hw->watchdog_timer, jiffies + 1);
  1669. /* Turn on link LED */
  1670. sky2_write8(hw, SK_REG(port, LNK_LED_REG),
  1671. LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
  1672. netif_info(sky2, link, sky2->netdev,
  1673. "Link is up at %d Mbps, %s duplex, flow control %s\n",
  1674. sky2->speed,
  1675. sky2->duplex == DUPLEX_FULL ? "full" : "half",
  1676. fc_name[sky2->flow_status]);
  1677. }
  1678. static void sky2_link_down(struct sky2_port *sky2)
  1679. {
  1680. struct sky2_hw *hw = sky2->hw;
  1681. unsigned port = sky2->port;
  1682. u16 reg;
  1683. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1684. reg = gma_read16(hw, port, GM_GP_CTRL);
  1685. reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1686. gma_write16(hw, port, GM_GP_CTRL, reg);
  1687. netif_carrier_off(sky2->netdev);
  1688. /* Turn off link LED */
  1689. sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  1690. netif_info(sky2, link, sky2->netdev, "Link is down\n");
  1691. sky2_phy_init(hw, port);
  1692. }
  1693. static enum flow_control sky2_flow(int rx, int tx)
  1694. {
  1695. if (rx)
  1696. return tx ? FC_BOTH : FC_RX;
  1697. else
  1698. return tx ? FC_TX : FC_NONE;
  1699. }
  1700. static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
  1701. {
  1702. struct sky2_hw *hw = sky2->hw;
  1703. unsigned port = sky2->port;
  1704. u16 advert, lpa;
  1705. advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1706. lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
  1707. if (lpa & PHY_M_AN_RF) {
  1708. netdev_err(sky2->netdev, "remote fault\n");
  1709. return -1;
  1710. }
  1711. if (!(aux & PHY_M_PS_SPDUP_RES)) {
  1712. netdev_err(sky2->netdev, "speed/duplex mismatch\n");
  1713. return -1;
  1714. }
  1715. sky2->speed = sky2_phy_speed(hw, aux);
  1716. sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1717. /* Since the pause result bits seem to in different positions on
  1718. * different chips. look at registers.
  1719. */
  1720. if (hw->flags & SKY2_HW_FIBRE_PHY) {
  1721. /* Shift for bits in fiber PHY */
  1722. advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
  1723. lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
  1724. if (advert & ADVERTISE_1000XPAUSE)
  1725. advert |= ADVERTISE_PAUSE_CAP;
  1726. if (advert & ADVERTISE_1000XPSE_ASYM)
  1727. advert |= ADVERTISE_PAUSE_ASYM;
  1728. if (lpa & LPA_1000XPAUSE)
  1729. lpa |= LPA_PAUSE_CAP;
  1730. if (lpa & LPA_1000XPAUSE_ASYM)
  1731. lpa |= LPA_PAUSE_ASYM;
  1732. }
  1733. sky2->flow_status = FC_NONE;
  1734. if (advert & ADVERTISE_PAUSE_CAP) {
  1735. if (lpa & LPA_PAUSE_CAP)
  1736. sky2->flow_status = FC_BOTH;
  1737. else if (advert & ADVERTISE_PAUSE_ASYM)
  1738. sky2->flow_status = FC_RX;
  1739. } else if (advert & ADVERTISE_PAUSE_ASYM) {
  1740. if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
  1741. sky2->flow_status = FC_TX;
  1742. }
  1743. if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
  1744. !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
  1745. sky2->flow_status = FC_NONE;
  1746. if (sky2->flow_status & FC_TX)
  1747. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1748. else
  1749. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1750. return 0;
  1751. }
  1752. /* Interrupt from PHY */
  1753. static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
  1754. {
  1755. struct net_device *dev = hw->dev[port];
  1756. struct sky2_port *sky2 = netdev_priv(dev);
  1757. u16 istatus, phystat;
  1758. if (!netif_running(dev))
  1759. return;
  1760. spin_lock(&sky2->phy_lock);
  1761. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1762. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1763. netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
  1764. istatus, phystat);
  1765. if (istatus & PHY_M_IS_AN_COMPL) {
  1766. if (sky2_autoneg_done(sky2, phystat) == 0 &&
  1767. !netif_carrier_ok(dev))
  1768. sky2_link_up(sky2);
  1769. goto out;
  1770. }
  1771. if (istatus & PHY_M_IS_LSP_CHANGE)
  1772. sky2->speed = sky2_phy_speed(hw, phystat);
  1773. if (istatus & PHY_M_IS_DUP_CHANGE)
  1774. sky2->duplex =
  1775. (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1776. if (istatus & PHY_M_IS_LST_CHANGE) {
  1777. if (phystat & PHY_M_PS_LINK_UP)
  1778. sky2_link_up(sky2);
  1779. else
  1780. sky2_link_down(sky2);
  1781. }
  1782. out:
  1783. spin_unlock(&sky2->phy_lock);
  1784. }
  1785. /* Special quick link interrupt (Yukon-2 Optima only) */
  1786. static void sky2_qlink_intr(struct sky2_hw *hw)
  1787. {
  1788. struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
  1789. u32 imask;
  1790. u16 phy;
  1791. /* disable irq */
  1792. imask = sky2_read32(hw, B0_IMSK);
  1793. imask &= ~Y2_IS_PHY_QLNK;
  1794. sky2_write32(hw, B0_IMSK, imask);
  1795. /* reset PHY Link Detect */
  1796. phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
  1797. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1798. sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
  1799. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1800. sky2_link_up(sky2);
  1801. }
  1802. /* Transmit timeout is only called if we are running, carrier is up
  1803. * and tx queue is full (stopped).
  1804. */
  1805. static void sky2_tx_timeout(struct net_device *dev)
  1806. {
  1807. struct sky2_port *sky2 = netdev_priv(dev);
  1808. struct sky2_hw *hw = sky2->hw;
  1809. netif_err(sky2, timer, dev, "tx timeout\n");
  1810. netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
  1811. sky2->tx_cons, sky2->tx_prod,
  1812. sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
  1813. sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
  1814. /* can't restart safely under softirq */
  1815. schedule_work(&hw->restart_work);
  1816. }
  1817. static int sky2_change_mtu(struct net_device *dev, int new_mtu)
  1818. {
  1819. struct sky2_port *sky2 = netdev_priv(dev);
  1820. struct sky2_hw *hw = sky2->hw;
  1821. unsigned port = sky2->port;
  1822. int err;
  1823. u16 ctl, mode;
  1824. u32 imask;
  1825. /* MTU size outside the spec */
  1826. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  1827. return -EINVAL;
  1828. /* MTU > 1500 on yukon FE and FE+ not allowed */
  1829. if (new_mtu > ETH_DATA_LEN &&
  1830. (hw->chip_id == CHIP_ID_YUKON_FE ||
  1831. hw->chip_id == CHIP_ID_YUKON_FE_P))
  1832. return -EINVAL;
  1833. /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
  1834. if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
  1835. dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
  1836. if (!netif_running(dev)) {
  1837. dev->mtu = new_mtu;
  1838. return 0;
  1839. }
  1840. imask = sky2_read32(hw, B0_IMSK);
  1841. sky2_write32(hw, B0_IMSK, 0);
  1842. dev->trans_start = jiffies; /* prevent tx timeout */
  1843. napi_disable(&hw->napi);
  1844. netif_tx_disable(dev);
  1845. synchronize_irq(hw->pdev->irq);
  1846. if (!(hw->flags & SKY2_HW_RAM_BUFFER))
  1847. sky2_set_tx_stfwd(hw, port);
  1848. ctl = gma_read16(hw, port, GM_GP_CTRL);
  1849. gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
  1850. sky2_rx_stop(sky2);
  1851. sky2_rx_clean(sky2);
  1852. dev->mtu = new_mtu;
  1853. mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  1854. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1855. if (dev->mtu > ETH_DATA_LEN)
  1856. mode |= GM_SMOD_JUMBO_ENA;
  1857. gma_write16(hw, port, GM_SERIAL_MODE, mode);
  1858. sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
  1859. err = sky2_alloc_rx_skbs(sky2);
  1860. if (!err)
  1861. sky2_rx_start(sky2);
  1862. else
  1863. sky2_rx_clean(sky2);
  1864. sky2_write32(hw, B0_IMSK, imask);
  1865. sky2_read32(hw, B0_Y2_SP_LISR);
  1866. napi_enable(&hw->napi);
  1867. if (err)
  1868. dev_close(dev);
  1869. else {
  1870. gma_write16(hw, port, GM_GP_CTRL, ctl);
  1871. netif_wake_queue(dev);
  1872. }
  1873. return err;
  1874. }
  1875. /* For small just reuse existing skb for next receive */
  1876. static struct sk_buff *receive_copy(struct sky2_port *sky2,
  1877. const struct rx_ring_info *re,
  1878. unsigned length)
  1879. {
  1880. struct sk_buff *skb;
  1881. skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
  1882. if (likely(skb)) {
  1883. pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
  1884. length, PCI_DMA_FROMDEVICE);
  1885. skb_copy_from_linear_data(re->skb, skb->data, length);
  1886. skb->ip_summed = re->skb->ip_summed;
  1887. skb->csum = re->skb->csum;
  1888. pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
  1889. length, PCI_DMA_FROMDEVICE);
  1890. re->skb->ip_summed = CHECKSUM_NONE;
  1891. skb_put(skb, length);
  1892. }
  1893. return skb;
  1894. }
  1895. /* Adjust length of skb with fragments to match received data */
  1896. static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
  1897. unsigned int length)
  1898. {
  1899. int i, num_frags;
  1900. unsigned int size;
  1901. /* put header into skb */
  1902. size = min(length, hdr_space);
  1903. skb->tail += size;
  1904. skb->len += size;
  1905. length -= size;
  1906. num_frags = skb_shinfo(skb)->nr_frags;
  1907. for (i = 0; i < num_frags; i++) {
  1908. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1909. if (length == 0) {
  1910. /* don't need this page */
  1911. __free_page(frag->page);
  1912. --skb_shinfo(skb)->nr_frags;
  1913. } else {
  1914. size = min(length, (unsigned) PAGE_SIZE);
  1915. frag->size = size;
  1916. skb->data_len += size;
  1917. skb->truesize += size;
  1918. skb->len += size;
  1919. length -= size;
  1920. }
  1921. }
  1922. }
  1923. /* Normal packet - take skb from ring element and put in a new one */
  1924. static struct sk_buff *receive_new(struct sky2_port *sky2,
  1925. struct rx_ring_info *re,
  1926. unsigned int length)
  1927. {
  1928. struct sk_buff *skb;
  1929. struct rx_ring_info nre;
  1930. unsigned hdr_space = sky2->rx_data_size;
  1931. nre.skb = sky2_rx_alloc(sky2);
  1932. if (unlikely(!nre.skb))
  1933. goto nobuf;
  1934. if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
  1935. goto nomap;
  1936. skb = re->skb;
  1937. sky2_rx_unmap_skb(sky2->hw->pdev, re);
  1938. prefetch(skb->data);
  1939. *re = nre;
  1940. if (skb_shinfo(skb)->nr_frags)
  1941. skb_put_frags(skb, hdr_space, length);
  1942. else
  1943. skb_put(skb, length);
  1944. return skb;
  1945. nomap:
  1946. dev_kfree_skb(nre.skb);
  1947. nobuf:
  1948. return NULL;
  1949. }
  1950. /*
  1951. * Receive one packet.
  1952. * For larger packets, get new buffer.
  1953. */
  1954. static struct sk_buff *sky2_receive(struct net_device *dev,
  1955. u16 length, u32 status)
  1956. {
  1957. struct sky2_port *sky2 = netdev_priv(dev);
  1958. struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
  1959. struct sk_buff *skb = NULL;
  1960. u16 count = (status & GMR_FS_LEN) >> 16;
  1961. #ifdef SKY2_VLAN_TAG_USED
  1962. /* Account for vlan tag */
  1963. if (sky2->vlgrp && (status & GMR_FS_VLAN))
  1964. count -= VLAN_HLEN;
  1965. #endif
  1966. netif_printk(sky2, rx_status, KERN_DEBUG, dev,
  1967. "rx slot %u status 0x%x len %d\n",
  1968. sky2->rx_next, status, length);
  1969. sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
  1970. prefetch(sky2->rx_ring + sky2->rx_next);
  1971. /* This chip has hardware problems that generates bogus status.
  1972. * So do only marginal checking and expect higher level protocols
  1973. * to handle crap frames.
  1974. */
  1975. if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
  1976. sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
  1977. length != count)
  1978. goto okay;
  1979. if (status & GMR_FS_ANY_ERR)
  1980. goto error;
  1981. if (!(status & GMR_FS_RX_OK))
  1982. goto resubmit;
  1983. /* if length reported by DMA does not match PHY, packet was truncated */
  1984. if (length != count)
  1985. goto len_error;
  1986. okay:
  1987. if (length < copybreak)
  1988. skb = receive_copy(sky2, re, length);
  1989. else
  1990. skb = receive_new(sky2, re, length);
  1991. dev->stats.rx_dropped += (skb == NULL);
  1992. resubmit:
  1993. sky2_rx_submit(sky2, re);
  1994. return skb;
  1995. len_error:
  1996. /* Truncation of overlength packets
  1997. causes PHY length to not match MAC length */
  1998. ++dev->stats.rx_length_errors;
  1999. if (net_ratelimit())
  2000. netif_info(sky2, rx_err, dev,
  2001. "rx length error: status %#x length %d\n",
  2002. status, length);
  2003. goto resubmit;
  2004. error:
  2005. ++dev->stats.rx_errors;
  2006. if (status & GMR_FS_RX_FF_OV) {
  2007. dev->stats.rx_over_errors++;
  2008. goto resubmit;
  2009. }
  2010. if (net_ratelimit())
  2011. netif_info(sky2, rx_err, dev,
  2012. "rx error, status 0x%x length %d\n", status, length);
  2013. if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
  2014. dev->stats.rx_length_errors++;
  2015. if (status & GMR_FS_FRAGMENT)
  2016. dev->stats.rx_frame_errors++;
  2017. if (status & GMR_FS_CRC_ERR)
  2018. dev->stats.rx_crc_errors++;
  2019. goto resubmit;
  2020. }
  2021. /* Transmit complete */
  2022. static inline void sky2_tx_done(struct net_device *dev, u16 last)
  2023. {
  2024. struct sky2_port *sky2 = netdev_priv(dev);
  2025. if (netif_running(dev)) {
  2026. sky2_tx_complete(sky2, last);
  2027. /* Wake unless it's detached, and called e.g. from sky2_down() */
  2028. if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
  2029. netif_wake_queue(dev);
  2030. }
  2031. }
  2032. static inline void sky2_skb_rx(const struct sky2_port *sky2,
  2033. u32 status, struct sk_buff *skb)
  2034. {
  2035. #ifdef SKY2_VLAN_TAG_USED
  2036. u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
  2037. if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
  2038. if (skb->ip_summed == CHECKSUM_NONE)
  2039. vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
  2040. else
  2041. vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
  2042. vlan_tag, skb);
  2043. return;
  2044. }
  2045. #endif
  2046. if (skb->ip_summed == CHECKSUM_NONE)
  2047. netif_receive_skb(skb);
  2048. else
  2049. napi_gro_receive(&sky2->hw->napi, skb);
  2050. }
  2051. static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
  2052. unsigned packets, unsigned bytes)
  2053. {
  2054. if (packets) {
  2055. struct net_device *dev = hw->dev[port];
  2056. dev->stats.rx_packets += packets;
  2057. dev->stats.rx_bytes += bytes;
  2058. dev->last_rx = jiffies;
  2059. sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
  2060. }
  2061. }
  2062. static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
  2063. {
  2064. /* If this happens then driver assuming wrong format for chip type */
  2065. BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
  2066. /* Both checksum counters are programmed to start at
  2067. * the same offset, so unless there is a problem they
  2068. * should match. This failure is an early indication that
  2069. * hardware receive checksumming won't work.
  2070. */
  2071. if (likely((u16)(status >> 16) == (u16)status)) {
  2072. struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
  2073. skb->ip_summed = CHECKSUM_COMPLETE;
  2074. skb->csum = le16_to_cpu(status);
  2075. } else {
  2076. dev_notice(&sky2->hw->pdev->dev,
  2077. "%s: receive checksum problem (status = %#x)\n",
  2078. sky2->netdev->name, status);
  2079. /* Disable checksum offload */
  2080. sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
  2081. sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  2082. BMU_DIS_RX_CHKSUM);
  2083. }
  2084. }
  2085. static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
  2086. {
  2087. struct sk_buff *skb;
  2088. skb = sky2->rx_ring[sky2->rx_next].skb;
  2089. skb->rxhash = le32_to_cpu(status);
  2090. }
  2091. /* Process status response ring */
  2092. static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
  2093. {
  2094. int work_done = 0;
  2095. unsigned int total_bytes[2] = { 0 };
  2096. unsigned int total_packets[2] = { 0 };
  2097. rmb();
  2098. do {
  2099. struct sky2_port *sky2;
  2100. struct sky2_status_le *le = hw->st_le + hw->st_idx;
  2101. unsigned port;
  2102. struct net_device *dev;
  2103. struct sk_buff *skb;
  2104. u32 status;
  2105. u16 length;
  2106. u8 opcode = le->opcode;
  2107. if (!(opcode & HW_OWNER))
  2108. break;
  2109. hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
  2110. port = le->css & CSS_LINK_BIT;
  2111. dev = hw->dev[port];
  2112. sky2 = netdev_priv(dev);
  2113. length = le16_to_cpu(le->length);
  2114. status = le32_to_cpu(le->status);
  2115. le->opcode = 0;
  2116. switch (opcode & ~HW_OWNER) {
  2117. case OP_RXSTAT:
  2118. total_packets[port]++;
  2119. total_bytes[port] += length;
  2120. skb = sky2_receive(dev, length, status);
  2121. if (!skb)
  2122. break;
  2123. /* This chip reports checksum status differently */
  2124. if (hw->flags & SKY2_HW_NEW_LE) {
  2125. if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
  2126. (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
  2127. (le->css & CSS_TCPUDPCSOK))
  2128. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2129. else
  2130. skb->ip_summed = CHECKSUM_NONE;
  2131. }
  2132. skb->protocol = eth_type_trans(skb, dev);
  2133. sky2_skb_rx(sky2, status, skb);
  2134. /* Stop after net poll weight */
  2135. if (++work_done >= to_do)
  2136. goto exit_loop;
  2137. break;
  2138. #ifdef SKY2_VLAN_TAG_USED
  2139. case OP_RXVLAN:
  2140. sky2->rx_tag = length;
  2141. break;
  2142. case OP_RXCHKSVLAN:
  2143. sky2->rx_tag = length;
  2144. /* fall through */
  2145. #endif
  2146. case OP_RXCHKS:
  2147. if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
  2148. sky2_rx_checksum(sky2, status);
  2149. break;
  2150. case OP_RSS_HASH:
  2151. sky2_rx_hash(sky2, status);
  2152. break;
  2153. case OP_TXINDEXLE:
  2154. /* TX index reports status for both ports */
  2155. sky2_tx_done(hw->dev[0], status & 0xfff);
  2156. if (hw->dev[1])
  2157. sky2_tx_done(hw->dev[1],
  2158. ((status >> 24) & 0xff)
  2159. | (u16)(length & 0xf) << 8);
  2160. break;
  2161. default:
  2162. if (net_ratelimit())
  2163. pr_warning("unknown status opcode 0x%x\n", opcode);
  2164. }
  2165. } while (hw->st_idx != idx);
  2166. /* Fully processed status ring so clear irq */
  2167. sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
  2168. exit_loop:
  2169. sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
  2170. sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
  2171. return work_done;
  2172. }
  2173. static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
  2174. {
  2175. struct net_device *dev = hw->dev[port];
  2176. if (net_ratelimit())
  2177. netdev_info(dev, "hw error interrupt status 0x%x\n", status);
  2178. if (status & Y2_IS_PAR_RD1) {
  2179. if (net_ratelimit())
  2180. netdev_err(dev, "ram data read parity error\n");
  2181. /* Clear IRQ */
  2182. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
  2183. }
  2184. if (status & Y2_IS_PAR_WR1) {
  2185. if (net_ratelimit())
  2186. netdev_err(dev, "ram data write parity error\n");
  2187. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
  2188. }
  2189. if (status & Y2_IS_PAR_MAC1) {
  2190. if (net_ratelimit())
  2191. netdev_err(dev, "MAC parity error\n");
  2192. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
  2193. }
  2194. if (status & Y2_IS_PAR_RX1) {
  2195. if (net_ratelimit())
  2196. netdev_err(dev, "RX parity error\n");
  2197. sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
  2198. }
  2199. if (status & Y2_IS_TCP_TXA1) {
  2200. if (net_ratelimit())
  2201. netdev_err(dev, "TCP segmentation error\n");
  2202. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
  2203. }
  2204. }
  2205. static void sky2_hw_intr(struct sky2_hw *hw)
  2206. {
  2207. struct pci_dev *pdev = hw->pdev;
  2208. u32 status = sky2_read32(hw, B0_HWE_ISRC);
  2209. u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
  2210. status &= hwmsk;
  2211. if (status & Y2_IS_TIST_OV)
  2212. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2213. if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
  2214. u16 pci_err;
  2215. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2216. pci_err = sky2_pci_read16(hw, PCI_STATUS);
  2217. if (net_ratelimit())
  2218. dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
  2219. pci_err);
  2220. sky2_pci_write16(hw, PCI_STATUS,
  2221. pci_err | PCI_STATUS_ERROR_BITS);
  2222. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2223. }
  2224. if (status & Y2_IS_PCI_EXP) {
  2225. /* PCI-Express uncorrectable Error occurred */
  2226. u32 err;
  2227. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2228. err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
  2229. sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
  2230. 0xfffffffful);
  2231. if (net_ratelimit())
  2232. dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
  2233. sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
  2234. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2235. }
  2236. if (status & Y2_HWE_L1_MASK)
  2237. sky2_hw_error(hw, 0, status);
  2238. status >>= 8;
  2239. if (status & Y2_HWE_L1_MASK)
  2240. sky2_hw_error(hw, 1, status);
  2241. }
  2242. static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
  2243. {
  2244. struct net_device *dev = hw->dev[port];
  2245. struct sky2_port *sky2 = netdev_priv(dev);
  2246. u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  2247. netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
  2248. if (status & GM_IS_RX_CO_OV)
  2249. gma_read16(hw, port, GM_RX_IRQ_SRC);
  2250. if (status & GM_IS_TX_CO_OV)
  2251. gma_read16(hw, port, GM_TX_IRQ_SRC);
  2252. if (status & GM_IS_RX_FF_OR) {
  2253. ++dev->stats.rx_fifo_errors;
  2254. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  2255. }
  2256. if (status & GM_IS_TX_FF_UR) {
  2257. ++dev->stats.tx_fifo_errors;
  2258. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  2259. }
  2260. }
  2261. /* This should never happen it is a bug. */
  2262. static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
  2263. {
  2264. struct net_device *dev = hw->dev[port];
  2265. u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
  2266. dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
  2267. dev->name, (unsigned) q, (unsigned) idx,
  2268. (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
  2269. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
  2270. }
  2271. static int sky2_rx_hung(struct net_device *dev)
  2272. {
  2273. struct sky2_port *sky2 = netdev_priv(dev);
  2274. struct sky2_hw *hw = sky2->hw;
  2275. unsigned port = sky2->port;
  2276. unsigned rxq = rxqaddr[port];
  2277. u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
  2278. u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
  2279. u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
  2280. u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
  2281. /* If idle and MAC or PCI is stuck */
  2282. if (sky2->check.last == dev->last_rx &&
  2283. ((mac_rp == sky2->check.mac_rp &&
  2284. mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
  2285. /* Check if the PCI RX hang */
  2286. (fifo_rp == sky2->check.fifo_rp &&
  2287. fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
  2288. netdev_printk(KERN_DEBUG, dev,
  2289. "hung mac %d:%d fifo %d (%d:%d)\n",
  2290. mac_lev, mac_rp, fifo_lev,
  2291. fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
  2292. return 1;
  2293. } else {
  2294. sky2->check.last = dev->last_rx;
  2295. sky2->check.mac_rp = mac_rp;
  2296. sky2->check.mac_lev = mac_lev;
  2297. sky2->check.fifo_rp = fifo_rp;
  2298. sky2->check.fifo_lev = fifo_lev;
  2299. return 0;
  2300. }
  2301. }
  2302. static void sky2_watchdog(unsigned long arg)
  2303. {
  2304. struct sky2_hw *hw = (struct sky2_hw *) arg;
  2305. /* Check for lost IRQ once a second */
  2306. if (sky2_read32(hw, B0_ISRC)) {
  2307. napi_schedule(&hw->napi);
  2308. } else {
  2309. int i, active = 0;
  2310. for (i = 0; i < hw->ports; i++) {
  2311. struct net_device *dev = hw->dev[i];
  2312. if (!netif_running(dev))
  2313. continue;
  2314. ++active;
  2315. /* For chips with Rx FIFO, check if stuck */
  2316. if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
  2317. sky2_rx_hung(dev)) {
  2318. netdev_info(dev, "receiver hang detected\n");
  2319. schedule_work(&hw->restart_work);
  2320. return;
  2321. }
  2322. }
  2323. if (active == 0)
  2324. return;
  2325. }
  2326. mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
  2327. }
  2328. /* Hardware/software error handling */
  2329. static void sky2_err_intr(struct sky2_hw *hw, u32 status)
  2330. {
  2331. if (net_ratelimit())
  2332. dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
  2333. if (status & Y2_IS_HW_ERR)
  2334. sky2_hw_intr(hw);
  2335. if (status & Y2_IS_IRQ_MAC1)
  2336. sky2_mac_intr(hw, 0);
  2337. if (status & Y2_IS_IRQ_MAC2)
  2338. sky2_mac_intr(hw, 1);
  2339. if (status & Y2_IS_CHK_RX1)
  2340. sky2_le_error(hw, 0, Q_R1);
  2341. if (status & Y2_IS_CHK_RX2)
  2342. sky2_le_error(hw, 1, Q_R2);
  2343. if (status & Y2_IS_CHK_TXA1)
  2344. sky2_le_error(hw, 0, Q_XA1);
  2345. if (status & Y2_IS_CHK_TXA2)
  2346. sky2_le_error(hw, 1, Q_XA2);
  2347. }
  2348. static int sky2_poll(struct napi_struct *napi, int work_limit)
  2349. {
  2350. struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
  2351. u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
  2352. int work_done = 0;
  2353. u16 idx;
  2354. if (unlikely(status & Y2_IS_ERROR))
  2355. sky2_err_intr(hw, status);
  2356. if (status & Y2_IS_IRQ_PHY1)
  2357. sky2_phy_intr(hw, 0);
  2358. if (status & Y2_IS_IRQ_PHY2)
  2359. sky2_phy_intr(hw, 1);
  2360. if (status & Y2_IS_PHY_QLNK)
  2361. sky2_qlink_intr(hw);
  2362. while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
  2363. work_done += sky2_status_intr(hw, work_limit - work_done, idx);
  2364. if (work_done >= work_limit)
  2365. goto done;
  2366. }
  2367. napi_complete(napi);
  2368. sky2_read32(hw, B0_Y2_SP_LISR);
  2369. done:
  2370. return work_done;
  2371. }
  2372. static irqreturn_t sky2_intr(int irq, void *dev_id)
  2373. {
  2374. struct sky2_hw *hw = dev_id;
  2375. u32 status;
  2376. /* Reading this mask interrupts as side effect */
  2377. status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  2378. if (status == 0 || status == ~0)
  2379. return IRQ_NONE;
  2380. prefetch(&hw->st_le[hw->st_idx]);
  2381. napi_schedule(&hw->napi);
  2382. return IRQ_HANDLED;
  2383. }
  2384. #ifdef CONFIG_NET_POLL_CONTROLLER
  2385. static void sky2_netpoll(struct net_device *dev)
  2386. {
  2387. struct sky2_port *sky2 = netdev_priv(dev);
  2388. napi_schedule(&sky2->hw->napi);
  2389. }
  2390. #endif
  2391. /* Chip internal frequency for clock calculations */
  2392. static u32 sky2_mhz(const struct sky2_hw *hw)
  2393. {
  2394. switch (hw->chip_id) {
  2395. case CHIP_ID_YUKON_EC:
  2396. case CHIP_ID_YUKON_EC_U:
  2397. case CHIP_ID_YUKON_EX:
  2398. case CHIP_ID_YUKON_SUPR:
  2399. case CHIP_ID_YUKON_UL_2:
  2400. case CHIP_ID_YUKON_OPT:
  2401. return 125;
  2402. case CHIP_ID_YUKON_FE:
  2403. return 100;
  2404. case CHIP_ID_YUKON_FE_P:
  2405. return 50;
  2406. case CHIP_ID_YUKON_XL:
  2407. return 156;
  2408. default:
  2409. BUG();
  2410. }
  2411. }
  2412. static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
  2413. {
  2414. return sky2_mhz(hw) * us;
  2415. }
  2416. static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
  2417. {
  2418. return clk / sky2_mhz(hw);
  2419. }
  2420. static int __devinit sky2_init(struct sky2_hw *hw)
  2421. {
  2422. u8 t8;
  2423. /* Enable all clocks and check for bad PCI access */
  2424. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  2425. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  2426. hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
  2427. hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
  2428. switch (hw->chip_id) {
  2429. case CHIP_ID_YUKON_XL:
  2430. hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
  2431. if (hw->chip_rev < CHIP_REV_YU_XL_A2)
  2432. hw->flags |= SKY2_HW_RSS_BROKEN;
  2433. break;
  2434. case CHIP_ID_YUKON_EC_U:
  2435. hw->flags = SKY2_HW_GIGABIT
  2436. | SKY2_HW_NEWER_PHY
  2437. | SKY2_HW_ADV_POWER_CTL;
  2438. break;
  2439. case CHIP_ID_YUKON_EX:
  2440. hw->flags = SKY2_HW_GIGABIT
  2441. | SKY2_HW_NEWER_PHY
  2442. | SKY2_HW_NEW_LE
  2443. | SKY2_HW_ADV_POWER_CTL;
  2444. /* New transmit checksum */
  2445. if (hw->chip_rev != CHIP_REV_YU_EX_B0)
  2446. hw->flags |= SKY2_HW_AUTO_TX_SUM;
  2447. break;
  2448. case CHIP_ID_YUKON_EC:
  2449. /* This rev is really old, and requires untested workarounds */
  2450. if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
  2451. dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
  2452. return -EOPNOTSUPP;
  2453. }
  2454. hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
  2455. break;
  2456. case CHIP_ID_YUKON_FE:
  2457. hw->flags = SKY2_HW_RSS_BROKEN;
  2458. break;
  2459. case CHIP_ID_YUKON_FE_P:
  2460. hw->flags = SKY2_HW_NEWER_PHY
  2461. | SKY2_HW_NEW_LE
  2462. | SKY2_HW_AUTO_TX_SUM
  2463. | SKY2_HW_ADV_POWER_CTL;
  2464. break;
  2465. case CHIP_ID_YUKON_SUPR:
  2466. hw->flags = SKY2_HW_GIGABIT
  2467. | SKY2_HW_NEWER_PHY
  2468. | SKY2_HW_NEW_LE
  2469. | SKY2_HW_AUTO_TX_SUM
  2470. | SKY2_HW_ADV_POWER_CTL;
  2471. break;
  2472. case CHIP_ID_YUKON_UL_2:
  2473. hw->flags = SKY2_HW_GIGABIT
  2474. | SKY2_HW_ADV_POWER_CTL;
  2475. break;
  2476. case CHIP_ID_YUKON_OPT:
  2477. hw->flags = SKY2_HW_GIGABIT
  2478. | SKY2_HW_NEW_LE
  2479. | SKY2_HW_ADV_POWER_CTL;
  2480. break;
  2481. default:
  2482. dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
  2483. hw->chip_id);
  2484. return -EOPNOTSUPP;
  2485. }
  2486. hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
  2487. if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
  2488. hw->flags |= SKY2_HW_FIBRE_PHY;
  2489. hw->ports = 1;
  2490. t8 = sky2_read8(hw, B2_Y2_HW_RES);
  2491. if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
  2492. if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
  2493. ++hw->ports;
  2494. }
  2495. if (sky2_read8(hw, B2_E_0))
  2496. hw->flags |= SKY2_HW_RAM_BUFFER;
  2497. return 0;
  2498. }
  2499. static void sky2_reset(struct sky2_hw *hw)
  2500. {
  2501. struct pci_dev *pdev = hw->pdev;
  2502. u16 status;
  2503. int i, cap;
  2504. u32 hwe_mask = Y2_HWE_ALL_MASK;
  2505. /* disable ASF */
  2506. if (hw->chip_id == CHIP_ID_YUKON_EX
  2507. || hw->chip_id == CHIP_ID_YUKON_SUPR) {
  2508. sky2_write32(hw, CPU_WDOG, 0);
  2509. status = sky2_read16(hw, HCU_CCSR);
  2510. status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
  2511. HCU_CCSR_UC_STATE_MSK);
  2512. /*
  2513. * CPU clock divider shouldn't be used because
  2514. * - ASF firmware may malfunction
  2515. * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
  2516. */
  2517. status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
  2518. sky2_write16(hw, HCU_CCSR, status);
  2519. sky2_write32(hw, CPU_WDOG, 0);
  2520. } else
  2521. sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
  2522. sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
  2523. /* do a SW reset */
  2524. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2525. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  2526. /* allow writes to PCI config */
  2527. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2528. /* clear PCI errors, if any */
  2529. status = sky2_pci_read16(hw, PCI_STATUS);
  2530. status |= PCI_STATUS_ERROR_BITS;
  2531. sky2_pci_write16(hw, PCI_STATUS, status);
  2532. sky2_write8(hw, B0_CTST, CS_MRST_CLR);
  2533. cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  2534. if (cap) {
  2535. sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
  2536. 0xfffffffful);
  2537. /* If error bit is stuck on ignore it */
  2538. if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
  2539. dev_info(&pdev->dev, "ignoring stuck error report bit\n");
  2540. else
  2541. hwe_mask |= Y2_IS_PCI_EXP;
  2542. }
  2543. sky2_power_on(hw);
  2544. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2545. for (i = 0; i < hw->ports; i++) {
  2546. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  2547. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  2548. if (hw->chip_id == CHIP_ID_YUKON_EX ||
  2549. hw->chip_id == CHIP_ID_YUKON_SUPR)
  2550. sky2_write16(hw, SK_REG(i, GMAC_CTRL),
  2551. GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
  2552. | GMC_BYP_RETR_ON);
  2553. }
  2554. if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
  2555. /* enable MACSec clock gating */
  2556. sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
  2557. }
  2558. if (hw->chip_id == CHIP_ID_YUKON_OPT) {
  2559. u16 reg;
  2560. u32 msk;
  2561. if (hw->chip_rev == 0) {
  2562. /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
  2563. sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
  2564. /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
  2565. reg = 10;
  2566. } else {
  2567. /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
  2568. reg = 3;
  2569. }
  2570. reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
  2571. /* reset PHY Link Detect */
  2572. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2573. sky2_pci_write16(hw, PSM_CONFIG_REG4,
  2574. reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
  2575. sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
  2576. /* enable PHY Quick Link */
  2577. msk = sky2_read32(hw, B0_IMSK);
  2578. msk |= Y2_IS_PHY_QLNK;
  2579. sky2_write32(hw, B0_IMSK, msk);
  2580. /* check if PSMv2 was running before */
  2581. reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
  2582. if (reg & PCI_EXP_LNKCTL_ASPMC) {
  2583. cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  2584. /* restore the PCIe Link Control register */
  2585. sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
  2586. }
  2587. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2588. /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
  2589. sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
  2590. }
  2591. /* Clear I2C IRQ noise */
  2592. sky2_write32(hw, B2_I2C_IRQ, 1);
  2593. /* turn off hardware timer (unused) */
  2594. sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
  2595. sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  2596. /* Turn off descriptor polling */
  2597. sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
  2598. /* Turn off receive timestamp */
  2599. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  2600. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2601. /* enable the Tx Arbiters */
  2602. for (i = 0; i < hw->ports; i++)
  2603. sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  2604. /* Initialize ram interface */
  2605. for (i = 0; i < hw->ports; i++) {
  2606. sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  2607. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
  2608. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
  2609. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
  2610. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
  2611. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
  2612. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
  2613. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
  2614. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
  2615. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
  2616. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
  2617. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
  2618. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
  2619. }
  2620. sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
  2621. for (i = 0; i < hw->ports; i++)
  2622. sky2_gmac_reset(hw, i);
  2623. memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
  2624. hw->st_idx = 0;
  2625. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
  2626. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
  2627. sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
  2628. sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
  2629. /* Set the list last index */
  2630. sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
  2631. sky2_write16(hw, STAT_TX_IDX_TH, 10);
  2632. sky2_write8(hw, STAT_FIFO_WM, 16);
  2633. /* set Status-FIFO ISR watermark */
  2634. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
  2635. sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
  2636. else
  2637. sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
  2638. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
  2639. sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
  2640. sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
  2641. /* enable status unit */
  2642. sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
  2643. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  2644. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  2645. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  2646. }
  2647. /* Take device down (offline).
  2648. * Equivalent to doing dev_stop() but this does not
  2649. * inform upper layers of the transistion.
  2650. */
  2651. static void sky2_detach(struct net_device *dev)
  2652. {
  2653. if (netif_running(dev)) {
  2654. netif_tx_lock(dev);
  2655. netif_device_detach(dev); /* stop txq */
  2656. netif_tx_unlock(dev);
  2657. sky2_down(dev);
  2658. }
  2659. }
  2660. /* Bring device back after doing sky2_detach */
  2661. static int sky2_reattach(struct net_device *dev)
  2662. {
  2663. int err = 0;
  2664. if (netif_running(dev)) {
  2665. err = sky2_up(dev);
  2666. if (err) {
  2667. netdev_info(dev, "could not restart %d\n", err);
  2668. dev_close(dev);
  2669. } else {
  2670. netif_device_attach(dev);
  2671. sky2_set_multicast(dev);
  2672. }
  2673. }
  2674. return err;
  2675. }
  2676. static void sky2_all_down(struct sky2_hw *hw)
  2677. {
  2678. int i;
  2679. sky2_read32(hw, B0_IMSK);
  2680. sky2_write32(hw, B0_IMSK, 0);
  2681. synchronize_irq(hw->pdev->irq);
  2682. napi_disable(&hw->napi);
  2683. for (i = 0; i < hw->ports; i++) {
  2684. struct net_device *dev = hw->dev[i];
  2685. struct sky2_port *sky2 = netdev_priv(dev);
  2686. if (!netif_running(dev))
  2687. continue;
  2688. netif_carrier_off(dev);
  2689. netif_tx_disable(dev);
  2690. sky2_hw_down(sky2);
  2691. }
  2692. }
  2693. static void sky2_all_up(struct sky2_hw *hw)
  2694. {
  2695. u32 imask = Y2_IS_BASE;
  2696. int i;
  2697. for (i = 0; i < hw->ports; i++) {
  2698. struct net_device *dev = hw->dev[i];
  2699. struct sky2_port *sky2 = netdev_priv(dev);
  2700. if (!netif_running(dev))
  2701. continue;
  2702. sky2_hw_up(sky2);
  2703. sky2_set_multicast(dev);
  2704. imask |= portirq_msk[i];
  2705. netif_wake_queue(dev);
  2706. }
  2707. sky2_write32(hw, B0_IMSK, imask);
  2708. sky2_read32(hw, B0_IMSK);
  2709. sky2_read32(hw, B0_Y2_SP_LISR);
  2710. napi_enable(&hw->napi);
  2711. }
  2712. static void sky2_restart(struct work_struct *work)
  2713. {
  2714. struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
  2715. rtnl_lock();
  2716. sky2_all_down(hw);
  2717. sky2_reset(hw);
  2718. sky2_all_up(hw);
  2719. rtnl_unlock();
  2720. }
  2721. static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
  2722. {
  2723. return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
  2724. }
  2725. static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2726. {
  2727. const struct sky2_port *sky2 = netdev_priv(dev);
  2728. wol->supported = sky2_wol_supported(sky2->hw);
  2729. wol->wolopts = sky2->wol;
  2730. }
  2731. static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2732. {
  2733. struct sky2_port *sky2 = netdev_priv(dev);
  2734. struct sky2_hw *hw = sky2->hw;
  2735. if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
  2736. !device_can_wakeup(&hw->pdev->dev))
  2737. return -EOPNOTSUPP;
  2738. sky2->wol = wol->wolopts;
  2739. return 0;
  2740. }
  2741. static u32 sky2_supported_modes(const struct sky2_hw *hw)
  2742. {
  2743. if (sky2_is_copper(hw)) {
  2744. u32 modes = SUPPORTED_10baseT_Half
  2745. | SUPPORTED_10baseT_Full
  2746. | SUPPORTED_100baseT_Half
  2747. | SUPPORTED_100baseT_Full
  2748. | SUPPORTED_Autoneg | SUPPORTED_TP;
  2749. if (hw->flags & SKY2_HW_GIGABIT)
  2750. modes |= SUPPORTED_1000baseT_Half
  2751. | SUPPORTED_1000baseT_Full;
  2752. return modes;
  2753. } else
  2754. return SUPPORTED_1000baseT_Half
  2755. | SUPPORTED_1000baseT_Full
  2756. | SUPPORTED_Autoneg
  2757. | SUPPORTED_FIBRE;
  2758. }
  2759. static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2760. {
  2761. struct sky2_port *sky2 = netdev_priv(dev);
  2762. struct sky2_hw *hw = sky2->hw;
  2763. ecmd->transceiver = XCVR_INTERNAL;
  2764. ecmd->supported = sky2_supported_modes(hw);
  2765. ecmd->phy_address = PHY_ADDR_MARV;
  2766. if (sky2_is_copper(hw)) {
  2767. ecmd->port = PORT_TP;
  2768. ecmd->speed = sky2->speed;
  2769. } else {
  2770. ecmd->speed = SPEED_1000;
  2771. ecmd->port = PORT_FIBRE;
  2772. }
  2773. ecmd->advertising = sky2->advertising;
  2774. ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
  2775. ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  2776. ecmd->duplex = sky2->duplex;
  2777. return 0;
  2778. }
  2779. static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2780. {
  2781. struct sky2_port *sky2 = netdev_priv(dev);
  2782. const struct sky2_hw *hw = sky2->hw;
  2783. u32 supported = sky2_supported_modes(hw);
  2784. if (ecmd->autoneg == AUTONEG_ENABLE) {
  2785. sky2->flags |= SKY2_FLAG_AUTO_SPEED;
  2786. ecmd->advertising = supported;
  2787. sky2->duplex = -1;
  2788. sky2->speed = -1;
  2789. } else {
  2790. u32 setting;
  2791. switch (ecmd->speed) {
  2792. case SPEED_1000:
  2793. if (ecmd->duplex == DUPLEX_FULL)
  2794. setting = SUPPORTED_1000baseT_Full;
  2795. else if (ecmd->duplex == DUPLEX_HALF)
  2796. setting = SUPPORTED_1000baseT_Half;
  2797. else
  2798. return -EINVAL;
  2799. break;
  2800. case SPEED_100:
  2801. if (ecmd->duplex == DUPLEX_FULL)
  2802. setting = SUPPORTED_100baseT_Full;
  2803. else if (ecmd->duplex == DUPLEX_HALF)
  2804. setting = SUPPORTED_100baseT_Half;
  2805. else
  2806. return -EINVAL;
  2807. break;
  2808. case SPEED_10:
  2809. if (ecmd->duplex == DUPLEX_FULL)
  2810. setting = SUPPORTED_10baseT_Full;
  2811. else if (ecmd->duplex == DUPLEX_HALF)
  2812. setting = SUPPORTED_10baseT_Half;
  2813. else
  2814. return -EINVAL;
  2815. break;
  2816. default:
  2817. return -EINVAL;
  2818. }
  2819. if ((setting & supported) == 0)
  2820. return -EINVAL;
  2821. sky2->speed = ecmd->speed;
  2822. sky2->duplex = ecmd->duplex;
  2823. sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
  2824. }
  2825. sky2->advertising = ecmd->advertising;
  2826. if (netif_running(dev)) {
  2827. sky2_phy_reinit(sky2);
  2828. sky2_set_multicast(dev);
  2829. }
  2830. return 0;
  2831. }
  2832. static void sky2_get_drvinfo(struct net_device *dev,
  2833. struct ethtool_drvinfo *info)
  2834. {
  2835. struct sky2_port *sky2 = netdev_priv(dev);
  2836. strcpy(info->driver, DRV_NAME);
  2837. strcpy(info->version, DRV_VERSION);
  2838. strcpy(info->fw_version, "N/A");
  2839. strcpy(info->bus_info, pci_name(sky2->hw->pdev));
  2840. }
  2841. static const struct sky2_stat {
  2842. char name[ETH_GSTRING_LEN];
  2843. u16 offset;
  2844. } sky2_stats[] = {
  2845. { "tx_bytes", GM_TXO_OK_HI },
  2846. { "rx_bytes", GM_RXO_OK_HI },
  2847. { "tx_broadcast", GM_TXF_BC_OK },
  2848. { "rx_broadcast", GM_RXF_BC_OK },
  2849. { "tx_multicast", GM_TXF_MC_OK },
  2850. { "rx_multicast", GM_RXF_MC_OK },
  2851. { "tx_unicast", GM_TXF_UC_OK },
  2852. { "rx_unicast", GM_RXF_UC_OK },
  2853. { "tx_mac_pause", GM_TXF_MPAUSE },
  2854. { "rx_mac_pause", GM_RXF_MPAUSE },
  2855. { "collisions", GM_TXF_COL },
  2856. { "late_collision",GM_TXF_LAT_COL },
  2857. { "aborted", GM_TXF_ABO_COL },
  2858. { "single_collisions", GM_TXF_SNG_COL },
  2859. { "multi_collisions", GM_TXF_MUL_COL },
  2860. { "rx_short", GM_RXF_SHT },
  2861. { "rx_runt", GM_RXE_FRAG },
  2862. { "rx_64_byte_packets", GM_RXF_64B },
  2863. { "rx_65_to_127_byte_packets", GM_RXF_127B },
  2864. { "rx_128_to_255_byte_packets", GM_RXF_255B },
  2865. { "rx_256_to_511_byte_packets", GM_RXF_511B },
  2866. { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
  2867. { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
  2868. { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
  2869. { "rx_too_long", GM_RXF_LNG_ERR },
  2870. { "rx_fifo_overflow", GM_RXE_FIFO_OV },
  2871. { "rx_jabber", GM_RXF_JAB_PKT },
  2872. { "rx_fcs_error", GM_RXF_FCS_ERR },
  2873. { "tx_64_byte_packets", GM_TXF_64B },
  2874. { "tx_65_to_127_byte_packets", GM_TXF_127B },
  2875. { "tx_128_to_255_byte_packets", GM_TXF_255B },
  2876. { "tx_256_to_511_byte_packets", GM_TXF_511B },
  2877. { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
  2878. { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
  2879. { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
  2880. { "tx_fifo_underrun", GM_TXE_FIFO_UR },
  2881. };
  2882. static u32 sky2_get_rx_csum(struct net_device *dev)
  2883. {
  2884. struct sky2_port *sky2 = netdev_priv(dev);
  2885. return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
  2886. }
  2887. static int sky2_set_rx_csum(struct net_device *dev, u32 data)
  2888. {
  2889. struct sky2_port *sky2 = netdev_priv(dev);
  2890. if (data)
  2891. sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
  2892. else
  2893. sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
  2894. sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  2895. data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  2896. return 0;
  2897. }
  2898. static u32 sky2_get_msglevel(struct net_device *netdev)
  2899. {
  2900. struct sky2_port *sky2 = netdev_priv(netdev);
  2901. return sky2->msg_enable;
  2902. }
  2903. static int sky2_nway_reset(struct net_device *dev)
  2904. {
  2905. struct sky2_port *sky2 = netdev_priv(dev);
  2906. if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
  2907. return -EINVAL;
  2908. sky2_phy_reinit(sky2);
  2909. sky2_set_multicast(dev);
  2910. return 0;
  2911. }
  2912. static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
  2913. {
  2914. struct sky2_hw *hw = sky2->hw;
  2915. unsigned port = sky2->port;
  2916. int i;
  2917. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  2918. | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
  2919. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  2920. | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
  2921. for (i = 2; i < count; i++)
  2922. data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
  2923. }
  2924. static void sky2_set_msglevel(struct net_device *netdev, u32 value)
  2925. {
  2926. struct sky2_port *sky2 = netdev_priv(netdev);
  2927. sky2->msg_enable = value;
  2928. }
  2929. static int sky2_get_sset_count(struct net_device *dev, int sset)
  2930. {
  2931. switch (sset) {
  2932. case ETH_SS_STATS:
  2933. return ARRAY_SIZE(sky2_stats);
  2934. default:
  2935. return -EOPNOTSUPP;
  2936. }
  2937. }
  2938. static void sky2_get_ethtool_stats(struct net_device *dev,
  2939. struct ethtool_stats *stats, u64 * data)
  2940. {
  2941. struct sky2_port *sky2 = netdev_priv(dev);
  2942. sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
  2943. }
  2944. static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
  2945. {
  2946. int i;
  2947. switch (stringset) {
  2948. case ETH_SS_STATS:
  2949. for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
  2950. memcpy(data + i * ETH_GSTRING_LEN,
  2951. sky2_stats[i].name, ETH_GSTRING_LEN);
  2952. break;
  2953. }
  2954. }
  2955. static int sky2_set_mac_address(struct net_device *dev, void *p)
  2956. {
  2957. struct sky2_port *sky2 = netdev_priv(dev);
  2958. struct sky2_hw *hw = sky2->hw;
  2959. unsigned port = sky2->port;
  2960. const struct sockaddr *addr = p;
  2961. if (!is_valid_ether_addr(addr->sa_data))
  2962. return -EADDRNOTAVAIL;
  2963. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2964. memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
  2965. dev->dev_addr, ETH_ALEN);
  2966. memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
  2967. dev->dev_addr, ETH_ALEN);
  2968. /* virtual address for data */
  2969. gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
  2970. /* physical address: used for pause frames */
  2971. gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
  2972. return 0;
  2973. }
  2974. static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
  2975. {
  2976. u32 bit;
  2977. bit = ether_crc(ETH_ALEN, addr) & 63;
  2978. filter[bit >> 3] |= 1 << (bit & 7);
  2979. }
  2980. static void sky2_set_multicast(struct net_device *dev)
  2981. {
  2982. struct sky2_port *sky2 = netdev_priv(dev);
  2983. struct sky2_hw *hw = sky2->hw;
  2984. unsigned port = sky2->port;
  2985. struct netdev_hw_addr *ha;
  2986. u16 reg;
  2987. u8 filter[8];
  2988. int rx_pause;
  2989. static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
  2990. rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
  2991. memset(filter, 0, sizeof(filter));
  2992. reg = gma_read16(hw, port, GM_RX_CTRL);
  2993. reg |= GM_RXCR_UCF_ENA;
  2994. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2995. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2996. else if (dev->flags & IFF_ALLMULTI)
  2997. memset(filter, 0xff, sizeof(filter));
  2998. else if (netdev_mc_empty(dev) && !rx_pause)
  2999. reg &= ~GM_RXCR_MCF_ENA;
  3000. else {
  3001. reg |= GM_RXCR_MCF_ENA;
  3002. if (rx_pause)
  3003. sky2_add_filter(filter, pause_mc_addr);
  3004. netdev_for_each_mc_addr(ha, dev)
  3005. sky2_add_filter(filter, ha->addr);
  3006. }
  3007. gma_write16(hw, port, GM_MC_ADDR_H1,
  3008. (u16) filter[0] | ((u16) filter[1] << 8));
  3009. gma_write16(hw, port, GM_MC_ADDR_H2,
  3010. (u16) filter[2] | ((u16) filter[3] << 8));
  3011. gma_write16(hw, port, GM_MC_ADDR_H3,
  3012. (u16) filter[4] | ((u16) filter[5] << 8));
  3013. gma_write16(hw, port, GM_MC_ADDR_H4,
  3014. (u16) filter[6] | ((u16) filter[7] << 8));
  3015. gma_write16(hw, port, GM_RX_CTRL, reg);
  3016. }
  3017. /* Can have one global because blinking is controlled by
  3018. * ethtool and that is always under RTNL mutex
  3019. */
  3020. static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
  3021. {
  3022. struct sky2_hw *hw = sky2->hw;
  3023. unsigned port = sky2->port;
  3024. spin_lock_bh(&sky2->phy_lock);
  3025. if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
  3026. hw->chip_id == CHIP_ID_YUKON_EX ||
  3027. hw->chip_id == CHIP_ID_YUKON_SUPR) {
  3028. u16 pg;
  3029. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  3030. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  3031. switch (mode) {
  3032. case MO_LED_OFF:
  3033. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  3034. PHY_M_LEDC_LOS_CTRL(8) |
  3035. PHY_M_LEDC_INIT_CTRL(8) |
  3036. PHY_M_LEDC_STA1_CTRL(8) |
  3037. PHY_M_LEDC_STA0_CTRL(8));
  3038. break;
  3039. case MO_LED_ON:
  3040. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  3041. PHY_M_LEDC_LOS_CTRL(9) |
  3042. PHY_M_LEDC_INIT_CTRL(9) |
  3043. PHY_M_LEDC_STA1_CTRL(9) |
  3044. PHY_M_LEDC_STA0_CTRL(9));
  3045. break;
  3046. case MO_LED_BLINK:
  3047. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  3048. PHY_M_LEDC_LOS_CTRL(0xa) |
  3049. PHY_M_LEDC_INIT_CTRL(0xa) |
  3050. PHY_M_LEDC_STA1_CTRL(0xa) |
  3051. PHY_M_LEDC_STA0_CTRL(0xa));
  3052. break;
  3053. case MO_LED_NORM:
  3054. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  3055. PHY_M_LEDC_LOS_CTRL(1) |
  3056. PHY_M_LEDC_INIT_CTRL(8) |
  3057. PHY_M_LEDC_STA1_CTRL(7) |
  3058. PHY_M_LEDC_STA0_CTRL(7));
  3059. }
  3060. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  3061. } else
  3062. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  3063. PHY_M_LED_MO_DUP(mode) |
  3064. PHY_M_LED_MO_10(mode) |
  3065. PHY_M_LED_MO_100(mode) |
  3066. PHY_M_LED_MO_1000(mode) |
  3067. PHY_M_LED_MO_RX(mode) |
  3068. PHY_M_LED_MO_TX(mode));
  3069. spin_unlock_bh(&sky2->phy_lock);
  3070. }
  3071. /* blink LED's for finding board */
  3072. static int sky2_phys_id(struct net_device *dev, u32 data)
  3073. {
  3074. struct sky2_port *sky2 = netdev_priv(dev);
  3075. unsigned int i;
  3076. if (data == 0)
  3077. data = UINT_MAX;
  3078. for (i = 0; i < data; i++) {
  3079. sky2_led(sky2, MO_LED_ON);
  3080. if (msleep_interruptible(500))
  3081. break;
  3082. sky2_led(sky2, MO_LED_OFF);
  3083. if (msleep_interruptible(500))
  3084. break;
  3085. }
  3086. sky2_led(sky2, MO_LED_NORM);
  3087. return 0;
  3088. }
  3089. static void sky2_get_pauseparam(struct net_device *dev,
  3090. struct ethtool_pauseparam *ecmd)
  3091. {
  3092. struct sky2_port *sky2 = netdev_priv(dev);
  3093. switch (sky2->flow_mode) {
  3094. case FC_NONE:
  3095. ecmd->tx_pause = ecmd->rx_pause = 0;
  3096. break;
  3097. case FC_TX:
  3098. ecmd->tx_pause = 1, ecmd->rx_pause = 0;
  3099. break;
  3100. case FC_RX:
  3101. ecmd->tx_pause = 0, ecmd->rx_pause = 1;
  3102. break;
  3103. case FC_BOTH:
  3104. ecmd->tx_pause = ecmd->rx_pause = 1;
  3105. }
  3106. ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
  3107. ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  3108. }
  3109. static int sky2_set_pauseparam(struct net_device *dev,
  3110. struct ethtool_pauseparam *ecmd)
  3111. {
  3112. struct sky2_port *sky2 = netdev_priv(dev);
  3113. if (ecmd->autoneg == AUTONEG_ENABLE)
  3114. sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
  3115. else
  3116. sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
  3117. sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
  3118. if (netif_running(dev))
  3119. sky2_phy_reinit(sky2);
  3120. return 0;
  3121. }
  3122. static int sky2_get_coalesce(struct net_device *dev,
  3123. struct ethtool_coalesce *ecmd)
  3124. {
  3125. struct sky2_port *sky2 = netdev_priv(dev);
  3126. struct sky2_hw *hw = sky2->hw;
  3127. if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
  3128. ecmd->tx_coalesce_usecs = 0;
  3129. else {
  3130. u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
  3131. ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
  3132. }
  3133. ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
  3134. if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
  3135. ecmd->rx_coalesce_usecs = 0;
  3136. else {
  3137. u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
  3138. ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
  3139. }
  3140. ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
  3141. if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
  3142. ecmd->rx_coalesce_usecs_irq = 0;
  3143. else {
  3144. u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
  3145. ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
  3146. }
  3147. ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
  3148. return 0;
  3149. }
  3150. /* Note: this affect both ports */
  3151. static int sky2_set_coalesce(struct net_device *dev,
  3152. struct ethtool_coalesce *ecmd)
  3153. {
  3154. struct sky2_port *sky2 = netdev_priv(dev);
  3155. struct sky2_hw *hw = sky2->hw;
  3156. const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
  3157. if (ecmd->tx_coalesce_usecs > tmax ||
  3158. ecmd->rx_coalesce_usecs > tmax ||
  3159. ecmd->rx_coalesce_usecs_irq > tmax)
  3160. return -EINVAL;
  3161. if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
  3162. return -EINVAL;
  3163. if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
  3164. return -EINVAL;
  3165. if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
  3166. return -EINVAL;
  3167. if (ecmd->tx_coalesce_usecs == 0)
  3168. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  3169. else {
  3170. sky2_write32(hw, STAT_TX_TIMER_INI,
  3171. sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
  3172. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  3173. }
  3174. sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
  3175. if (ecmd->rx_coalesce_usecs == 0)
  3176. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
  3177. else {
  3178. sky2_write32(hw, STAT_LEV_TIMER_INI,
  3179. sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
  3180. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  3181. }
  3182. sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
  3183. if (ecmd->rx_coalesce_usecs_irq == 0)
  3184. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
  3185. else {
  3186. sky2_write32(hw, STAT_ISR_TIMER_INI,
  3187. sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
  3188. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  3189. }
  3190. sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
  3191. return 0;
  3192. }
  3193. static void sky2_get_ringparam(struct net_device *dev,
  3194. struct ethtool_ringparam *ering)
  3195. {
  3196. struct sky2_port *sky2 = netdev_priv(dev);
  3197. ering->rx_max_pending = RX_MAX_PENDING;
  3198. ering->rx_mini_max_pending = 0;
  3199. ering->rx_jumbo_max_pending = 0;
  3200. ering->tx_max_pending = TX_MAX_PENDING;
  3201. ering->rx_pending = sky2->rx_pending;
  3202. ering->rx_mini_pending = 0;
  3203. ering->rx_jumbo_pending = 0;
  3204. ering->tx_pending = sky2->tx_pending;
  3205. }
  3206. static int sky2_set_ringparam(struct net_device *dev,
  3207. struct ethtool_ringparam *ering)
  3208. {
  3209. struct sky2_port *sky2 = netdev_priv(dev);
  3210. if (ering->rx_pending > RX_MAX_PENDING ||
  3211. ering->rx_pending < 8 ||
  3212. ering->tx_pending < TX_MIN_PENDING ||
  3213. ering->tx_pending > TX_MAX_PENDING)
  3214. return -EINVAL;
  3215. sky2_detach(dev);
  3216. sky2->rx_pending = ering->rx_pending;
  3217. sky2->tx_pending = ering->tx_pending;
  3218. sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
  3219. return sky2_reattach(dev);
  3220. }
  3221. static int sky2_get_regs_len(struct net_device *dev)
  3222. {
  3223. return 0x4000;
  3224. }
  3225. static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
  3226. {
  3227. /* This complicated switch statement is to make sure and
  3228. * only access regions that are unreserved.
  3229. * Some blocks are only valid on dual port cards.
  3230. */
  3231. switch (b) {
  3232. /* second port */
  3233. case 5: /* Tx Arbiter 2 */
  3234. case 9: /* RX2 */
  3235. case 14 ... 15: /* TX2 */
  3236. case 17: case 19: /* Ram Buffer 2 */
  3237. case 22 ... 23: /* Tx Ram Buffer 2 */
  3238. case 25: /* Rx MAC Fifo 1 */
  3239. case 27: /* Tx MAC Fifo 2 */
  3240. case 31: /* GPHY 2 */
  3241. case 40 ... 47: /* Pattern Ram 2 */
  3242. case 52: case 54: /* TCP Segmentation 2 */
  3243. case 112 ... 116: /* GMAC 2 */
  3244. return hw->ports > 1;
  3245. case 0: /* Control */
  3246. case 2: /* Mac address */
  3247. case 4: /* Tx Arbiter 1 */
  3248. case 7: /* PCI express reg */
  3249. case 8: /* RX1 */
  3250. case 12 ... 13: /* TX1 */
  3251. case 16: case 18:/* Rx Ram Buffer 1 */
  3252. case 20 ... 21: /* Tx Ram Buffer 1 */
  3253. case 24: /* Rx MAC Fifo 1 */
  3254. case 26: /* Tx MAC Fifo 1 */
  3255. case 28 ... 29: /* Descriptor and status unit */
  3256. case 30: /* GPHY 1*/
  3257. case 32 ... 39: /* Pattern Ram 1 */
  3258. case 48: case 50: /* TCP Segmentation 1 */
  3259. case 56 ... 60: /* PCI space */
  3260. case 80 ... 84: /* GMAC 1 */
  3261. return 1;
  3262. default:
  3263. return 0;
  3264. }
  3265. }
  3266. /*
  3267. * Returns copy of control register region
  3268. * Note: ethtool_get_regs always provides full size (16k) buffer
  3269. */
  3270. static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  3271. void *p)
  3272. {
  3273. const struct sky2_port *sky2 = netdev_priv(dev);
  3274. const void __iomem *io = sky2->hw->regs;
  3275. unsigned int b;
  3276. regs->version = 1;
  3277. for (b = 0; b < 128; b++) {
  3278. /* skip poisonous diagnostic ram region in block 3 */
  3279. if (b == 3)
  3280. memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
  3281. else if (sky2_reg_access_ok(sky2->hw, b))
  3282. memcpy_fromio(p, io, 128);
  3283. else
  3284. memset(p, 0, 128);
  3285. p += 128;
  3286. io += 128;
  3287. }
  3288. }
  3289. /* In order to do Jumbo packets on these chips, need to turn off the
  3290. * transmit store/forward. Therefore checksum offload won't work.
  3291. */
  3292. static int no_tx_offload(struct net_device *dev)
  3293. {
  3294. const struct sky2_port *sky2 = netdev_priv(dev);
  3295. const struct sky2_hw *hw = sky2->hw;
  3296. return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
  3297. }
  3298. static int sky2_set_tx_csum(struct net_device *dev, u32 data)
  3299. {
  3300. if (data && no_tx_offload(dev))
  3301. return -EINVAL;
  3302. return ethtool_op_set_tx_csum(dev, data);
  3303. }
  3304. static int sky2_set_tso(struct net_device *dev, u32 data)
  3305. {
  3306. if (data && no_tx_offload(dev))
  3307. return -EINVAL;
  3308. return ethtool_op_set_tso(dev, data);
  3309. }
  3310. static int sky2_get_eeprom_len(struct net_device *dev)
  3311. {
  3312. struct sky2_port *sky2 = netdev_priv(dev);
  3313. struct sky2_hw *hw = sky2->hw;
  3314. u16 reg2;
  3315. reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
  3316. return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
  3317. }
  3318. static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
  3319. {
  3320. unsigned long start = jiffies;
  3321. while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
  3322. /* Can take up to 10.6 ms for write */
  3323. if (time_after(jiffies, start + HZ/4)) {
  3324. dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
  3325. return -ETIMEDOUT;
  3326. }
  3327. mdelay(1);
  3328. }
  3329. return 0;
  3330. }
  3331. static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
  3332. u16 offset, size_t length)
  3333. {
  3334. int rc = 0;
  3335. while (length > 0) {
  3336. u32 val;
  3337. sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
  3338. rc = sky2_vpd_wait(hw, cap, 0);
  3339. if (rc)
  3340. break;
  3341. val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
  3342. memcpy(data, &val, min(sizeof(val), length));
  3343. offset += sizeof(u32);
  3344. data += sizeof(u32);
  3345. length -= sizeof(u32);
  3346. }
  3347. return rc;
  3348. }
  3349. static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
  3350. u16 offset, unsigned int length)
  3351. {
  3352. unsigned int i;
  3353. int rc = 0;
  3354. for (i = 0; i < length; i += sizeof(u32)) {
  3355. u32 val = *(u32 *)(data + i);
  3356. sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
  3357. sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
  3358. rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
  3359. if (rc)
  3360. break;
  3361. }
  3362. return rc;
  3363. }
  3364. static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  3365. u8 *data)
  3366. {
  3367. struct sky2_port *sky2 = netdev_priv(dev);
  3368. int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
  3369. if (!cap)
  3370. return -EINVAL;
  3371. eeprom->magic = SKY2_EEPROM_MAGIC;
  3372. return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
  3373. }
  3374. static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  3375. u8 *data)
  3376. {
  3377. struct sky2_port *sky2 = netdev_priv(dev);
  3378. int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
  3379. if (!cap)
  3380. return -EINVAL;
  3381. if (eeprom->magic != SKY2_EEPROM_MAGIC)
  3382. return -EINVAL;
  3383. /* Partial writes not supported */
  3384. if ((eeprom->offset & 3) || (eeprom->len & 3))
  3385. return -EINVAL;
  3386. return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
  3387. }
  3388. static int sky2_set_flags(struct net_device *dev, u32 data)
  3389. {
  3390. struct sky2_port *sky2 = netdev_priv(dev);
  3391. u32 supported =
  3392. (sky2->hw->flags & SKY2_HW_RSS_BROKEN) ? 0 : ETH_FLAG_RXHASH;
  3393. int rc;
  3394. rc = ethtool_op_set_flags(dev, data, supported);
  3395. if (rc)
  3396. return rc;
  3397. rx_set_rss(dev);
  3398. return 0;
  3399. }
  3400. static const struct ethtool_ops sky2_ethtool_ops = {
  3401. .get_settings = sky2_get_settings,
  3402. .set_settings = sky2_set_settings,
  3403. .get_drvinfo = sky2_get_drvinfo,
  3404. .get_wol = sky2_get_wol,
  3405. .set_wol = sky2_set_wol,
  3406. .get_msglevel = sky2_get_msglevel,
  3407. .set_msglevel = sky2_set_msglevel,
  3408. .nway_reset = sky2_nway_reset,
  3409. .get_regs_len = sky2_get_regs_len,
  3410. .get_regs = sky2_get_regs,
  3411. .get_link = ethtool_op_get_link,
  3412. .get_eeprom_len = sky2_get_eeprom_len,
  3413. .get_eeprom = sky2_get_eeprom,
  3414. .set_eeprom = sky2_set_eeprom,
  3415. .set_sg = ethtool_op_set_sg,
  3416. .set_tx_csum = sky2_set_tx_csum,
  3417. .set_tso = sky2_set_tso,
  3418. .get_rx_csum = sky2_get_rx_csum,
  3419. .set_rx_csum = sky2_set_rx_csum,
  3420. .get_strings = sky2_get_strings,
  3421. .get_coalesce = sky2_get_coalesce,
  3422. .set_coalesce = sky2_set_coalesce,
  3423. .get_ringparam = sky2_get_ringparam,
  3424. .set_ringparam = sky2_set_ringparam,
  3425. .get_pauseparam = sky2_get_pauseparam,
  3426. .set_pauseparam = sky2_set_pauseparam,
  3427. .phys_id = sky2_phys_id,
  3428. .get_sset_count = sky2_get_sset_count,
  3429. .get_ethtool_stats = sky2_get_ethtool_stats,
  3430. .set_flags = sky2_set_flags,
  3431. };
  3432. #ifdef CONFIG_SKY2_DEBUG
  3433. static struct dentry *sky2_debug;
  3434. /*
  3435. * Read and parse the first part of Vital Product Data
  3436. */
  3437. #define VPD_SIZE 128
  3438. #define VPD_MAGIC 0x82
  3439. static const struct vpd_tag {
  3440. char tag[2];
  3441. char *label;
  3442. } vpd_tags[] = {
  3443. { "PN", "Part Number" },
  3444. { "EC", "Engineering Level" },
  3445. { "MN", "Manufacturer" },
  3446. { "SN", "Serial Number" },
  3447. { "YA", "Asset Tag" },
  3448. { "VL", "First Error Log Message" },
  3449. { "VF", "Second Error Log Message" },
  3450. { "VB", "Boot Agent ROM Configuration" },
  3451. { "VE", "EFI UNDI Configuration" },
  3452. };
  3453. static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
  3454. {
  3455. size_t vpd_size;
  3456. loff_t offs;
  3457. u8 len;
  3458. unsigned char *buf;
  3459. u16 reg2;
  3460. reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
  3461. vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
  3462. seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
  3463. buf = kmalloc(vpd_size, GFP_KERNEL);
  3464. if (!buf) {
  3465. seq_puts(seq, "no memory!\n");
  3466. return;
  3467. }
  3468. if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
  3469. seq_puts(seq, "VPD read failed\n");
  3470. goto out;
  3471. }
  3472. if (buf[0] != VPD_MAGIC) {
  3473. seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
  3474. goto out;
  3475. }
  3476. len = buf[1];
  3477. if (len == 0 || len > vpd_size - 4) {
  3478. seq_printf(seq, "Invalid id length: %d\n", len);
  3479. goto out;
  3480. }
  3481. seq_printf(seq, "%.*s\n", len, buf + 3);
  3482. offs = len + 3;
  3483. while (offs < vpd_size - 4) {
  3484. int i;
  3485. if (!memcmp("RW", buf + offs, 2)) /* end marker */
  3486. break;
  3487. len = buf[offs + 2];
  3488. if (offs + len + 3 >= vpd_size)
  3489. break;
  3490. for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
  3491. if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
  3492. seq_printf(seq, " %s: %.*s\n",
  3493. vpd_tags[i].label, len, buf + offs + 3);
  3494. break;
  3495. }
  3496. }
  3497. offs += len + 3;
  3498. }
  3499. out:
  3500. kfree(buf);
  3501. }
  3502. static int sky2_debug_show(struct seq_file *seq, void *v)
  3503. {
  3504. struct net_device *dev = seq->private;
  3505. const struct sky2_port *sky2 = netdev_priv(dev);
  3506. struct sky2_hw *hw = sky2->hw;
  3507. unsigned port = sky2->port;
  3508. unsigned idx, last;
  3509. int sop;
  3510. sky2_show_vpd(seq, hw);
  3511. seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
  3512. sky2_read32(hw, B0_ISRC),
  3513. sky2_read32(hw, B0_IMSK),
  3514. sky2_read32(hw, B0_Y2_SP_ICR));
  3515. if (!netif_running(dev)) {
  3516. seq_printf(seq, "network not running\n");
  3517. return 0;
  3518. }
  3519. napi_disable(&hw->napi);
  3520. last = sky2_read16(hw, STAT_PUT_IDX);
  3521. seq_printf(seq, "Status ring %u\n", hw->st_size);
  3522. if (hw->st_idx == last)
  3523. seq_puts(seq, "Status ring (empty)\n");
  3524. else {
  3525. seq_puts(seq, "Status ring\n");
  3526. for (idx = hw->st_idx; idx != last && idx < hw->st_size;
  3527. idx = RING_NEXT(idx, hw->st_size)) {
  3528. const struct sky2_status_le *le = hw->st_le + idx;
  3529. seq_printf(seq, "[%d] %#x %d %#x\n",
  3530. idx, le->opcode, le->length, le->status);
  3531. }
  3532. seq_puts(seq, "\n");
  3533. }
  3534. seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
  3535. sky2->tx_cons, sky2->tx_prod,
  3536. sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
  3537. sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
  3538. /* Dump contents of tx ring */
  3539. sop = 1;
  3540. for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
  3541. idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  3542. const struct sky2_tx_le *le = sky2->tx_le + idx;
  3543. u32 a = le32_to_cpu(le->addr);
  3544. if (sop)
  3545. seq_printf(seq, "%u:", idx);
  3546. sop = 0;
  3547. switch (le->opcode & ~HW_OWNER) {
  3548. case OP_ADDR64:
  3549. seq_printf(seq, " %#x:", a);
  3550. break;
  3551. case OP_LRGLEN:
  3552. seq_printf(seq, " mtu=%d", a);
  3553. break;
  3554. case OP_VLAN:
  3555. seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
  3556. break;
  3557. case OP_TCPLISW:
  3558. seq_printf(seq, " csum=%#x", a);
  3559. break;
  3560. case OP_LARGESEND:
  3561. seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
  3562. break;
  3563. case OP_PACKET:
  3564. seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
  3565. break;
  3566. case OP_BUFFER:
  3567. seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
  3568. break;
  3569. default:
  3570. seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
  3571. a, le16_to_cpu(le->length));
  3572. }
  3573. if (le->ctrl & EOP) {
  3574. seq_putc(seq, '\n');
  3575. sop = 1;
  3576. }
  3577. }
  3578. seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
  3579. sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
  3580. sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
  3581. sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
  3582. sky2_read32(hw, B0_Y2_SP_LISR);
  3583. napi_enable(&hw->napi);
  3584. return 0;
  3585. }
  3586. static int sky2_debug_open(struct inode *inode, struct file *file)
  3587. {
  3588. return single_open(file, sky2_debug_show, inode->i_private);
  3589. }
  3590. static const struct file_operations sky2_debug_fops = {
  3591. .owner = THIS_MODULE,
  3592. .open = sky2_debug_open,
  3593. .read = seq_read,
  3594. .llseek = seq_lseek,
  3595. .release = single_release,
  3596. };
  3597. /*
  3598. * Use network device events to create/remove/rename
  3599. * debugfs file entries
  3600. */
  3601. static int sky2_device_event(struct notifier_block *unused,
  3602. unsigned long event, void *ptr)
  3603. {
  3604. struct net_device *dev = ptr;
  3605. struct sky2_port *sky2 = netdev_priv(dev);
  3606. if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
  3607. return NOTIFY_DONE;
  3608. switch (event) {
  3609. case NETDEV_CHANGENAME:
  3610. if (sky2->debugfs) {
  3611. sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
  3612. sky2_debug, dev->name);
  3613. }
  3614. break;
  3615. case NETDEV_GOING_DOWN:
  3616. if (sky2->debugfs) {
  3617. netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
  3618. debugfs_remove(sky2->debugfs);
  3619. sky2->debugfs = NULL;
  3620. }
  3621. break;
  3622. case NETDEV_UP:
  3623. sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
  3624. sky2_debug, dev,
  3625. &sky2_debug_fops);
  3626. if (IS_ERR(sky2->debugfs))
  3627. sky2->debugfs = NULL;
  3628. }
  3629. return NOTIFY_DONE;
  3630. }
  3631. static struct notifier_block sky2_notifier = {
  3632. .notifier_call = sky2_device_event,
  3633. };
  3634. static __init void sky2_debug_init(void)
  3635. {
  3636. struct dentry *ent;
  3637. ent = debugfs_create_dir("sky2", NULL);
  3638. if (!ent || IS_ERR(ent))
  3639. return;
  3640. sky2_debug = ent;
  3641. register_netdevice_notifier(&sky2_notifier);
  3642. }
  3643. static __exit void sky2_debug_cleanup(void)
  3644. {
  3645. if (sky2_debug) {
  3646. unregister_netdevice_notifier(&sky2_notifier);
  3647. debugfs_remove(sky2_debug);
  3648. sky2_debug = NULL;
  3649. }
  3650. }
  3651. #else
  3652. #define sky2_debug_init()
  3653. #define sky2_debug_cleanup()
  3654. #endif
  3655. /* Two copies of network device operations to handle special case of
  3656. not allowing netpoll on second port */
  3657. static const struct net_device_ops sky2_netdev_ops[2] = {
  3658. {
  3659. .ndo_open = sky2_up,
  3660. .ndo_stop = sky2_down,
  3661. .ndo_start_xmit = sky2_xmit_frame,
  3662. .ndo_do_ioctl = sky2_ioctl,
  3663. .ndo_validate_addr = eth_validate_addr,
  3664. .ndo_set_mac_address = sky2_set_mac_address,
  3665. .ndo_set_multicast_list = sky2_set_multicast,
  3666. .ndo_change_mtu = sky2_change_mtu,
  3667. .ndo_tx_timeout = sky2_tx_timeout,
  3668. #ifdef SKY2_VLAN_TAG_USED
  3669. .ndo_vlan_rx_register = sky2_vlan_rx_register,
  3670. #endif
  3671. #ifdef CONFIG_NET_POLL_CONTROLLER
  3672. .ndo_poll_controller = sky2_netpoll,
  3673. #endif
  3674. },
  3675. {
  3676. .ndo_open = sky2_up,
  3677. .ndo_stop = sky2_down,
  3678. .ndo_start_xmit = sky2_xmit_frame,
  3679. .ndo_do_ioctl = sky2_ioctl,
  3680. .ndo_validate_addr = eth_validate_addr,
  3681. .ndo_set_mac_address = sky2_set_mac_address,
  3682. .ndo_set_multicast_list = sky2_set_multicast,
  3683. .ndo_change_mtu = sky2_change_mtu,
  3684. .ndo_tx_timeout = sky2_tx_timeout,
  3685. #ifdef SKY2_VLAN_TAG_USED
  3686. .ndo_vlan_rx_register = sky2_vlan_rx_register,
  3687. #endif
  3688. },
  3689. };
  3690. /* Initialize network device */
  3691. static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
  3692. unsigned port,
  3693. int highmem, int wol)
  3694. {
  3695. struct sky2_port *sky2;
  3696. struct net_device *dev = alloc_etherdev(sizeof(*sky2));
  3697. if (!dev) {
  3698. dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
  3699. return NULL;
  3700. }
  3701. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  3702. dev->irq = hw->pdev->irq;
  3703. SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
  3704. dev->watchdog_timeo = TX_WATCHDOG;
  3705. dev->netdev_ops = &sky2_netdev_ops[port];
  3706. sky2 = netdev_priv(dev);
  3707. sky2->netdev = dev;
  3708. sky2->hw = hw;
  3709. sky2->msg_enable = netif_msg_init(debug, default_msg);
  3710. /* Auto speed and flow control */
  3711. sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
  3712. if (hw->chip_id != CHIP_ID_YUKON_XL)
  3713. sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
  3714. sky2->flow_mode = FC_BOTH;
  3715. sky2->duplex = -1;
  3716. sky2->speed = -1;
  3717. sky2->advertising = sky2_supported_modes(hw);
  3718. sky2->wol = wol;
  3719. spin_lock_init(&sky2->phy_lock);
  3720. sky2->tx_pending = TX_DEF_PENDING;
  3721. sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
  3722. sky2->rx_pending = RX_DEF_PENDING;
  3723. hw->dev[port] = dev;
  3724. sky2->port = port;
  3725. dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
  3726. if (highmem)
  3727. dev->features |= NETIF_F_HIGHDMA;
  3728. /* Enable receive hashing unless hardware is known broken */
  3729. if (!(hw->flags & SKY2_HW_RSS_BROKEN))
  3730. dev->features |= NETIF_F_RXHASH;
  3731. #ifdef SKY2_VLAN_TAG_USED
  3732. /* The workaround for FE+ status conflicts with VLAN tag detection. */
  3733. if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
  3734. sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
  3735. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  3736. }
  3737. #endif
  3738. /* read the mac address */
  3739. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
  3740. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  3741. return dev;
  3742. }
  3743. static void __devinit sky2_show_addr(struct net_device *dev)
  3744. {
  3745. const struct sky2_port *sky2 = netdev_priv(dev);
  3746. netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
  3747. }
  3748. /* Handle software interrupt used during MSI test */
  3749. static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
  3750. {
  3751. struct sky2_hw *hw = dev_id;
  3752. u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  3753. if (status == 0)
  3754. return IRQ_NONE;
  3755. if (status & Y2_IS_IRQ_SW) {
  3756. hw->flags |= SKY2_HW_USE_MSI;
  3757. wake_up(&hw->msi_wait);
  3758. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  3759. }
  3760. sky2_write32(hw, B0_Y2_SP_ICR, 2);
  3761. return IRQ_HANDLED;
  3762. }
  3763. /* Test interrupt path by forcing a a software IRQ */
  3764. static int __devinit sky2_test_msi(struct sky2_hw *hw)
  3765. {
  3766. struct pci_dev *pdev = hw->pdev;
  3767. int err;
  3768. init_waitqueue_head(&hw->msi_wait);
  3769. sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
  3770. err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
  3771. if (err) {
  3772. dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
  3773. return err;
  3774. }
  3775. sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
  3776. sky2_read8(hw, B0_CTST);
  3777. wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
  3778. if (!(hw->flags & SKY2_HW_USE_MSI)) {
  3779. /* MSI test failed, go back to INTx mode */
  3780. dev_info(&pdev->dev, "No interrupt generated using MSI, "
  3781. "switching to INTx mode.\n");
  3782. err = -EOPNOTSUPP;
  3783. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  3784. }
  3785. sky2_write32(hw, B0_IMSK, 0);
  3786. sky2_read32(hw, B0_IMSK);
  3787. free_irq(pdev->irq, hw);
  3788. return err;
  3789. }
  3790. /* This driver supports yukon2 chipset only */
  3791. static const char *sky2_name(u8 chipid, char *buf, int sz)
  3792. {
  3793. const char *name[] = {
  3794. "XL", /* 0xb3 */
  3795. "EC Ultra", /* 0xb4 */
  3796. "Extreme", /* 0xb5 */
  3797. "EC", /* 0xb6 */
  3798. "FE", /* 0xb7 */
  3799. "FE+", /* 0xb8 */
  3800. "Supreme", /* 0xb9 */
  3801. "UL 2", /* 0xba */
  3802. "Unknown", /* 0xbb */
  3803. "Optima", /* 0xbc */
  3804. };
  3805. if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
  3806. strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
  3807. else
  3808. snprintf(buf, sz, "(chip %#x)", chipid);
  3809. return buf;
  3810. }
  3811. static int __devinit sky2_probe(struct pci_dev *pdev,
  3812. const struct pci_device_id *ent)
  3813. {
  3814. struct net_device *dev;
  3815. struct sky2_hw *hw;
  3816. int err, using_dac = 0, wol_default;
  3817. u32 reg;
  3818. char buf1[16];
  3819. err = pci_enable_device(pdev);
  3820. if (err) {
  3821. dev_err(&pdev->dev, "cannot enable PCI device\n");
  3822. goto err_out;
  3823. }
  3824. /* Get configuration information
  3825. * Note: only regular PCI config access once to test for HW issues
  3826. * other PCI access through shared memory for speed and to
  3827. * avoid MMCONFIG problems.
  3828. */
  3829. err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
  3830. if (err) {
  3831. dev_err(&pdev->dev, "PCI read config failed\n");
  3832. goto err_out;
  3833. }
  3834. if (~reg == 0) {
  3835. dev_err(&pdev->dev, "PCI configuration read error\n");
  3836. goto err_out;
  3837. }
  3838. err = pci_request_regions(pdev, DRV_NAME);
  3839. if (err) {
  3840. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  3841. goto err_out_disable;
  3842. }
  3843. pci_set_master(pdev);
  3844. if (sizeof(dma_addr_t) > sizeof(u32) &&
  3845. !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
  3846. using_dac = 1;
  3847. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  3848. if (err < 0) {
  3849. dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
  3850. "for consistent allocations\n");
  3851. goto err_out_free_regions;
  3852. }
  3853. } else {
  3854. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3855. if (err) {
  3856. dev_err(&pdev->dev, "no usable DMA configuration\n");
  3857. goto err_out_free_regions;
  3858. }
  3859. }
  3860. #ifdef __BIG_ENDIAN
  3861. /* The sk98lin vendor driver uses hardware byte swapping but
  3862. * this driver uses software swapping.
  3863. */
  3864. reg &= ~PCI_REV_DESC;
  3865. err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
  3866. if (err) {
  3867. dev_err(&pdev->dev, "PCI write config failed\n");
  3868. goto err_out_free_regions;
  3869. }
  3870. #endif
  3871. wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
  3872. err = -ENOMEM;
  3873. hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
  3874. + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
  3875. if (!hw) {
  3876. dev_err(&pdev->dev, "cannot allocate hardware struct\n");
  3877. goto err_out_free_regions;
  3878. }
  3879. hw->pdev = pdev;
  3880. sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
  3881. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  3882. if (!hw->regs) {
  3883. dev_err(&pdev->dev, "cannot map device registers\n");
  3884. goto err_out_free_hw;
  3885. }
  3886. err = sky2_init(hw);
  3887. if (err)
  3888. goto err_out_iounmap;
  3889. /* ring for status responses */
  3890. hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
  3891. hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
  3892. &hw->st_dma);
  3893. if (!hw->st_le)
  3894. goto err_out_reset;
  3895. dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
  3896. sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
  3897. sky2_reset(hw);
  3898. dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
  3899. if (!dev) {
  3900. err = -ENOMEM;
  3901. goto err_out_free_pci;
  3902. }
  3903. if (!disable_msi && pci_enable_msi(pdev) == 0) {
  3904. err = sky2_test_msi(hw);
  3905. if (err == -EOPNOTSUPP)
  3906. pci_disable_msi(pdev);
  3907. else if (err)
  3908. goto err_out_free_netdev;
  3909. }
  3910. err = register_netdev(dev);
  3911. if (err) {
  3912. dev_err(&pdev->dev, "cannot register net device\n");
  3913. goto err_out_free_netdev;
  3914. }
  3915. netif_carrier_off(dev);
  3916. netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
  3917. err = request_irq(pdev->irq, sky2_intr,
  3918. (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
  3919. hw->irq_name, hw);
  3920. if (err) {
  3921. dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
  3922. goto err_out_unregister;
  3923. }
  3924. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  3925. napi_enable(&hw->napi);
  3926. sky2_show_addr(dev);
  3927. if (hw->ports > 1) {
  3928. struct net_device *dev1;
  3929. err = -ENOMEM;
  3930. dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
  3931. if (dev1 && (err = register_netdev(dev1)) == 0)
  3932. sky2_show_addr(dev1);
  3933. else {
  3934. dev_warn(&pdev->dev,
  3935. "register of second port failed (%d)\n", err);
  3936. hw->dev[1] = NULL;
  3937. hw->ports = 1;
  3938. if (dev1)
  3939. free_netdev(dev1);
  3940. }
  3941. }
  3942. setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
  3943. INIT_WORK(&hw->restart_work, sky2_restart);
  3944. pci_set_drvdata(pdev, hw);
  3945. pdev->d3_delay = 150;
  3946. return 0;
  3947. err_out_unregister:
  3948. if (hw->flags & SKY2_HW_USE_MSI)
  3949. pci_disable_msi(pdev);
  3950. unregister_netdev(dev);
  3951. err_out_free_netdev:
  3952. free_netdev(dev);
  3953. err_out_free_pci:
  3954. pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
  3955. hw->st_le, hw->st_dma);
  3956. err_out_reset:
  3957. sky2_write8(hw, B0_CTST, CS_RST_SET);
  3958. err_out_iounmap:
  3959. iounmap(hw->regs);
  3960. err_out_free_hw:
  3961. kfree(hw);
  3962. err_out_free_regions:
  3963. pci_release_regions(pdev);
  3964. err_out_disable:
  3965. pci_disable_device(pdev);
  3966. err_out:
  3967. pci_set_drvdata(pdev, NULL);
  3968. return err;
  3969. }
  3970. static void __devexit sky2_remove(struct pci_dev *pdev)
  3971. {
  3972. struct sky2_hw *hw = pci_get_drvdata(pdev);
  3973. int i;
  3974. if (!hw)
  3975. return;
  3976. del_timer_sync(&hw->watchdog_timer);
  3977. cancel_work_sync(&hw->restart_work);
  3978. for (i = hw->ports-1; i >= 0; --i)
  3979. unregister_netdev(hw->dev[i]);
  3980. sky2_write32(hw, B0_IMSK, 0);
  3981. sky2_power_aux(hw);
  3982. sky2_write8(hw, B0_CTST, CS_RST_SET);
  3983. sky2_read8(hw, B0_CTST);
  3984. free_irq(pdev->irq, hw);
  3985. if (hw->flags & SKY2_HW_USE_MSI)
  3986. pci_disable_msi(pdev);
  3987. pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
  3988. hw->st_le, hw->st_dma);
  3989. pci_release_regions(pdev);
  3990. pci_disable_device(pdev);
  3991. for (i = hw->ports-1; i >= 0; --i)
  3992. free_netdev(hw->dev[i]);
  3993. iounmap(hw->regs);
  3994. kfree(hw);
  3995. pci_set_drvdata(pdev, NULL);
  3996. }
  3997. static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
  3998. {
  3999. struct sky2_hw *hw = pci_get_drvdata(pdev);
  4000. int i, wol = 0;
  4001. if (!hw)
  4002. return 0;
  4003. del_timer_sync(&hw->watchdog_timer);
  4004. cancel_work_sync(&hw->restart_work);
  4005. rtnl_lock();
  4006. sky2_all_down(hw);
  4007. for (i = 0; i < hw->ports; i++) {
  4008. struct net_device *dev = hw->dev[i];
  4009. struct sky2_port *sky2 = netdev_priv(dev);
  4010. if (sky2->wol)
  4011. sky2_wol_init(sky2);
  4012. wol |= sky2->wol;
  4013. }
  4014. device_set_wakeup_enable(&pdev->dev, wol != 0);
  4015. sky2_power_aux(hw);
  4016. rtnl_unlock();
  4017. pci_save_state(pdev);
  4018. pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
  4019. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  4020. return 0;
  4021. }
  4022. #ifdef CONFIG_PM
  4023. static int sky2_resume(struct pci_dev *pdev)
  4024. {
  4025. struct sky2_hw *hw = pci_get_drvdata(pdev);
  4026. int err;
  4027. if (!hw)
  4028. return 0;
  4029. err = pci_set_power_state(pdev, PCI_D0);
  4030. if (err)
  4031. goto out;
  4032. err = pci_restore_state(pdev);
  4033. if (err)
  4034. goto out;
  4035. pci_enable_wake(pdev, PCI_D0, 0);
  4036. /* Re-enable all clocks */
  4037. err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
  4038. if (err) {
  4039. dev_err(&pdev->dev, "PCI write config failed\n");
  4040. goto out;
  4041. }
  4042. rtnl_lock();
  4043. sky2_reset(hw);
  4044. sky2_all_up(hw);
  4045. rtnl_unlock();
  4046. return 0;
  4047. out:
  4048. dev_err(&pdev->dev, "resume failed (%d)\n", err);
  4049. pci_disable_device(pdev);
  4050. return err;
  4051. }
  4052. #endif
  4053. static void sky2_shutdown(struct pci_dev *pdev)
  4054. {
  4055. sky2_suspend(pdev, PMSG_SUSPEND);
  4056. }
  4057. static struct pci_driver sky2_driver = {
  4058. .name = DRV_NAME,
  4059. .id_table = sky2_id_table,
  4060. .probe = sky2_probe,
  4061. .remove = __devexit_p(sky2_remove),
  4062. #ifdef CONFIG_PM
  4063. .suspend = sky2_suspend,
  4064. .resume = sky2_resume,
  4065. #endif
  4066. .shutdown = sky2_shutdown,
  4067. };
  4068. static int __init sky2_init_module(void)
  4069. {
  4070. pr_info("driver version " DRV_VERSION "\n");
  4071. sky2_debug_init();
  4072. return pci_register_driver(&sky2_driver);
  4073. }
  4074. static void __exit sky2_cleanup_module(void)
  4075. {
  4076. pci_unregister_driver(&sky2_driver);
  4077. sky2_debug_cleanup();
  4078. }
  4079. module_init(sky2_init_module);
  4080. module_exit(sky2_cleanup_module);
  4081. MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
  4082. MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
  4083. MODULE_LICENSE("GPL");
  4084. MODULE_VERSION(DRV_VERSION);