tenxpress.c 24 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2007-2009 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include <linux/rtnetlink.h>
  11. #include <linux/seq_file.h>
  12. #include <linux/slab.h>
  13. #include "efx.h"
  14. #include "mdio_10g.h"
  15. #include "nic.h"
  16. #include "phy.h"
  17. #include "regs.h"
  18. #include "workarounds.h"
  19. #include "selftest.h"
  20. /* We expect these MMDs to be in the package. SFT9001 also has a
  21. * clause 22 extension MMD, but since it doesn't have all the generic
  22. * MMD registers it is pointless to include it here.
  23. */
  24. #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
  25. MDIO_DEVS_PCS | \
  26. MDIO_DEVS_PHYXS | \
  27. MDIO_DEVS_AN)
  28. #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
  29. (1 << LOOPBACK_PCS) | \
  30. (1 << LOOPBACK_PMAPMD) | \
  31. (1 << LOOPBACK_PHYXS_WS))
  32. #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
  33. (1 << LOOPBACK_PHYXS) | \
  34. (1 << LOOPBACK_PCS) | \
  35. (1 << LOOPBACK_PMAPMD) | \
  36. (1 << LOOPBACK_PHYXS_WS))
  37. /* We complain if we fail to see the link partner as 10G capable this many
  38. * times in a row (must be > 1 as sampling the autoneg. registers is racy)
  39. */
  40. #define MAX_BAD_LP_TRIES (5)
  41. /* Extended control register */
  42. #define PMA_PMD_XCONTROL_REG 49152
  43. #define PMA_PMD_EXT_GMII_EN_LBN 1
  44. #define PMA_PMD_EXT_GMII_EN_WIDTH 1
  45. #define PMA_PMD_EXT_CLK_OUT_LBN 2
  46. #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
  47. #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
  48. #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
  49. #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
  50. #define PMA_PMD_EXT_CLK312_WIDTH 1
  51. #define PMA_PMD_EXT_LPOWER_LBN 12
  52. #define PMA_PMD_EXT_LPOWER_WIDTH 1
  53. #define PMA_PMD_EXT_ROBUST_LBN 14
  54. #define PMA_PMD_EXT_ROBUST_WIDTH 1
  55. #define PMA_PMD_EXT_SSR_LBN 15
  56. #define PMA_PMD_EXT_SSR_WIDTH 1
  57. /* extended status register */
  58. #define PMA_PMD_XSTATUS_REG 49153
  59. #define PMA_PMD_XSTAT_MDIX_LBN 14
  60. #define PMA_PMD_XSTAT_FLP_LBN (12)
  61. /* LED control register */
  62. #define PMA_PMD_LED_CTRL_REG 49159
  63. #define PMA_PMA_LED_ACTIVITY_LBN (3)
  64. /* LED function override register */
  65. #define PMA_PMD_LED_OVERR_REG 49161
  66. /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
  67. #define PMA_PMD_LED_LINK_LBN (0)
  68. #define PMA_PMD_LED_SPEED_LBN (2)
  69. #define PMA_PMD_LED_TX_LBN (4)
  70. #define PMA_PMD_LED_RX_LBN (6)
  71. /* Override settings */
  72. #define PMA_PMD_LED_AUTO (0) /* H/W control */
  73. #define PMA_PMD_LED_ON (1)
  74. #define PMA_PMD_LED_OFF (2)
  75. #define PMA_PMD_LED_FLASH (3)
  76. #define PMA_PMD_LED_MASK 3
  77. /* All LEDs under hardware control */
  78. #define SFT9001_PMA_PMD_LED_DEFAULT 0
  79. /* Green and Amber under hardware control, Red off */
  80. #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
  81. #define PMA_PMD_SPEED_ENABLE_REG 49192
  82. #define PMA_PMD_100TX_ADV_LBN 1
  83. #define PMA_PMD_100TX_ADV_WIDTH 1
  84. #define PMA_PMD_1000T_ADV_LBN 2
  85. #define PMA_PMD_1000T_ADV_WIDTH 1
  86. #define PMA_PMD_10000T_ADV_LBN 3
  87. #define PMA_PMD_10000T_ADV_WIDTH 1
  88. #define PMA_PMD_SPEED_LBN 4
  89. #define PMA_PMD_SPEED_WIDTH 4
  90. /* Cable diagnostics - SFT9001 only */
  91. #define PMA_PMD_CDIAG_CTRL_REG 49213
  92. #define CDIAG_CTRL_IMMED_LBN 15
  93. #define CDIAG_CTRL_BRK_LINK_LBN 12
  94. #define CDIAG_CTRL_IN_PROG_LBN 11
  95. #define CDIAG_CTRL_LEN_UNIT_LBN 10
  96. #define CDIAG_CTRL_LEN_METRES 1
  97. #define PMA_PMD_CDIAG_RES_REG 49174
  98. #define CDIAG_RES_A_LBN 12
  99. #define CDIAG_RES_B_LBN 8
  100. #define CDIAG_RES_C_LBN 4
  101. #define CDIAG_RES_D_LBN 0
  102. #define CDIAG_RES_WIDTH 4
  103. #define CDIAG_RES_OPEN 2
  104. #define CDIAG_RES_OK 1
  105. #define CDIAG_RES_INVALID 0
  106. /* Set of 4 registers for pairs A-D */
  107. #define PMA_PMD_CDIAG_LEN_REG 49175
  108. /* Serdes control registers - SFT9001 only */
  109. #define PMA_PMD_CSERDES_CTRL_REG 64258
  110. /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
  111. #define PMA_PMD_CSERDES_DEFAULT 0x000f
  112. /* Misc register defines - SFX7101 only */
  113. #define PCS_CLOCK_CTRL_REG 55297
  114. #define PLL312_RST_N_LBN 2
  115. #define PCS_SOFT_RST2_REG 55302
  116. #define SERDES_RST_N_LBN 13
  117. #define XGXS_RST_N_LBN 12
  118. #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
  119. #define CLK312_EN_LBN 3
  120. /* PHYXS registers */
  121. #define PHYXS_XCONTROL_REG 49152
  122. #define PHYXS_RESET_LBN 15
  123. #define PHYXS_RESET_WIDTH 1
  124. #define PHYXS_TEST1 (49162)
  125. #define LOOPBACK_NEAR_LBN (8)
  126. #define LOOPBACK_NEAR_WIDTH (1)
  127. /* Boot status register */
  128. #define PCS_BOOT_STATUS_REG 53248
  129. #define PCS_BOOT_FATAL_ERROR_LBN 0
  130. #define PCS_BOOT_PROGRESS_LBN 1
  131. #define PCS_BOOT_PROGRESS_WIDTH 2
  132. #define PCS_BOOT_PROGRESS_INIT 0
  133. #define PCS_BOOT_PROGRESS_WAIT_MDIO 1
  134. #define PCS_BOOT_PROGRESS_CHECKSUM 2
  135. #define PCS_BOOT_PROGRESS_JUMP 3
  136. #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
  137. #define PCS_BOOT_CODE_STARTED_LBN 4
  138. /* 100M/1G PHY registers */
  139. #define GPHY_XCONTROL_REG 49152
  140. #define GPHY_ISOLATE_LBN 10
  141. #define GPHY_ISOLATE_WIDTH 1
  142. #define GPHY_DUPLEX_LBN 8
  143. #define GPHY_DUPLEX_WIDTH 1
  144. #define GPHY_LOOPBACK_NEAR_LBN 14
  145. #define GPHY_LOOPBACK_NEAR_WIDTH 1
  146. #define C22EXT_STATUS_REG 49153
  147. #define C22EXT_STATUS_LINK_LBN 2
  148. #define C22EXT_STATUS_LINK_WIDTH 1
  149. #define C22EXT_MSTSLV_CTRL 49161
  150. #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
  151. #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
  152. #define C22EXT_MSTSLV_STATUS 49162
  153. #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
  154. #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
  155. /* Time to wait between powering down the LNPGA and turning off the power
  156. * rails */
  157. #define LNPGA_PDOWN_WAIT (HZ / 5)
  158. struct tenxpress_phy_data {
  159. enum efx_loopback_mode loopback_mode;
  160. enum efx_phy_mode phy_mode;
  161. int bad_lp_tries;
  162. };
  163. static ssize_t show_phy_short_reach(struct device *dev,
  164. struct device_attribute *attr, char *buf)
  165. {
  166. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  167. int reg;
  168. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR);
  169. return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT));
  170. }
  171. static ssize_t set_phy_short_reach(struct device *dev,
  172. struct device_attribute *attr,
  173. const char *buf, size_t count)
  174. {
  175. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  176. int rc;
  177. rtnl_lock();
  178. if (efx->state != STATE_RUNNING) {
  179. rc = -EBUSY;
  180. } else {
  181. efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR,
  182. MDIO_PMA_10GBT_TXPWR_SHORT,
  183. count != 0 && *buf != '0');
  184. rc = efx_reconfigure_port(efx);
  185. }
  186. rtnl_unlock();
  187. return rc < 0 ? rc : (ssize_t)count;
  188. }
  189. static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
  190. set_phy_short_reach);
  191. int sft9001_wait_boot(struct efx_nic *efx)
  192. {
  193. unsigned long timeout = jiffies + HZ + 1;
  194. int boot_stat;
  195. for (;;) {
  196. boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS,
  197. PCS_BOOT_STATUS_REG);
  198. if (boot_stat >= 0) {
  199. netif_dbg(efx, hw, efx->net_dev,
  200. "PHY boot status = %#x\n", boot_stat);
  201. switch (boot_stat &
  202. ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
  203. (3 << PCS_BOOT_PROGRESS_LBN) |
  204. (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) |
  205. (1 << PCS_BOOT_CODE_STARTED_LBN))) {
  206. case ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
  207. (PCS_BOOT_PROGRESS_CHECKSUM <<
  208. PCS_BOOT_PROGRESS_LBN)):
  209. case ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
  210. (PCS_BOOT_PROGRESS_INIT <<
  211. PCS_BOOT_PROGRESS_LBN) |
  212. (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)):
  213. return -EINVAL;
  214. case ((PCS_BOOT_PROGRESS_WAIT_MDIO <<
  215. PCS_BOOT_PROGRESS_LBN) |
  216. (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)):
  217. return (efx->phy_mode & PHY_MODE_SPECIAL) ?
  218. 0 : -EIO;
  219. case ((PCS_BOOT_PROGRESS_JUMP <<
  220. PCS_BOOT_PROGRESS_LBN) |
  221. (1 << PCS_BOOT_CODE_STARTED_LBN)):
  222. case ((PCS_BOOT_PROGRESS_JUMP <<
  223. PCS_BOOT_PROGRESS_LBN) |
  224. (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) |
  225. (1 << PCS_BOOT_CODE_STARTED_LBN)):
  226. return (efx->phy_mode & PHY_MODE_SPECIAL) ?
  227. -EIO : 0;
  228. default:
  229. if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN))
  230. return -EIO;
  231. break;
  232. }
  233. }
  234. if (time_after_eq(jiffies, timeout))
  235. return -ETIMEDOUT;
  236. msleep(50);
  237. }
  238. }
  239. static int tenxpress_init(struct efx_nic *efx)
  240. {
  241. int reg;
  242. if (efx->phy_type == PHY_TYPE_SFX7101) {
  243. /* Enable 312.5 MHz clock */
  244. efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
  245. 1 << CLK312_EN_LBN);
  246. } else {
  247. /* Enable 312.5 MHz clock and GMII */
  248. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
  249. reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
  250. (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
  251. (1 << PMA_PMD_EXT_CLK312_LBN) |
  252. (1 << PMA_PMD_EXT_ROBUST_LBN));
  253. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
  254. efx_mdio_set_flag(efx, MDIO_MMD_C22EXT,
  255. GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN,
  256. false);
  257. }
  258. /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
  259. if (efx->phy_type == PHY_TYPE_SFX7101) {
  260. efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
  261. 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
  262. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
  263. SFX7101_PMA_PMD_LED_DEFAULT);
  264. }
  265. return 0;
  266. }
  267. static int tenxpress_phy_probe(struct efx_nic *efx)
  268. {
  269. struct tenxpress_phy_data *phy_data;
  270. int rc;
  271. /* Allocate phy private storage */
  272. phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
  273. if (!phy_data)
  274. return -ENOMEM;
  275. efx->phy_data = phy_data;
  276. phy_data->phy_mode = efx->phy_mode;
  277. /* Create any special files */
  278. if (efx->phy_type == PHY_TYPE_SFT9001B) {
  279. rc = device_create_file(&efx->pci_dev->dev,
  280. &dev_attr_phy_short_reach);
  281. if (rc)
  282. goto fail;
  283. }
  284. if (efx->phy_type == PHY_TYPE_SFX7101) {
  285. efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
  286. efx->mdio.mode_support = MDIO_SUPPORTS_C45;
  287. efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
  288. efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
  289. ADVERTISED_10000baseT_Full);
  290. } else {
  291. efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
  292. efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
  293. efx->loopback_modes = (SFT9001_LOOPBACKS |
  294. FALCON_XMAC_LOOPBACKS |
  295. FALCON_GMAC_LOOPBACKS);
  296. efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
  297. ADVERTISED_10000baseT_Full |
  298. ADVERTISED_1000baseT_Full |
  299. ADVERTISED_100baseT_Full);
  300. }
  301. return 0;
  302. fail:
  303. kfree(efx->phy_data);
  304. efx->phy_data = NULL;
  305. return rc;
  306. }
  307. static int tenxpress_phy_init(struct efx_nic *efx)
  308. {
  309. int rc;
  310. falcon_board(efx)->type->init_phy(efx);
  311. if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
  312. if (efx->phy_type == PHY_TYPE_SFT9001A) {
  313. int reg;
  314. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
  315. PMA_PMD_XCONTROL_REG);
  316. reg |= (1 << PMA_PMD_EXT_SSR_LBN);
  317. efx_mdio_write(efx, MDIO_MMD_PMAPMD,
  318. PMA_PMD_XCONTROL_REG, reg);
  319. mdelay(200);
  320. }
  321. rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
  322. if (rc < 0)
  323. return rc;
  324. rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
  325. if (rc < 0)
  326. return rc;
  327. }
  328. rc = tenxpress_init(efx);
  329. if (rc < 0)
  330. return rc;
  331. /* Reinitialise flow control settings */
  332. efx_link_set_wanted_fc(efx, efx->wanted_fc);
  333. efx_mdio_an_reconfigure(efx);
  334. schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
  335. /* Let XGXS and SerDes out of reset */
  336. falcon_reset_xaui(efx);
  337. return 0;
  338. }
  339. /* Perform a "special software reset" on the PHY. The caller is
  340. * responsible for saving and restoring the PHY hardware registers
  341. * properly, and masking/unmasking LASI */
  342. static int tenxpress_special_reset(struct efx_nic *efx)
  343. {
  344. int rc, reg;
  345. /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
  346. * a special software reset can glitch the XGMAC sufficiently for stats
  347. * requests to fail. */
  348. falcon_stop_nic_stats(efx);
  349. /* Initiate reset */
  350. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
  351. reg |= (1 << PMA_PMD_EXT_SSR_LBN);
  352. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
  353. mdelay(200);
  354. /* Wait for the blocks to come out of reset */
  355. rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
  356. if (rc < 0)
  357. goto out;
  358. /* Try and reconfigure the device */
  359. rc = tenxpress_init(efx);
  360. if (rc < 0)
  361. goto out;
  362. /* Wait for the XGXS state machine to churn */
  363. mdelay(10);
  364. out:
  365. falcon_start_nic_stats(efx);
  366. return rc;
  367. }
  368. static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
  369. {
  370. struct tenxpress_phy_data *pd = efx->phy_data;
  371. bool bad_lp;
  372. int reg;
  373. if (link_ok) {
  374. bad_lp = false;
  375. } else {
  376. /* Check that AN has started but not completed. */
  377. reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
  378. if (!(reg & MDIO_AN_STAT1_LPABLE))
  379. return; /* LP status is unknown */
  380. bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
  381. if (bad_lp)
  382. pd->bad_lp_tries++;
  383. }
  384. /* Nothing to do if all is well and was previously so. */
  385. if (!pd->bad_lp_tries)
  386. return;
  387. /* Use the RX (red) LED as an error indicator once we've seen AN
  388. * failure several times in a row, and also log a message. */
  389. if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
  390. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
  391. PMA_PMD_LED_OVERR_REG);
  392. reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
  393. if (!bad_lp) {
  394. reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
  395. } else {
  396. reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
  397. netif_err(efx, link, efx->net_dev,
  398. "appears to be plugged into a port"
  399. " that is not 10GBASE-T capable. The PHY"
  400. " supports 10GBASE-T ONLY, so no link can"
  401. " be established\n");
  402. }
  403. efx_mdio_write(efx, MDIO_MMD_PMAPMD,
  404. PMA_PMD_LED_OVERR_REG, reg);
  405. pd->bad_lp_tries = bad_lp;
  406. }
  407. }
  408. static bool sfx7101_link_ok(struct efx_nic *efx)
  409. {
  410. return efx_mdio_links_ok(efx,
  411. MDIO_DEVS_PMAPMD |
  412. MDIO_DEVS_PCS |
  413. MDIO_DEVS_PHYXS);
  414. }
  415. static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
  416. {
  417. u32 reg;
  418. if (efx_phy_mode_disabled(efx->phy_mode))
  419. return false;
  420. else if (efx->loopback_mode == LOOPBACK_GPHY)
  421. return true;
  422. else if (efx->loopback_mode)
  423. return efx_mdio_links_ok(efx,
  424. MDIO_DEVS_PMAPMD |
  425. MDIO_DEVS_PHYXS);
  426. /* We must use the same definition of link state as LASI,
  427. * otherwise we can miss a link state transition
  428. */
  429. if (ecmd->speed == 10000) {
  430. reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
  431. return reg & MDIO_PCS_10GBRT_STAT1_BLKLK;
  432. } else {
  433. reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG);
  434. return reg & (1 << C22EXT_STATUS_LINK_LBN);
  435. }
  436. }
  437. static void tenxpress_ext_loopback(struct efx_nic *efx)
  438. {
  439. efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
  440. 1 << LOOPBACK_NEAR_LBN,
  441. efx->loopback_mode == LOOPBACK_PHYXS);
  442. if (efx->phy_type != PHY_TYPE_SFX7101)
  443. efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG,
  444. 1 << GPHY_LOOPBACK_NEAR_LBN,
  445. efx->loopback_mode == LOOPBACK_GPHY);
  446. }
  447. static void tenxpress_low_power(struct efx_nic *efx)
  448. {
  449. if (efx->phy_type == PHY_TYPE_SFX7101)
  450. efx_mdio_set_mmds_lpower(
  451. efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
  452. TENXPRESS_REQUIRED_DEVS);
  453. else
  454. efx_mdio_set_flag(
  455. efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG,
  456. 1 << PMA_PMD_EXT_LPOWER_LBN,
  457. !!(efx->phy_mode & PHY_MODE_LOW_POWER));
  458. }
  459. static int tenxpress_phy_reconfigure(struct efx_nic *efx)
  460. {
  461. struct tenxpress_phy_data *phy_data = efx->phy_data;
  462. bool phy_mode_change, loop_reset;
  463. if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
  464. phy_data->phy_mode = efx->phy_mode;
  465. return 0;
  466. }
  467. phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
  468. phy_data->phy_mode != PHY_MODE_NORMAL);
  469. loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
  470. LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
  471. if (loop_reset || phy_mode_change) {
  472. tenxpress_special_reset(efx);
  473. /* Reset XAUI if we were in 10G, and are staying
  474. * in 10G. If we're moving into and out of 10G
  475. * then xaui will be reset anyway */
  476. if (EFX_IS10G(efx))
  477. falcon_reset_xaui(efx);
  478. }
  479. tenxpress_low_power(efx);
  480. efx_mdio_transmit_disable(efx);
  481. efx_mdio_phy_reconfigure(efx);
  482. tenxpress_ext_loopback(efx);
  483. efx_mdio_an_reconfigure(efx);
  484. phy_data->loopback_mode = efx->loopback_mode;
  485. phy_data->phy_mode = efx->phy_mode;
  486. return 0;
  487. }
  488. static void
  489. tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);
  490. /* Poll for link state changes */
  491. static bool tenxpress_phy_poll(struct efx_nic *efx)
  492. {
  493. struct efx_link_state old_state = efx->link_state;
  494. if (efx->phy_type == PHY_TYPE_SFX7101) {
  495. efx->link_state.up = sfx7101_link_ok(efx);
  496. efx->link_state.speed = 10000;
  497. efx->link_state.fd = true;
  498. efx->link_state.fc = efx_mdio_get_pause(efx);
  499. sfx7101_check_bad_lp(efx, efx->link_state.up);
  500. } else {
  501. struct ethtool_cmd ecmd;
  502. /* Check the LASI alarm first */
  503. if (efx->loopback_mode == LOOPBACK_NONE &&
  504. !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) &
  505. MDIO_PMA_LASI_LSALARM))
  506. return false;
  507. tenxpress_get_settings(efx, &ecmd);
  508. efx->link_state.up = sft9001_link_ok(efx, &ecmd);
  509. efx->link_state.speed = ecmd.speed;
  510. efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL);
  511. efx->link_state.fc = efx_mdio_get_pause(efx);
  512. }
  513. return !efx_link_state_equal(&efx->link_state, &old_state);
  514. }
  515. static void sfx7101_phy_fini(struct efx_nic *efx)
  516. {
  517. int reg;
  518. /* Power down the LNPGA */
  519. reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
  520. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
  521. /* Waiting here ensures that the board fini, which can turn
  522. * off the power to the PHY, won't get run until the LNPGA
  523. * powerdown has been given long enough to complete. */
  524. schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
  525. }
  526. static void tenxpress_phy_remove(struct efx_nic *efx)
  527. {
  528. if (efx->phy_type == PHY_TYPE_SFT9001B)
  529. device_remove_file(&efx->pci_dev->dev,
  530. &dev_attr_phy_short_reach);
  531. kfree(efx->phy_data);
  532. efx->phy_data = NULL;
  533. }
  534. /* Override the RX, TX and link LEDs */
  535. void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  536. {
  537. int reg;
  538. switch (mode) {
  539. case EFX_LED_OFF:
  540. reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
  541. (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
  542. (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
  543. break;
  544. case EFX_LED_ON:
  545. reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
  546. (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
  547. (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
  548. break;
  549. default:
  550. if (efx->phy_type == PHY_TYPE_SFX7101)
  551. reg = SFX7101_PMA_PMD_LED_DEFAULT;
  552. else
  553. reg = SFT9001_PMA_PMD_LED_DEFAULT;
  554. break;
  555. }
  556. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
  557. }
  558. static const char *const sfx7101_test_names[] = {
  559. "bist"
  560. };
  561. static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index)
  562. {
  563. if (index < ARRAY_SIZE(sfx7101_test_names))
  564. return sfx7101_test_names[index];
  565. return NULL;
  566. }
  567. static int
  568. sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
  569. {
  570. int rc;
  571. if (!(flags & ETH_TEST_FL_OFFLINE))
  572. return 0;
  573. /* BIST is automatically run after a special software reset */
  574. rc = tenxpress_special_reset(efx);
  575. results[0] = rc ? -1 : 1;
  576. efx_mdio_an_reconfigure(efx);
  577. return rc;
  578. }
  579. static const char *const sft9001_test_names[] = {
  580. "bist",
  581. "cable.pairA.status",
  582. "cable.pairB.status",
  583. "cable.pairC.status",
  584. "cable.pairD.status",
  585. "cable.pairA.length",
  586. "cable.pairB.length",
  587. "cable.pairC.length",
  588. "cable.pairD.length",
  589. };
  590. static const char *sft9001_test_name(struct efx_nic *efx, unsigned int index)
  591. {
  592. if (index < ARRAY_SIZE(sft9001_test_names))
  593. return sft9001_test_names[index];
  594. return NULL;
  595. }
  596. static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
  597. {
  598. int rc = 0, rc2, i, ctrl_reg, res_reg;
  599. /* Initialise cable diagnostic results to unknown failure */
  600. for (i = 1; i < 9; ++i)
  601. results[i] = -1;
  602. /* Run cable diagnostics; wait up to 5 seconds for them to complete.
  603. * A cable fault is not a self-test failure, but a timeout is. */
  604. ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) |
  605. (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
  606. if (flags & ETH_TEST_FL_OFFLINE) {
  607. /* Break the link in order to run full diagnostics. We
  608. * must reset the PHY to resume normal service. */
  609. ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN);
  610. }
  611. efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG,
  612. ctrl_reg);
  613. i = 0;
  614. while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) &
  615. (1 << CDIAG_CTRL_IN_PROG_LBN)) {
  616. if (++i == 50) {
  617. rc = -ETIMEDOUT;
  618. goto out;
  619. }
  620. msleep(100);
  621. }
  622. res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG);
  623. for (i = 0; i < 4; i++) {
  624. int pair_res =
  625. (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
  626. & ((1 << CDIAG_RES_WIDTH) - 1);
  627. int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
  628. PMA_PMD_CDIAG_LEN_REG + i);
  629. if (pair_res == CDIAG_RES_OK)
  630. results[1 + i] = 1;
  631. else if (pair_res == CDIAG_RES_INVALID)
  632. results[1 + i] = -1;
  633. else
  634. results[1 + i] = -pair_res;
  635. if (pair_res != CDIAG_RES_INVALID &&
  636. pair_res != CDIAG_RES_OPEN &&
  637. len_reg != 0xffff)
  638. results[5 + i] = len_reg;
  639. }
  640. out:
  641. if (flags & ETH_TEST_FL_OFFLINE) {
  642. /* Reset, running the BIST and then resuming normal service. */
  643. rc2 = tenxpress_special_reset(efx);
  644. results[0] = rc2 ? -1 : 1;
  645. if (!rc)
  646. rc = rc2;
  647. efx_mdio_an_reconfigure(efx);
  648. }
  649. return rc;
  650. }
  651. static void
  652. tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
  653. {
  654. u32 adv = 0, lpa = 0;
  655. int reg;
  656. if (efx->phy_type != PHY_TYPE_SFX7101) {
  657. reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL);
  658. if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN))
  659. adv |= ADVERTISED_1000baseT_Full;
  660. reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS);
  661. if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN))
  662. lpa |= ADVERTISED_1000baseT_Half;
  663. if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN))
  664. lpa |= ADVERTISED_1000baseT_Full;
  665. }
  666. reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
  667. if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
  668. adv |= ADVERTISED_10000baseT_Full;
  669. reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
  670. if (reg & MDIO_AN_10GBT_STAT_LP10G)
  671. lpa |= ADVERTISED_10000baseT_Full;
  672. mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
  673. if (efx->phy_type != PHY_TYPE_SFX7101) {
  674. ecmd->supported |= (SUPPORTED_100baseT_Full |
  675. SUPPORTED_1000baseT_Full);
  676. if (ecmd->speed != SPEED_10000) {
  677. ecmd->eth_tp_mdix =
  678. (efx_mdio_read(efx, MDIO_MMD_PMAPMD,
  679. PMA_PMD_XSTATUS_REG) &
  680. (1 << PMA_PMD_XSTAT_MDIX_LBN))
  681. ? ETH_TP_MDI_X : ETH_TP_MDI;
  682. }
  683. }
  684. /* In loopback, the PHY automatically brings up the correct interface,
  685. * but doesn't advertise the correct speed. So override it */
  686. if (efx->loopback_mode == LOOPBACK_GPHY)
  687. ecmd->speed = SPEED_1000;
  688. else if (LOOPBACK_EXTERNAL(efx))
  689. ecmd->speed = SPEED_10000;
  690. }
  691. static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
  692. {
  693. if (!ecmd->autoneg)
  694. return -EINVAL;
  695. return efx_mdio_set_settings(efx, ecmd);
  696. }
  697. static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
  698. {
  699. efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
  700. MDIO_AN_10GBT_CTRL_ADV10G,
  701. advertising & ADVERTISED_10000baseT_Full);
  702. }
  703. static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising)
  704. {
  705. efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL,
  706. 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN,
  707. advertising & ADVERTISED_1000baseT_Full);
  708. efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
  709. MDIO_AN_10GBT_CTRL_ADV10G,
  710. advertising & ADVERTISED_10000baseT_Full);
  711. }
  712. struct efx_phy_operations falcon_sfx7101_phy_ops = {
  713. .probe = tenxpress_phy_probe,
  714. .init = tenxpress_phy_init,
  715. .reconfigure = tenxpress_phy_reconfigure,
  716. .poll = tenxpress_phy_poll,
  717. .fini = sfx7101_phy_fini,
  718. .remove = tenxpress_phy_remove,
  719. .get_settings = tenxpress_get_settings,
  720. .set_settings = tenxpress_set_settings,
  721. .set_npage_adv = sfx7101_set_npage_adv,
  722. .test_alive = efx_mdio_test_alive,
  723. .test_name = sfx7101_test_name,
  724. .run_tests = sfx7101_run_tests,
  725. };
  726. struct efx_phy_operations falcon_sft9001_phy_ops = {
  727. .probe = tenxpress_phy_probe,
  728. .init = tenxpress_phy_init,
  729. .reconfigure = tenxpress_phy_reconfigure,
  730. .poll = tenxpress_phy_poll,
  731. .fini = efx_port_dummy_op_void,
  732. .remove = tenxpress_phy_remove,
  733. .get_settings = tenxpress_get_settings,
  734. .set_settings = tenxpress_set_settings,
  735. .set_npage_adv = sft9001_set_npage_adv,
  736. .test_alive = efx_mdio_test_alive,
  737. .test_name = sft9001_test_name,
  738. .run_tests = sft9001_run_tests,
  739. };