qlcnic_init.c 41 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include <linux/netdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include "qlcnic.h"
  28. struct crb_addr_pair {
  29. u32 addr;
  30. u32 data;
  31. };
  32. #define QLCNIC_MAX_CRB_XFORM 60
  33. static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
  34. #define crb_addr_transform(name) \
  35. (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
  36. QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
  37. #define QLCNIC_ADDR_ERROR (0xffffffff)
  38. static void
  39. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  40. struct qlcnic_host_rds_ring *rds_ring);
  41. static void crb_addr_transform_setup(void)
  42. {
  43. crb_addr_transform(XDMA);
  44. crb_addr_transform(TIMR);
  45. crb_addr_transform(SRE);
  46. crb_addr_transform(SQN3);
  47. crb_addr_transform(SQN2);
  48. crb_addr_transform(SQN1);
  49. crb_addr_transform(SQN0);
  50. crb_addr_transform(SQS3);
  51. crb_addr_transform(SQS2);
  52. crb_addr_transform(SQS1);
  53. crb_addr_transform(SQS0);
  54. crb_addr_transform(RPMX7);
  55. crb_addr_transform(RPMX6);
  56. crb_addr_transform(RPMX5);
  57. crb_addr_transform(RPMX4);
  58. crb_addr_transform(RPMX3);
  59. crb_addr_transform(RPMX2);
  60. crb_addr_transform(RPMX1);
  61. crb_addr_transform(RPMX0);
  62. crb_addr_transform(ROMUSB);
  63. crb_addr_transform(SN);
  64. crb_addr_transform(QMN);
  65. crb_addr_transform(QMS);
  66. crb_addr_transform(PGNI);
  67. crb_addr_transform(PGND);
  68. crb_addr_transform(PGN3);
  69. crb_addr_transform(PGN2);
  70. crb_addr_transform(PGN1);
  71. crb_addr_transform(PGN0);
  72. crb_addr_transform(PGSI);
  73. crb_addr_transform(PGSD);
  74. crb_addr_transform(PGS3);
  75. crb_addr_transform(PGS2);
  76. crb_addr_transform(PGS1);
  77. crb_addr_transform(PGS0);
  78. crb_addr_transform(PS);
  79. crb_addr_transform(PH);
  80. crb_addr_transform(NIU);
  81. crb_addr_transform(I2Q);
  82. crb_addr_transform(EG);
  83. crb_addr_transform(MN);
  84. crb_addr_transform(MS);
  85. crb_addr_transform(CAS2);
  86. crb_addr_transform(CAS1);
  87. crb_addr_transform(CAS0);
  88. crb_addr_transform(CAM);
  89. crb_addr_transform(C2C1);
  90. crb_addr_transform(C2C0);
  91. crb_addr_transform(SMB);
  92. crb_addr_transform(OCM0);
  93. crb_addr_transform(I2C0);
  94. }
  95. void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
  96. {
  97. struct qlcnic_recv_context *recv_ctx;
  98. struct qlcnic_host_rds_ring *rds_ring;
  99. struct qlcnic_rx_buffer *rx_buf;
  100. int i, ring;
  101. recv_ctx = &adapter->recv_ctx;
  102. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  103. rds_ring = &recv_ctx->rds_rings[ring];
  104. for (i = 0; i < rds_ring->num_desc; ++i) {
  105. rx_buf = &(rds_ring->rx_buf_arr[i]);
  106. if (rx_buf->skb == NULL)
  107. continue;
  108. pci_unmap_single(adapter->pdev,
  109. rx_buf->dma,
  110. rds_ring->dma_size,
  111. PCI_DMA_FROMDEVICE);
  112. dev_kfree_skb_any(rx_buf->skb);
  113. }
  114. }
  115. }
  116. void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter)
  117. {
  118. struct qlcnic_recv_context *recv_ctx;
  119. struct qlcnic_host_rds_ring *rds_ring;
  120. struct qlcnic_rx_buffer *rx_buf;
  121. int i, ring;
  122. recv_ctx = &adapter->recv_ctx;
  123. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  124. rds_ring = &recv_ctx->rds_rings[ring];
  125. spin_lock(&rds_ring->lock);
  126. INIT_LIST_HEAD(&rds_ring->free_list);
  127. rx_buf = rds_ring->rx_buf_arr;
  128. for (i = 0; i < rds_ring->num_desc; i++) {
  129. list_add_tail(&rx_buf->list,
  130. &rds_ring->free_list);
  131. rx_buf++;
  132. }
  133. spin_unlock(&rds_ring->lock);
  134. }
  135. }
  136. void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
  137. {
  138. struct qlcnic_cmd_buffer *cmd_buf;
  139. struct qlcnic_skb_frag *buffrag;
  140. int i, j;
  141. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  142. cmd_buf = tx_ring->cmd_buf_arr;
  143. for (i = 0; i < tx_ring->num_desc; i++) {
  144. buffrag = cmd_buf->frag_array;
  145. if (buffrag->dma) {
  146. pci_unmap_single(adapter->pdev, buffrag->dma,
  147. buffrag->length, PCI_DMA_TODEVICE);
  148. buffrag->dma = 0ULL;
  149. }
  150. for (j = 0; j < cmd_buf->frag_count; j++) {
  151. buffrag++;
  152. if (buffrag->dma) {
  153. pci_unmap_page(adapter->pdev, buffrag->dma,
  154. buffrag->length,
  155. PCI_DMA_TODEVICE);
  156. buffrag->dma = 0ULL;
  157. }
  158. }
  159. if (cmd_buf->skb) {
  160. dev_kfree_skb_any(cmd_buf->skb);
  161. cmd_buf->skb = NULL;
  162. }
  163. cmd_buf++;
  164. }
  165. }
  166. void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
  167. {
  168. struct qlcnic_recv_context *recv_ctx;
  169. struct qlcnic_host_rds_ring *rds_ring;
  170. struct qlcnic_host_tx_ring *tx_ring;
  171. int ring;
  172. recv_ctx = &adapter->recv_ctx;
  173. if (recv_ctx->rds_rings == NULL)
  174. goto skip_rds;
  175. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  176. rds_ring = &recv_ctx->rds_rings[ring];
  177. vfree(rds_ring->rx_buf_arr);
  178. rds_ring->rx_buf_arr = NULL;
  179. }
  180. kfree(recv_ctx->rds_rings);
  181. skip_rds:
  182. if (adapter->tx_ring == NULL)
  183. return;
  184. tx_ring = adapter->tx_ring;
  185. vfree(tx_ring->cmd_buf_arr);
  186. tx_ring->cmd_buf_arr = NULL;
  187. kfree(adapter->tx_ring);
  188. adapter->tx_ring = NULL;
  189. }
  190. int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
  191. {
  192. struct qlcnic_recv_context *recv_ctx;
  193. struct qlcnic_host_rds_ring *rds_ring;
  194. struct qlcnic_host_sds_ring *sds_ring;
  195. struct qlcnic_host_tx_ring *tx_ring;
  196. struct qlcnic_rx_buffer *rx_buf;
  197. int ring, i, size;
  198. struct qlcnic_cmd_buffer *cmd_buf_arr;
  199. struct net_device *netdev = adapter->netdev;
  200. size = sizeof(struct qlcnic_host_tx_ring);
  201. tx_ring = kzalloc(size, GFP_KERNEL);
  202. if (tx_ring == NULL) {
  203. dev_err(&netdev->dev, "failed to allocate tx ring struct\n");
  204. return -ENOMEM;
  205. }
  206. adapter->tx_ring = tx_ring;
  207. tx_ring->num_desc = adapter->num_txd;
  208. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  209. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  210. if (cmd_buf_arr == NULL) {
  211. dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
  212. goto err_out;
  213. }
  214. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  215. tx_ring->cmd_buf_arr = cmd_buf_arr;
  216. recv_ctx = &adapter->recv_ctx;
  217. size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
  218. rds_ring = kzalloc(size, GFP_KERNEL);
  219. if (rds_ring == NULL) {
  220. dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
  221. goto err_out;
  222. }
  223. recv_ctx->rds_rings = rds_ring;
  224. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  225. rds_ring = &recv_ctx->rds_rings[ring];
  226. switch (ring) {
  227. case RCV_RING_NORMAL:
  228. rds_ring->num_desc = adapter->num_rxd;
  229. rds_ring->dma_size = QLCNIC_P3_RX_BUF_MAX_LEN;
  230. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  231. break;
  232. case RCV_RING_JUMBO:
  233. rds_ring->num_desc = adapter->num_jumbo_rxd;
  234. rds_ring->dma_size =
  235. QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN;
  236. if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
  237. rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
  238. rds_ring->skb_size =
  239. rds_ring->dma_size + NET_IP_ALIGN;
  240. break;
  241. }
  242. rds_ring->rx_buf_arr = (struct qlcnic_rx_buffer *)
  243. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  244. if (rds_ring->rx_buf_arr == NULL) {
  245. dev_err(&netdev->dev, "Failed to allocate "
  246. "rx buffer ring %d\n", ring);
  247. goto err_out;
  248. }
  249. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  250. INIT_LIST_HEAD(&rds_ring->free_list);
  251. /*
  252. * Now go through all of them, set reference handles
  253. * and put them in the queues.
  254. */
  255. rx_buf = rds_ring->rx_buf_arr;
  256. for (i = 0; i < rds_ring->num_desc; i++) {
  257. list_add_tail(&rx_buf->list,
  258. &rds_ring->free_list);
  259. rx_buf->ref_handle = i;
  260. rx_buf++;
  261. }
  262. spin_lock_init(&rds_ring->lock);
  263. }
  264. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  265. sds_ring = &recv_ctx->sds_rings[ring];
  266. sds_ring->irq = adapter->msix_entries[ring].vector;
  267. sds_ring->adapter = adapter;
  268. sds_ring->num_desc = adapter->num_rxd;
  269. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  270. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  271. }
  272. return 0;
  273. err_out:
  274. qlcnic_free_sw_resources(adapter);
  275. return -ENOMEM;
  276. }
  277. /*
  278. * Utility to translate from internal Phantom CRB address
  279. * to external PCI CRB address.
  280. */
  281. static u32 qlcnic_decode_crb_addr(u32 addr)
  282. {
  283. int i;
  284. u32 base_addr, offset, pci_base;
  285. crb_addr_transform_setup();
  286. pci_base = QLCNIC_ADDR_ERROR;
  287. base_addr = addr & 0xfff00000;
  288. offset = addr & 0x000fffff;
  289. for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
  290. if (crb_addr_xform[i] == base_addr) {
  291. pci_base = i << 20;
  292. break;
  293. }
  294. }
  295. if (pci_base == QLCNIC_ADDR_ERROR)
  296. return pci_base;
  297. else
  298. return pci_base + offset;
  299. }
  300. #define QLCNIC_MAX_ROM_WAIT_USEC 100
  301. static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
  302. {
  303. long timeout = 0;
  304. long done = 0;
  305. cond_resched();
  306. while (done == 0) {
  307. done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
  308. done &= 2;
  309. if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
  310. dev_err(&adapter->pdev->dev,
  311. "Timeout reached waiting for rom done");
  312. return -EIO;
  313. }
  314. udelay(1);
  315. }
  316. return 0;
  317. }
  318. static int do_rom_fast_read(struct qlcnic_adapter *adapter,
  319. int addr, int *valp)
  320. {
  321. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
  322. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  323. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
  324. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  325. if (qlcnic_wait_rom_done(adapter)) {
  326. dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
  327. return -EIO;
  328. }
  329. /* reset abyte_cnt and dummy_byte_cnt */
  330. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
  331. udelay(10);
  332. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  333. *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
  334. return 0;
  335. }
  336. static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  337. u8 *bytes, size_t size)
  338. {
  339. int addridx;
  340. int ret = 0;
  341. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  342. int v;
  343. ret = do_rom_fast_read(adapter, addridx, &v);
  344. if (ret != 0)
  345. break;
  346. *(__le32 *)bytes = cpu_to_le32(v);
  347. bytes += 4;
  348. }
  349. return ret;
  350. }
  351. int
  352. qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  353. u8 *bytes, size_t size)
  354. {
  355. int ret;
  356. ret = qlcnic_rom_lock(adapter);
  357. if (ret < 0)
  358. return ret;
  359. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  360. qlcnic_rom_unlock(adapter);
  361. return ret;
  362. }
  363. int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp)
  364. {
  365. int ret;
  366. if (qlcnic_rom_lock(adapter) != 0)
  367. return -EIO;
  368. ret = do_rom_fast_read(adapter, addr, valp);
  369. qlcnic_rom_unlock(adapter);
  370. return ret;
  371. }
  372. int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
  373. {
  374. int addr, val;
  375. int i, n, init_delay;
  376. struct crb_addr_pair *buf;
  377. unsigned offset;
  378. u32 off;
  379. struct pci_dev *pdev = adapter->pdev;
  380. /* resetall */
  381. qlcnic_rom_lock(adapter);
  382. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  383. qlcnic_rom_unlock(adapter);
  384. if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
  385. qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
  386. dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
  387. return -EIO;
  388. }
  389. offset = n & 0xffffU;
  390. n = (n >> 16) & 0xffffU;
  391. if (n >= 1024) {
  392. dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
  393. return -EIO;
  394. }
  395. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  396. if (buf == NULL) {
  397. dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
  398. return -ENOMEM;
  399. }
  400. for (i = 0; i < n; i++) {
  401. if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  402. qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  403. kfree(buf);
  404. return -EIO;
  405. }
  406. buf[i].addr = addr;
  407. buf[i].data = val;
  408. }
  409. for (i = 0; i < n; i++) {
  410. off = qlcnic_decode_crb_addr(buf[i].addr);
  411. if (off == QLCNIC_ADDR_ERROR) {
  412. dev_err(&pdev->dev, "CRB init value out of range %x\n",
  413. buf[i].addr);
  414. continue;
  415. }
  416. off += QLCNIC_PCI_CRBSPACE;
  417. if (off & 1)
  418. continue;
  419. /* skipping cold reboot MAGIC */
  420. if (off == QLCNIC_CAM_RAM(0x1fc))
  421. continue;
  422. if (off == (QLCNIC_CRB_I2C0 + 0x1c))
  423. continue;
  424. if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
  425. continue;
  426. if (off == (ROMUSB_GLB + 0xa8))
  427. continue;
  428. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  429. continue;
  430. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  431. continue;
  432. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  433. continue;
  434. if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
  435. continue;
  436. /* skip the function enable register */
  437. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
  438. continue;
  439. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
  440. continue;
  441. if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
  442. continue;
  443. init_delay = 1;
  444. /* After writing this register, HW needs time for CRB */
  445. /* to quiet down (else crb_window returns 0xffffffff) */
  446. if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
  447. init_delay = 1000;
  448. QLCWR32(adapter, off, buf[i].data);
  449. msleep(init_delay);
  450. }
  451. kfree(buf);
  452. /* p2dn replyCount */
  453. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
  454. /* disable_peg_cache 0 & 1*/
  455. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
  456. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
  457. /* peg_clr_all */
  458. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
  459. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
  460. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
  461. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
  462. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
  463. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
  464. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
  465. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
  466. return 0;
  467. }
  468. int
  469. qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
  470. int timeo;
  471. u32 val;
  472. val = QLCRD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
  473. val = QLC_DEV_GET_DRV(val, adapter->portnum);
  474. if ((val & 0x3) != QLCNIC_TYPE_NIC) {
  475. dev_err(&adapter->pdev->dev,
  476. "Not an Ethernet NIC func=%u\n", val);
  477. return -EIO;
  478. }
  479. adapter->physical_port = (val >> 2);
  480. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
  481. timeo = 30;
  482. adapter->dev_init_timeo = timeo;
  483. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
  484. timeo = 10;
  485. adapter->reset_ack_timeo = timeo;
  486. return 0;
  487. }
  488. int
  489. qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
  490. {
  491. u32 ver = -1, min_ver;
  492. qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET, (int *)&ver);
  493. ver = QLCNIC_DECODE_VERSION(ver);
  494. min_ver = QLCNIC_MIN_FW_VERSION;
  495. if (ver < min_ver) {
  496. dev_err(&adapter->pdev->dev,
  497. "firmware version %d.%d.%d unsupported."
  498. "Min supported version %d.%d.%d\n",
  499. _major(ver), _minor(ver), _build(ver),
  500. _major(min_ver), _minor(min_ver), _build(min_ver));
  501. return -EINVAL;
  502. }
  503. return 0;
  504. }
  505. static int
  506. qlcnic_has_mn(struct qlcnic_adapter *adapter)
  507. {
  508. u32 capability;
  509. capability = 0;
  510. capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
  511. if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
  512. return 1;
  513. return 0;
  514. }
  515. static
  516. struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
  517. {
  518. u32 i;
  519. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  520. __le32 entries = cpu_to_le32(directory->num_entries);
  521. for (i = 0; i < entries; i++) {
  522. __le32 offs = cpu_to_le32(directory->findex) +
  523. (i * cpu_to_le32(directory->entry_size));
  524. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  525. if (tab_type == section)
  526. return (struct uni_table_desc *) &unirom[offs];
  527. }
  528. return NULL;
  529. }
  530. #define FILEHEADER_SIZE (14 * 4)
  531. static int
  532. qlcnic_validate_header(struct qlcnic_adapter *adapter)
  533. {
  534. const u8 *unirom = adapter->fw->data;
  535. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  536. __le32 fw_file_size = adapter->fw->size;
  537. __le32 entries;
  538. __le32 entry_size;
  539. __le32 tab_size;
  540. if (fw_file_size < FILEHEADER_SIZE)
  541. return -EINVAL;
  542. entries = cpu_to_le32(directory->num_entries);
  543. entry_size = cpu_to_le32(directory->entry_size);
  544. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  545. if (fw_file_size < tab_size)
  546. return -EINVAL;
  547. return 0;
  548. }
  549. static int
  550. qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
  551. {
  552. struct uni_table_desc *tab_desc;
  553. struct uni_data_desc *descr;
  554. const u8 *unirom = adapter->fw->data;
  555. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  556. QLCNIC_UNI_BOOTLD_IDX_OFF));
  557. __le32 offs;
  558. __le32 tab_size;
  559. __le32 data_size;
  560. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
  561. if (!tab_desc)
  562. return -EINVAL;
  563. tab_size = cpu_to_le32(tab_desc->findex) +
  564. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  565. if (adapter->fw->size < tab_size)
  566. return -EINVAL;
  567. offs = cpu_to_le32(tab_desc->findex) +
  568. (cpu_to_le32(tab_desc->entry_size) * (idx));
  569. descr = (struct uni_data_desc *)&unirom[offs];
  570. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  571. if (adapter->fw->size < data_size)
  572. return -EINVAL;
  573. return 0;
  574. }
  575. static int
  576. qlcnic_validate_fw(struct qlcnic_adapter *adapter)
  577. {
  578. struct uni_table_desc *tab_desc;
  579. struct uni_data_desc *descr;
  580. const u8 *unirom = adapter->fw->data;
  581. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  582. QLCNIC_UNI_FIRMWARE_IDX_OFF));
  583. __le32 offs;
  584. __le32 tab_size;
  585. __le32 data_size;
  586. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
  587. if (!tab_desc)
  588. return -EINVAL;
  589. tab_size = cpu_to_le32(tab_desc->findex) +
  590. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  591. if (adapter->fw->size < tab_size)
  592. return -EINVAL;
  593. offs = cpu_to_le32(tab_desc->findex) +
  594. (cpu_to_le32(tab_desc->entry_size) * (idx));
  595. descr = (struct uni_data_desc *)&unirom[offs];
  596. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  597. if (adapter->fw->size < data_size)
  598. return -EINVAL;
  599. return 0;
  600. }
  601. static int
  602. qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
  603. {
  604. struct uni_table_desc *ptab_descr;
  605. const u8 *unirom = adapter->fw->data;
  606. int mn_present = qlcnic_has_mn(adapter);
  607. __le32 entries;
  608. __le32 entry_size;
  609. __le32 tab_size;
  610. u32 i;
  611. ptab_descr = qlcnic_get_table_desc(unirom,
  612. QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
  613. if (!ptab_descr)
  614. return -EINVAL;
  615. entries = cpu_to_le32(ptab_descr->num_entries);
  616. entry_size = cpu_to_le32(ptab_descr->entry_size);
  617. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  618. if (adapter->fw->size < tab_size)
  619. return -EINVAL;
  620. nomn:
  621. for (i = 0; i < entries; i++) {
  622. __le32 flags, file_chiprev, offs;
  623. u8 chiprev = adapter->ahw.revision_id;
  624. u32 flagbit;
  625. offs = cpu_to_le32(ptab_descr->findex) +
  626. (i * cpu_to_le32(ptab_descr->entry_size));
  627. flags = cpu_to_le32(*((int *)&unirom[offs] +
  628. QLCNIC_UNI_FLAGS_OFF));
  629. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  630. QLCNIC_UNI_CHIP_REV_OFF));
  631. flagbit = mn_present ? 1 : 2;
  632. if ((chiprev == file_chiprev) &&
  633. ((1ULL << flagbit) & flags)) {
  634. adapter->file_prd_off = offs;
  635. return 0;
  636. }
  637. }
  638. if (mn_present) {
  639. mn_present = 0;
  640. goto nomn;
  641. }
  642. return -EINVAL;
  643. }
  644. static int
  645. qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
  646. {
  647. if (qlcnic_validate_header(adapter)) {
  648. dev_err(&adapter->pdev->dev,
  649. "unified image: header validation failed\n");
  650. return -EINVAL;
  651. }
  652. if (qlcnic_validate_product_offs(adapter)) {
  653. dev_err(&adapter->pdev->dev,
  654. "unified image: product validation failed\n");
  655. return -EINVAL;
  656. }
  657. if (qlcnic_validate_bootld(adapter)) {
  658. dev_err(&adapter->pdev->dev,
  659. "unified image: bootld validation failed\n");
  660. return -EINVAL;
  661. }
  662. if (qlcnic_validate_fw(adapter)) {
  663. dev_err(&adapter->pdev->dev,
  664. "unified image: firmware validation failed\n");
  665. return -EINVAL;
  666. }
  667. return 0;
  668. }
  669. static
  670. struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
  671. u32 section, u32 idx_offset)
  672. {
  673. const u8 *unirom = adapter->fw->data;
  674. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  675. idx_offset));
  676. struct uni_table_desc *tab_desc;
  677. __le32 offs;
  678. tab_desc = qlcnic_get_table_desc(unirom, section);
  679. if (tab_desc == NULL)
  680. return NULL;
  681. offs = cpu_to_le32(tab_desc->findex) +
  682. (cpu_to_le32(tab_desc->entry_size) * idx);
  683. return (struct uni_data_desc *)&unirom[offs];
  684. }
  685. static u8 *
  686. qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
  687. {
  688. u32 offs = QLCNIC_BOOTLD_START;
  689. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  690. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  691. QLCNIC_UNI_DIR_SECT_BOOTLD,
  692. QLCNIC_UNI_BOOTLD_IDX_OFF))->findex);
  693. return (u8 *)&adapter->fw->data[offs];
  694. }
  695. static u8 *
  696. qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
  697. {
  698. u32 offs = QLCNIC_IMAGE_START;
  699. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  700. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  701. QLCNIC_UNI_DIR_SECT_FW,
  702. QLCNIC_UNI_FIRMWARE_IDX_OFF))->findex);
  703. return (u8 *)&adapter->fw->data[offs];
  704. }
  705. static __le32
  706. qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
  707. {
  708. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  709. return cpu_to_le32((qlcnic_get_data_desc(adapter,
  710. QLCNIC_UNI_DIR_SECT_FW,
  711. QLCNIC_UNI_FIRMWARE_IDX_OFF))->size);
  712. else
  713. return cpu_to_le32(
  714. *(u32 *)&adapter->fw->data[QLCNIC_FW_SIZE_OFFSET]);
  715. }
  716. static __le32
  717. qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
  718. {
  719. struct uni_data_desc *fw_data_desc;
  720. const struct firmware *fw = adapter->fw;
  721. __le32 major, minor, sub;
  722. const u8 *ver_str;
  723. int i, ret;
  724. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  725. return cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET]);
  726. fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  727. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  728. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  729. cpu_to_le32(fw_data_desc->size) - 17;
  730. for (i = 0; i < 12; i++) {
  731. if (!strncmp(&ver_str[i], "REV=", 4)) {
  732. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  733. &major, &minor, &sub);
  734. if (ret != 3)
  735. return 0;
  736. else
  737. return major + (minor << 8) + (sub << 16);
  738. }
  739. }
  740. return 0;
  741. }
  742. static __le32
  743. qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
  744. {
  745. const struct firmware *fw = adapter->fw;
  746. __le32 bios_ver, prd_off = adapter->file_prd_off;
  747. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  748. return cpu_to_le32(
  749. *(u32 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET]);
  750. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  751. + QLCNIC_UNI_BIOS_VERSION_OFF));
  752. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
  753. }
  754. int
  755. qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
  756. {
  757. u32 count, old_count;
  758. u32 val, version, major, minor, build;
  759. int i, timeout;
  760. if (adapter->need_fw_reset)
  761. return 1;
  762. /* last attempt had failed */
  763. if (QLCRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  764. return 1;
  765. old_count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  766. for (i = 0; i < 10; i++) {
  767. timeout = msleep_interruptible(200);
  768. if (timeout) {
  769. QLCWR32(adapter, CRB_CMDPEG_STATE,
  770. PHAN_INITIALIZE_FAILED);
  771. return -EINTR;
  772. }
  773. count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  774. if (count != old_count)
  775. break;
  776. }
  777. /* firmware is dead */
  778. if (count == old_count)
  779. return 1;
  780. /* check if we have got newer or different file firmware */
  781. if (adapter->fw) {
  782. val = qlcnic_get_fw_version(adapter);
  783. version = QLCNIC_DECODE_VERSION(val);
  784. major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
  785. minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
  786. build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
  787. if (version > QLCNIC_VERSION_CODE(major, minor, build))
  788. return 1;
  789. }
  790. return 0;
  791. }
  792. static const char *fw_name[] = {
  793. QLCNIC_UNIFIED_ROMIMAGE_NAME,
  794. QLCNIC_FLASH_ROMIMAGE_NAME,
  795. };
  796. int
  797. qlcnic_load_firmware(struct qlcnic_adapter *adapter)
  798. {
  799. u64 *ptr64;
  800. u32 i, flashaddr, size;
  801. const struct firmware *fw = adapter->fw;
  802. struct pci_dev *pdev = adapter->pdev;
  803. dev_info(&pdev->dev, "loading firmware from %s\n",
  804. fw_name[adapter->fw_type]);
  805. if (fw) {
  806. __le64 data;
  807. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  808. ptr64 = (u64 *)qlcnic_get_bootld_offs(adapter);
  809. flashaddr = QLCNIC_BOOTLD_START;
  810. for (i = 0; i < size; i++) {
  811. data = cpu_to_le64(ptr64[i]);
  812. if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
  813. return -EIO;
  814. flashaddr += 8;
  815. }
  816. size = (__force u32)qlcnic_get_fw_size(adapter) / 8;
  817. ptr64 = (u64 *)qlcnic_get_fw_offs(adapter);
  818. flashaddr = QLCNIC_IMAGE_START;
  819. for (i = 0; i < size; i++) {
  820. data = cpu_to_le64(ptr64[i]);
  821. if (qlcnic_pci_mem_write_2M(adapter,
  822. flashaddr, data))
  823. return -EIO;
  824. flashaddr += 8;
  825. }
  826. size = (__force u32)qlcnic_get_fw_size(adapter) % 8;
  827. if (size) {
  828. data = cpu_to_le64(ptr64[i]);
  829. if (qlcnic_pci_mem_write_2M(adapter,
  830. flashaddr, data))
  831. return -EIO;
  832. }
  833. } else {
  834. u64 data;
  835. u32 hi, lo;
  836. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  837. flashaddr = QLCNIC_BOOTLD_START;
  838. for (i = 0; i < size; i++) {
  839. if (qlcnic_rom_fast_read(adapter,
  840. flashaddr, (int *)&lo) != 0)
  841. return -EIO;
  842. if (qlcnic_rom_fast_read(adapter,
  843. flashaddr + 4, (int *)&hi) != 0)
  844. return -EIO;
  845. data = (((u64)hi << 32) | lo);
  846. if (qlcnic_pci_mem_write_2M(adapter,
  847. flashaddr, data))
  848. return -EIO;
  849. flashaddr += 8;
  850. }
  851. }
  852. msleep(1);
  853. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
  854. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
  855. return 0;
  856. }
  857. static int
  858. qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
  859. {
  860. __le32 val;
  861. u32 ver, bios, min_size;
  862. struct pci_dev *pdev = adapter->pdev;
  863. const struct firmware *fw = adapter->fw;
  864. u8 fw_type = adapter->fw_type;
  865. if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
  866. if (qlcnic_validate_unified_romimage(adapter))
  867. return -EINVAL;
  868. min_size = QLCNIC_UNI_FW_MIN_SIZE;
  869. } else {
  870. val = cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
  871. if ((__force u32)val != QLCNIC_BDINFO_MAGIC)
  872. return -EINVAL;
  873. min_size = QLCNIC_FW_MIN_SIZE;
  874. }
  875. if (fw->size < min_size)
  876. return -EINVAL;
  877. val = qlcnic_get_fw_version(adapter);
  878. ver = QLCNIC_DECODE_VERSION(val);
  879. if (ver < QLCNIC_MIN_FW_VERSION) {
  880. dev_err(&pdev->dev,
  881. "%s: firmware version %d.%d.%d unsupported\n",
  882. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  883. return -EINVAL;
  884. }
  885. val = qlcnic_get_bios_version(adapter);
  886. qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
  887. if ((__force u32)val != bios) {
  888. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  889. fw_name[fw_type]);
  890. return -EINVAL;
  891. }
  892. /* check if flashed firmware is newer */
  893. if (qlcnic_rom_fast_read(adapter,
  894. QLCNIC_FW_VERSION_OFFSET, (int *)&val))
  895. return -EIO;
  896. val = QLCNIC_DECODE_VERSION(val);
  897. if (val > ver) {
  898. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  899. fw_name[fw_type]);
  900. return -EINVAL;
  901. }
  902. QLCWR32(adapter, QLCNIC_CAM_RAM(0x1fc), QLCNIC_BDINFO_MAGIC);
  903. return 0;
  904. }
  905. static void
  906. qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
  907. {
  908. u8 fw_type;
  909. switch (adapter->fw_type) {
  910. case QLCNIC_UNKNOWN_ROMIMAGE:
  911. fw_type = QLCNIC_UNIFIED_ROMIMAGE;
  912. break;
  913. case QLCNIC_UNIFIED_ROMIMAGE:
  914. default:
  915. fw_type = QLCNIC_FLASH_ROMIMAGE;
  916. break;
  917. }
  918. adapter->fw_type = fw_type;
  919. }
  920. void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
  921. {
  922. struct pci_dev *pdev = adapter->pdev;
  923. int rc;
  924. adapter->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
  925. next:
  926. qlcnic_get_next_fwtype(adapter);
  927. if (adapter->fw_type == QLCNIC_FLASH_ROMIMAGE) {
  928. adapter->fw = NULL;
  929. } else {
  930. rc = request_firmware(&adapter->fw,
  931. fw_name[adapter->fw_type], &pdev->dev);
  932. if (rc != 0)
  933. goto next;
  934. rc = qlcnic_validate_firmware(adapter);
  935. if (rc != 0) {
  936. release_firmware(adapter->fw);
  937. msleep(1);
  938. goto next;
  939. }
  940. }
  941. }
  942. void
  943. qlcnic_release_firmware(struct qlcnic_adapter *adapter)
  944. {
  945. if (adapter->fw)
  946. release_firmware(adapter->fw);
  947. adapter->fw = NULL;
  948. }
  949. static int qlcnic_cmd_peg_ready(struct qlcnic_adapter *adapter)
  950. {
  951. u32 val;
  952. int retries = 60;
  953. do {
  954. val = QLCRD32(adapter, CRB_CMDPEG_STATE);
  955. switch (val) {
  956. case PHAN_INITIALIZE_COMPLETE:
  957. case PHAN_INITIALIZE_ACK:
  958. return 0;
  959. case PHAN_INITIALIZE_FAILED:
  960. goto out_err;
  961. default:
  962. break;
  963. }
  964. msleep(500);
  965. } while (--retries);
  966. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  967. out_err:
  968. dev_err(&adapter->pdev->dev, "Command Peg initialization not "
  969. "complete, state: 0x%x.\n", val);
  970. return -EIO;
  971. }
  972. static int
  973. qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
  974. {
  975. u32 val;
  976. int retries = 2000;
  977. do {
  978. val = QLCRD32(adapter, CRB_RCVPEG_STATE);
  979. if (val == PHAN_PEG_RCV_INITIALIZED)
  980. return 0;
  981. msleep(10);
  982. } while (--retries);
  983. if (!retries) {
  984. dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
  985. "complete, state: 0x%x.\n", val);
  986. return -EIO;
  987. }
  988. return 0;
  989. }
  990. int qlcnic_init_firmware(struct qlcnic_adapter *adapter)
  991. {
  992. int err;
  993. err = qlcnic_cmd_peg_ready(adapter);
  994. if (err)
  995. return err;
  996. err = qlcnic_receive_peg_ready(adapter);
  997. if (err)
  998. return err;
  999. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1000. return err;
  1001. }
  1002. static void
  1003. qlcnic_handle_linkevent(struct qlcnic_adapter *adapter,
  1004. struct qlcnic_fw_msg *msg)
  1005. {
  1006. u32 cable_OUI;
  1007. u16 cable_len;
  1008. u16 link_speed;
  1009. u8 link_status, module, duplex, autoneg;
  1010. struct net_device *netdev = adapter->netdev;
  1011. adapter->has_link_events = 1;
  1012. cable_OUI = msg->body[1] & 0xffffffff;
  1013. cable_len = (msg->body[1] >> 32) & 0xffff;
  1014. link_speed = (msg->body[1] >> 48) & 0xffff;
  1015. link_status = msg->body[2] & 0xff;
  1016. duplex = (msg->body[2] >> 16) & 0xff;
  1017. autoneg = (msg->body[2] >> 24) & 0xff;
  1018. module = (msg->body[2] >> 8) & 0xff;
  1019. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE)
  1020. dev_info(&netdev->dev, "unsupported cable: OUI 0x%x, "
  1021. "length %d\n", cable_OUI, cable_len);
  1022. else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN)
  1023. dev_info(&netdev->dev, "unsupported cable length %d\n",
  1024. cable_len);
  1025. qlcnic_advert_link_change(adapter, link_status);
  1026. if (duplex == LINKEVENT_FULL_DUPLEX)
  1027. adapter->link_duplex = DUPLEX_FULL;
  1028. else
  1029. adapter->link_duplex = DUPLEX_HALF;
  1030. adapter->module_type = module;
  1031. adapter->link_autoneg = autoneg;
  1032. adapter->link_speed = link_speed;
  1033. }
  1034. static void
  1035. qlcnic_handle_fw_message(int desc_cnt, int index,
  1036. struct qlcnic_host_sds_ring *sds_ring)
  1037. {
  1038. struct qlcnic_fw_msg msg;
  1039. struct status_desc *desc;
  1040. int i = 0, opcode;
  1041. while (desc_cnt > 0 && i < 8) {
  1042. desc = &sds_ring->desc_head[index];
  1043. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1044. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1045. index = get_next_index(index, sds_ring->num_desc);
  1046. desc_cnt--;
  1047. }
  1048. opcode = qlcnic_get_nic_msg_opcode(msg.body[0]);
  1049. switch (opcode) {
  1050. case QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1051. qlcnic_handle_linkevent(sds_ring->adapter, &msg);
  1052. break;
  1053. default:
  1054. break;
  1055. }
  1056. }
  1057. static int
  1058. qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
  1059. struct qlcnic_host_rds_ring *rds_ring,
  1060. struct qlcnic_rx_buffer *buffer)
  1061. {
  1062. struct sk_buff *skb;
  1063. dma_addr_t dma;
  1064. struct pci_dev *pdev = adapter->pdev;
  1065. skb = dev_alloc_skb(rds_ring->skb_size);
  1066. if (!skb) {
  1067. adapter->stats.skb_alloc_failure++;
  1068. return -ENOMEM;
  1069. }
  1070. skb_reserve(skb, 2);
  1071. dma = pci_map_single(pdev, skb->data,
  1072. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1073. if (pci_dma_mapping_error(pdev, dma)) {
  1074. adapter->stats.rx_dma_map_error++;
  1075. dev_kfree_skb_any(skb);
  1076. return -ENOMEM;
  1077. }
  1078. buffer->skb = skb;
  1079. buffer->dma = dma;
  1080. return 0;
  1081. }
  1082. static struct sk_buff *qlcnic_process_rxbuf(struct qlcnic_adapter *adapter,
  1083. struct qlcnic_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1084. {
  1085. struct qlcnic_rx_buffer *buffer;
  1086. struct sk_buff *skb;
  1087. buffer = &rds_ring->rx_buf_arr[index];
  1088. if (unlikely(buffer->skb == NULL)) {
  1089. WARN_ON(1);
  1090. return NULL;
  1091. }
  1092. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1093. PCI_DMA_FROMDEVICE);
  1094. skb = buffer->skb;
  1095. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1096. adapter->stats.csummed++;
  1097. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1098. } else {
  1099. skb->ip_summed = CHECKSUM_NONE;
  1100. }
  1101. skb->dev = adapter->netdev;
  1102. buffer->skb = NULL;
  1103. return skb;
  1104. }
  1105. static struct qlcnic_rx_buffer *
  1106. qlcnic_process_rcv(struct qlcnic_adapter *adapter,
  1107. struct qlcnic_host_sds_ring *sds_ring,
  1108. int ring, u64 sts_data0)
  1109. {
  1110. struct net_device *netdev = adapter->netdev;
  1111. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1112. struct qlcnic_rx_buffer *buffer;
  1113. struct sk_buff *skb;
  1114. struct qlcnic_host_rds_ring *rds_ring;
  1115. int index, length, cksum, pkt_offset;
  1116. if (unlikely(ring >= adapter->max_rds_rings))
  1117. return NULL;
  1118. rds_ring = &recv_ctx->rds_rings[ring];
  1119. index = qlcnic_get_sts_refhandle(sts_data0);
  1120. if (unlikely(index >= rds_ring->num_desc))
  1121. return NULL;
  1122. buffer = &rds_ring->rx_buf_arr[index];
  1123. length = qlcnic_get_sts_totallength(sts_data0);
  1124. cksum = qlcnic_get_sts_status(sts_data0);
  1125. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1126. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1127. if (!skb)
  1128. return buffer;
  1129. if (length > rds_ring->skb_size)
  1130. skb_put(skb, rds_ring->skb_size);
  1131. else
  1132. skb_put(skb, length);
  1133. if (pkt_offset)
  1134. skb_pull(skb, pkt_offset);
  1135. skb->truesize = skb->len + sizeof(struct sk_buff);
  1136. skb->protocol = eth_type_trans(skb, netdev);
  1137. napi_gro_receive(&sds_ring->napi, skb);
  1138. adapter->stats.rx_pkts++;
  1139. adapter->stats.rxbytes += length;
  1140. return buffer;
  1141. }
  1142. #define QLC_TCP_HDR_SIZE 20
  1143. #define QLC_TCP_TS_OPTION_SIZE 12
  1144. #define QLC_TCP_TS_HDR_SIZE (QLC_TCP_HDR_SIZE + QLC_TCP_TS_OPTION_SIZE)
  1145. static struct qlcnic_rx_buffer *
  1146. qlcnic_process_lro(struct qlcnic_adapter *adapter,
  1147. struct qlcnic_host_sds_ring *sds_ring,
  1148. int ring, u64 sts_data0, u64 sts_data1)
  1149. {
  1150. struct net_device *netdev = adapter->netdev;
  1151. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1152. struct qlcnic_rx_buffer *buffer;
  1153. struct sk_buff *skb;
  1154. struct qlcnic_host_rds_ring *rds_ring;
  1155. struct iphdr *iph;
  1156. struct tcphdr *th;
  1157. bool push, timestamp;
  1158. int l2_hdr_offset, l4_hdr_offset;
  1159. int index;
  1160. u16 lro_length, length, data_offset;
  1161. u32 seq_number;
  1162. if (unlikely(ring > adapter->max_rds_rings))
  1163. return NULL;
  1164. rds_ring = &recv_ctx->rds_rings[ring];
  1165. index = qlcnic_get_lro_sts_refhandle(sts_data0);
  1166. if (unlikely(index > rds_ring->num_desc))
  1167. return NULL;
  1168. buffer = &rds_ring->rx_buf_arr[index];
  1169. timestamp = qlcnic_get_lro_sts_timestamp(sts_data0);
  1170. lro_length = qlcnic_get_lro_sts_length(sts_data0);
  1171. l2_hdr_offset = qlcnic_get_lro_sts_l2_hdr_offset(sts_data0);
  1172. l4_hdr_offset = qlcnic_get_lro_sts_l4_hdr_offset(sts_data0);
  1173. push = qlcnic_get_lro_sts_push_flag(sts_data0);
  1174. seq_number = qlcnic_get_lro_sts_seq_number(sts_data1);
  1175. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1176. if (!skb)
  1177. return buffer;
  1178. if (timestamp)
  1179. data_offset = l4_hdr_offset + QLC_TCP_TS_HDR_SIZE;
  1180. else
  1181. data_offset = l4_hdr_offset + QLC_TCP_HDR_SIZE;
  1182. skb_put(skb, lro_length + data_offset);
  1183. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1184. skb_pull(skb, l2_hdr_offset);
  1185. skb->protocol = eth_type_trans(skb, netdev);
  1186. iph = (struct iphdr *)skb->data;
  1187. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1188. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1189. iph->tot_len = htons(length);
  1190. iph->check = 0;
  1191. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1192. th->psh = push;
  1193. th->seq = htonl(seq_number);
  1194. length = skb->len;
  1195. netif_receive_skb(skb);
  1196. adapter->stats.lro_pkts++;
  1197. adapter->stats.lrobytes += length;
  1198. return buffer;
  1199. }
  1200. int
  1201. qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max)
  1202. {
  1203. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1204. struct list_head *cur;
  1205. struct status_desc *desc;
  1206. struct qlcnic_rx_buffer *rxbuf;
  1207. u64 sts_data0, sts_data1;
  1208. int count = 0;
  1209. int opcode, ring, desc_cnt;
  1210. u32 consumer = sds_ring->consumer;
  1211. while (count < max) {
  1212. desc = &sds_ring->desc_head[consumer];
  1213. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1214. if (!(sts_data0 & STATUS_OWNER_HOST))
  1215. break;
  1216. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1217. opcode = qlcnic_get_sts_opcode(sts_data0);
  1218. switch (opcode) {
  1219. case QLCNIC_RXPKT_DESC:
  1220. case QLCNIC_OLD_RXPKT_DESC:
  1221. case QLCNIC_SYN_OFFLOAD:
  1222. ring = qlcnic_get_sts_type(sts_data0);
  1223. rxbuf = qlcnic_process_rcv(adapter, sds_ring,
  1224. ring, sts_data0);
  1225. break;
  1226. case QLCNIC_LRO_DESC:
  1227. ring = qlcnic_get_lro_sts_type(sts_data0);
  1228. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1229. rxbuf = qlcnic_process_lro(adapter, sds_ring,
  1230. ring, sts_data0, sts_data1);
  1231. break;
  1232. case QLCNIC_RESPONSE_DESC:
  1233. qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
  1234. default:
  1235. goto skip;
  1236. }
  1237. WARN_ON(desc_cnt > 1);
  1238. if (likely(rxbuf))
  1239. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1240. else
  1241. adapter->stats.null_rxbuf++;
  1242. skip:
  1243. for (; desc_cnt > 0; desc_cnt--) {
  1244. desc = &sds_ring->desc_head[consumer];
  1245. desc->status_desc_data[0] =
  1246. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1247. consumer = get_next_index(consumer, sds_ring->num_desc);
  1248. }
  1249. count++;
  1250. }
  1251. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1252. struct qlcnic_host_rds_ring *rds_ring =
  1253. &adapter->recv_ctx.rds_rings[ring];
  1254. if (!list_empty(&sds_ring->free_list[ring])) {
  1255. list_for_each(cur, &sds_ring->free_list[ring]) {
  1256. rxbuf = list_entry(cur,
  1257. struct qlcnic_rx_buffer, list);
  1258. qlcnic_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1259. }
  1260. spin_lock(&rds_ring->lock);
  1261. list_splice_tail_init(&sds_ring->free_list[ring],
  1262. &rds_ring->free_list);
  1263. spin_unlock(&rds_ring->lock);
  1264. }
  1265. qlcnic_post_rx_buffers_nodb(adapter, rds_ring);
  1266. }
  1267. if (count) {
  1268. sds_ring->consumer = consumer;
  1269. writel(consumer, sds_ring->crb_sts_consumer);
  1270. }
  1271. return count;
  1272. }
  1273. void
  1274. qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
  1275. struct qlcnic_host_rds_ring *rds_ring)
  1276. {
  1277. struct rcv_desc *pdesc;
  1278. struct qlcnic_rx_buffer *buffer;
  1279. int producer, count = 0;
  1280. struct list_head *head;
  1281. spin_lock(&rds_ring->lock);
  1282. producer = rds_ring->producer;
  1283. head = &rds_ring->free_list;
  1284. while (!list_empty(head)) {
  1285. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1286. if (!buffer->skb) {
  1287. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1288. break;
  1289. }
  1290. count++;
  1291. list_del(&buffer->list);
  1292. /* make a rcv descriptor */
  1293. pdesc = &rds_ring->desc_head[producer];
  1294. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1295. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1296. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1297. producer = get_next_index(producer, rds_ring->num_desc);
  1298. }
  1299. if (count) {
  1300. rds_ring->producer = producer;
  1301. writel((producer-1) & (rds_ring->num_desc-1),
  1302. rds_ring->crb_rcv_producer);
  1303. }
  1304. spin_unlock(&rds_ring->lock);
  1305. }
  1306. static void
  1307. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  1308. struct qlcnic_host_rds_ring *rds_ring)
  1309. {
  1310. struct rcv_desc *pdesc;
  1311. struct qlcnic_rx_buffer *buffer;
  1312. int producer, count = 0;
  1313. struct list_head *head;
  1314. if (!spin_trylock(&rds_ring->lock))
  1315. return;
  1316. producer = rds_ring->producer;
  1317. head = &rds_ring->free_list;
  1318. while (!list_empty(head)) {
  1319. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1320. if (!buffer->skb) {
  1321. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1322. break;
  1323. }
  1324. count++;
  1325. list_del(&buffer->list);
  1326. /* make a rcv descriptor */
  1327. pdesc = &rds_ring->desc_head[producer];
  1328. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1329. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1330. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1331. producer = get_next_index(producer, rds_ring->num_desc);
  1332. }
  1333. if (count) {
  1334. rds_ring->producer = producer;
  1335. writel((producer - 1) & (rds_ring->num_desc - 1),
  1336. rds_ring->crb_rcv_producer);
  1337. }
  1338. spin_unlock(&rds_ring->lock);
  1339. }
  1340. static struct qlcnic_rx_buffer *
  1341. qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
  1342. struct qlcnic_host_sds_ring *sds_ring,
  1343. int ring, u64 sts_data0)
  1344. {
  1345. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1346. struct qlcnic_rx_buffer *buffer;
  1347. struct sk_buff *skb;
  1348. struct qlcnic_host_rds_ring *rds_ring;
  1349. int index, length, cksum, pkt_offset;
  1350. if (unlikely(ring >= adapter->max_rds_rings))
  1351. return NULL;
  1352. rds_ring = &recv_ctx->rds_rings[ring];
  1353. index = qlcnic_get_sts_refhandle(sts_data0);
  1354. if (unlikely(index >= rds_ring->num_desc))
  1355. return NULL;
  1356. buffer = &rds_ring->rx_buf_arr[index];
  1357. length = qlcnic_get_sts_totallength(sts_data0);
  1358. cksum = qlcnic_get_sts_status(sts_data0);
  1359. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1360. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1361. if (!skb)
  1362. return buffer;
  1363. skb_put(skb, rds_ring->skb_size);
  1364. if (pkt_offset)
  1365. skb_pull(skb, pkt_offset);
  1366. skb->truesize = skb->len + sizeof(struct sk_buff);
  1367. if (!qlcnic_check_loopback_buff(skb->data))
  1368. adapter->diag_cnt++;
  1369. dev_kfree_skb_any(skb);
  1370. adapter->stats.rx_pkts++;
  1371. adapter->stats.rxbytes += length;
  1372. return buffer;
  1373. }
  1374. void
  1375. qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
  1376. {
  1377. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1378. struct status_desc *desc;
  1379. struct qlcnic_rx_buffer *rxbuf;
  1380. u64 sts_data0;
  1381. int opcode, ring, desc_cnt;
  1382. u32 consumer = sds_ring->consumer;
  1383. desc = &sds_ring->desc_head[consumer];
  1384. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1385. if (!(sts_data0 & STATUS_OWNER_HOST))
  1386. return;
  1387. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1388. opcode = qlcnic_get_sts_opcode(sts_data0);
  1389. ring = qlcnic_get_sts_type(sts_data0);
  1390. rxbuf = qlcnic_process_rcv_diag(adapter, sds_ring,
  1391. ring, sts_data0);
  1392. desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
  1393. consumer = get_next_index(consumer, sds_ring->num_desc);
  1394. sds_ring->consumer = consumer;
  1395. writel(consumer, sds_ring->crb_sts_consumer);
  1396. }
  1397. void
  1398. qlcnic_fetch_mac(struct qlcnic_adapter *adapter, u32 off1, u32 off2,
  1399. u8 alt_mac, u8 *mac)
  1400. {
  1401. u32 mac_low, mac_high;
  1402. int i;
  1403. mac_low = QLCRD32(adapter, off1);
  1404. mac_high = QLCRD32(adapter, off2);
  1405. if (alt_mac) {
  1406. mac_low |= (mac_low >> 16) | (mac_high << 16);
  1407. mac_high >>= 16;
  1408. }
  1409. for (i = 0; i < 2; i++)
  1410. mac[i] = (u8)(mac_high >> ((1 - i) * 8));
  1411. for (i = 2; i < 6; i++)
  1412. mac[i] = (u8)(mac_low >> ((5 - i) * 8));
  1413. }